1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Thunderbolt driver - NHI registers
  4 *
  5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  6 */
  7
  8#ifndef NHI_REGS_H_
  9#define NHI_REGS_H_
 10
 11#include <linux/types.h>
 12
 13enum ring_flags {
 14	RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
 15	RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
 16	RING_FLAG_PCI_NO_SNOOP = 1 << 29,
 17	RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
 18	RING_FLAG_ENABLE = 1 << 31,
 19};
 20
 21/**
 22 * struct ring_desc - TX/RX ring entry
 23 *
 24 * For TX set length/eof/sof.
 25 * For RX length/eof/sof are set by the NHI.
 26 */
 27struct ring_desc {
 28	u64 phys;
 29	u32 length:12;
 30	u32 eof:4;
 31	u32 sof:4;
 32	enum ring_desc_flags flags:12;
 33	u32 time; /* write zero */
 34} __packed;
 35
 36/* NHI registers in bar 0 */
 37
 38/*
 39 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 40 * 00: physical pointer to an array of struct ring_desc
 41 * 08: ring tail (set by NHI)
 42 * 10: ring head (index of first non posted descriptor)
 43 * 12: descriptor count
 44 */
 45#define REG_TX_RING_BASE	0x00000
 46
 47/*
 48 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 49 * 00: physical pointer to an array of struct ring_desc
 50 * 08: ring head (index of first not posted descriptor)
 51 * 10: ring tail (set by NHI)
 52 * 12: descriptor count
 53 * 14: max frame sizes (anything larger than 0x100 has no effect)
 54 */
 55#define REG_RX_RING_BASE	0x08000
 56
 57/*
 58 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 59 * 00: enum_ring_flags
 60 * 04: isoch time stamp ?? (write 0)
 61 * ..: unknown
 62 */
 63#define REG_TX_OPTIONS_BASE	0x19800
 64
 65/*
 66 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
 67 * 00: enum ring_flags
 68 *     If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
 69 *     the corresponding TX hop id.
 70 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
 71 * ..: unknown
 72 */
 73#define REG_RX_OPTIONS_BASE	0x29800
 74#define REG_RX_OPTIONS_E2E_HOP_MASK	GENMASK(22, 12)
 75#define REG_RX_OPTIONS_E2E_HOP_SHIFT	12
 76
 77/*
 78 * three bitfields: tx, rx, rx overflow
 79 * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
 80 * cleared on read. New interrupts are fired only after ALL registers have been
 81 * read (even those containing only disabled rings).
 82 */
 83#define REG_RING_NOTIFY_BASE	0x37800
 84#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
 85
 86/*
 87 * two bitfields: rx, tx
 88 * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
 89 * enable/disable interrupts set/clear the corresponding bits.
 90 */
 91#define REG_RING_INTERRUPT_BASE	0x38200
 92#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
 93
 94#define REG_INT_THROTTLING_RATE	0x38c00
 95
 96/* Interrupt Vector Allocation */
 97#define REG_INT_VEC_ALLOC_BASE	0x38c40
 98#define REG_INT_VEC_ALLOC_BITS	4
 99#define REG_INT_VEC_ALLOC_MASK	GENMASK(3, 0)
100#define REG_INT_VEC_ALLOC_REGS	(32 / REG_INT_VEC_ALLOC_BITS)
101
102/* The last 11 bits contain the number of hops supported by the NHI port. */
103#define REG_HOP_COUNT		0x39640
104
105#define REG_DMA_MISC			0x39864
106#define REG_DMA_MISC_INT_AUTO_CLEAR     BIT(2)
107
108#define REG_INMAIL_DATA			0x39900
109
110#define REG_INMAIL_CMD			0x39904
111#define REG_INMAIL_CMD_MASK		GENMASK(7, 0)
112#define REG_INMAIL_ERROR		BIT(30)
113#define REG_INMAIL_OP_REQUEST		BIT(31)
114
115#define REG_OUTMAIL_CMD			0x3990c
116#define REG_OUTMAIL_CMD_OPMODE_SHIFT	8
117#define REG_OUTMAIL_CMD_OPMODE_MASK	GENMASK(11, 8)
118
119#define REG_FW_STS			0x39944
120#define REG_FW_STS_NVM_AUTH_DONE	BIT(31)
121#define REG_FW_STS_CIO_RESET_REQ	BIT(30)
122#define REG_FW_STS_ICM_EN_CPU		BIT(2)
123#define REG_FW_STS_ICM_EN_INVERT	BIT(1)
124#define REG_FW_STS_ICM_EN		BIT(0)
125
126#endif