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1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/gpio.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/module.h>
28#include <linux/irqdomain.h>
29#include <linux/pinctrl/consumer.h>
30
31#include <asm/mach/irq.h>
32
33#include <mach/iomap.h>
34#include <mach/suspend.h>
35
36#define GPIO_BANK(x) ((x) >> 5)
37#define GPIO_PORT(x) (((x) >> 3) & 0x3)
38#define GPIO_BIT(x) ((x) & 0x7)
39
40#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
41 GPIO_PORT(x) * 4)
42
43#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
44#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
45#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
46#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
47#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
48#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
49#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
50#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
51
52#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
53#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
54#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
55#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
56#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
57#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
58
59#define GPIO_INT_LVL_MASK 0x010101
60#define GPIO_INT_LVL_EDGE_RISING 0x000101
61#define GPIO_INT_LVL_EDGE_FALLING 0x000100
62#define GPIO_INT_LVL_EDGE_BOTH 0x010100
63#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
64#define GPIO_INT_LVL_LEVEL_LOW 0x000000
65
66struct tegra_gpio_bank {
67 int bank;
68 int irq;
69 spinlock_t lvl_lock[4];
70#ifdef CONFIG_PM
71 u32 cnf[4];
72 u32 out[4];
73 u32 oe[4];
74 u32 int_enb[4];
75 u32 int_lvl[4];
76#endif
77};
78
79static struct irq_domain *irq_domain;
80static void __iomem *regs;
81static u32 tegra_gpio_bank_count;
82static u32 tegra_gpio_bank_stride;
83static u32 tegra_gpio_upper_offset;
84static struct tegra_gpio_bank *tegra_gpio_banks;
85
86static inline void tegra_gpio_writel(u32 val, u32 reg)
87{
88 __raw_writel(val, regs + reg);
89}
90
91static inline u32 tegra_gpio_readl(u32 reg)
92{
93 return __raw_readl(regs + reg);
94}
95
96static int tegra_gpio_compose(int bank, int port, int bit)
97{
98 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
99}
100
101static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
102{
103 u32 val;
104
105 val = 0x100 << GPIO_BIT(gpio);
106 if (value)
107 val |= 1 << GPIO_BIT(gpio);
108 tegra_gpio_writel(val, reg);
109}
110
111static void tegra_gpio_enable(int gpio)
112{
113 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
114}
115EXPORT_SYMBOL_GPL(tegra_gpio_enable);
116
117static void tegra_gpio_disable(int gpio)
118{
119 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
120}
121EXPORT_SYMBOL_GPL(tegra_gpio_disable);
122
123int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
124{
125 return pinctrl_request_gpio(offset);
126}
127
128void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
129{
130 pinctrl_free_gpio(offset);
131 tegra_gpio_disable(offset);
132}
133
134static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
135{
136 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
137}
138
139static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
140{
141 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
142}
143
144static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
145{
146 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
147 tegra_gpio_enable(offset);
148 return 0;
149}
150
151static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
152 int value)
153{
154 tegra_gpio_set(chip, offset, value);
155 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
156 tegra_gpio_enable(offset);
157 return 0;
158}
159
160static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
161{
162 return irq_find_mapping(irq_domain, offset);
163}
164
165static struct gpio_chip tegra_gpio_chip = {
166 .label = "tegra-gpio",
167 .request = tegra_gpio_request,
168 .free = tegra_gpio_free,
169 .direction_input = tegra_gpio_direction_input,
170 .get = tegra_gpio_get,
171 .direction_output = tegra_gpio_direction_output,
172 .set = tegra_gpio_set,
173 .to_irq = tegra_gpio_to_irq,
174 .base = 0,
175};
176
177static void tegra_gpio_irq_ack(struct irq_data *d)
178{
179 int gpio = d->hwirq;
180
181 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
182}
183
184static void tegra_gpio_irq_mask(struct irq_data *d)
185{
186 int gpio = d->hwirq;
187
188 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
189}
190
191static void tegra_gpio_irq_unmask(struct irq_data *d)
192{
193 int gpio = d->hwirq;
194
195 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
196}
197
198static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
199{
200 int gpio = d->hwirq;
201 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
202 int port = GPIO_PORT(gpio);
203 int lvl_type;
204 int val;
205 unsigned long flags;
206
207 switch (type & IRQ_TYPE_SENSE_MASK) {
208 case IRQ_TYPE_EDGE_RISING:
209 lvl_type = GPIO_INT_LVL_EDGE_RISING;
210 break;
211
212 case IRQ_TYPE_EDGE_FALLING:
213 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
214 break;
215
216 case IRQ_TYPE_EDGE_BOTH:
217 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
218 break;
219
220 case IRQ_TYPE_LEVEL_HIGH:
221 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
222 break;
223
224 case IRQ_TYPE_LEVEL_LOW:
225 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
226 break;
227
228 default:
229 return -EINVAL;
230 }
231
232 spin_lock_irqsave(&bank->lvl_lock[port], flags);
233
234 val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
235 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
236 val |= lvl_type << GPIO_BIT(gpio);
237 tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
238
239 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
240
241 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
242 tegra_gpio_enable(gpio);
243
244 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
245 __irq_set_handler_locked(d->irq, handle_level_irq);
246 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
247 __irq_set_handler_locked(d->irq, handle_edge_irq);
248
249 return 0;
250}
251
252static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
253{
254 struct tegra_gpio_bank *bank;
255 int port;
256 int pin;
257 int unmasked = 0;
258 struct irq_chip *chip = irq_desc_get_chip(desc);
259
260 chained_irq_enter(chip, desc);
261
262 bank = irq_get_handler_data(irq);
263
264 for (port = 0; port < 4; port++) {
265 int gpio = tegra_gpio_compose(bank->bank, port, 0);
266 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
267 tegra_gpio_readl(GPIO_INT_ENB(gpio));
268 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
269
270 for_each_set_bit(pin, &sta, 8) {
271 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
272
273 /* if gpio is edge triggered, clear condition
274 * before executing the hander so that we don't
275 * miss edges
276 */
277 if (lvl & (0x100 << pin)) {
278 unmasked = 1;
279 chained_irq_exit(chip, desc);
280 }
281
282 generic_handle_irq(gpio_to_irq(gpio + pin));
283 }
284 }
285
286 if (!unmasked)
287 chained_irq_exit(chip, desc);
288
289}
290
291#ifdef CONFIG_PM
292void tegra_gpio_resume(void)
293{
294 unsigned long flags;
295 int b;
296 int p;
297
298 local_irq_save(flags);
299
300 for (b = 0; b < tegra_gpio_bank_count; b++) {
301 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
302
303 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
304 unsigned int gpio = (b<<5) | (p<<3);
305 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
306 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
307 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
308 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
309 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
310 }
311 }
312
313 local_irq_restore(flags);
314}
315
316void tegra_gpio_suspend(void)
317{
318 unsigned long flags;
319 int b;
320 int p;
321
322 local_irq_save(flags);
323 for (b = 0; b < tegra_gpio_bank_count; b++) {
324 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
325
326 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
327 unsigned int gpio = (b<<5) | (p<<3);
328 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
329 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
330 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
331 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
332 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
333 }
334 }
335 local_irq_restore(flags);
336}
337
338static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
339{
340 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
341 return irq_set_irq_wake(bank->irq, enable);
342}
343#endif
344
345static struct irq_chip tegra_gpio_irq_chip = {
346 .name = "GPIO",
347 .irq_ack = tegra_gpio_irq_ack,
348 .irq_mask = tegra_gpio_irq_mask,
349 .irq_unmask = tegra_gpio_irq_unmask,
350 .irq_set_type = tegra_gpio_irq_set_type,
351#ifdef CONFIG_PM
352 .irq_set_wake = tegra_gpio_wake_enable,
353#endif
354};
355
356struct tegra_gpio_soc_config {
357 u32 bank_stride;
358 u32 upper_offset;
359};
360
361static struct tegra_gpio_soc_config tegra20_gpio_config = {
362 .bank_stride = 0x80,
363 .upper_offset = 0x800,
364};
365
366static struct tegra_gpio_soc_config tegra30_gpio_config = {
367 .bank_stride = 0x100,
368 .upper_offset = 0x80,
369};
370
371static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
372 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
373 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
374 { },
375};
376
377/* This lock class tells lockdep that GPIO irqs are in a different
378 * category than their parents, so it won't report false recursion.
379 */
380static struct lock_class_key gpio_lock_class;
381
382static int __devinit tegra_gpio_probe(struct platform_device *pdev)
383{
384 const struct of_device_id *match;
385 struct tegra_gpio_soc_config *config;
386 int irq_base;
387 struct resource *res;
388 struct tegra_gpio_bank *bank;
389 int gpio;
390 int i;
391 int j;
392
393 match = of_match_device(tegra_gpio_of_match, &pdev->dev);
394 if (match)
395 config = (struct tegra_gpio_soc_config *)match->data;
396 else
397 config = &tegra20_gpio_config;
398
399 tegra_gpio_bank_stride = config->bank_stride;
400 tegra_gpio_upper_offset = config->upper_offset;
401
402 for (;;) {
403 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
404 if (!res)
405 break;
406 tegra_gpio_bank_count++;
407 }
408 if (!tegra_gpio_bank_count) {
409 dev_err(&pdev->dev, "Missing IRQ resource\n");
410 return -ENODEV;
411 }
412
413 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
414
415 tegra_gpio_banks = devm_kzalloc(&pdev->dev,
416 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
417 GFP_KERNEL);
418 if (!tegra_gpio_banks) {
419 dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
420 return -ENODEV;
421 }
422
423 irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0);
424 if (irq_base < 0) {
425 dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n");
426 return -ENODEV;
427 }
428 irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
429 tegra_gpio_chip.ngpio, irq_base, 0,
430 &irq_domain_simple_ops, NULL);
431
432 for (i = 0; i < tegra_gpio_bank_count; i++) {
433 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
434 if (!res) {
435 dev_err(&pdev->dev, "Missing IRQ resource\n");
436 return -ENODEV;
437 }
438
439 bank = &tegra_gpio_banks[i];
440 bank->bank = i;
441 bank->irq = res->start;
442 }
443
444 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
445 if (!res) {
446 dev_err(&pdev->dev, "Missing MEM resource\n");
447 return -ENODEV;
448 }
449
450 regs = devm_request_and_ioremap(&pdev->dev, res);
451 if (!regs) {
452 dev_err(&pdev->dev, "Couldn't ioremap regs\n");
453 return -ENODEV;
454 }
455
456 for (i = 0; i < tegra_gpio_bank_count; i++) {
457 for (j = 0; j < 4; j++) {
458 int gpio = tegra_gpio_compose(i, j, 0);
459 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
460 }
461 }
462
463#ifdef CONFIG_OF_GPIO
464 tegra_gpio_chip.of_node = pdev->dev.of_node;
465#endif
466
467 gpiochip_add(&tegra_gpio_chip);
468
469 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
470 int irq = irq_find_mapping(irq_domain, gpio);
471 /* No validity check; all Tegra GPIOs are valid IRQs */
472
473 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
474
475 irq_set_lockdep_class(irq, &gpio_lock_class);
476 irq_set_chip_data(irq, bank);
477 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
478 handle_simple_irq);
479 set_irq_flags(irq, IRQF_VALID);
480 }
481
482 for (i = 0; i < tegra_gpio_bank_count; i++) {
483 bank = &tegra_gpio_banks[i];
484
485 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
486 irq_set_handler_data(bank->irq, bank);
487
488 for (j = 0; j < 4; j++)
489 spin_lock_init(&bank->lvl_lock[j]);
490 }
491
492 return 0;
493}
494
495static struct platform_driver tegra_gpio_driver = {
496 .driver = {
497 .name = "tegra-gpio",
498 .owner = THIS_MODULE,
499 .of_match_table = tegra_gpio_of_match,
500 },
501 .probe = tegra_gpio_probe,
502};
503
504static int __init tegra_gpio_init(void)
505{
506 return platform_driver_register(&tegra_gpio_driver);
507}
508postcore_initcall(tegra_gpio_init);
509
510#ifdef CONFIG_DEBUG_FS
511
512#include <linux/debugfs.h>
513#include <linux/seq_file.h>
514
515static int dbg_gpio_show(struct seq_file *s, void *unused)
516{
517 int i;
518 int j;
519
520 for (i = 0; i < tegra_gpio_bank_count; i++) {
521 for (j = 0; j < 4; j++) {
522 int gpio = tegra_gpio_compose(i, j, 0);
523 seq_printf(s,
524 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
525 i, j,
526 tegra_gpio_readl(GPIO_CNF(gpio)),
527 tegra_gpio_readl(GPIO_OE(gpio)),
528 tegra_gpio_readl(GPIO_OUT(gpio)),
529 tegra_gpio_readl(GPIO_IN(gpio)),
530 tegra_gpio_readl(GPIO_INT_STA(gpio)),
531 tegra_gpio_readl(GPIO_INT_ENB(gpio)),
532 tegra_gpio_readl(GPIO_INT_LVL(gpio)));
533 }
534 }
535 return 0;
536}
537
538static int dbg_gpio_open(struct inode *inode, struct file *file)
539{
540 return single_open(file, dbg_gpio_show, &inode->i_private);
541}
542
543static const struct file_operations debug_fops = {
544 .open = dbg_gpio_open,
545 .read = seq_read,
546 .llseek = seq_lseek,
547 .release = single_release,
548};
549
550static int __init tegra_gpio_debuginit(void)
551{
552 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
553 NULL, NULL, &debug_fops);
554 return 0;
555}
556late_initcall(tegra_gpio_debuginit);
557#endif
1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/of_device.h>
27#include <linux/platform_device.h>
28#include <linux/module.h>
29#include <linux/irqdomain.h>
30#include <linux/irqchip/chained_irq.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pm.h>
33
34#define GPIO_BANK(x) ((x) >> 5)
35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
36#define GPIO_BIT(x) ((x) & 0x7)
37
38#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
39 GPIO_PORT(x) * 4)
40
41#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
51
52#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
59
60#define GPIO_INT_LVL_MASK 0x010101
61#define GPIO_INT_LVL_EDGE_RISING 0x000101
62#define GPIO_INT_LVL_EDGE_FALLING 0x000100
63#define GPIO_INT_LVL_EDGE_BOTH 0x010100
64#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65#define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
67struct tegra_gpio_info;
68
69struct tegra_gpio_bank {
70 unsigned int bank;
71 unsigned int irq;
72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74#ifdef CONFIG_PM_SLEEP
75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
80 u32 wake_enb[4];
81 u32 dbc_enb[4];
82#endif
83 u32 dbc_cnt[4];
84 struct tegra_gpio_info *tgi;
85};
86
87struct tegra_gpio_soc_config {
88 bool debounce_supported;
89 u32 bank_stride;
90 u32 upper_offset;
91};
92
93struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
101 u32 bank_count;
102};
103
104static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
105 u32 val, u32 reg)
106{
107 __raw_writel(val, tgi->regs + reg);
108}
109
110static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
111{
112 return __raw_readl(tgi->regs + reg);
113}
114
115static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
116 unsigned int bit)
117{
118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
119}
120
121static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
122 unsigned int gpio, u32 value)
123{
124 u32 val;
125
126 val = 0x100 << GPIO_BIT(gpio);
127 if (value)
128 val |= 1 << GPIO_BIT(gpio);
129 tegra_gpio_writel(tgi, val, reg);
130}
131
132static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
133{
134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
135}
136
137static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
138{
139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
140}
141
142static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
143{
144 return pinctrl_gpio_request(offset);
145}
146
147static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
148{
149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150
151 pinctrl_gpio_free(offset);
152 tegra_gpio_disable(tgi, offset);
153}
154
155static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
156 int value)
157{
158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
159
160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
161}
162
163static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
164{
165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
166 unsigned int bval = BIT(GPIO_BIT(offset));
167
168 /* If gpio is in output mode then read from the out value */
169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
170 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
171
172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
173}
174
175static int tegra_gpio_direction_input(struct gpio_chip *chip,
176 unsigned int offset)
177{
178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
179
180 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
181 tegra_gpio_enable(tgi, offset);
182 return 0;
183}
184
185static int tegra_gpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset,
187 int value)
188{
189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
190
191 tegra_gpio_set(chip, offset, value);
192 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
193 tegra_gpio_enable(tgi, offset);
194 return 0;
195}
196
197static int tegra_gpio_get_direction(struct gpio_chip *chip,
198 unsigned int offset)
199{
200 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
201 u32 pin_mask = BIT(GPIO_BIT(offset));
202 u32 cnf, oe;
203
204 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
205 if (!(cnf & pin_mask))
206 return -EINVAL;
207
208 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
209
210 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN;
211}
212
213static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
214 unsigned int debounce)
215{
216 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
217 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
218 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
219 unsigned long flags;
220 unsigned int port;
221
222 if (!debounce_ms) {
223 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
224 offset, 0);
225 return 0;
226 }
227
228 debounce_ms = min(debounce_ms, 255U);
229 port = GPIO_PORT(offset);
230
231 /* There is only one debounce count register per port and hence
232 * set the maximum of current and requested debounce time.
233 */
234 spin_lock_irqsave(&bank->dbc_lock[port], flags);
235 if (bank->dbc_cnt[port] < debounce_ms) {
236 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
237 bank->dbc_cnt[port] = debounce_ms;
238 }
239 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
240
241 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
242
243 return 0;
244}
245
246static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
247 unsigned long config)
248{
249 u32 debounce;
250
251 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
252 return -ENOTSUPP;
253
254 debounce = pinconf_to_config_argument(config);
255 return tegra_gpio_set_debounce(chip, offset, debounce);
256}
257
258static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
259{
260 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
261
262 return irq_find_mapping(tgi->irq_domain, offset);
263}
264
265static void tegra_gpio_irq_ack(struct irq_data *d)
266{
267 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
268 struct tegra_gpio_info *tgi = bank->tgi;
269 unsigned int gpio = d->hwirq;
270
271 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
272}
273
274static void tegra_gpio_irq_mask(struct irq_data *d)
275{
276 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
277 struct tegra_gpio_info *tgi = bank->tgi;
278 unsigned int gpio = d->hwirq;
279
280 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
281}
282
283static void tegra_gpio_irq_unmask(struct irq_data *d)
284{
285 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
286 struct tegra_gpio_info *tgi = bank->tgi;
287 unsigned int gpio = d->hwirq;
288
289 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
290}
291
292static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
293{
294 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
296 struct tegra_gpio_info *tgi = bank->tgi;
297 unsigned long flags;
298 u32 val;
299 int ret;
300
301 switch (type & IRQ_TYPE_SENSE_MASK) {
302 case IRQ_TYPE_EDGE_RISING:
303 lvl_type = GPIO_INT_LVL_EDGE_RISING;
304 break;
305
306 case IRQ_TYPE_EDGE_FALLING:
307 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
308 break;
309
310 case IRQ_TYPE_EDGE_BOTH:
311 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
312 break;
313
314 case IRQ_TYPE_LEVEL_HIGH:
315 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
316 break;
317
318 case IRQ_TYPE_LEVEL_LOW:
319 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
320 break;
321
322 default:
323 return -EINVAL;
324 }
325
326 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
327 if (ret) {
328 dev_err(tgi->dev,
329 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
330 return ret;
331 }
332
333 spin_lock_irqsave(&bank->lvl_lock[port], flags);
334
335 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
336 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
337 val |= lvl_type << GPIO_BIT(gpio);
338 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
339
340 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
341
342 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
343 tegra_gpio_enable(tgi, gpio);
344
345 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
346 irq_set_handler_locked(d, handle_level_irq);
347 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
348 irq_set_handler_locked(d, handle_edge_irq);
349
350 return 0;
351}
352
353static void tegra_gpio_irq_shutdown(struct irq_data *d)
354{
355 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
356 struct tegra_gpio_info *tgi = bank->tgi;
357 unsigned int gpio = d->hwirq;
358
359 gpiochip_unlock_as_irq(&tgi->gc, gpio);
360}
361
362static void tegra_gpio_irq_handler(struct irq_desc *desc)
363{
364 unsigned int port, pin, gpio;
365 bool unmasked = false;
366 u32 lvl;
367 unsigned long sta;
368 struct irq_chip *chip = irq_desc_get_chip(desc);
369 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
370 struct tegra_gpio_info *tgi = bank->tgi;
371
372 chained_irq_enter(chip, desc);
373
374 for (port = 0; port < 4; port++) {
375 gpio = tegra_gpio_compose(bank->bank, port, 0);
376 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
377 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
378 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
379
380 for_each_set_bit(pin, &sta, 8) {
381 tegra_gpio_writel(tgi, 1 << pin,
382 GPIO_INT_CLR(tgi, gpio));
383
384 /* if gpio is edge triggered, clear condition
385 * before executing the handler so that we don't
386 * miss edges
387 */
388 if (!unmasked && lvl & (0x100 << pin)) {
389 unmasked = true;
390 chained_irq_exit(chip, desc);
391 }
392
393 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
394 gpio + pin));
395 }
396 }
397
398 if (!unmasked)
399 chained_irq_exit(chip, desc);
400
401}
402
403#ifdef CONFIG_PM_SLEEP
404static int tegra_gpio_resume(struct device *dev)
405{
406 struct platform_device *pdev = to_platform_device(dev);
407 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
408 unsigned long flags;
409 unsigned int b, p;
410
411 local_irq_save(flags);
412
413 for (b = 0; b < tgi->bank_count; b++) {
414 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
415
416 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
417 unsigned int gpio = (b << 5) | (p << 3);
418
419 tegra_gpio_writel(tgi, bank->cnf[p],
420 GPIO_CNF(tgi, gpio));
421
422 if (tgi->soc->debounce_supported) {
423 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
424 GPIO_DBC_CNT(tgi, gpio));
425 tegra_gpio_writel(tgi, bank->dbc_enb[p],
426 GPIO_MSK_DBC_EN(tgi, gpio));
427 }
428
429 tegra_gpio_writel(tgi, bank->out[p],
430 GPIO_OUT(tgi, gpio));
431 tegra_gpio_writel(tgi, bank->oe[p],
432 GPIO_OE(tgi, gpio));
433 tegra_gpio_writel(tgi, bank->int_lvl[p],
434 GPIO_INT_LVL(tgi, gpio));
435 tegra_gpio_writel(tgi, bank->int_enb[p],
436 GPIO_INT_ENB(tgi, gpio));
437 }
438 }
439
440 local_irq_restore(flags);
441 return 0;
442}
443
444static int tegra_gpio_suspend(struct device *dev)
445{
446 struct platform_device *pdev = to_platform_device(dev);
447 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
448 unsigned long flags;
449 unsigned int b, p;
450
451 local_irq_save(flags);
452 for (b = 0; b < tgi->bank_count; b++) {
453 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
454
455 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
456 unsigned int gpio = (b << 5) | (p << 3);
457
458 bank->cnf[p] = tegra_gpio_readl(tgi,
459 GPIO_CNF(tgi, gpio));
460 bank->out[p] = tegra_gpio_readl(tgi,
461 GPIO_OUT(tgi, gpio));
462 bank->oe[p] = tegra_gpio_readl(tgi,
463 GPIO_OE(tgi, gpio));
464 if (tgi->soc->debounce_supported) {
465 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
466 GPIO_MSK_DBC_EN(tgi, gpio));
467 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
468 bank->dbc_enb[p];
469 }
470
471 bank->int_enb[p] = tegra_gpio_readl(tgi,
472 GPIO_INT_ENB(tgi, gpio));
473 bank->int_lvl[p] = tegra_gpio_readl(tgi,
474 GPIO_INT_LVL(tgi, gpio));
475
476 /* Enable gpio irq for wake up source */
477 tegra_gpio_writel(tgi, bank->wake_enb[p],
478 GPIO_INT_ENB(tgi, gpio));
479 }
480 }
481 local_irq_restore(flags);
482 return 0;
483}
484
485static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
486{
487 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
488 unsigned int gpio = d->hwirq;
489 u32 port, bit, mask;
490
491 port = GPIO_PORT(gpio);
492 bit = GPIO_BIT(gpio);
493 mask = BIT(bit);
494
495 if (enable)
496 bank->wake_enb[port] |= mask;
497 else
498 bank->wake_enb[port] &= ~mask;
499
500 return irq_set_irq_wake(bank->irq, enable);
501}
502#endif
503
504#ifdef CONFIG_DEBUG_FS
505
506#include <linux/debugfs.h>
507#include <linux/seq_file.h>
508
509static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
510{
511 struct tegra_gpio_info *tgi = s->private;
512 unsigned int i, j;
513
514 for (i = 0; i < tgi->bank_count; i++) {
515 for (j = 0; j < 4; j++) {
516 unsigned int gpio = tegra_gpio_compose(i, j, 0);
517
518 seq_printf(s,
519 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
520 i, j,
521 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
522 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
523 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
524 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
525 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
526 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
527 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
528 }
529 }
530 return 0;
531}
532
533DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
534
535static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
536{
537 (void) debugfs_create_file("tegra_gpio", 0444,
538 NULL, tgi, &tegra_dbg_gpio_fops);
539}
540
541#else
542
543static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
544{
545}
546
547#endif
548
549static const struct dev_pm_ops tegra_gpio_pm_ops = {
550 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
551};
552
553/*
554 * This lock class tells lockdep that GPIO irqs are in a different category
555 * than their parents, so it won't report false recursion.
556 */
557static struct lock_class_key gpio_lock_class;
558static struct lock_class_key gpio_request_class;
559
560static int tegra_gpio_probe(struct platform_device *pdev)
561{
562 struct tegra_gpio_info *tgi;
563 struct resource *res;
564 struct tegra_gpio_bank *bank;
565 unsigned int gpio, i, j;
566 int ret;
567
568 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
569 if (!tgi)
570 return -ENODEV;
571
572 tgi->soc = of_device_get_match_data(&pdev->dev);
573 tgi->dev = &pdev->dev;
574
575 ret = platform_irq_count(pdev);
576 if (ret < 0)
577 return ret;
578
579 tgi->bank_count = ret;
580
581 if (!tgi->bank_count) {
582 dev_err(&pdev->dev, "Missing IRQ resource\n");
583 return -ENODEV;
584 }
585
586 tgi->gc.label = "tegra-gpio";
587 tgi->gc.request = tegra_gpio_request;
588 tgi->gc.free = tegra_gpio_free;
589 tgi->gc.direction_input = tegra_gpio_direction_input;
590 tgi->gc.get = tegra_gpio_get;
591 tgi->gc.direction_output = tegra_gpio_direction_output;
592 tgi->gc.set = tegra_gpio_set;
593 tgi->gc.get_direction = tegra_gpio_get_direction;
594 tgi->gc.to_irq = tegra_gpio_to_irq;
595 tgi->gc.base = 0;
596 tgi->gc.ngpio = tgi->bank_count * 32;
597 tgi->gc.parent = &pdev->dev;
598 tgi->gc.of_node = pdev->dev.of_node;
599
600 tgi->ic.name = "GPIO";
601 tgi->ic.irq_ack = tegra_gpio_irq_ack;
602 tgi->ic.irq_mask = tegra_gpio_irq_mask;
603 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
604 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
605 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
606#ifdef CONFIG_PM_SLEEP
607 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
608#endif
609
610 platform_set_drvdata(pdev, tgi);
611
612 if (tgi->soc->debounce_supported)
613 tgi->gc.set_config = tegra_gpio_set_config;
614
615 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
616 sizeof(*tgi->bank_info), GFP_KERNEL);
617 if (!tgi->bank_info)
618 return -ENOMEM;
619
620 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
621 tgi->gc.ngpio,
622 &irq_domain_simple_ops, NULL);
623 if (!tgi->irq_domain)
624 return -ENODEV;
625
626 for (i = 0; i < tgi->bank_count; i++) {
627 ret = platform_get_irq(pdev, i);
628 if (ret < 0) {
629 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
630 return ret;
631 }
632
633 bank = &tgi->bank_info[i];
634 bank->bank = i;
635 bank->irq = ret;
636 bank->tgi = tgi;
637 }
638
639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
641 if (IS_ERR(tgi->regs))
642 return PTR_ERR(tgi->regs);
643
644 for (i = 0; i < tgi->bank_count; i++) {
645 for (j = 0; j < 4; j++) {
646 int gpio = tegra_gpio_compose(i, j, 0);
647
648 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
649 }
650 }
651
652 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
653 if (ret < 0) {
654 irq_domain_remove(tgi->irq_domain);
655 return ret;
656 }
657
658 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
659 int irq = irq_create_mapping(tgi->irq_domain, gpio);
660 /* No validity check; all Tegra GPIOs are valid IRQs */
661
662 bank = &tgi->bank_info[GPIO_BANK(gpio)];
663
664 irq_set_lockdep_class(irq, &gpio_lock_class,
665 &gpio_request_class);
666 irq_set_chip_data(irq, bank);
667 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
668 }
669
670 for (i = 0; i < tgi->bank_count; i++) {
671 bank = &tgi->bank_info[i];
672
673 irq_set_chained_handler_and_data(bank->irq,
674 tegra_gpio_irq_handler, bank);
675
676 for (j = 0; j < 4; j++) {
677 spin_lock_init(&bank->lvl_lock[j]);
678 spin_lock_init(&bank->dbc_lock[j]);
679 }
680 }
681
682 tegra_gpio_debuginit(tgi);
683
684 return 0;
685}
686
687static const struct tegra_gpio_soc_config tegra20_gpio_config = {
688 .bank_stride = 0x80,
689 .upper_offset = 0x800,
690};
691
692static const struct tegra_gpio_soc_config tegra30_gpio_config = {
693 .bank_stride = 0x100,
694 .upper_offset = 0x80,
695};
696
697static const struct tegra_gpio_soc_config tegra210_gpio_config = {
698 .debounce_supported = true,
699 .bank_stride = 0x100,
700 .upper_offset = 0x80,
701};
702
703static const struct of_device_id tegra_gpio_of_match[] = {
704 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
705 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
706 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
707 { },
708};
709
710static struct platform_driver tegra_gpio_driver = {
711 .driver = {
712 .name = "tegra-gpio",
713 .pm = &tegra_gpio_pm_ops,
714 .of_match_table = tegra_gpio_of_match,
715 },
716 .probe = tegra_gpio_probe,
717};
718
719static int __init tegra_gpio_init(void)
720{
721 return platform_driver_register(&tegra_gpio_driver);
722}
723postcore_initcall(tegra_gpio_init);