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1/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33#include <linux/slab.h>
34#include <linux/module.h>
35#include <linux/pm_domain.h>
36
37struct sh_tmu_priv {
38 void __iomem *mapbase;
39 struct clk *clk;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
42 unsigned long rate;
43 unsigned long periodic;
44 struct clock_event_device ced;
45 struct clocksource cs;
46};
47
48static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
49
50#define TSTR -1 /* shared register */
51#define TCOR 0 /* channel register */
52#define TCNT 1 /* channel register */
53#define TCR 2 /* channel register */
54
55static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
56{
57 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
58 void __iomem *base = p->mapbase;
59 unsigned long offs;
60
61 if (reg_nr == TSTR)
62 return ioread8(base - cfg->channel_offset);
63
64 offs = reg_nr << 2;
65
66 if (reg_nr == TCR)
67 return ioread16(base + offs);
68 else
69 return ioread32(base + offs);
70}
71
72static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
73 unsigned long value)
74{
75 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
76 void __iomem *base = p->mapbase;
77 unsigned long offs;
78
79 if (reg_nr == TSTR) {
80 iowrite8(value, base - cfg->channel_offset);
81 return;
82 }
83
84 offs = reg_nr << 2;
85
86 if (reg_nr == TCR)
87 iowrite16(value, base + offs);
88 else
89 iowrite32(value, base + offs);
90}
91
92static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
93{
94 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
95 unsigned long flags, value;
96
97 /* start stop register shared by multiple timer channels */
98 raw_spin_lock_irqsave(&sh_tmu_lock, flags);
99 value = sh_tmu_read(p, TSTR);
100
101 if (start)
102 value |= 1 << cfg->timer_bit;
103 else
104 value &= ~(1 << cfg->timer_bit);
105
106 sh_tmu_write(p, TSTR, value);
107 raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
108}
109
110static int sh_tmu_enable(struct sh_tmu_priv *p)
111{
112 int ret;
113
114 /* enable clock */
115 ret = clk_enable(p->clk);
116 if (ret) {
117 dev_err(&p->pdev->dev, "cannot enable clock\n");
118 return ret;
119 }
120
121 /* make sure channel is disabled */
122 sh_tmu_start_stop_ch(p, 0);
123
124 /* maximum timeout */
125 sh_tmu_write(p, TCOR, 0xffffffff);
126 sh_tmu_write(p, TCNT, 0xffffffff);
127
128 /* configure channel to parent clock / 4, irq off */
129 p->rate = clk_get_rate(p->clk) / 4;
130 sh_tmu_write(p, TCR, 0x0000);
131
132 /* enable channel */
133 sh_tmu_start_stop_ch(p, 1);
134
135 return 0;
136}
137
138static void sh_tmu_disable(struct sh_tmu_priv *p)
139{
140 /* disable channel */
141 sh_tmu_start_stop_ch(p, 0);
142
143 /* disable interrupts in TMU block */
144 sh_tmu_write(p, TCR, 0x0000);
145
146 /* stop clock */
147 clk_disable(p->clk);
148}
149
150static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
151 int periodic)
152{
153 /* stop timer */
154 sh_tmu_start_stop_ch(p, 0);
155
156 /* acknowledge interrupt */
157 sh_tmu_read(p, TCR);
158
159 /* enable interrupt */
160 sh_tmu_write(p, TCR, 0x0020);
161
162 /* reload delta value in case of periodic timer */
163 if (periodic)
164 sh_tmu_write(p, TCOR, delta);
165 else
166 sh_tmu_write(p, TCOR, 0xffffffff);
167
168 sh_tmu_write(p, TCNT, delta);
169
170 /* start timer */
171 sh_tmu_start_stop_ch(p, 1);
172}
173
174static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
175{
176 struct sh_tmu_priv *p = dev_id;
177
178 /* disable or acknowledge interrupt */
179 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
180 sh_tmu_write(p, TCR, 0x0000);
181 else
182 sh_tmu_write(p, TCR, 0x0020);
183
184 /* notify clockevent layer */
185 p->ced.event_handler(&p->ced);
186 return IRQ_HANDLED;
187}
188
189static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
190{
191 return container_of(cs, struct sh_tmu_priv, cs);
192}
193
194static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
195{
196 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
197
198 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
199}
200
201static int sh_tmu_clocksource_enable(struct clocksource *cs)
202{
203 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
204 int ret;
205
206 ret = sh_tmu_enable(p);
207 if (!ret)
208 __clocksource_updatefreq_hz(cs, p->rate);
209 return ret;
210}
211
212static void sh_tmu_clocksource_disable(struct clocksource *cs)
213{
214 sh_tmu_disable(cs_to_sh_tmu(cs));
215}
216
217static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
218 char *name, unsigned long rating)
219{
220 struct clocksource *cs = &p->cs;
221
222 cs->name = name;
223 cs->rating = rating;
224 cs->read = sh_tmu_clocksource_read;
225 cs->enable = sh_tmu_clocksource_enable;
226 cs->disable = sh_tmu_clocksource_disable;
227 cs->mask = CLOCKSOURCE_MASK(32);
228 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
229
230 dev_info(&p->pdev->dev, "used as clock source\n");
231
232 /* Register with dummy 1 Hz value, gets updated in ->enable() */
233 clocksource_register_hz(cs, 1);
234 return 0;
235}
236
237static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
238{
239 return container_of(ced, struct sh_tmu_priv, ced);
240}
241
242static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
243{
244 struct clock_event_device *ced = &p->ced;
245
246 sh_tmu_enable(p);
247
248 clockevents_config(ced, p->rate);
249
250 if (periodic) {
251 p->periodic = (p->rate + HZ/2) / HZ;
252 sh_tmu_set_next(p, p->periodic, 1);
253 }
254}
255
256static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
257 struct clock_event_device *ced)
258{
259 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
260 int disabled = 0;
261
262 /* deal with old setting first */
263 switch (ced->mode) {
264 case CLOCK_EVT_MODE_PERIODIC:
265 case CLOCK_EVT_MODE_ONESHOT:
266 sh_tmu_disable(p);
267 disabled = 1;
268 break;
269 default:
270 break;
271 }
272
273 switch (mode) {
274 case CLOCK_EVT_MODE_PERIODIC:
275 dev_info(&p->pdev->dev, "used for periodic clock events\n");
276 sh_tmu_clock_event_start(p, 1);
277 break;
278 case CLOCK_EVT_MODE_ONESHOT:
279 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
280 sh_tmu_clock_event_start(p, 0);
281 break;
282 case CLOCK_EVT_MODE_UNUSED:
283 if (!disabled)
284 sh_tmu_disable(p);
285 break;
286 case CLOCK_EVT_MODE_SHUTDOWN:
287 default:
288 break;
289 }
290}
291
292static int sh_tmu_clock_event_next(unsigned long delta,
293 struct clock_event_device *ced)
294{
295 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
296
297 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
298
299 /* program new delta value */
300 sh_tmu_set_next(p, delta, 0);
301 return 0;
302}
303
304static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
305 char *name, unsigned long rating)
306{
307 struct clock_event_device *ced = &p->ced;
308 int ret;
309
310 memset(ced, 0, sizeof(*ced));
311
312 ced->name = name;
313 ced->features = CLOCK_EVT_FEAT_PERIODIC;
314 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
315 ced->rating = rating;
316 ced->cpumask = cpumask_of(0);
317 ced->set_next_event = sh_tmu_clock_event_next;
318 ced->set_mode = sh_tmu_clock_event_mode;
319
320 dev_info(&p->pdev->dev, "used for clock events\n");
321
322 clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
323
324 ret = setup_irq(p->irqaction.irq, &p->irqaction);
325 if (ret) {
326 dev_err(&p->pdev->dev, "failed to request irq %d\n",
327 p->irqaction.irq);
328 return;
329 }
330}
331
332static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
333 unsigned long clockevent_rating,
334 unsigned long clocksource_rating)
335{
336 if (clockevent_rating)
337 sh_tmu_register_clockevent(p, name, clockevent_rating);
338 else if (clocksource_rating)
339 sh_tmu_register_clocksource(p, name, clocksource_rating);
340
341 return 0;
342}
343
344static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
345{
346 struct sh_timer_config *cfg = pdev->dev.platform_data;
347 struct resource *res;
348 int irq, ret;
349 ret = -ENXIO;
350
351 memset(p, 0, sizeof(*p));
352 p->pdev = pdev;
353
354 if (!cfg) {
355 dev_err(&p->pdev->dev, "missing platform data\n");
356 goto err0;
357 }
358
359 platform_set_drvdata(pdev, p);
360
361 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
362 if (!res) {
363 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
364 goto err0;
365 }
366
367 irq = platform_get_irq(p->pdev, 0);
368 if (irq < 0) {
369 dev_err(&p->pdev->dev, "failed to get irq\n");
370 goto err0;
371 }
372
373 /* map memory, let mapbase point to our channel */
374 p->mapbase = ioremap_nocache(res->start, resource_size(res));
375 if (p->mapbase == NULL) {
376 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
377 goto err0;
378 }
379
380 /* setup data for setup_irq() (too early for request_irq()) */
381 p->irqaction.name = dev_name(&p->pdev->dev);
382 p->irqaction.handler = sh_tmu_interrupt;
383 p->irqaction.dev_id = p;
384 p->irqaction.irq = irq;
385 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
386 IRQF_IRQPOLL | IRQF_NOBALANCING;
387
388 /* get hold of clock */
389 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
390 if (IS_ERR(p->clk)) {
391 dev_err(&p->pdev->dev, "cannot get clock\n");
392 ret = PTR_ERR(p->clk);
393 goto err1;
394 }
395
396 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
397 cfg->clockevent_rating,
398 cfg->clocksource_rating);
399 err1:
400 iounmap(p->mapbase);
401 err0:
402 return ret;
403}
404
405static int __devinit sh_tmu_probe(struct platform_device *pdev)
406{
407 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
408 int ret;
409
410 if (!is_early_platform_device(pdev))
411 pm_genpd_dev_always_on(&pdev->dev, true);
412
413 if (p) {
414 dev_info(&pdev->dev, "kept as earlytimer\n");
415 return 0;
416 }
417
418 p = kmalloc(sizeof(*p), GFP_KERNEL);
419 if (p == NULL) {
420 dev_err(&pdev->dev, "failed to allocate driver data\n");
421 return -ENOMEM;
422 }
423
424 ret = sh_tmu_setup(p, pdev);
425 if (ret) {
426 kfree(p);
427 platform_set_drvdata(pdev, NULL);
428 }
429 return ret;
430}
431
432static int __devexit sh_tmu_remove(struct platform_device *pdev)
433{
434 return -EBUSY; /* cannot unregister clockevent and clocksource */
435}
436
437static struct platform_driver sh_tmu_device_driver = {
438 .probe = sh_tmu_probe,
439 .remove = __devexit_p(sh_tmu_remove),
440 .driver = {
441 .name = "sh_tmu",
442 }
443};
444
445static int __init sh_tmu_init(void)
446{
447 return platform_driver_register(&sh_tmu_device_driver);
448}
449
450static void __exit sh_tmu_exit(void)
451{
452 platform_driver_unregister(&sh_tmu_device_driver);
453}
454
455early_platform_init("earlytimer", &sh_tmu_device_driver);
456module_init(sh_tmu_init);
457module_exit(sh_tmu_exit);
458
459MODULE_AUTHOR("Magnus Damm");
460MODULE_DESCRIPTION("SuperH TMU Timer Driver");
461MODULE_LICENSE("GPL v2");
1/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pm_domain.h>
30#include <linux/pm_runtime.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35enum sh_tmu_model {
36 SH_TMU,
37 SH_TMU_SH3,
38};
39
40struct sh_tmu_device;
41
42struct sh_tmu_channel {
43 struct sh_tmu_device *tmu;
44 unsigned int index;
45
46 void __iomem *base;
47 int irq;
48
49 unsigned long periodic;
50 struct clock_event_device ced;
51 struct clocksource cs;
52 bool cs_enabled;
53 unsigned int enable_count;
54};
55
56struct sh_tmu_device {
57 struct platform_device *pdev;
58
59 void __iomem *mapbase;
60 struct clk *clk;
61 unsigned long rate;
62
63 enum sh_tmu_model model;
64
65 raw_spinlock_t lock; /* Protect the shared start/stop register */
66
67 struct sh_tmu_channel *channels;
68 unsigned int num_channels;
69
70 bool has_clockevent;
71 bool has_clocksource;
72};
73
74#define TSTR -1 /* shared register */
75#define TCOR 0 /* channel register */
76#define TCNT 1 /* channel register */
77#define TCR 2 /* channel register */
78
79#define TCR_UNF (1 << 8)
80#define TCR_UNIE (1 << 5)
81#define TCR_TPSC_CLK4 (0 << 0)
82#define TCR_TPSC_CLK16 (1 << 0)
83#define TCR_TPSC_CLK64 (2 << 0)
84#define TCR_TPSC_CLK256 (3 << 0)
85#define TCR_TPSC_CLK1024 (4 << 0)
86#define TCR_TPSC_MASK (7 << 0)
87
88static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
89{
90 unsigned long offs;
91
92 if (reg_nr == TSTR) {
93 switch (ch->tmu->model) {
94 case SH_TMU_SH3:
95 return ioread8(ch->tmu->mapbase + 2);
96 case SH_TMU:
97 return ioread8(ch->tmu->mapbase + 4);
98 }
99 }
100
101 offs = reg_nr << 2;
102
103 if (reg_nr == TCR)
104 return ioread16(ch->base + offs);
105 else
106 return ioread32(ch->base + offs);
107}
108
109static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
110 unsigned long value)
111{
112 unsigned long offs;
113
114 if (reg_nr == TSTR) {
115 switch (ch->tmu->model) {
116 case SH_TMU_SH3:
117 return iowrite8(value, ch->tmu->mapbase + 2);
118 case SH_TMU:
119 return iowrite8(value, ch->tmu->mapbase + 4);
120 }
121 }
122
123 offs = reg_nr << 2;
124
125 if (reg_nr == TCR)
126 iowrite16(value, ch->base + offs);
127 else
128 iowrite32(value, ch->base + offs);
129}
130
131static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
132{
133 unsigned long flags, value;
134
135 /* start stop register shared by multiple timer channels */
136 raw_spin_lock_irqsave(&ch->tmu->lock, flags);
137 value = sh_tmu_read(ch, TSTR);
138
139 if (start)
140 value |= 1 << ch->index;
141 else
142 value &= ~(1 << ch->index);
143
144 sh_tmu_write(ch, TSTR, value);
145 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
146}
147
148static int __sh_tmu_enable(struct sh_tmu_channel *ch)
149{
150 int ret;
151
152 /* enable clock */
153 ret = clk_enable(ch->tmu->clk);
154 if (ret) {
155 dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
156 ch->index);
157 return ret;
158 }
159
160 /* make sure channel is disabled */
161 sh_tmu_start_stop_ch(ch, 0);
162
163 /* maximum timeout */
164 sh_tmu_write(ch, TCOR, 0xffffffff);
165 sh_tmu_write(ch, TCNT, 0xffffffff);
166
167 /* configure channel to parent clock / 4, irq off */
168 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
169
170 /* enable channel */
171 sh_tmu_start_stop_ch(ch, 1);
172
173 return 0;
174}
175
176static int sh_tmu_enable(struct sh_tmu_channel *ch)
177{
178 if (ch->enable_count++ > 0)
179 return 0;
180
181 pm_runtime_get_sync(&ch->tmu->pdev->dev);
182 dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
183
184 return __sh_tmu_enable(ch);
185}
186
187static void __sh_tmu_disable(struct sh_tmu_channel *ch)
188{
189 /* disable channel */
190 sh_tmu_start_stop_ch(ch, 0);
191
192 /* disable interrupts in TMU block */
193 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
194
195 /* stop clock */
196 clk_disable(ch->tmu->clk);
197}
198
199static void sh_tmu_disable(struct sh_tmu_channel *ch)
200{
201 if (WARN_ON(ch->enable_count == 0))
202 return;
203
204 if (--ch->enable_count > 0)
205 return;
206
207 __sh_tmu_disable(ch);
208
209 dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
210 pm_runtime_put(&ch->tmu->pdev->dev);
211}
212
213static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
214 int periodic)
215{
216 /* stop timer */
217 sh_tmu_start_stop_ch(ch, 0);
218
219 /* acknowledge interrupt */
220 sh_tmu_read(ch, TCR);
221
222 /* enable interrupt */
223 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
224
225 /* reload delta value in case of periodic timer */
226 if (periodic)
227 sh_tmu_write(ch, TCOR, delta);
228 else
229 sh_tmu_write(ch, TCOR, 0xffffffff);
230
231 sh_tmu_write(ch, TCNT, delta);
232
233 /* start timer */
234 sh_tmu_start_stop_ch(ch, 1);
235}
236
237static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
238{
239 struct sh_tmu_channel *ch = dev_id;
240
241 /* disable or acknowledge interrupt */
242 if (clockevent_state_oneshot(&ch->ced))
243 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
244 else
245 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
246
247 /* notify clockevent layer */
248 ch->ced.event_handler(&ch->ced);
249 return IRQ_HANDLED;
250}
251
252static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
253{
254 return container_of(cs, struct sh_tmu_channel, cs);
255}
256
257static u64 sh_tmu_clocksource_read(struct clocksource *cs)
258{
259 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
260
261 return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
262}
263
264static int sh_tmu_clocksource_enable(struct clocksource *cs)
265{
266 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
267 int ret;
268
269 if (WARN_ON(ch->cs_enabled))
270 return 0;
271
272 ret = sh_tmu_enable(ch);
273 if (!ret)
274 ch->cs_enabled = true;
275
276 return ret;
277}
278
279static void sh_tmu_clocksource_disable(struct clocksource *cs)
280{
281 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
282
283 if (WARN_ON(!ch->cs_enabled))
284 return;
285
286 sh_tmu_disable(ch);
287 ch->cs_enabled = false;
288}
289
290static void sh_tmu_clocksource_suspend(struct clocksource *cs)
291{
292 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
293
294 if (!ch->cs_enabled)
295 return;
296
297 if (--ch->enable_count == 0) {
298 __sh_tmu_disable(ch);
299 pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
300 }
301}
302
303static void sh_tmu_clocksource_resume(struct clocksource *cs)
304{
305 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
306
307 if (!ch->cs_enabled)
308 return;
309
310 if (ch->enable_count++ == 0) {
311 pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
312 __sh_tmu_enable(ch);
313 }
314}
315
316static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
317 const char *name)
318{
319 struct clocksource *cs = &ch->cs;
320
321 cs->name = name;
322 cs->rating = 200;
323 cs->read = sh_tmu_clocksource_read;
324 cs->enable = sh_tmu_clocksource_enable;
325 cs->disable = sh_tmu_clocksource_disable;
326 cs->suspend = sh_tmu_clocksource_suspend;
327 cs->resume = sh_tmu_clocksource_resume;
328 cs->mask = CLOCKSOURCE_MASK(32);
329 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
330
331 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
332 ch->index);
333
334 clocksource_register_hz(cs, ch->tmu->rate);
335 return 0;
336}
337
338static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
339{
340 return container_of(ced, struct sh_tmu_channel, ced);
341}
342
343static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
344{
345 sh_tmu_enable(ch);
346
347 if (periodic) {
348 ch->periodic = (ch->tmu->rate + HZ/2) / HZ;
349 sh_tmu_set_next(ch, ch->periodic, 1);
350 }
351}
352
353static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced)
354{
355 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
356
357 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
358 sh_tmu_disable(ch);
359 return 0;
360}
361
362static int sh_tmu_clock_event_set_state(struct clock_event_device *ced,
363 int periodic)
364{
365 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
366
367 /* deal with old setting first */
368 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
369 sh_tmu_disable(ch);
370
371 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n",
372 ch->index, periodic ? "periodic" : "oneshot");
373 sh_tmu_clock_event_start(ch, periodic);
374 return 0;
375}
376
377static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced)
378{
379 return sh_tmu_clock_event_set_state(ced, 0);
380}
381
382static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced)
383{
384 return sh_tmu_clock_event_set_state(ced, 1);
385}
386
387static int sh_tmu_clock_event_next(unsigned long delta,
388 struct clock_event_device *ced)
389{
390 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
391
392 BUG_ON(!clockevent_state_oneshot(ced));
393
394 /* program new delta value */
395 sh_tmu_set_next(ch, delta, 0);
396 return 0;
397}
398
399static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
400{
401 pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
402}
403
404static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
405{
406 pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
407}
408
409static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
410 const char *name)
411{
412 struct clock_event_device *ced = &ch->ced;
413 int ret;
414
415 ced->name = name;
416 ced->features = CLOCK_EVT_FEAT_PERIODIC;
417 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
418 ced->rating = 200;
419 ced->cpumask = cpu_possible_mask;
420 ced->set_next_event = sh_tmu_clock_event_next;
421 ced->set_state_shutdown = sh_tmu_clock_event_shutdown;
422 ced->set_state_periodic = sh_tmu_clock_event_set_periodic;
423 ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot;
424 ced->suspend = sh_tmu_clock_event_suspend;
425 ced->resume = sh_tmu_clock_event_resume;
426
427 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
428 ch->index);
429
430 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff);
431
432 ret = request_irq(ch->irq, sh_tmu_interrupt,
433 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
434 dev_name(&ch->tmu->pdev->dev), ch);
435 if (ret) {
436 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
437 ch->index, ch->irq);
438 return;
439 }
440}
441
442static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
443 bool clockevent, bool clocksource)
444{
445 if (clockevent) {
446 ch->tmu->has_clockevent = true;
447 sh_tmu_register_clockevent(ch, name);
448 } else if (clocksource) {
449 ch->tmu->has_clocksource = true;
450 sh_tmu_register_clocksource(ch, name);
451 }
452
453 return 0;
454}
455
456static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
457 bool clockevent, bool clocksource,
458 struct sh_tmu_device *tmu)
459{
460 /* Skip unused channels. */
461 if (!clockevent && !clocksource)
462 return 0;
463
464 ch->tmu = tmu;
465 ch->index = index;
466
467 if (tmu->model == SH_TMU_SH3)
468 ch->base = tmu->mapbase + 4 + ch->index * 12;
469 else
470 ch->base = tmu->mapbase + 8 + ch->index * 12;
471
472 ch->irq = platform_get_irq(tmu->pdev, index);
473 if (ch->irq < 0) {
474 dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
475 ch->index);
476 return ch->irq;
477 }
478
479 ch->cs_enabled = false;
480 ch->enable_count = 0;
481
482 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
483 clockevent, clocksource);
484}
485
486static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
487{
488 struct resource *res;
489
490 res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
491 if (!res) {
492 dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
493 return -ENXIO;
494 }
495
496 tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
497 if (tmu->mapbase == NULL)
498 return -ENXIO;
499
500 return 0;
501}
502
503static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
504{
505 struct device_node *np = tmu->pdev->dev.of_node;
506
507 tmu->model = SH_TMU;
508 tmu->num_channels = 3;
509
510 of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
511
512 if (tmu->num_channels != 2 && tmu->num_channels != 3) {
513 dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
514 tmu->num_channels);
515 return -EINVAL;
516 }
517
518 return 0;
519}
520
521static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
522{
523 unsigned int i;
524 int ret;
525
526 tmu->pdev = pdev;
527
528 raw_spin_lock_init(&tmu->lock);
529
530 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
531 ret = sh_tmu_parse_dt(tmu);
532 if (ret < 0)
533 return ret;
534 } else if (pdev->dev.platform_data) {
535 const struct platform_device_id *id = pdev->id_entry;
536 struct sh_timer_config *cfg = pdev->dev.platform_data;
537
538 tmu->model = id->driver_data;
539 tmu->num_channels = hweight8(cfg->channels_mask);
540 } else {
541 dev_err(&tmu->pdev->dev, "missing platform data\n");
542 return -ENXIO;
543 }
544
545 /* Get hold of clock. */
546 tmu->clk = clk_get(&tmu->pdev->dev, "fck");
547 if (IS_ERR(tmu->clk)) {
548 dev_err(&tmu->pdev->dev, "cannot get clock\n");
549 return PTR_ERR(tmu->clk);
550 }
551
552 ret = clk_prepare(tmu->clk);
553 if (ret < 0)
554 goto err_clk_put;
555
556 /* Determine clock rate. */
557 ret = clk_enable(tmu->clk);
558 if (ret < 0)
559 goto err_clk_unprepare;
560
561 tmu->rate = clk_get_rate(tmu->clk) / 4;
562 clk_disable(tmu->clk);
563
564 /* Map the memory resource. */
565 ret = sh_tmu_map_memory(tmu);
566 if (ret < 0) {
567 dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
568 goto err_clk_unprepare;
569 }
570
571 /* Allocate and setup the channels. */
572 tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
573 GFP_KERNEL);
574 if (tmu->channels == NULL) {
575 ret = -ENOMEM;
576 goto err_unmap;
577 }
578
579 /*
580 * Use the first channel as a clock event device and the second channel
581 * as a clock source.
582 */
583 for (i = 0; i < tmu->num_channels; ++i) {
584 ret = sh_tmu_channel_setup(&tmu->channels[i], i,
585 i == 0, i == 1, tmu);
586 if (ret < 0)
587 goto err_unmap;
588 }
589
590 platform_set_drvdata(pdev, tmu);
591
592 return 0;
593
594err_unmap:
595 kfree(tmu->channels);
596 iounmap(tmu->mapbase);
597err_clk_unprepare:
598 clk_unprepare(tmu->clk);
599err_clk_put:
600 clk_put(tmu->clk);
601 return ret;
602}
603
604static int sh_tmu_probe(struct platform_device *pdev)
605{
606 struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
607 int ret;
608
609 if (!is_early_platform_device(pdev)) {
610 pm_runtime_set_active(&pdev->dev);
611 pm_runtime_enable(&pdev->dev);
612 }
613
614 if (tmu) {
615 dev_info(&pdev->dev, "kept as earlytimer\n");
616 goto out;
617 }
618
619 tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
620 if (tmu == NULL)
621 return -ENOMEM;
622
623 ret = sh_tmu_setup(tmu, pdev);
624 if (ret) {
625 kfree(tmu);
626 pm_runtime_idle(&pdev->dev);
627 return ret;
628 }
629 if (is_early_platform_device(pdev))
630 return 0;
631
632 out:
633 if (tmu->has_clockevent || tmu->has_clocksource)
634 pm_runtime_irq_safe(&pdev->dev);
635 else
636 pm_runtime_idle(&pdev->dev);
637
638 return 0;
639}
640
641static int sh_tmu_remove(struct platform_device *pdev)
642{
643 return -EBUSY; /* cannot unregister clockevent and clocksource */
644}
645
646static const struct platform_device_id sh_tmu_id_table[] = {
647 { "sh-tmu", SH_TMU },
648 { "sh-tmu-sh3", SH_TMU_SH3 },
649 { }
650};
651MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
652
653static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
654 { .compatible = "renesas,tmu" },
655 { }
656};
657MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
658
659static struct platform_driver sh_tmu_device_driver = {
660 .probe = sh_tmu_probe,
661 .remove = sh_tmu_remove,
662 .driver = {
663 .name = "sh_tmu",
664 .of_match_table = of_match_ptr(sh_tmu_of_table),
665 },
666 .id_table = sh_tmu_id_table,
667};
668
669static int __init sh_tmu_init(void)
670{
671 return platform_driver_register(&sh_tmu_device_driver);
672}
673
674static void __exit sh_tmu_exit(void)
675{
676 platform_driver_unregister(&sh_tmu_device_driver);
677}
678
679early_platform_init("earlytimer", &sh_tmu_device_driver);
680subsys_initcall(sh_tmu_init);
681module_exit(sh_tmu_exit);
682
683MODULE_AUTHOR("Magnus Damm");
684MODULE_DESCRIPTION("SuperH TMU Timer Driver");
685MODULE_LICENSE("GPL v2");