1/*
 2 *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 *
 8 * This program is distributed in the hope that it will be useful,
 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18#include <linux/clkdev.h>
19#include <linux/clk-provider.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <dt-bindings/clock/imx1-clock.h>
25#include <soc/imx/timer.h>
26#include <asm/irq.h>
27
28#include "clk.h"
29
30#define MX1_CCM_BASE_ADDR	0x0021b000
31#define MX1_TIM1_BASE_ADDR	0x00220000
32#define MX1_TIM1_INT		(NR_IRQS_LEGACY + 59)
33
34static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
35static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
36				       "prem", "fclk", };
37
38static struct clk *clk[IMX1_CLK_MAX];
39static struct clk_onecell_data clk_data;
40
41static void __iomem *ccm __initdata;
42#define CCM_CSCR	(ccm + 0x0000)
43#define CCM_MPCTL0	(ccm + 0x0004)
44#define CCM_SPCTL0	(ccm + 0x000c)
45#define CCM_PCDR	(ccm + 0x0020)
46#define SCM_GCCR	(ccm + 0x0810)
47
48static void __init mx1_clocks_init_dt(struct device_node *np)
49{
50	ccm = of_iomap(np, 0);
51	BUG_ON(!ccm);
52
53	clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
54	clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
55	clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
56	clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
57	clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
58	clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
59	clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0);
60	clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
61	clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0);
62	clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
63	clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
64	clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
65	clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
66	clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
67	clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
68	clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
69	clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
70	clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
71	clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
72	clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
73	clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
74	clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
75	clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
76	clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
77	clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
78
79	imx_check_clocks(clk, ARRAY_SIZE(clk));
80
81	clk_data.clks = clk;
82	clk_data.clk_num = ARRAY_SIZE(clk);
83	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
84}
85CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);