1/*
  2 * tsc_msr.c - TSC frequency enumeration via MSR
  3 *
  4 * Copyright (C) 2013 Intel Corporation
  5 * Author: Bin Gao <bin.gao@intel.com>
  6 *
  7 * This file is released under the GPLv2.
  8 */
  9
 10#include <linux/kernel.h>
 11#include <asm/processor.h>
 12#include <asm/setup.h>
 13#include <asm/apic.h>
 14#include <asm/param.h>
 15
 16#define MAX_NUM_FREQS	9
 17
 18/*
 19 * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
 20 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
 21 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
 22 * so we need manually differentiate SoC families. This is what the
 23 * field msr_plat does.
 24 */
 25struct freq_desc {
 26	u8 x86_family;	/* CPU family */
 27	u8 x86_model;	/* model */
 28	u8 msr_plat;	/* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
 29	u32 freqs[MAX_NUM_FREQS];
 30};
 31
 32static struct freq_desc freq_desc_tables[] = {
 33	/* PNW */
 34	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
 35	/* CLV+ */
 36	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
 37	/* TNG - Intel Atom processor Z3400 series */
 38	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
 39	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
 40	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
 41	/* ANN - Intel Atom processor Z3500 series */
 42	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
 43	/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
 44	{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
 45			80000, 93300, 90000, 88900, 87500 } },
 46};
 47
 48static int match_cpu(u8 family, u8 model)
 49{
 50	int i;
 51
 52	for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
 53		if ((family == freq_desc_tables[i].x86_family) &&
 54			(model == freq_desc_tables[i].x86_model))
 55			return i;
 56	}
 57
 58	return -1;
 59}
 60
 61/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
 62#define id_to_freq(cpu_index, freq_id) \
 63	(freq_desc_tables[cpu_index].freqs[freq_id])
 64
 65/*
 66 * MSR-based CPU/TSC frequency discovery for certain CPUs.
 67 *
 68 * Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
 69 * Return processor base frequency in KHz, or 0 on failure.
 70 */
 71unsigned long cpu_khz_from_msr(void)
 72{
 73	u32 lo, hi, ratio, freq_id, freq;
 74	unsigned long res;
 75	int cpu_index;
 76
 77	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 78		return 0;
 79
 80	cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
 81	if (cpu_index < 0)
 82		return 0;
 83
 84	if (freq_desc_tables[cpu_index].msr_plat) {
 85		rdmsr(MSR_PLATFORM_INFO, lo, hi);
 86		ratio = (lo >> 8) & 0xff;
 87	} else {
 88		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 89		ratio = (hi >> 8) & 0x1f;
 90	}
 91
 92	/* Get FSB FREQ ID */
 93	rdmsr(MSR_FSB_FREQ, lo, hi);
 94	freq_id = lo & 0x7;
 95	freq = id_to_freq(cpu_index, freq_id);
 96
 97	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
 98	res = freq * ratio;
 99
100#ifdef CONFIG_X86_LOCAL_APIC
101	lapic_timer_frequency = (freq * 1000) / HZ;
102#endif
103
104	/*
105	 * TSC frequency determined by MSR is always considered "known"
106	 * because it is reported by HW.
107	 * Another fact is that on MSR capable platforms, PIT/HPET is
108	 * generally not available so calibration won't work at all.
109	 */
110	setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
111
112	/*
113	 * Unfortunately there is no way for hardware to tell whether the
114	 * TSC is reliable.  We were told by silicon design team that TSC
115	 * on Atom SoCs are always "reliable". TSC is also the only
116	 * reliable clocksource on these SoCs (HPET is either not present
117	 * or not functional) so mark TSC reliable which removes the
118	 * requirement for a watchdog clocksource.
119	 */
120	setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
121
122	return res;
123}