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1/*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
4 *
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/gpio.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25#include <linux/smsc911x.h>
26#include <linux/types.h>
27#include <linux/regulator/machine.h>
28#include <linux/regulator/fixed.h>
29
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32#include <asm/memory.h>
33#include <asm/setup.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/irq.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38
39#include <mach/clock.h>
40#include <mach/common.h>
41#include <mach/hardware.h>
42#include <mach/iomux-mx3.h>
43
44#include "devices-imx31.h"
45
46#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
47 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
48 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
49 MX31_IO_ADDRESS(x))
50
51/*
52 * KZM-ARM11-01 Board Control Registers on FPGA
53 */
54#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
55#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
56#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
57#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
58#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
59#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
60#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
61#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
62
63/*
64 * External UART for touch panel on FPGA
65 */
66#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
67
68#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
69/*
70 * KZM-ARM11-01 has an external UART on FPGA
71 */
72static struct plat_serial8250_port serial_platform_data[] = {
73 {
74 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
75 .mapbase = KZM_ARM11_16550,
76 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
77 .irqflags = IRQ_TYPE_EDGE_RISING,
78 .uartclk = 14745600,
79 .regshift = 0,
80 .iotype = UPIO_MEM,
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
82 UPF_BUGGY_UART,
83 },
84 {},
85};
86
87static struct resource serial8250_resources[] = {
88 {
89 .start = KZM_ARM11_16550,
90 .end = KZM_ARM11_16550 + 0x10,
91 .flags = IORESOURCE_MEM,
92 },
93 {
94 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
95 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static struct platform_device serial_device = {
101 .name = "serial8250",
102 .id = PLAT8250_DEV_PLATFORM,
103 .dev = {
104 .platform_data = serial_platform_data,
105 },
106 .num_resources = ARRAY_SIZE(serial8250_resources),
107 .resource = serial8250_resources,
108};
109
110static int __init kzm_init_ext_uart(void)
111{
112 u8 tmp;
113
114 /*
115 * GPIO 1-1: external UART interrupt line
116 */
117 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
118 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
119 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
120
121 /*
122 * Unmask UART interrupt
123 */
124 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
125 tmp |= 0x2;
126 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
127
128 return platform_device_register(&serial_device);
129}
130#else
131static inline int kzm_init_ext_uart(void)
132{
133 return 0;
134}
135#endif
136
137/*
138 * SMSC LAN9118
139 */
140#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
141static struct smsc911x_platform_config kzm_smsc9118_config = {
142 .phy_interface = PHY_INTERFACE_MODE_MII,
143 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
144 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
145 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
146};
147
148static struct resource kzm_smsc9118_resources[] = {
149 {
150 .start = MX31_CS5_BASE_ADDR,
151 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
152 .flags = IORESOURCE_MEM,
153 },
154 {
155 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
156 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
157 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
158 },
159};
160
161static struct platform_device kzm_smsc9118_device = {
162 .name = "smsc911x",
163 .id = -1,
164 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
165 .resource = kzm_smsc9118_resources,
166 .dev = {
167 .platform_data = &kzm_smsc9118_config,
168 },
169};
170
171static struct regulator_consumer_supply dummy_supplies[] = {
172 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
173 REGULATOR_SUPPLY("vddvario", "smsc911x"),
174};
175
176static int __init kzm_init_smsc9118(void)
177{
178 /*
179 * GPIO 1-2: SMSC9118 interrupt line
180 */
181 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
182 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
183 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
184
185 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
186
187 return platform_device_register(&kzm_smsc9118_device);
188}
189#else
190static inline int kzm_init_smsc9118(void)
191{
192 return 0;
193}
194#endif
195
196#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
197static const struct imxuart_platform_data uart_pdata __initconst = {
198 .flags = IMXUART_HAVE_RTSCTS,
199};
200
201static void __init kzm_init_imx_uart(void)
202{
203 imx31_add_imx_uart0(&uart_pdata);
204 imx31_add_imx_uart1(&uart_pdata);
205}
206#else
207static inline void kzm_init_imx_uart(void)
208{
209}
210#endif
211
212static int kzm_pins[] __initdata = {
213 MX31_PIN_CTS1__CTS1,
214 MX31_PIN_RTS1__RTS1,
215 MX31_PIN_TXD1__TXD1,
216 MX31_PIN_RXD1__RXD1,
217 MX31_PIN_DCD_DCE1__DCD_DCE1,
218 MX31_PIN_RI_DCE1__RI_DCE1,
219 MX31_PIN_DSR_DCE1__DSR_DCE1,
220 MX31_PIN_DTR_DCE1__DTR_DCE1,
221 MX31_PIN_CTS2__CTS2,
222 MX31_PIN_RTS2__RTS2,
223 MX31_PIN_TXD2__TXD2,
224 MX31_PIN_RXD2__RXD2,
225 MX31_PIN_DCD_DTE1__DCD_DTE2,
226 MX31_PIN_RI_DTE1__RI_DTE2,
227 MX31_PIN_DSR_DTE1__DSR_DTE2,
228 MX31_PIN_DTR_DTE1__DTR_DTE2,
229};
230
231/*
232 * Board specific initialization.
233 */
234static void __init kzm_board_init(void)
235{
236 imx31_soc_init();
237
238 mxc_iomux_setup_multiple_pins(kzm_pins,
239 ARRAY_SIZE(kzm_pins), "kzm");
240 kzm_init_ext_uart();
241 kzm_init_smsc9118();
242 kzm_init_imx_uart();
243
244 pr_info("Clock input source is 26MHz\n");
245}
246
247/*
248 * This structure defines static mappings for the kzm-arm11-01 board.
249 */
250static struct map_desc kzm_io_desc[] __initdata = {
251 {
252 .virtual = MX31_CS4_BASE_ADDR_VIRT,
253 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
254 .length = MX31_CS4_SIZE,
255 .type = MT_DEVICE
256 },
257 {
258 .virtual = MX31_CS5_BASE_ADDR_VIRT,
259 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
260 .length = MX31_CS5_SIZE,
261 .type = MT_DEVICE
262 },
263};
264
265/*
266 * Set up static virtual mappings.
267 */
268static void __init kzm_map_io(void)
269{
270 mx31_map_io();
271 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
272}
273
274static void __init kzm_timer_init(void)
275{
276 mx31_clocks_init(26000000);
277}
278
279static struct sys_timer kzm_timer = {
280 .init = kzm_timer_init,
281};
282
283MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
284 .atag_offset = 0x100,
285 .map_io = kzm_map_io,
286 .init_early = imx31_init_early,
287 .init_irq = mx31_init_irq,
288 .handle_irq = imx31_handle_irq,
289 .timer = &kzm_timer,
290 .init_machine = kzm_board_init,
291 .restart = mxc_restart,
292MACHINE_END
1/*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
4 *
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/gpio.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25#include <linux/smsc911x.h>
26#include <linux/types.h>
27#include <linux/regulator/machine.h>
28#include <linux/regulator/fixed.h>
29
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32#include <asm/memory.h>
33#include <asm/setup.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/irq.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38
39#include "common.h"
40#include "devices-imx31.h"
41#include "hardware.h"
42#include "iomux-mx3.h"
43
44#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
46 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
47 MX31_IO_ADDRESS(x))
48
49/*
50 * KZM-ARM11-01 Board Control Registers on FPGA
51 */
52#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
53#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
54#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
55#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
56#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
57#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
58#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
59#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
60
61/*
62 * External UART for touch panel on FPGA
63 */
64#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
65
66#if IS_ENABLED(CONFIG_SERIAL_8250)
67/*
68 * KZM-ARM11-01 has an external UART on FPGA
69 */
70static struct plat_serial8250_port serial_platform_data[] = {
71 {
72 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
73 .mapbase = KZM_ARM11_16550,
74 /* irq number is run-time assigned */
75 .irqflags = IRQ_TYPE_EDGE_RISING,
76 .uartclk = 14745600,
77 .regshift = 0,
78 .iotype = UPIO_MEM,
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_BUGGY_UART,
81 },
82 {},
83};
84
85static struct resource serial8250_resources[] = {
86 {
87 .start = KZM_ARM11_16550,
88 .end = KZM_ARM11_16550 + 0x10,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 /* irq number is run-time assigned */
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device serial_device = {
98 .name = "serial8250",
99 .id = PLAT8250_DEV_PLATFORM,
100 .dev = {
101 .platform_data = serial_platform_data,
102 },
103 .num_resources = ARRAY_SIZE(serial8250_resources),
104 .resource = serial8250_resources,
105};
106
107static int __init kzm_init_ext_uart(void)
108{
109 u8 tmp;
110
111 /*
112 * GPIO 1-1: external UART interrupt line
113 */
114 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
115 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
116 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
117
118 /*
119 * Unmask UART interrupt
120 */
121 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
122 tmp |= 0x2;
123 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
124
125 serial_platform_data[0].irq =
126 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
127 serial8250_resources[1].start =
128 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
129 serial8250_resources[1].end =
130 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
131
132 return platform_device_register(&serial_device);
133}
134#else
135static inline int kzm_init_ext_uart(void)
136{
137 return 0;
138}
139#endif
140
141/*
142 * SMSC LAN9118
143 */
144#if IS_ENABLED(CONFIG_SMSC911X)
145static struct smsc911x_platform_config kzm_smsc9118_config = {
146 .phy_interface = PHY_INTERFACE_MODE_MII,
147 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
148 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
149 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
150};
151
152static struct resource kzm_smsc9118_resources[] = {
153 {
154 .start = MX31_CS5_BASE_ADDR,
155 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 /* irq number is run-time assigned */
160 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
161 },
162};
163
164static struct platform_device kzm_smsc9118_device = {
165 .name = "smsc911x",
166 .id = -1,
167 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
168 .resource = kzm_smsc9118_resources,
169 .dev = {
170 .platform_data = &kzm_smsc9118_config,
171 },
172};
173
174static struct regulator_consumer_supply dummy_supplies[] = {
175 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
176 REGULATOR_SUPPLY("vddvario", "smsc911x"),
177};
178
179static int __init kzm_init_smsc9118(void)
180{
181 /*
182 * GPIO 1-2: SMSC9118 interrupt line
183 */
184 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
185 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
186 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
187
188 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
189
190 kzm_smsc9118_resources[1].start =
191 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
192 kzm_smsc9118_resources[1].end =
193 gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
194
195 return platform_device_register(&kzm_smsc9118_device);
196}
197#else
198static inline int kzm_init_smsc9118(void)
199{
200 return 0;
201}
202#endif
203
204#if IS_ENABLED(CONFIG_SERIAL_IMX)
205static const struct imxuart_platform_data uart_pdata __initconst = {
206 .flags = IMXUART_HAVE_RTSCTS,
207};
208
209static void __init kzm_init_imx_uart(void)
210{
211 imx31_add_imx_uart0(&uart_pdata);
212 imx31_add_imx_uart1(&uart_pdata);
213}
214#else
215static inline void kzm_init_imx_uart(void)
216{
217}
218#endif
219
220static int kzm_pins[] __initdata = {
221 MX31_PIN_CTS1__CTS1,
222 MX31_PIN_RTS1__RTS1,
223 MX31_PIN_TXD1__TXD1,
224 MX31_PIN_RXD1__RXD1,
225 MX31_PIN_DCD_DCE1__DCD_DCE1,
226 MX31_PIN_RI_DCE1__RI_DCE1,
227 MX31_PIN_DSR_DCE1__DSR_DCE1,
228 MX31_PIN_DTR_DCE1__DTR_DCE1,
229 MX31_PIN_CTS2__CTS2,
230 MX31_PIN_RTS2__RTS2,
231 MX31_PIN_TXD2__TXD2,
232 MX31_PIN_RXD2__RXD2,
233 MX31_PIN_DCD_DTE1__DCD_DTE2,
234 MX31_PIN_RI_DTE1__RI_DTE2,
235 MX31_PIN_DSR_DTE1__DSR_DTE2,
236 MX31_PIN_DTR_DTE1__DTR_DTE2,
237};
238
239/*
240 * Board specific initialization.
241 */
242static void __init kzm_board_init(void)
243{
244 imx31_soc_init();
245
246 mxc_iomux_setup_multiple_pins(kzm_pins,
247 ARRAY_SIZE(kzm_pins), "kzm");
248 kzm_init_imx_uart();
249
250 pr_info("Clock input source is 26MHz\n");
251}
252
253static void __init kzm_late_init(void)
254{
255 kzm_init_ext_uart();
256 kzm_init_smsc9118();
257}
258
259/*
260 * This structure defines static mappings for the kzm-arm11-01 board.
261 */
262static struct map_desc kzm_io_desc[] __initdata = {
263 {
264 .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
265 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
266 .length = MX31_CS4_SIZE,
267 .type = MT_DEVICE
268 },
269 {
270 .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
271 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
272 .length = MX31_CS5_SIZE,
273 .type = MT_DEVICE
274 },
275};
276
277/*
278 * Set up static virtual mappings.
279 */
280static void __init kzm_map_io(void)
281{
282 mx31_map_io();
283 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
284}
285
286static void __init kzm_timer_init(void)
287{
288 mx31_clocks_init(26000000);
289}
290
291MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
292 .atag_offset = 0x100,
293 .map_io = kzm_map_io,
294 .init_early = imx31_init_early,
295 .init_irq = mx31_init_irq,
296 .init_time = kzm_timer_init,
297 .init_machine = kzm_board_init,
298 .init_late = kzm_late_init,
299 .restart = mxc_restart,
300MACHINE_END