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1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/device.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/mmc.h>
24#include <linux/scatterlist.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/pm_runtime.h>
28#include <linux/mmc/slot-gpio.h>
29#include <linux/mmc/sdhci-pci-data.h>
30#include <linux/acpi.h>
31
32#include "sdhci.h"
33#include "sdhci-pci.h"
34#include "sdhci-pci-o2micro.h"
35
36static int sdhci_pci_enable_dma(struct sdhci_host *host);
37static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width);
38static void sdhci_pci_hw_reset(struct sdhci_host *host);
39static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
40 struct mmc_card *card,
41 unsigned int max_dtr, int host_drv,
42 int card_drv, int *drv_type);
43
44/*****************************************************************************\
45 * *
46 * Hardware specific quirk handling *
47 * *
48\*****************************************************************************/
49
50static int ricoh_probe(struct sdhci_pci_chip *chip)
51{
52 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
53 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
54 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
55 return 0;
56}
57
58static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
59{
60 slot->host->caps =
61 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
62 & SDHCI_TIMEOUT_CLK_MASK) |
63
64 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
65 & SDHCI_CLOCK_BASE_MASK) |
66
67 SDHCI_TIMEOUT_CLK_UNIT |
68 SDHCI_CAN_VDD_330 |
69 SDHCI_CAN_DO_HISPD |
70 SDHCI_CAN_DO_SDMA;
71 return 0;
72}
73
74static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
75{
76 /* Apply a delay to allow controller to settle */
77 /* Otherwise it becomes confused if card state changed
78 during suspend */
79 msleep(500);
80 return 0;
81}
82
83static const struct sdhci_pci_fixes sdhci_ricoh = {
84 .probe = ricoh_probe,
85 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
86 SDHCI_QUIRK_FORCE_DMA |
87 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
88};
89
90static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
91 .probe_slot = ricoh_mmc_probe_slot,
92 .resume = ricoh_mmc_resume,
93 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
94 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
95 SDHCI_QUIRK_NO_CARD_NO_RESET |
96 SDHCI_QUIRK_MISSING_CAPS
97};
98
99static const struct sdhci_pci_fixes sdhci_ene_712 = {
100 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
101 SDHCI_QUIRK_BROKEN_DMA,
102};
103
104static const struct sdhci_pci_fixes sdhci_ene_714 = {
105 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
106 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
107 SDHCI_QUIRK_BROKEN_DMA,
108};
109
110static const struct sdhci_pci_fixes sdhci_cafe = {
111 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
112 SDHCI_QUIRK_NO_BUSY_IRQ |
113 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
114 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
115};
116
117static const struct sdhci_pci_fixes sdhci_intel_qrk = {
118 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
119};
120
121static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
122{
123 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
124 return 0;
125}
126
127/*
128 * ADMA operation is disabled for Moorestown platform due to
129 * hardware bugs.
130 */
131static int mrst_hc_probe(struct sdhci_pci_chip *chip)
132{
133 /*
134 * slots number is fixed here for MRST as SDIO3/5 are never used and
135 * have hardware bugs.
136 */
137 chip->num_slots = 1;
138 return 0;
139}
140
141static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
142{
143 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
144 return 0;
145}
146
147#ifdef CONFIG_PM
148
149static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
150{
151 struct sdhci_pci_slot *slot = dev_id;
152 struct sdhci_host *host = slot->host;
153
154 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
155 return IRQ_HANDLED;
156}
157
158static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
159{
160 int err, irq, gpio = slot->cd_gpio;
161
162 slot->cd_gpio = -EINVAL;
163 slot->cd_irq = -EINVAL;
164
165 if (!gpio_is_valid(gpio))
166 return;
167
168 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
169 if (err < 0)
170 goto out;
171
172 err = gpio_direction_input(gpio);
173 if (err < 0)
174 goto out_free;
175
176 irq = gpio_to_irq(gpio);
177 if (irq < 0)
178 goto out_free;
179
180 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
181 IRQF_TRIGGER_FALLING, "sd_cd", slot);
182 if (err)
183 goto out_free;
184
185 slot->cd_gpio = gpio;
186 slot->cd_irq = irq;
187
188 return;
189
190out_free:
191 devm_gpio_free(&slot->chip->pdev->dev, gpio);
192out:
193 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
194}
195
196static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
197{
198 if (slot->cd_irq >= 0)
199 free_irq(slot->cd_irq, slot);
200}
201
202#else
203
204static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
205{
206}
207
208static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
209{
210}
211
212#endif
213
214static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
215{
216 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
217 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
218 MMC_CAP2_HC_ERASE_SZ;
219 return 0;
220}
221
222static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
223{
224 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
225 return 0;
226}
227
228static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
229 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
230 .probe_slot = mrst_hc_probe_slot,
231};
232
233static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
234 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
235 .probe = mrst_hc_probe,
236};
237
238static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
240 .allow_runtime_pm = true,
241 .own_cd_for_runtime_pm = true,
242};
243
244static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
247 .allow_runtime_pm = true,
248 .probe_slot = mfd_sdio_probe_slot,
249};
250
251static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
252 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
253 .allow_runtime_pm = true,
254 .probe_slot = mfd_emmc_probe_slot,
255};
256
257static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
258 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
259 .probe_slot = pch_hc_probe_slot,
260};
261
262static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
263{
264 u8 reg;
265
266 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
267 reg |= 0x10;
268 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
269 /* For eMMC, minimum is 1us but give it 9us for good measure */
270 udelay(9);
271 reg &= ~0x10;
272 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
273 /* For eMMC, minimum is 200us but give it 300us for good measure */
274 usleep_range(300, 1000);
275}
276
277static int spt_select_drive_strength(struct sdhci_host *host,
278 struct mmc_card *card,
279 unsigned int max_dtr,
280 int host_drv, int card_drv, int *drv_type)
281{
282 int drive_strength;
283
284 if (sdhci_pci_spt_drive_strength > 0)
285 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
286 else
287 drive_strength = 0; /* Default 50-ohm */
288
289 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
290 drive_strength = 0; /* Default 50-ohm */
291
292 return drive_strength;
293}
294
295/* Try to read the drive strength from the card */
296static void spt_read_drive_strength(struct sdhci_host *host)
297{
298 u32 val, i, t;
299 u16 m;
300
301 if (sdhci_pci_spt_drive_strength)
302 return;
303
304 sdhci_pci_spt_drive_strength = -1;
305
306 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
307 if (m != 3 && m != 5)
308 return;
309 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
310 if (val & 0x3)
311 return;
312 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
313 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
314 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
315 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
316 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
317 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
318 sdhci_writel(host, 0, SDHCI_ARGUMENT);
319 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
320 for (i = 0; i < 1000; i++) {
321 val = sdhci_readl(host, SDHCI_INT_STATUS);
322 if (val & 0xffff8000)
323 return;
324 if (val & 0x20)
325 break;
326 udelay(1);
327 }
328 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
329 if (!(val & 0x800))
330 return;
331 for (i = 0; i < 47; i++)
332 val = sdhci_readl(host, SDHCI_BUFFER);
333 t = val & 0xf00;
334 if (t != 0x200 && t != 0x300)
335 return;
336
337 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
338}
339
340static int bxt_get_cd(struct mmc_host *mmc)
341{
342 int gpio_cd = mmc_gpio_get_cd(mmc);
343 struct sdhci_host *host = mmc_priv(mmc);
344 unsigned long flags;
345 int ret = 0;
346
347 if (!gpio_cd)
348 return 0;
349
350 spin_lock_irqsave(&host->lock, flags);
351
352 if (host->flags & SDHCI_DEVICE_DEAD)
353 goto out;
354
355 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
356out:
357 spin_unlock_irqrestore(&host->lock, flags);
358
359 return ret;
360}
361
362static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
363{
364 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
365 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
366 MMC_CAP_CMD_DURING_TFR |
367 MMC_CAP_WAIT_WHILE_BUSY;
368 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
369 slot->hw_reset = sdhci_pci_int_hw_reset;
370 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
371 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
372 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
373 spt_read_drive_strength(slot->host);
374 slot->select_drive_strength = spt_select_drive_strength;
375 }
376 return 0;
377}
378
379#ifdef CONFIG_ACPI
380static int ni_set_max_freq(struct sdhci_pci_slot *slot)
381{
382 acpi_status status;
383 unsigned long long max_freq;
384
385 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
386 "MXFQ", NULL, &max_freq);
387 if (ACPI_FAILURE(status)) {
388 dev_err(&slot->chip->pdev->dev,
389 "MXFQ not found in acpi table\n");
390 return -EINVAL;
391 }
392
393 slot->host->mmc->f_max = max_freq * 1000000;
394
395 return 0;
396}
397#else
398static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
399{
400 return 0;
401}
402#endif
403
404static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
405{
406 int err;
407
408 err = ni_set_max_freq(slot);
409 if (err)
410 return err;
411
412 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
413 MMC_CAP_WAIT_WHILE_BUSY;
414 return 0;
415}
416
417static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
418{
419 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
420 MMC_CAP_WAIT_WHILE_BUSY;
421 return 0;
422}
423
424static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
425{
426 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
427 slot->cd_con_id = NULL;
428 slot->cd_idx = 0;
429 slot->cd_override_level = true;
430 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
431 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
432 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
433 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) {
434 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
435 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM;
436 }
437
438 return 0;
439}
440
441#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
442#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
443
444static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
445 unsigned short vdd)
446{
447 int cntr;
448 u8 reg;
449
450 sdhci_set_power(host, mode, vdd);
451
452 if (mode == MMC_POWER_OFF)
453 return;
454
455 spin_unlock_irq(&host->lock);
456
457 /*
458 * Bus power might not enable after D3 -> D0 transition due to the
459 * present state not yet having propagated. Retry for up to 2ms.
460 */
461 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
462 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
463 if (reg & SDHCI_POWER_ON)
464 break;
465 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
466 reg |= SDHCI_POWER_ON;
467 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
468 }
469
470 spin_lock_irq(&host->lock);
471}
472
473static const struct sdhci_ops sdhci_intel_byt_ops = {
474 .set_clock = sdhci_set_clock,
475 .set_power = sdhci_intel_set_power,
476 .enable_dma = sdhci_pci_enable_dma,
477 .set_bus_width = sdhci_pci_set_bus_width,
478 .reset = sdhci_reset,
479 .set_uhs_signaling = sdhci_set_uhs_signaling,
480 .hw_reset = sdhci_pci_hw_reset,
481 .select_drive_strength = sdhci_pci_select_drive_strength,
482};
483
484static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
485 .allow_runtime_pm = true,
486 .probe_slot = byt_emmc_probe_slot,
487 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
488 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
489 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
490 SDHCI_QUIRK2_STOP_WITH_TC,
491 .ops = &sdhci_intel_byt_ops,
492};
493
494static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
495 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
496 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
497 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
498 .allow_runtime_pm = true,
499 .probe_slot = ni_byt_sdio_probe_slot,
500 .ops = &sdhci_intel_byt_ops,
501};
502
503static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
504 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
505 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
506 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
507 .allow_runtime_pm = true,
508 .probe_slot = byt_sdio_probe_slot,
509 .ops = &sdhci_intel_byt_ops,
510};
511
512static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
513 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
514 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
515 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
516 SDHCI_QUIRK2_STOP_WITH_TC,
517 .allow_runtime_pm = true,
518 .own_cd_for_runtime_pm = true,
519 .probe_slot = byt_sd_probe_slot,
520 .ops = &sdhci_intel_byt_ops,
521};
522
523/* Define Host controllers for Intel Merrifield platform */
524#define INTEL_MRFLD_EMMC_0 0
525#define INTEL_MRFLD_EMMC_1 1
526#define INTEL_MRFLD_SD 2
527#define INTEL_MRFLD_SDIO 3
528
529static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
530{
531 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
532
533 switch (func) {
534 case INTEL_MRFLD_EMMC_0:
535 case INTEL_MRFLD_EMMC_1:
536 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
537 MMC_CAP_8_BIT_DATA |
538 MMC_CAP_1_8V_DDR;
539 break;
540 case INTEL_MRFLD_SD:
541 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
542 break;
543 case INTEL_MRFLD_SDIO:
544 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
545 MMC_CAP_POWER_OFF_CARD;
546 break;
547 default:
548 return -ENODEV;
549 }
550 return 0;
551}
552
553static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
554 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
555 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
556 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
557 .allow_runtime_pm = true,
558 .probe_slot = intel_mrfld_mmc_probe_slot,
559};
560
561/* O2Micro extra registers */
562#define O2_SD_LOCK_WP 0xD3
563#define O2_SD_MULTI_VCC3V 0xEE
564#define O2_SD_CLKREQ 0xEC
565#define O2_SD_CAPS 0xE0
566#define O2_SD_ADMA1 0xE2
567#define O2_SD_ADMA2 0xE7
568#define O2_SD_INF_MOD 0xF1
569
570static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
571{
572 u8 scratch;
573 int ret;
574
575 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
576 if (ret)
577 return ret;
578
579 /*
580 * Turn PMOS on [bit 0], set over current detection to 2.4 V
581 * [bit 1:2] and enable over current debouncing [bit 6].
582 */
583 if (on)
584 scratch |= 0x47;
585 else
586 scratch &= ~0x47;
587
588 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
589}
590
591static int jmicron_probe(struct sdhci_pci_chip *chip)
592{
593 int ret;
594 u16 mmcdev = 0;
595
596 if (chip->pdev->revision == 0) {
597 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
598 SDHCI_QUIRK_32BIT_DMA_SIZE |
599 SDHCI_QUIRK_32BIT_ADMA_SIZE |
600 SDHCI_QUIRK_RESET_AFTER_REQUEST |
601 SDHCI_QUIRK_BROKEN_SMALL_PIO;
602 }
603
604 /*
605 * JMicron chips can have two interfaces to the same hardware
606 * in order to work around limitations in Microsoft's driver.
607 * We need to make sure we only bind to one of them.
608 *
609 * This code assumes two things:
610 *
611 * 1. The PCI code adds subfunctions in order.
612 *
613 * 2. The MMC interface has a lower subfunction number
614 * than the SD interface.
615 */
616 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
617 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
618 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
619 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
620
621 if (mmcdev) {
622 struct pci_dev *sd_dev;
623
624 sd_dev = NULL;
625 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
626 mmcdev, sd_dev)) != NULL) {
627 if ((PCI_SLOT(chip->pdev->devfn) ==
628 PCI_SLOT(sd_dev->devfn)) &&
629 (chip->pdev->bus == sd_dev->bus))
630 break;
631 }
632
633 if (sd_dev) {
634 pci_dev_put(sd_dev);
635 dev_info(&chip->pdev->dev, "Refusing to bind to "
636 "secondary interface.\n");
637 return -ENODEV;
638 }
639 }
640
641 /*
642 * JMicron chips need a bit of a nudge to enable the power
643 * output pins.
644 */
645 ret = jmicron_pmos(chip, 1);
646 if (ret) {
647 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
648 return ret;
649 }
650
651 /* quirk for unsable RO-detection on JM388 chips */
652 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
653 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
654 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
655
656 return 0;
657}
658
659static void jmicron_enable_mmc(struct sdhci_host *host, int on)
660{
661 u8 scratch;
662
663 scratch = readb(host->ioaddr + 0xC0);
664
665 if (on)
666 scratch |= 0x01;
667 else
668 scratch &= ~0x01;
669
670 writeb(scratch, host->ioaddr + 0xC0);
671}
672
673static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
674{
675 if (slot->chip->pdev->revision == 0) {
676 u16 version;
677
678 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
679 version = (version & SDHCI_VENDOR_VER_MASK) >>
680 SDHCI_VENDOR_VER_SHIFT;
681
682 /*
683 * Older versions of the chip have lots of nasty glitches
684 * in the ADMA engine. It's best just to avoid it
685 * completely.
686 */
687 if (version < 0xAC)
688 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
689 }
690
691 /* JM388 MMC doesn't support 1.8V while SD supports it */
692 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
693 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
694 MMC_VDD_29_30 | MMC_VDD_30_31 |
695 MMC_VDD_165_195; /* allow 1.8V */
696 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
697 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
698 }
699
700 /*
701 * The secondary interface requires a bit set to get the
702 * interrupts.
703 */
704 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
705 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
706 jmicron_enable_mmc(slot->host, 1);
707
708 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
709
710 return 0;
711}
712
713static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
714{
715 if (dead)
716 return;
717
718 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
719 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
720 jmicron_enable_mmc(slot->host, 0);
721}
722
723static int jmicron_suspend(struct sdhci_pci_chip *chip)
724{
725 int i;
726
727 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
728 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
729 for (i = 0; i < chip->num_slots; i++)
730 jmicron_enable_mmc(chip->slots[i]->host, 0);
731 }
732
733 return 0;
734}
735
736static int jmicron_resume(struct sdhci_pci_chip *chip)
737{
738 int ret, i;
739
740 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
741 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
742 for (i = 0; i < chip->num_slots; i++)
743 jmicron_enable_mmc(chip->slots[i]->host, 1);
744 }
745
746 ret = jmicron_pmos(chip, 1);
747 if (ret) {
748 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
749 return ret;
750 }
751
752 return 0;
753}
754
755static const struct sdhci_pci_fixes sdhci_o2 = {
756 .probe = sdhci_pci_o2_probe,
757 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
758 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
759 .probe_slot = sdhci_pci_o2_probe_slot,
760 .resume = sdhci_pci_o2_resume,
761};
762
763static const struct sdhci_pci_fixes sdhci_jmicron = {
764 .probe = jmicron_probe,
765
766 .probe_slot = jmicron_probe_slot,
767 .remove_slot = jmicron_remove_slot,
768
769 .suspend = jmicron_suspend,
770 .resume = jmicron_resume,
771};
772
773/* SysKonnect CardBus2SDIO extra registers */
774#define SYSKT_CTRL 0x200
775#define SYSKT_RDFIFO_STAT 0x204
776#define SYSKT_WRFIFO_STAT 0x208
777#define SYSKT_POWER_DATA 0x20c
778#define SYSKT_POWER_330 0xef
779#define SYSKT_POWER_300 0xf8
780#define SYSKT_POWER_184 0xcc
781#define SYSKT_POWER_CMD 0x20d
782#define SYSKT_POWER_START (1 << 7)
783#define SYSKT_POWER_STATUS 0x20e
784#define SYSKT_POWER_STATUS_OK (1 << 0)
785#define SYSKT_BOARD_REV 0x210
786#define SYSKT_CHIP_REV 0x211
787#define SYSKT_CONF_DATA 0x212
788#define SYSKT_CONF_DATA_1V8 (1 << 2)
789#define SYSKT_CONF_DATA_2V5 (1 << 1)
790#define SYSKT_CONF_DATA_3V3 (1 << 0)
791
792static int syskt_probe(struct sdhci_pci_chip *chip)
793{
794 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
795 chip->pdev->class &= ~0x0000FF;
796 chip->pdev->class |= PCI_SDHCI_IFDMA;
797 }
798 return 0;
799}
800
801static int syskt_probe_slot(struct sdhci_pci_slot *slot)
802{
803 int tm, ps;
804
805 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
806 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
807 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
808 "board rev %d.%d, chip rev %d.%d\n",
809 board_rev >> 4, board_rev & 0xf,
810 chip_rev >> 4, chip_rev & 0xf);
811 if (chip_rev >= 0x20)
812 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
813
814 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
815 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
816 udelay(50);
817 tm = 10; /* Wait max 1 ms */
818 do {
819 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
820 if (ps & SYSKT_POWER_STATUS_OK)
821 break;
822 udelay(100);
823 } while (--tm);
824 if (!tm) {
825 dev_err(&slot->chip->pdev->dev,
826 "power regulator never stabilized");
827 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
828 return -ENODEV;
829 }
830
831 return 0;
832}
833
834static const struct sdhci_pci_fixes sdhci_syskt = {
835 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
836 .probe = syskt_probe,
837 .probe_slot = syskt_probe_slot,
838};
839
840static int via_probe(struct sdhci_pci_chip *chip)
841{
842 if (chip->pdev->revision == 0x10)
843 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
844
845 return 0;
846}
847
848static const struct sdhci_pci_fixes sdhci_via = {
849 .probe = via_probe,
850};
851
852static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
853{
854 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
855 return 0;
856}
857
858static const struct sdhci_pci_fixes sdhci_rtsx = {
859 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
860 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
861 SDHCI_QUIRK2_BROKEN_DDR50,
862 .probe_slot = rtsx_probe_slot,
863};
864
865/*AMD chipset generation*/
866enum amd_chipset_gen {
867 AMD_CHIPSET_BEFORE_ML,
868 AMD_CHIPSET_CZ,
869 AMD_CHIPSET_NL,
870 AMD_CHIPSET_UNKNOWN,
871};
872
873static int amd_probe(struct sdhci_pci_chip *chip)
874{
875 struct pci_dev *smbus_dev;
876 enum amd_chipset_gen gen;
877
878 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
879 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
880 if (smbus_dev) {
881 gen = AMD_CHIPSET_BEFORE_ML;
882 } else {
883 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
884 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
885 if (smbus_dev) {
886 if (smbus_dev->revision < 0x51)
887 gen = AMD_CHIPSET_CZ;
888 else
889 gen = AMD_CHIPSET_NL;
890 } else {
891 gen = AMD_CHIPSET_UNKNOWN;
892 }
893 }
894
895 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
896 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
897 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
898 }
899
900 return 0;
901}
902
903static const struct sdhci_pci_fixes sdhci_amd = {
904 .probe = amd_probe,
905};
906
907static const struct pci_device_id pci_ids[] = {
908 {
909 .vendor = PCI_VENDOR_ID_RICOH,
910 .device = PCI_DEVICE_ID_RICOH_R5C822,
911 .subvendor = PCI_ANY_ID,
912 .subdevice = PCI_ANY_ID,
913 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
914 },
915
916 {
917 .vendor = PCI_VENDOR_ID_RICOH,
918 .device = 0x843,
919 .subvendor = PCI_ANY_ID,
920 .subdevice = PCI_ANY_ID,
921 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
922 },
923
924 {
925 .vendor = PCI_VENDOR_ID_RICOH,
926 .device = 0xe822,
927 .subvendor = PCI_ANY_ID,
928 .subdevice = PCI_ANY_ID,
929 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
930 },
931
932 {
933 .vendor = PCI_VENDOR_ID_RICOH,
934 .device = 0xe823,
935 .subvendor = PCI_ANY_ID,
936 .subdevice = PCI_ANY_ID,
937 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
938 },
939
940 {
941 .vendor = PCI_VENDOR_ID_ENE,
942 .device = PCI_DEVICE_ID_ENE_CB712_SD,
943 .subvendor = PCI_ANY_ID,
944 .subdevice = PCI_ANY_ID,
945 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
946 },
947
948 {
949 .vendor = PCI_VENDOR_ID_ENE,
950 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
951 .subvendor = PCI_ANY_ID,
952 .subdevice = PCI_ANY_ID,
953 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
954 },
955
956 {
957 .vendor = PCI_VENDOR_ID_ENE,
958 .device = PCI_DEVICE_ID_ENE_CB714_SD,
959 .subvendor = PCI_ANY_ID,
960 .subdevice = PCI_ANY_ID,
961 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
962 },
963
964 {
965 .vendor = PCI_VENDOR_ID_ENE,
966 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
967 .subvendor = PCI_ANY_ID,
968 .subdevice = PCI_ANY_ID,
969 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
970 },
971
972 {
973 .vendor = PCI_VENDOR_ID_MARVELL,
974 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
975 .subvendor = PCI_ANY_ID,
976 .subdevice = PCI_ANY_ID,
977 .driver_data = (kernel_ulong_t)&sdhci_cafe,
978 },
979
980 {
981 .vendor = PCI_VENDOR_ID_JMICRON,
982 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
983 .subvendor = PCI_ANY_ID,
984 .subdevice = PCI_ANY_ID,
985 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
986 },
987
988 {
989 .vendor = PCI_VENDOR_ID_JMICRON,
990 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
991 .subvendor = PCI_ANY_ID,
992 .subdevice = PCI_ANY_ID,
993 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
994 },
995
996 {
997 .vendor = PCI_VENDOR_ID_JMICRON,
998 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
999 .subvendor = PCI_ANY_ID,
1000 .subdevice = PCI_ANY_ID,
1001 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
1002 },
1003
1004 {
1005 .vendor = PCI_VENDOR_ID_JMICRON,
1006 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
1007 .subvendor = PCI_ANY_ID,
1008 .subdevice = PCI_ANY_ID,
1009 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
1010 },
1011
1012 {
1013 .vendor = PCI_VENDOR_ID_SYSKONNECT,
1014 .device = 0x8000,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .driver_data = (kernel_ulong_t)&sdhci_syskt,
1018 },
1019
1020 {
1021 .vendor = PCI_VENDOR_ID_VIA,
1022 .device = 0x95d0,
1023 .subvendor = PCI_ANY_ID,
1024 .subdevice = PCI_ANY_ID,
1025 .driver_data = (kernel_ulong_t)&sdhci_via,
1026 },
1027
1028 {
1029 .vendor = PCI_VENDOR_ID_REALTEK,
1030 .device = 0x5250,
1031 .subvendor = PCI_ANY_ID,
1032 .subdevice = PCI_ANY_ID,
1033 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
1034 },
1035
1036 {
1037 .vendor = PCI_VENDOR_ID_INTEL,
1038 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
1039 .subvendor = PCI_ANY_ID,
1040 .subdevice = PCI_ANY_ID,
1041 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
1042 },
1043
1044 {
1045 .vendor = PCI_VENDOR_ID_INTEL,
1046 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
1047 .subvendor = PCI_ANY_ID,
1048 .subdevice = PCI_ANY_ID,
1049 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
1050 },
1051
1052 {
1053 .vendor = PCI_VENDOR_ID_INTEL,
1054 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
1055 .subvendor = PCI_ANY_ID,
1056 .subdevice = PCI_ANY_ID,
1057 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
1058 },
1059
1060 {
1061 .vendor = PCI_VENDOR_ID_INTEL,
1062 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
1063 .subvendor = PCI_ANY_ID,
1064 .subdevice = PCI_ANY_ID,
1065 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
1066 },
1067
1068 {
1069 .vendor = PCI_VENDOR_ID_INTEL,
1070 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
1071 .subvendor = PCI_ANY_ID,
1072 .subdevice = PCI_ANY_ID,
1073 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1074 },
1075
1076 {
1077 .vendor = PCI_VENDOR_ID_INTEL,
1078 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
1079 .subvendor = PCI_ANY_ID,
1080 .subdevice = PCI_ANY_ID,
1081 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1082 },
1083
1084 {
1085 .vendor = PCI_VENDOR_ID_INTEL,
1086 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
1087 .subvendor = PCI_ANY_ID,
1088 .subdevice = PCI_ANY_ID,
1089 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1090 },
1091
1092 {
1093 .vendor = PCI_VENDOR_ID_INTEL,
1094 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
1095 .subvendor = PCI_ANY_ID,
1096 .subdevice = PCI_ANY_ID,
1097 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1098 },
1099
1100 {
1101 .vendor = PCI_VENDOR_ID_INTEL,
1102 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
1103 .subvendor = PCI_ANY_ID,
1104 .subdevice = PCI_ANY_ID,
1105 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1106 },
1107
1108 {
1109 .vendor = PCI_VENDOR_ID_INTEL,
1110 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1111 .subvendor = PCI_ANY_ID,
1112 .subdevice = PCI_ANY_ID,
1113 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1114 },
1115
1116 {
1117 .vendor = PCI_VENDOR_ID_INTEL,
1118 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1119 .subvendor = PCI_ANY_ID,
1120 .subdevice = PCI_ANY_ID,
1121 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1122 },
1123
1124 {
1125 .vendor = PCI_VENDOR_ID_INTEL,
1126 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1127 .subvendor = PCI_ANY_ID,
1128 .subdevice = PCI_ANY_ID,
1129 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1130 },
1131
1132 {
1133 .vendor = PCI_VENDOR_ID_INTEL,
1134 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1135 .subvendor = PCI_VENDOR_ID_NI,
1136 .subdevice = 0x7884,
1137 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio,
1138 },
1139
1140 {
1141 .vendor = PCI_VENDOR_ID_INTEL,
1142 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1146 },
1147
1148 {
1149 .vendor = PCI_VENDOR_ID_INTEL,
1150 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1151 .subvendor = PCI_ANY_ID,
1152 .subdevice = PCI_ANY_ID,
1153 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1154 },
1155
1156 {
1157 .vendor = PCI_VENDOR_ID_INTEL,
1158 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1159 .subvendor = PCI_ANY_ID,
1160 .subdevice = PCI_ANY_ID,
1161 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1162 },
1163
1164 {
1165 .vendor = PCI_VENDOR_ID_INTEL,
1166 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1167 .subvendor = PCI_ANY_ID,
1168 .subdevice = PCI_ANY_ID,
1169 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1170 },
1171
1172 {
1173 .vendor = PCI_VENDOR_ID_INTEL,
1174 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1175 .subvendor = PCI_ANY_ID,
1176 .subdevice = PCI_ANY_ID,
1177 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1178 },
1179
1180 {
1181 .vendor = PCI_VENDOR_ID_INTEL,
1182 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1183 .subvendor = PCI_ANY_ID,
1184 .subdevice = PCI_ANY_ID,
1185 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1186 },
1187
1188 {
1189 .vendor = PCI_VENDOR_ID_INTEL,
1190 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1191 .subvendor = PCI_ANY_ID,
1192 .subdevice = PCI_ANY_ID,
1193 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1194 },
1195
1196 {
1197 .vendor = PCI_VENDOR_ID_INTEL,
1198 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1199 .subvendor = PCI_ANY_ID,
1200 .subdevice = PCI_ANY_ID,
1201 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1202 },
1203
1204 {
1205 .vendor = PCI_VENDOR_ID_INTEL,
1206 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1207 .subvendor = PCI_ANY_ID,
1208 .subdevice = PCI_ANY_ID,
1209 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1210 },
1211
1212 {
1213 .vendor = PCI_VENDOR_ID_INTEL,
1214 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1215 .subvendor = PCI_ANY_ID,
1216 .subdevice = PCI_ANY_ID,
1217 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1218 },
1219
1220 {
1221 .vendor = PCI_VENDOR_ID_INTEL,
1222 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1223 .subvendor = PCI_ANY_ID,
1224 .subdevice = PCI_ANY_ID,
1225 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1226 },
1227
1228 {
1229 .vendor = PCI_VENDOR_ID_INTEL,
1230 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
1231 .subvendor = PCI_ANY_ID,
1232 .subdevice = PCI_ANY_ID,
1233 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
1234 },
1235
1236 {
1237 .vendor = PCI_VENDOR_ID_INTEL,
1238 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1239 .subvendor = PCI_ANY_ID,
1240 .subdevice = PCI_ANY_ID,
1241 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1242 },
1243
1244 {
1245 .vendor = PCI_VENDOR_ID_INTEL,
1246 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1247 .subvendor = PCI_ANY_ID,
1248 .subdevice = PCI_ANY_ID,
1249 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1250 },
1251
1252 {
1253 .vendor = PCI_VENDOR_ID_INTEL,
1254 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1255 .subvendor = PCI_ANY_ID,
1256 .subdevice = PCI_ANY_ID,
1257 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1258 },
1259
1260 {
1261 .vendor = PCI_VENDOR_ID_INTEL,
1262 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1266 },
1267
1268 {
1269 .vendor = PCI_VENDOR_ID_INTEL,
1270 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1271 .subvendor = PCI_ANY_ID,
1272 .subdevice = PCI_ANY_ID,
1273 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1274 },
1275
1276 {
1277 .vendor = PCI_VENDOR_ID_INTEL,
1278 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1279 .subvendor = PCI_ANY_ID,
1280 .subdevice = PCI_ANY_ID,
1281 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1282 },
1283
1284 {
1285 .vendor = PCI_VENDOR_ID_INTEL,
1286 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1290 },
1291
1292 {
1293 .vendor = PCI_VENDOR_ID_INTEL,
1294 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1295 .subvendor = PCI_ANY_ID,
1296 .subdevice = PCI_ANY_ID,
1297 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1298 },
1299
1300 {
1301 .vendor = PCI_VENDOR_ID_INTEL,
1302 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1303 .subvendor = PCI_ANY_ID,
1304 .subdevice = PCI_ANY_ID,
1305 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1306 },
1307
1308 {
1309 .vendor = PCI_VENDOR_ID_INTEL,
1310 .device = PCI_DEVICE_ID_INTEL_BXTM_SD,
1311 .subvendor = PCI_ANY_ID,
1312 .subdevice = PCI_ANY_ID,
1313 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1314 },
1315
1316 {
1317 .vendor = PCI_VENDOR_ID_INTEL,
1318 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1319 .subvendor = PCI_ANY_ID,
1320 .subdevice = PCI_ANY_ID,
1321 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1322 },
1323
1324 {
1325 .vendor = PCI_VENDOR_ID_INTEL,
1326 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1327 .subvendor = PCI_ANY_ID,
1328 .subdevice = PCI_ANY_ID,
1329 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1330 },
1331
1332 {
1333 .vendor = PCI_VENDOR_ID_INTEL,
1334 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1335 .subvendor = PCI_ANY_ID,
1336 .subdevice = PCI_ANY_ID,
1337 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1338 },
1339
1340 {
1341 .vendor = PCI_VENDOR_ID_INTEL,
1342 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC,
1343 .subvendor = PCI_ANY_ID,
1344 .subdevice = PCI_ANY_ID,
1345 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1346 },
1347
1348 {
1349 .vendor = PCI_VENDOR_ID_INTEL,
1350 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO,
1351 .subvendor = PCI_ANY_ID,
1352 .subdevice = PCI_ANY_ID,
1353 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1354 },
1355
1356 {
1357 .vendor = PCI_VENDOR_ID_INTEL,
1358 .device = PCI_DEVICE_ID_INTEL_GLK_SD,
1359 .subvendor = PCI_ANY_ID,
1360 .subdevice = PCI_ANY_ID,
1361 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1362 },
1363
1364 {
1365 .vendor = PCI_VENDOR_ID_O2,
1366 .device = PCI_DEVICE_ID_O2_8120,
1367 .subvendor = PCI_ANY_ID,
1368 .subdevice = PCI_ANY_ID,
1369 .driver_data = (kernel_ulong_t)&sdhci_o2,
1370 },
1371
1372 {
1373 .vendor = PCI_VENDOR_ID_O2,
1374 .device = PCI_DEVICE_ID_O2_8220,
1375 .subvendor = PCI_ANY_ID,
1376 .subdevice = PCI_ANY_ID,
1377 .driver_data = (kernel_ulong_t)&sdhci_o2,
1378 },
1379
1380 {
1381 .vendor = PCI_VENDOR_ID_O2,
1382 .device = PCI_DEVICE_ID_O2_8221,
1383 .subvendor = PCI_ANY_ID,
1384 .subdevice = PCI_ANY_ID,
1385 .driver_data = (kernel_ulong_t)&sdhci_o2,
1386 },
1387
1388 {
1389 .vendor = PCI_VENDOR_ID_O2,
1390 .device = PCI_DEVICE_ID_O2_8320,
1391 .subvendor = PCI_ANY_ID,
1392 .subdevice = PCI_ANY_ID,
1393 .driver_data = (kernel_ulong_t)&sdhci_o2,
1394 },
1395
1396 {
1397 .vendor = PCI_VENDOR_ID_O2,
1398 .device = PCI_DEVICE_ID_O2_8321,
1399 .subvendor = PCI_ANY_ID,
1400 .subdevice = PCI_ANY_ID,
1401 .driver_data = (kernel_ulong_t)&sdhci_o2,
1402 },
1403
1404 {
1405 .vendor = PCI_VENDOR_ID_O2,
1406 .device = PCI_DEVICE_ID_O2_FUJIN2,
1407 .subvendor = PCI_ANY_ID,
1408 .subdevice = PCI_ANY_ID,
1409 .driver_data = (kernel_ulong_t)&sdhci_o2,
1410 },
1411
1412 {
1413 .vendor = PCI_VENDOR_ID_O2,
1414 .device = PCI_DEVICE_ID_O2_SDS0,
1415 .subvendor = PCI_ANY_ID,
1416 .subdevice = PCI_ANY_ID,
1417 .driver_data = (kernel_ulong_t)&sdhci_o2,
1418 },
1419
1420 {
1421 .vendor = PCI_VENDOR_ID_O2,
1422 .device = PCI_DEVICE_ID_O2_SDS1,
1423 .subvendor = PCI_ANY_ID,
1424 .subdevice = PCI_ANY_ID,
1425 .driver_data = (kernel_ulong_t)&sdhci_o2,
1426 },
1427
1428 {
1429 .vendor = PCI_VENDOR_ID_O2,
1430 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1431 .subvendor = PCI_ANY_ID,
1432 .subdevice = PCI_ANY_ID,
1433 .driver_data = (kernel_ulong_t)&sdhci_o2,
1434 },
1435
1436 {
1437 .vendor = PCI_VENDOR_ID_O2,
1438 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1439 .subvendor = PCI_ANY_ID,
1440 .subdevice = PCI_ANY_ID,
1441 .driver_data = (kernel_ulong_t)&sdhci_o2,
1442 },
1443 {
1444 .vendor = PCI_VENDOR_ID_AMD,
1445 .device = PCI_ANY_ID,
1446 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1447 .class_mask = 0xFFFF00,
1448 .subvendor = PCI_ANY_ID,
1449 .subdevice = PCI_ANY_ID,
1450 .driver_data = (kernel_ulong_t)&sdhci_amd,
1451 },
1452 { /* Generic SD host controller */
1453 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1454 },
1455
1456 { /* end: all zeroes */ },
1457};
1458
1459MODULE_DEVICE_TABLE(pci, pci_ids);
1460
1461/*****************************************************************************\
1462 * *
1463 * SDHCI core callbacks *
1464 * *
1465\*****************************************************************************/
1466
1467static int sdhci_pci_enable_dma(struct sdhci_host *host)
1468{
1469 struct sdhci_pci_slot *slot;
1470 struct pci_dev *pdev;
1471
1472 slot = sdhci_priv(host);
1473 pdev = slot->chip->pdev;
1474
1475 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1476 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1477 (host->flags & SDHCI_USE_SDMA)) {
1478 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1479 "doesn't fully claim to support it.\n");
1480 }
1481
1482 pci_set_master(pdev);
1483
1484 return 0;
1485}
1486
1487static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1488{
1489 u8 ctrl;
1490
1491 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1492
1493 switch (width) {
1494 case MMC_BUS_WIDTH_8:
1495 ctrl |= SDHCI_CTRL_8BITBUS;
1496 ctrl &= ~SDHCI_CTRL_4BITBUS;
1497 break;
1498 case MMC_BUS_WIDTH_4:
1499 ctrl |= SDHCI_CTRL_4BITBUS;
1500 ctrl &= ~SDHCI_CTRL_8BITBUS;
1501 break;
1502 default:
1503 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1504 break;
1505 }
1506
1507 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1508}
1509
1510static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1511{
1512 struct sdhci_pci_slot *slot = sdhci_priv(host);
1513 int rst_n_gpio = slot->rst_n_gpio;
1514
1515 if (!gpio_is_valid(rst_n_gpio))
1516 return;
1517 gpio_set_value_cansleep(rst_n_gpio, 0);
1518 /* For eMMC, minimum is 1us but give it 10us for good measure */
1519 udelay(10);
1520 gpio_set_value_cansleep(rst_n_gpio, 1);
1521 /* For eMMC, minimum is 200us but give it 300us for good measure */
1522 usleep_range(300, 1000);
1523}
1524
1525static void sdhci_pci_hw_reset(struct sdhci_host *host)
1526{
1527 struct sdhci_pci_slot *slot = sdhci_priv(host);
1528
1529 if (slot->hw_reset)
1530 slot->hw_reset(host);
1531}
1532
1533static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1534 struct mmc_card *card,
1535 unsigned int max_dtr, int host_drv,
1536 int card_drv, int *drv_type)
1537{
1538 struct sdhci_pci_slot *slot = sdhci_priv(host);
1539
1540 if (!slot->select_drive_strength)
1541 return 0;
1542
1543 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1544 card_drv, drv_type);
1545}
1546
1547static const struct sdhci_ops sdhci_pci_ops = {
1548 .set_clock = sdhci_set_clock,
1549 .enable_dma = sdhci_pci_enable_dma,
1550 .set_bus_width = sdhci_pci_set_bus_width,
1551 .reset = sdhci_reset,
1552 .set_uhs_signaling = sdhci_set_uhs_signaling,
1553 .hw_reset = sdhci_pci_hw_reset,
1554 .select_drive_strength = sdhci_pci_select_drive_strength,
1555};
1556
1557/*****************************************************************************\
1558 * *
1559 * Suspend/resume *
1560 * *
1561\*****************************************************************************/
1562
1563#ifdef CONFIG_PM_SLEEP
1564static int sdhci_pci_suspend(struct device *dev)
1565{
1566 struct pci_dev *pdev = to_pci_dev(dev);
1567 struct sdhci_pci_chip *chip;
1568 struct sdhci_pci_slot *slot;
1569 mmc_pm_flag_t slot_pm_flags;
1570 mmc_pm_flag_t pm_flags = 0;
1571 int i, ret;
1572
1573 chip = pci_get_drvdata(pdev);
1574 if (!chip)
1575 return 0;
1576
1577 for (i = 0; i < chip->num_slots; i++) {
1578 slot = chip->slots[i];
1579 if (!slot)
1580 continue;
1581
1582 ret = sdhci_suspend_host(slot->host);
1583
1584 if (ret)
1585 goto err_pci_suspend;
1586
1587 slot_pm_flags = slot->host->mmc->pm_flags;
1588 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1589 sdhci_enable_irq_wakeups(slot->host);
1590
1591 pm_flags |= slot_pm_flags;
1592 }
1593
1594 if (chip->fixes && chip->fixes->suspend) {
1595 ret = chip->fixes->suspend(chip);
1596 if (ret)
1597 goto err_pci_suspend;
1598 }
1599
1600 if (pm_flags & MMC_PM_KEEP_POWER) {
1601 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1602 device_init_wakeup(dev, true);
1603 else
1604 device_init_wakeup(dev, false);
1605 } else
1606 device_init_wakeup(dev, false);
1607
1608 return 0;
1609
1610err_pci_suspend:
1611 while (--i >= 0)
1612 sdhci_resume_host(chip->slots[i]->host);
1613 return ret;
1614}
1615
1616static int sdhci_pci_resume(struct device *dev)
1617{
1618 struct pci_dev *pdev = to_pci_dev(dev);
1619 struct sdhci_pci_chip *chip;
1620 struct sdhci_pci_slot *slot;
1621 int i, ret;
1622
1623 chip = pci_get_drvdata(pdev);
1624 if (!chip)
1625 return 0;
1626
1627 if (chip->fixes && chip->fixes->resume) {
1628 ret = chip->fixes->resume(chip);
1629 if (ret)
1630 return ret;
1631 }
1632
1633 for (i = 0; i < chip->num_slots; i++) {
1634 slot = chip->slots[i];
1635 if (!slot)
1636 continue;
1637
1638 ret = sdhci_resume_host(slot->host);
1639 if (ret)
1640 return ret;
1641 }
1642
1643 return 0;
1644}
1645#endif
1646
1647#ifdef CONFIG_PM
1648static int sdhci_pci_runtime_suspend(struct device *dev)
1649{
1650 struct pci_dev *pdev = to_pci_dev(dev);
1651 struct sdhci_pci_chip *chip;
1652 struct sdhci_pci_slot *slot;
1653 int i, ret;
1654
1655 chip = pci_get_drvdata(pdev);
1656 if (!chip)
1657 return 0;
1658
1659 for (i = 0; i < chip->num_slots; i++) {
1660 slot = chip->slots[i];
1661 if (!slot)
1662 continue;
1663
1664 ret = sdhci_runtime_suspend_host(slot->host);
1665
1666 if (ret)
1667 goto err_pci_runtime_suspend;
1668 }
1669
1670 if (chip->fixes && chip->fixes->suspend) {
1671 ret = chip->fixes->suspend(chip);
1672 if (ret)
1673 goto err_pci_runtime_suspend;
1674 }
1675
1676 return 0;
1677
1678err_pci_runtime_suspend:
1679 while (--i >= 0)
1680 sdhci_runtime_resume_host(chip->slots[i]->host);
1681 return ret;
1682}
1683
1684static int sdhci_pci_runtime_resume(struct device *dev)
1685{
1686 struct pci_dev *pdev = to_pci_dev(dev);
1687 struct sdhci_pci_chip *chip;
1688 struct sdhci_pci_slot *slot;
1689 int i, ret;
1690
1691 chip = pci_get_drvdata(pdev);
1692 if (!chip)
1693 return 0;
1694
1695 if (chip->fixes && chip->fixes->resume) {
1696 ret = chip->fixes->resume(chip);
1697 if (ret)
1698 return ret;
1699 }
1700
1701 for (i = 0; i < chip->num_slots; i++) {
1702 slot = chip->slots[i];
1703 if (!slot)
1704 continue;
1705
1706 ret = sdhci_runtime_resume_host(slot->host);
1707 if (ret)
1708 return ret;
1709 }
1710
1711 return 0;
1712}
1713#endif
1714
1715static const struct dev_pm_ops sdhci_pci_pm_ops = {
1716 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1717 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1718 sdhci_pci_runtime_resume, NULL)
1719};
1720
1721/*****************************************************************************\
1722 * *
1723 * Device probing/removal *
1724 * *
1725\*****************************************************************************/
1726
1727static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1728 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1729 int slotno)
1730{
1731 struct sdhci_pci_slot *slot;
1732 struct sdhci_host *host;
1733 int ret, bar = first_bar + slotno;
1734
1735 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1736 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1737 return ERR_PTR(-ENODEV);
1738 }
1739
1740 if (pci_resource_len(pdev, bar) < 0x100) {
1741 dev_err(&pdev->dev, "Invalid iomem size. You may "
1742 "experience problems.\n");
1743 }
1744
1745 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1746 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1747 return ERR_PTR(-ENODEV);
1748 }
1749
1750 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1751 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1752 return ERR_PTR(-ENODEV);
1753 }
1754
1755 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1756 if (IS_ERR(host)) {
1757 dev_err(&pdev->dev, "cannot allocate host\n");
1758 return ERR_CAST(host);
1759 }
1760
1761 slot = sdhci_priv(host);
1762
1763 slot->chip = chip;
1764 slot->host = host;
1765 slot->rst_n_gpio = -EINVAL;
1766 slot->cd_gpio = -EINVAL;
1767 slot->cd_idx = -1;
1768
1769 /* Retrieve platform data if there is any */
1770 if (*sdhci_pci_get_data)
1771 slot->data = sdhci_pci_get_data(pdev, slotno);
1772
1773 if (slot->data) {
1774 if (slot->data->setup) {
1775 ret = slot->data->setup(slot->data);
1776 if (ret) {
1777 dev_err(&pdev->dev, "platform setup failed\n");
1778 goto free;
1779 }
1780 }
1781 slot->rst_n_gpio = slot->data->rst_n_gpio;
1782 slot->cd_gpio = slot->data->cd_gpio;
1783 }
1784
1785 host->hw_name = "PCI";
1786 host->ops = chip->fixes && chip->fixes->ops ?
1787 chip->fixes->ops :
1788 &sdhci_pci_ops;
1789 host->quirks = chip->quirks;
1790 host->quirks2 = chip->quirks2;
1791
1792 host->irq = pdev->irq;
1793
1794 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1795 if (ret) {
1796 dev_err(&pdev->dev, "cannot request region\n");
1797 goto cleanup;
1798 }
1799
1800 host->ioaddr = pcim_iomap_table(pdev)[bar];
1801
1802 if (chip->fixes && chip->fixes->probe_slot) {
1803 ret = chip->fixes->probe_slot(slot);
1804 if (ret)
1805 goto cleanup;
1806 }
1807
1808 if (gpio_is_valid(slot->rst_n_gpio)) {
1809 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1810 gpio_direction_output(slot->rst_n_gpio, 1);
1811 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1812 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1813 } else {
1814 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1815 slot->rst_n_gpio = -EINVAL;
1816 }
1817 }
1818
1819 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1820 host->mmc->slotno = slotno;
1821 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1822
1823 if (slot->cd_idx >= 0) {
1824 ret = mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1825 slot->cd_override_level, 0, NULL);
1826 if (ret == -EPROBE_DEFER)
1827 goto remove;
1828
1829 if (ret) {
1830 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1831 slot->cd_idx = -1;
1832 }
1833 }
1834
1835 ret = sdhci_add_host(host);
1836 if (ret)
1837 goto remove;
1838
1839 sdhci_pci_add_own_cd(slot);
1840
1841 /*
1842 * Check if the chip needs a separate GPIO for card detect to wake up
1843 * from runtime suspend. If it is not there, don't allow runtime PM.
1844 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1845 */
1846 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1847 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1848 chip->allow_runtime_pm = false;
1849
1850 return slot;
1851
1852remove:
1853 if (chip->fixes && chip->fixes->remove_slot)
1854 chip->fixes->remove_slot(slot, 0);
1855
1856cleanup:
1857 if (slot->data && slot->data->cleanup)
1858 slot->data->cleanup(slot->data);
1859
1860free:
1861 sdhci_free_host(host);
1862
1863 return ERR_PTR(ret);
1864}
1865
1866static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1867{
1868 int dead;
1869 u32 scratch;
1870
1871 sdhci_pci_remove_own_cd(slot);
1872
1873 dead = 0;
1874 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1875 if (scratch == (u32)-1)
1876 dead = 1;
1877
1878 sdhci_remove_host(slot->host, dead);
1879
1880 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1881 slot->chip->fixes->remove_slot(slot, dead);
1882
1883 if (slot->data && slot->data->cleanup)
1884 slot->data->cleanup(slot->data);
1885
1886 sdhci_free_host(slot->host);
1887}
1888
1889static void sdhci_pci_runtime_pm_allow(struct device *dev)
1890{
1891 pm_suspend_ignore_children(dev, 1);
1892 pm_runtime_set_autosuspend_delay(dev, 50);
1893 pm_runtime_use_autosuspend(dev);
1894 pm_runtime_allow(dev);
1895 /* Stay active until mmc core scans for a card */
1896 pm_runtime_put_noidle(dev);
1897}
1898
1899static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1900{
1901 pm_runtime_forbid(dev);
1902 pm_runtime_get_noresume(dev);
1903}
1904
1905static int sdhci_pci_probe(struct pci_dev *pdev,
1906 const struct pci_device_id *ent)
1907{
1908 struct sdhci_pci_chip *chip;
1909 struct sdhci_pci_slot *slot;
1910
1911 u8 slots, first_bar;
1912 int ret, i;
1913
1914 BUG_ON(pdev == NULL);
1915 BUG_ON(ent == NULL);
1916
1917 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1918 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1919
1920 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1921 if (ret)
1922 return ret;
1923
1924 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1925 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1926 if (slots == 0)
1927 return -ENODEV;
1928
1929 BUG_ON(slots > MAX_SLOTS);
1930
1931 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1932 if (ret)
1933 return ret;
1934
1935 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1936
1937 if (first_bar > 5) {
1938 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1939 return -ENODEV;
1940 }
1941
1942 ret = pcim_enable_device(pdev);
1943 if (ret)
1944 return ret;
1945
1946 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1947 if (!chip)
1948 return -ENOMEM;
1949
1950 chip->pdev = pdev;
1951 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1952 if (chip->fixes) {
1953 chip->quirks = chip->fixes->quirks;
1954 chip->quirks2 = chip->fixes->quirks2;
1955 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1956 }
1957 chip->num_slots = slots;
1958
1959 pci_set_drvdata(pdev, chip);
1960
1961 if (chip->fixes && chip->fixes->probe) {
1962 ret = chip->fixes->probe(chip);
1963 if (ret)
1964 return ret;
1965 }
1966
1967 slots = chip->num_slots; /* Quirk may have changed this */
1968
1969 for (i = 0; i < slots; i++) {
1970 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1971 if (IS_ERR(slot)) {
1972 for (i--; i >= 0; i--)
1973 sdhci_pci_remove_slot(chip->slots[i]);
1974 return PTR_ERR(slot);
1975 }
1976
1977 chip->slots[i] = slot;
1978 }
1979
1980 if (chip->allow_runtime_pm)
1981 sdhci_pci_runtime_pm_allow(&pdev->dev);
1982
1983 return 0;
1984}
1985
1986static void sdhci_pci_remove(struct pci_dev *pdev)
1987{
1988 int i;
1989 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1990
1991 if (chip->allow_runtime_pm)
1992 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1993
1994 for (i = 0; i < chip->num_slots; i++)
1995 sdhci_pci_remove_slot(chip->slots[i]);
1996}
1997
1998static struct pci_driver sdhci_driver = {
1999 .name = "sdhci-pci",
2000 .id_table = pci_ids,
2001 .probe = sdhci_pci_probe,
2002 .remove = sdhci_pci_remove,
2003 .driver = {
2004 .pm = &sdhci_pci_pm_ops
2005 },
2006};
2007
2008module_pci_driver(sdhci_driver);
2009
2010MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2011MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2012MODULE_LICENSE("GPL");