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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#ifndef __AST_DRV_H__
29#define __AST_DRV_H__
30
31#include "drm_fb_helper.h"
32
33#include "ttm/ttm_bo_api.h"
34#include "ttm/ttm_bo_driver.h"
35#include "ttm/ttm_placement.h"
36#include "ttm/ttm_memory.h"
37#include "ttm/ttm_module.h"
38
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41
42#define DRIVER_AUTHOR "Dave Airlie"
43
44#define DRIVER_NAME "ast"
45#define DRIVER_DESC "AST"
46#define DRIVER_DATE "20120228"
47
48#define DRIVER_MAJOR 0
49#define DRIVER_MINOR 1
50#define DRIVER_PATCHLEVEL 0
51
52#define PCI_CHIP_AST2000 0x2000
53#define PCI_CHIP_AST2100 0x2010
54#define PCI_CHIP_AST1180 0x1180
55
56
57enum ast_chip {
58 AST2000,
59 AST2100,
60 AST1100,
61 AST2200,
62 AST2150,
63 AST2300,
64 AST1180,
65};
66
67#define AST_DRAM_512Mx16 0
68#define AST_DRAM_1Gx16 1
69#define AST_DRAM_512Mx32 2
70#define AST_DRAM_1Gx32 3
71#define AST_DRAM_2Gx16 6
72#define AST_DRAM_4Gx16 7
73
74struct ast_fbdev;
75
76struct ast_private {
77 struct drm_device *dev;
78
79 void __iomem *regs;
80 void __iomem *ioregs;
81
82 enum ast_chip chip;
83 bool vga2_clone;
84 uint32_t dram_bus_width;
85 uint32_t dram_type;
86 uint32_t mclk;
87 uint32_t vram_size;
88
89 struct ast_fbdev *fbdev;
90
91 int fb_mtrr;
92
93 struct {
94 struct drm_global_reference mem_global_ref;
95 struct ttm_bo_global_ref bo_global_ref;
96 struct ttm_bo_device bdev;
97 atomic_t validate_sequence;
98 } ttm;
99
100 struct drm_gem_object *cursor_cache;
101 uint64_t cursor_cache_gpu_addr;
102 struct ttm_bo_kmap_obj cache_kmap;
103 int next_cursor;
104};
105
106int ast_driver_load(struct drm_device *dev, unsigned long flags);
107int ast_driver_unload(struct drm_device *dev);
108
109struct ast_gem_object;
110
111#define AST_IO_AR_PORT_WRITE (0x40)
112#define AST_IO_MISC_PORT_WRITE (0x42)
113#define AST_IO_SEQ_PORT (0x44)
114#define AST_DAC_INDEX_READ (0x3c7)
115#define AST_IO_DAC_INDEX_WRITE (0x48)
116#define AST_IO_DAC_DATA (0x49)
117#define AST_IO_GR_PORT (0x4E)
118#define AST_IO_CRTC_PORT (0x54)
119#define AST_IO_INPUT_STATUS1_READ (0x5A)
120#define AST_IO_MISC_PORT_READ (0x4C)
121
122#define __ast_read(x) \
123static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
124u##x val = 0;\
125val = ioread##x(ast->regs + reg); \
126return val;\
127}
128
129__ast_read(8);
130__ast_read(16);
131__ast_read(32)
132
133#define __ast_io_read(x) \
134static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
135u##x val = 0;\
136val = ioread##x(ast->ioregs + reg); \
137return val;\
138}
139
140__ast_io_read(8);
141__ast_io_read(16);
142__ast_io_read(32);
143
144#define __ast_write(x) \
145static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
146 iowrite##x(val, ast->regs + reg);\
147 }
148
149__ast_write(8);
150__ast_write(16);
151__ast_write(32);
152
153#define __ast_io_write(x) \
154static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
155 iowrite##x(val, ast->ioregs + reg);\
156 }
157
158__ast_io_write(8);
159__ast_io_write(16);
160#undef __ast_io_write
161
162static inline void ast_set_index_reg(struct ast_private *ast,
163 uint32_t base, uint8_t index,
164 uint8_t val)
165{
166 ast_io_write16(ast, base, ((u16)val << 8) | index);
167}
168
169void ast_set_index_reg_mask(struct ast_private *ast,
170 uint32_t base, uint8_t index,
171 uint8_t mask, uint8_t val);
172uint8_t ast_get_index_reg(struct ast_private *ast,
173 uint32_t base, uint8_t index);
174uint8_t ast_get_index_reg_mask(struct ast_private *ast,
175 uint32_t base, uint8_t index, uint8_t mask);
176
177static inline void ast_open_key(struct ast_private *ast)
178{
179 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xA1, 0xFF, 0x04);
180}
181
182#define AST_VIDMEM_SIZE_8M 0x00800000
183#define AST_VIDMEM_SIZE_16M 0x01000000
184#define AST_VIDMEM_SIZE_32M 0x02000000
185#define AST_VIDMEM_SIZE_64M 0x04000000
186#define AST_VIDMEM_SIZE_128M 0x08000000
187
188#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
189
190#define AST_MAX_HWC_WIDTH 64
191#define AST_MAX_HWC_HEIGHT 64
192
193#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2)
194#define AST_HWC_SIGNATURE_SIZE 32
195
196#define AST_DEFAULT_HWC_NUM 2
197/* define for signature structure */
198#define AST_HWC_SIGNATURE_CHECKSUM 0x00
199#define AST_HWC_SIGNATURE_SizeX 0x04
200#define AST_HWC_SIGNATURE_SizeY 0x08
201#define AST_HWC_SIGNATURE_X 0x0C
202#define AST_HWC_SIGNATURE_Y 0x10
203#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
204#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
205
206
207struct ast_i2c_chan {
208 struct i2c_adapter adapter;
209 struct drm_device *dev;
210 struct i2c_algo_bit_data bit;
211};
212
213struct ast_connector {
214 struct drm_connector base;
215 struct ast_i2c_chan *i2c;
216};
217
218struct ast_crtc {
219 struct drm_crtc base;
220 u8 lut_r[256], lut_g[256], lut_b[256];
221 struct drm_gem_object *cursor_bo;
222 uint64_t cursor_addr;
223 int cursor_width, cursor_height;
224 u8 offset_x, offset_y;
225};
226
227struct ast_encoder {
228 struct drm_encoder base;
229};
230
231struct ast_framebuffer {
232 struct drm_framebuffer base;
233 struct drm_gem_object *obj;
234};
235
236struct ast_fbdev {
237 struct drm_fb_helper helper;
238 struct ast_framebuffer afb;
239 struct list_head fbdev_list;
240 void *sysram;
241 int size;
242 struct ttm_bo_kmap_obj mapping;
243};
244
245#define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
246#define to_ast_connector(x) container_of(x, struct ast_connector, base)
247#define to_ast_encoder(x) container_of(x, struct ast_encoder, base)
248#define to_ast_framebuffer(x) container_of(x, struct ast_framebuffer, base)
249
250struct ast_vbios_stdtable {
251 u8 misc;
252 u8 seq[4];
253 u8 crtc[25];
254 u8 ar[20];
255 u8 gr[9];
256};
257
258struct ast_vbios_enhtable {
259 u32 ht;
260 u32 hde;
261 u32 hfp;
262 u32 hsync;
263 u32 vt;
264 u32 vde;
265 u32 vfp;
266 u32 vsync;
267 u32 dclk_index;
268 u32 flags;
269 u32 refresh_rate;
270 u32 refresh_rate_index;
271 u32 mode_id;
272};
273
274struct ast_vbios_dclk_info {
275 u8 param1;
276 u8 param2;
277 u8 param3;
278};
279
280struct ast_vbios_mode_info {
281 struct ast_vbios_stdtable *std_table;
282 struct ast_vbios_enhtable *enh_table;
283};
284
285extern int ast_mode_init(struct drm_device *dev);
286extern void ast_mode_fini(struct drm_device *dev);
287
288int ast_framebuffer_init(struct drm_device *dev,
289 struct ast_framebuffer *ast_fb,
290 struct drm_mode_fb_cmd2 *mode_cmd,
291 struct drm_gem_object *obj);
292
293int ast_fbdev_init(struct drm_device *dev);
294void ast_fbdev_fini(struct drm_device *dev);
295void ast_fbdev_set_suspend(struct drm_device *dev, int state);
296
297struct ast_bo {
298 struct ttm_buffer_object bo;
299 struct ttm_placement placement;
300 struct ttm_bo_kmap_obj kmap;
301 struct drm_gem_object gem;
302 u32 placements[3];
303 int pin_count;
304};
305#define gem_to_ast_bo(gobj) container_of((gobj), struct ast_bo, gem)
306
307static inline struct ast_bo *
308ast_bo(struct ttm_buffer_object *bo)
309{
310 return container_of(bo, struct ast_bo, bo);
311}
312
313
314#define to_ast_obj(x) container_of(x, struct ast_gem_object, base)
315
316#define AST_MM_ALIGN_SHIFT 4
317#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
318
319extern int ast_dumb_create(struct drm_file *file,
320 struct drm_device *dev,
321 struct drm_mode_create_dumb *args);
322extern int ast_dumb_destroy(struct drm_file *file,
323 struct drm_device *dev,
324 uint32_t handle);
325
326extern int ast_gem_init_object(struct drm_gem_object *obj);
327extern void ast_gem_free_object(struct drm_gem_object *obj);
328extern int ast_dumb_mmap_offset(struct drm_file *file,
329 struct drm_device *dev,
330 uint32_t handle,
331 uint64_t *offset);
332
333#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
334
335int ast_mm_init(struct ast_private *ast);
336void ast_mm_fini(struct ast_private *ast);
337
338int ast_bo_create(struct drm_device *dev, int size, int align,
339 uint32_t flags, struct ast_bo **pastbo);
340
341int ast_gem_create(struct drm_device *dev,
342 u32 size, bool iskernel,
343 struct drm_gem_object **obj);
344
345int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr);
346int ast_bo_unpin(struct ast_bo *bo);
347
348int ast_bo_reserve(struct ast_bo *bo, bool no_wait);
349void ast_bo_unreserve(struct ast_bo *bo);
350void ast_ttm_placement(struct ast_bo *bo, int domain);
351int ast_bo_push_sysram(struct ast_bo *bo);
352int ast_mmap(struct file *filp, struct vm_area_struct *vma);
353
354/* ast post */
355void ast_post_gpu(struct drm_device *dev);
356#endif
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#ifndef __AST_DRV_H__
29#define __AST_DRV_H__
30
31#include <drm/drm_fb_helper.h>
32
33#include <drm/ttm/ttm_bo_api.h>
34#include <drm/ttm/ttm_bo_driver.h>
35#include <drm/ttm/ttm_placement.h>
36#include <drm/ttm/ttm_memory.h>
37#include <drm/ttm/ttm_module.h>
38
39#include <drm/drm_gem.h>
40
41#include <linux/i2c.h>
42#include <linux/i2c-algo-bit.h>
43
44#define DRIVER_AUTHOR "Dave Airlie"
45
46#define DRIVER_NAME "ast"
47#define DRIVER_DESC "AST"
48#define DRIVER_DATE "20120228"
49
50#define DRIVER_MAJOR 0
51#define DRIVER_MINOR 1
52#define DRIVER_PATCHLEVEL 0
53
54#define PCI_CHIP_AST2000 0x2000
55#define PCI_CHIP_AST2100 0x2010
56#define PCI_CHIP_AST1180 0x1180
57
58
59enum ast_chip {
60 AST2000,
61 AST2100,
62 AST1100,
63 AST2200,
64 AST2150,
65 AST2300,
66 AST2400,
67 AST1180,
68};
69
70enum ast_tx_chip {
71 AST_TX_NONE,
72 AST_TX_SIL164,
73 AST_TX_ITE66121,
74 AST_TX_DP501,
75};
76
77#define AST_DRAM_512Mx16 0
78#define AST_DRAM_1Gx16 1
79#define AST_DRAM_512Mx32 2
80#define AST_DRAM_1Gx32 3
81#define AST_DRAM_2Gx16 6
82#define AST_DRAM_4Gx16 7
83
84struct ast_fbdev;
85
86struct ast_private {
87 struct drm_device *dev;
88
89 void __iomem *regs;
90 void __iomem *ioregs;
91
92 enum ast_chip chip;
93 bool vga2_clone;
94 uint32_t dram_bus_width;
95 uint32_t dram_type;
96 uint32_t mclk;
97 uint32_t vram_size;
98
99 struct ast_fbdev *fbdev;
100
101 int fb_mtrr;
102
103 struct {
104 struct drm_global_reference mem_global_ref;
105 struct ttm_bo_global_ref bo_global_ref;
106 struct ttm_bo_device bdev;
107 } ttm;
108
109 struct drm_gem_object *cursor_cache;
110 uint64_t cursor_cache_gpu_addr;
111 /* Acces to this cache is protected by the crtc->mutex of the only crtc
112 * we have. */
113 struct ttm_bo_kmap_obj cache_kmap;
114 int next_cursor;
115 bool support_wide_screen;
116 enum {
117 ast_use_p2a,
118 ast_use_dt,
119 ast_use_defaults
120 } config_mode;
121
122 enum ast_tx_chip tx_chip_type;
123 u8 dp501_maxclk;
124 u8 *dp501_fw_addr;
125 const struct firmware *dp501_fw; /* dp501 fw */
126};
127
128int ast_driver_load(struct drm_device *dev, unsigned long flags);
129int ast_driver_unload(struct drm_device *dev);
130
131struct ast_gem_object;
132
133#define AST_IO_AR_PORT_WRITE (0x40)
134#define AST_IO_MISC_PORT_WRITE (0x42)
135#define AST_IO_VGA_ENABLE_PORT (0x43)
136#define AST_IO_SEQ_PORT (0x44)
137#define AST_IO_DAC_INDEX_READ (0x47)
138#define AST_IO_DAC_INDEX_WRITE (0x48)
139#define AST_IO_DAC_DATA (0x49)
140#define AST_IO_GR_PORT (0x4E)
141#define AST_IO_CRTC_PORT (0x54)
142#define AST_IO_INPUT_STATUS1_READ (0x5A)
143#define AST_IO_MISC_PORT_READ (0x4C)
144
145#define AST_IO_MM_OFFSET (0x380)
146
147#define __ast_read(x) \
148static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
149u##x val = 0;\
150val = ioread##x(ast->regs + reg); \
151return val;\
152}
153
154__ast_read(8);
155__ast_read(16);
156__ast_read(32)
157
158#define __ast_io_read(x) \
159static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
160u##x val = 0;\
161val = ioread##x(ast->ioregs + reg); \
162return val;\
163}
164
165__ast_io_read(8);
166__ast_io_read(16);
167__ast_io_read(32);
168
169#define __ast_write(x) \
170static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
171 iowrite##x(val, ast->regs + reg);\
172 }
173
174__ast_write(8);
175__ast_write(16);
176__ast_write(32);
177
178#define __ast_io_write(x) \
179static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
180 iowrite##x(val, ast->ioregs + reg);\
181 }
182
183__ast_io_write(8);
184__ast_io_write(16);
185#undef __ast_io_write
186
187static inline void ast_set_index_reg(struct ast_private *ast,
188 uint32_t base, uint8_t index,
189 uint8_t val)
190{
191 ast_io_write16(ast, base, ((u16)val << 8) | index);
192}
193
194void ast_set_index_reg_mask(struct ast_private *ast,
195 uint32_t base, uint8_t index,
196 uint8_t mask, uint8_t val);
197uint8_t ast_get_index_reg(struct ast_private *ast,
198 uint32_t base, uint8_t index);
199uint8_t ast_get_index_reg_mask(struct ast_private *ast,
200 uint32_t base, uint8_t index, uint8_t mask);
201
202static inline void ast_open_key(struct ast_private *ast)
203{
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
205}
206
207#define AST_VIDMEM_SIZE_8M 0x00800000
208#define AST_VIDMEM_SIZE_16M 0x01000000
209#define AST_VIDMEM_SIZE_32M 0x02000000
210#define AST_VIDMEM_SIZE_64M 0x04000000
211#define AST_VIDMEM_SIZE_128M 0x08000000
212
213#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
214
215#define AST_MAX_HWC_WIDTH 64
216#define AST_MAX_HWC_HEIGHT 64
217
218#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH*AST_MAX_HWC_HEIGHT*2)
219#define AST_HWC_SIGNATURE_SIZE 32
220
221#define AST_DEFAULT_HWC_NUM 2
222/* define for signature structure */
223#define AST_HWC_SIGNATURE_CHECKSUM 0x00
224#define AST_HWC_SIGNATURE_SizeX 0x04
225#define AST_HWC_SIGNATURE_SizeY 0x08
226#define AST_HWC_SIGNATURE_X 0x0C
227#define AST_HWC_SIGNATURE_Y 0x10
228#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
229#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
230
231
232struct ast_i2c_chan {
233 struct i2c_adapter adapter;
234 struct drm_device *dev;
235 struct i2c_algo_bit_data bit;
236};
237
238struct ast_connector {
239 struct drm_connector base;
240 struct ast_i2c_chan *i2c;
241};
242
243struct ast_crtc {
244 struct drm_crtc base;
245 u8 lut_r[256], lut_g[256], lut_b[256];
246 struct drm_gem_object *cursor_bo;
247 uint64_t cursor_addr;
248 int cursor_width, cursor_height;
249 u8 offset_x, offset_y;
250};
251
252struct ast_encoder {
253 struct drm_encoder base;
254};
255
256struct ast_framebuffer {
257 struct drm_framebuffer base;
258 struct drm_gem_object *obj;
259};
260
261struct ast_fbdev {
262 struct drm_fb_helper helper;
263 struct ast_framebuffer afb;
264 void *sysram;
265 int size;
266 struct ttm_bo_kmap_obj mapping;
267 int x1, y1, x2, y2; /* dirty rect */
268 spinlock_t dirty_lock;
269};
270
271#define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
272#define to_ast_connector(x) container_of(x, struct ast_connector, base)
273#define to_ast_encoder(x) container_of(x, struct ast_encoder, base)
274#define to_ast_framebuffer(x) container_of(x, struct ast_framebuffer, base)
275
276struct ast_vbios_stdtable {
277 u8 misc;
278 u8 seq[4];
279 u8 crtc[25];
280 u8 ar[20];
281 u8 gr[9];
282};
283
284struct ast_vbios_enhtable {
285 u32 ht;
286 u32 hde;
287 u32 hfp;
288 u32 hsync;
289 u32 vt;
290 u32 vde;
291 u32 vfp;
292 u32 vsync;
293 u32 dclk_index;
294 u32 flags;
295 u32 refresh_rate;
296 u32 refresh_rate_index;
297 u32 mode_id;
298};
299
300struct ast_vbios_dclk_info {
301 u8 param1;
302 u8 param2;
303 u8 param3;
304};
305
306struct ast_vbios_mode_info {
307 struct ast_vbios_stdtable *std_table;
308 struct ast_vbios_enhtable *enh_table;
309};
310
311extern int ast_mode_init(struct drm_device *dev);
312extern void ast_mode_fini(struct drm_device *dev);
313
314int ast_framebuffer_init(struct drm_device *dev,
315 struct ast_framebuffer *ast_fb,
316 const struct drm_mode_fb_cmd2 *mode_cmd,
317 struct drm_gem_object *obj);
318
319int ast_fbdev_init(struct drm_device *dev);
320void ast_fbdev_fini(struct drm_device *dev);
321void ast_fbdev_set_suspend(struct drm_device *dev, int state);
322void ast_fbdev_set_base(struct ast_private *ast, unsigned long gpu_addr);
323
324struct ast_bo {
325 struct ttm_buffer_object bo;
326 struct ttm_placement placement;
327 struct ttm_bo_kmap_obj kmap;
328 struct drm_gem_object gem;
329 struct ttm_place placements[3];
330 int pin_count;
331};
332#define gem_to_ast_bo(gobj) container_of((gobj), struct ast_bo, gem)
333
334static inline struct ast_bo *
335ast_bo(struct ttm_buffer_object *bo)
336{
337 return container_of(bo, struct ast_bo, bo);
338}
339
340
341#define to_ast_obj(x) container_of(x, struct ast_gem_object, base)
342
343#define AST_MM_ALIGN_SHIFT 4
344#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
345
346extern int ast_dumb_create(struct drm_file *file,
347 struct drm_device *dev,
348 struct drm_mode_create_dumb *args);
349
350extern void ast_gem_free_object(struct drm_gem_object *obj);
351extern int ast_dumb_mmap_offset(struct drm_file *file,
352 struct drm_device *dev,
353 uint32_t handle,
354 uint64_t *offset);
355
356#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
357
358int ast_mm_init(struct ast_private *ast);
359void ast_mm_fini(struct ast_private *ast);
360
361int ast_bo_create(struct drm_device *dev, int size, int align,
362 uint32_t flags, struct ast_bo **pastbo);
363
364int ast_gem_create(struct drm_device *dev,
365 u32 size, bool iskernel,
366 struct drm_gem_object **obj);
367
368int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr);
369int ast_bo_unpin(struct ast_bo *bo);
370
371static inline int ast_bo_reserve(struct ast_bo *bo, bool no_wait)
372{
373 int ret;
374
375 ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL);
376 if (ret) {
377 if (ret != -ERESTARTSYS && ret != -EBUSY)
378 DRM_ERROR("reserve failed %p\n", bo);
379 return ret;
380 }
381 return 0;
382}
383
384static inline void ast_bo_unreserve(struct ast_bo *bo)
385{
386 ttm_bo_unreserve(&bo->bo);
387}
388
389void ast_ttm_placement(struct ast_bo *bo, int domain);
390int ast_bo_push_sysram(struct ast_bo *bo);
391int ast_mmap(struct file *filp, struct vm_area_struct *vma);
392
393/* ast post */
394void ast_enable_vga(struct drm_device *dev);
395void ast_enable_mmio(struct drm_device *dev);
396bool ast_is_vga_enabled(struct drm_device *dev);
397void ast_post_gpu(struct drm_device *dev);
398u32 ast_mindwm(struct ast_private *ast, u32 r);
399void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
400/* ast dp501 */
401int ast_load_dp501_microcode(struct drm_device *dev);
402void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
403bool ast_launch_m68k(struct drm_device *dev);
404bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
405bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
406u8 ast_get_dp501_max_clk(struct drm_device *dev);
407void ast_init_3rdtx(struct drm_device *dev);
408#endif