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1/* arch/sparc64/kernel/traps.c
2 *
3 * Copyright (C) 1995,1997,2008,2009 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
5 */
6
7/*
8 * I like traps on v9, :))))
9 */
10
11#include <linux/module.h>
12#include <linux/sched.h>
13#include <linux/linkage.h>
14#include <linux/kernel.h>
15#include <linux/signal.h>
16#include <linux/smp.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/kdebug.h>
20#include <linux/ftrace.h>
21#include <linux/gfp.h>
22
23#include <asm/smp.h>
24#include <asm/delay.h>
25#include <asm/ptrace.h>
26#include <asm/oplib.h>
27#include <asm/page.h>
28#include <asm/pgtable.h>
29#include <asm/unistd.h>
30#include <asm/uaccess.h>
31#include <asm/fpumacro.h>
32#include <asm/lsu.h>
33#include <asm/dcu.h>
34#include <asm/estate.h>
35#include <asm/chafsr.h>
36#include <asm/sfafsr.h>
37#include <asm/psrcompat.h>
38#include <asm/processor.h>
39#include <asm/timer.h>
40#include <asm/head.h>
41#include <asm/prom.h>
42#include <asm/memctrl.h>
43#include <asm/cacheflush.h>
44
45#include "entry.h"
46#include "kstack.h"
47
48/* When an irrecoverable trap occurs at tl > 0, the trap entry
49 * code logs the trap state registers at every level in the trap
50 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
51 * is as follows:
52 */
53struct tl1_traplog {
54 struct {
55 unsigned long tstate;
56 unsigned long tpc;
57 unsigned long tnpc;
58 unsigned long tt;
59 } trapstack[4];
60 unsigned long tl;
61};
62
63static void dump_tl1_traplog(struct tl1_traplog *p)
64{
65 int i, limit;
66
67 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
68 "dumping track stack.\n", p->tl);
69
70 limit = (tlb_type == hypervisor) ? 2 : 4;
71 for (i = 0; i < limit; i++) {
72 printk(KERN_EMERG
73 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
74 "TNPC[%016lx] TT[%lx]\n",
75 i + 1,
76 p->trapstack[i].tstate, p->trapstack[i].tpc,
77 p->trapstack[i].tnpc, p->trapstack[i].tt);
78 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
79 }
80}
81
82void bad_trap(struct pt_regs *regs, long lvl)
83{
84 char buffer[32];
85 siginfo_t info;
86
87 if (notify_die(DIE_TRAP, "bad trap", regs,
88 0, lvl, SIGTRAP) == NOTIFY_STOP)
89 return;
90
91 if (lvl < 0x100) {
92 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
93 die_if_kernel(buffer, regs);
94 }
95
96 lvl -= 0x100;
97 if (regs->tstate & TSTATE_PRIV) {
98 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
99 die_if_kernel(buffer, regs);
100 }
101 if (test_thread_flag(TIF_32BIT)) {
102 regs->tpc &= 0xffffffff;
103 regs->tnpc &= 0xffffffff;
104 }
105 info.si_signo = SIGILL;
106 info.si_errno = 0;
107 info.si_code = ILL_ILLTRP;
108 info.si_addr = (void __user *)regs->tpc;
109 info.si_trapno = lvl;
110 force_sig_info(SIGILL, &info, current);
111}
112
113void bad_trap_tl1(struct pt_regs *regs, long lvl)
114{
115 char buffer[32];
116
117 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
118 0, lvl, SIGTRAP) == NOTIFY_STOP)
119 return;
120
121 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
122
123 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
124 die_if_kernel (buffer, regs);
125}
126
127#ifdef CONFIG_DEBUG_BUGVERBOSE
128void do_BUG(const char *file, int line)
129{
130 bust_spinlocks(1);
131 printk("kernel BUG at %s:%d!\n", file, line);
132}
133EXPORT_SYMBOL(do_BUG);
134#endif
135
136static DEFINE_SPINLOCK(dimm_handler_lock);
137static dimm_printer_t dimm_handler;
138
139static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
140{
141 unsigned long flags;
142 int ret = -ENODEV;
143
144 spin_lock_irqsave(&dimm_handler_lock, flags);
145 if (dimm_handler) {
146 ret = dimm_handler(synd_code, paddr, buf, buflen);
147 } else if (tlb_type == spitfire) {
148 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
149 ret = -EINVAL;
150 else
151 ret = 0;
152 } else
153 ret = -ENODEV;
154 spin_unlock_irqrestore(&dimm_handler_lock, flags);
155
156 return ret;
157}
158
159int register_dimm_printer(dimm_printer_t func)
160{
161 unsigned long flags;
162 int ret = 0;
163
164 spin_lock_irqsave(&dimm_handler_lock, flags);
165 if (!dimm_handler)
166 dimm_handler = func;
167 else
168 ret = -EEXIST;
169 spin_unlock_irqrestore(&dimm_handler_lock, flags);
170
171 return ret;
172}
173EXPORT_SYMBOL_GPL(register_dimm_printer);
174
175void unregister_dimm_printer(dimm_printer_t func)
176{
177 unsigned long flags;
178
179 spin_lock_irqsave(&dimm_handler_lock, flags);
180 if (dimm_handler == func)
181 dimm_handler = NULL;
182 spin_unlock_irqrestore(&dimm_handler_lock, flags);
183}
184EXPORT_SYMBOL_GPL(unregister_dimm_printer);
185
186void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
187{
188 siginfo_t info;
189
190 if (notify_die(DIE_TRAP, "instruction access exception", regs,
191 0, 0x8, SIGTRAP) == NOTIFY_STOP)
192 return;
193
194 if (regs->tstate & TSTATE_PRIV) {
195 printk("spitfire_insn_access_exception: SFSR[%016lx] "
196 "SFAR[%016lx], going.\n", sfsr, sfar);
197 die_if_kernel("Iax", regs);
198 }
199 if (test_thread_flag(TIF_32BIT)) {
200 regs->tpc &= 0xffffffff;
201 regs->tnpc &= 0xffffffff;
202 }
203 info.si_signo = SIGSEGV;
204 info.si_errno = 0;
205 info.si_code = SEGV_MAPERR;
206 info.si_addr = (void __user *)regs->tpc;
207 info.si_trapno = 0;
208 force_sig_info(SIGSEGV, &info, current);
209}
210
211void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
212{
213 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
214 0, 0x8, SIGTRAP) == NOTIFY_STOP)
215 return;
216
217 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
218 spitfire_insn_access_exception(regs, sfsr, sfar);
219}
220
221void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
222{
223 unsigned short type = (type_ctx >> 16);
224 unsigned short ctx = (type_ctx & 0xffff);
225 siginfo_t info;
226
227 if (notify_die(DIE_TRAP, "instruction access exception", regs,
228 0, 0x8, SIGTRAP) == NOTIFY_STOP)
229 return;
230
231 if (regs->tstate & TSTATE_PRIV) {
232 printk("sun4v_insn_access_exception: ADDR[%016lx] "
233 "CTX[%04x] TYPE[%04x], going.\n",
234 addr, ctx, type);
235 die_if_kernel("Iax", regs);
236 }
237
238 if (test_thread_flag(TIF_32BIT)) {
239 regs->tpc &= 0xffffffff;
240 regs->tnpc &= 0xffffffff;
241 }
242 info.si_signo = SIGSEGV;
243 info.si_errno = 0;
244 info.si_code = SEGV_MAPERR;
245 info.si_addr = (void __user *) addr;
246 info.si_trapno = 0;
247 force_sig_info(SIGSEGV, &info, current);
248}
249
250void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
251{
252 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
253 0, 0x8, SIGTRAP) == NOTIFY_STOP)
254 return;
255
256 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
257 sun4v_insn_access_exception(regs, addr, type_ctx);
258}
259
260void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
261{
262 siginfo_t info;
263
264 if (notify_die(DIE_TRAP, "data access exception", regs,
265 0, 0x30, SIGTRAP) == NOTIFY_STOP)
266 return;
267
268 if (regs->tstate & TSTATE_PRIV) {
269 /* Test if this comes from uaccess places. */
270 const struct exception_table_entry *entry;
271
272 entry = search_exception_tables(regs->tpc);
273 if (entry) {
274 /* Ouch, somebody is trying VM hole tricks on us... */
275#ifdef DEBUG_EXCEPTIONS
276 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
277 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
278 regs->tpc, entry->fixup);
279#endif
280 regs->tpc = entry->fixup;
281 regs->tnpc = regs->tpc + 4;
282 return;
283 }
284 /* Shit... */
285 printk("spitfire_data_access_exception: SFSR[%016lx] "
286 "SFAR[%016lx], going.\n", sfsr, sfar);
287 die_if_kernel("Dax", regs);
288 }
289
290 info.si_signo = SIGSEGV;
291 info.si_errno = 0;
292 info.si_code = SEGV_MAPERR;
293 info.si_addr = (void __user *)sfar;
294 info.si_trapno = 0;
295 force_sig_info(SIGSEGV, &info, current);
296}
297
298void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
299{
300 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
301 0, 0x30, SIGTRAP) == NOTIFY_STOP)
302 return;
303
304 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
305 spitfire_data_access_exception(regs, sfsr, sfar);
306}
307
308void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
309{
310 unsigned short type = (type_ctx >> 16);
311 unsigned short ctx = (type_ctx & 0xffff);
312 siginfo_t info;
313
314 if (notify_die(DIE_TRAP, "data access exception", regs,
315 0, 0x8, SIGTRAP) == NOTIFY_STOP)
316 return;
317
318 if (regs->tstate & TSTATE_PRIV) {
319 /* Test if this comes from uaccess places. */
320 const struct exception_table_entry *entry;
321
322 entry = search_exception_tables(regs->tpc);
323 if (entry) {
324 /* Ouch, somebody is trying VM hole tricks on us... */
325#ifdef DEBUG_EXCEPTIONS
326 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
327 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
328 regs->tpc, entry->fixup);
329#endif
330 regs->tpc = entry->fixup;
331 regs->tnpc = regs->tpc + 4;
332 return;
333 }
334 printk("sun4v_data_access_exception: ADDR[%016lx] "
335 "CTX[%04x] TYPE[%04x], going.\n",
336 addr, ctx, type);
337 die_if_kernel("Dax", regs);
338 }
339
340 if (test_thread_flag(TIF_32BIT)) {
341 regs->tpc &= 0xffffffff;
342 regs->tnpc &= 0xffffffff;
343 }
344 info.si_signo = SIGSEGV;
345 info.si_errno = 0;
346 info.si_code = SEGV_MAPERR;
347 info.si_addr = (void __user *) addr;
348 info.si_trapno = 0;
349 force_sig_info(SIGSEGV, &info, current);
350}
351
352void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
353{
354 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
355 0, 0x8, SIGTRAP) == NOTIFY_STOP)
356 return;
357
358 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
359 sun4v_data_access_exception(regs, addr, type_ctx);
360}
361
362#ifdef CONFIG_PCI
363#include "pci_impl.h"
364#endif
365
366/* When access exceptions happen, we must do this. */
367static void spitfire_clean_and_reenable_l1_caches(void)
368{
369 unsigned long va;
370
371 if (tlb_type != spitfire)
372 BUG();
373
374 /* Clean 'em. */
375 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
376 spitfire_put_icache_tag(va, 0x0);
377 spitfire_put_dcache_tag(va, 0x0);
378 }
379
380 /* Re-enable in LSU. */
381 __asm__ __volatile__("flush %%g6\n\t"
382 "membar #Sync\n\t"
383 "stxa %0, [%%g0] %1\n\t"
384 "membar #Sync"
385 : /* no outputs */
386 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
387 LSU_CONTROL_IM | LSU_CONTROL_DM),
388 "i" (ASI_LSU_CONTROL)
389 : "memory");
390}
391
392static void spitfire_enable_estate_errors(void)
393{
394 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
395 "membar #Sync"
396 : /* no outputs */
397 : "r" (ESTATE_ERR_ALL),
398 "i" (ASI_ESTATE_ERROR_EN));
399}
400
401static char ecc_syndrome_table[] = {
402 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
403 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
404 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
405 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
406 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
407 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
408 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
409 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
410 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
411 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
412 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
413 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
414 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
415 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
416 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
417 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
418 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
419 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
420 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
421 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
422 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
423 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
424 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
425 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
426 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
427 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
428 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
429 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
430 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
431 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
432 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
433 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
434};
435
436static char *syndrome_unknown = "<Unknown>";
437
438static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
439{
440 unsigned short scode;
441 char memmod_str[64], *p;
442
443 if (udbl & bit) {
444 scode = ecc_syndrome_table[udbl & 0xff];
445 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
446 p = syndrome_unknown;
447 else
448 p = memmod_str;
449 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
450 "Memory Module \"%s\"\n",
451 smp_processor_id(), scode, p);
452 }
453
454 if (udbh & bit) {
455 scode = ecc_syndrome_table[udbh & 0xff];
456 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
457 p = syndrome_unknown;
458 else
459 p = memmod_str;
460 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
461 "Memory Module \"%s\"\n",
462 smp_processor_id(), scode, p);
463 }
464
465}
466
467static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
468{
469
470 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
471 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
472 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
473
474 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
475
476 /* We always log it, even if someone is listening for this
477 * trap.
478 */
479 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
480 0, TRAP_TYPE_CEE, SIGTRAP);
481
482 /* The Correctable ECC Error trap does not disable I/D caches. So
483 * we only have to restore the ESTATE Error Enable register.
484 */
485 spitfire_enable_estate_errors();
486}
487
488static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
489{
490 siginfo_t info;
491
492 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
493 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
494 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
495
496 /* XXX add more human friendly logging of the error status
497 * XXX as is implemented for cheetah
498 */
499
500 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
501
502 /* We always log it, even if someone is listening for this
503 * trap.
504 */
505 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
506 0, tt, SIGTRAP);
507
508 if (regs->tstate & TSTATE_PRIV) {
509 if (tl1)
510 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
511 die_if_kernel("UE", regs);
512 }
513
514 /* XXX need more intelligent processing here, such as is implemented
515 * XXX for cheetah errors, in fact if the E-cache still holds the
516 * XXX line with bad parity this will loop
517 */
518
519 spitfire_clean_and_reenable_l1_caches();
520 spitfire_enable_estate_errors();
521
522 if (test_thread_flag(TIF_32BIT)) {
523 regs->tpc &= 0xffffffff;
524 regs->tnpc &= 0xffffffff;
525 }
526 info.si_signo = SIGBUS;
527 info.si_errno = 0;
528 info.si_code = BUS_OBJERR;
529 info.si_addr = (void *)0;
530 info.si_trapno = 0;
531 force_sig_info(SIGBUS, &info, current);
532}
533
534void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
535{
536 unsigned long afsr, tt, udbh, udbl;
537 int tl1;
538
539 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
540 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
541 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
542 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
543 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
544
545#ifdef CONFIG_PCI
546 if (tt == TRAP_TYPE_DAE &&
547 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
548 spitfire_clean_and_reenable_l1_caches();
549 spitfire_enable_estate_errors();
550
551 pci_poke_faulted = 1;
552 regs->tnpc = regs->tpc + 4;
553 return;
554 }
555#endif
556
557 if (afsr & SFAFSR_UE)
558 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
559
560 if (tt == TRAP_TYPE_CEE) {
561 /* Handle the case where we took a CEE trap, but ACK'd
562 * only the UE state in the UDB error registers.
563 */
564 if (afsr & SFAFSR_UE) {
565 if (udbh & UDBE_CE) {
566 __asm__ __volatile__(
567 "stxa %0, [%1] %2\n\t"
568 "membar #Sync"
569 : /* no outputs */
570 : "r" (udbh & UDBE_CE),
571 "r" (0x0), "i" (ASI_UDB_ERROR_W));
572 }
573 if (udbl & UDBE_CE) {
574 __asm__ __volatile__(
575 "stxa %0, [%1] %2\n\t"
576 "membar #Sync"
577 : /* no outputs */
578 : "r" (udbl & UDBE_CE),
579 "r" (0x18), "i" (ASI_UDB_ERROR_W));
580 }
581 }
582
583 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
584 }
585}
586
587int cheetah_pcache_forced_on;
588
589void cheetah_enable_pcache(void)
590{
591 unsigned long dcr;
592
593 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
594 smp_processor_id());
595
596 __asm__ __volatile__("ldxa [%%g0] %1, %0"
597 : "=r" (dcr)
598 : "i" (ASI_DCU_CONTROL_REG));
599 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
600 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
601 "membar #Sync"
602 : /* no outputs */
603 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
604}
605
606/* Cheetah error trap handling. */
607static unsigned long ecache_flush_physbase;
608static unsigned long ecache_flush_linesize;
609static unsigned long ecache_flush_size;
610
611/* This table is ordered in priority of errors and matches the
612 * AFAR overwrite policy as well.
613 */
614
615struct afsr_error_table {
616 unsigned long mask;
617 const char *name;
618};
619
620static const char CHAFSR_PERR_msg[] =
621 "System interface protocol error";
622static const char CHAFSR_IERR_msg[] =
623 "Internal processor error";
624static const char CHAFSR_ISAP_msg[] =
625 "System request parity error on incoming address";
626static const char CHAFSR_UCU_msg[] =
627 "Uncorrectable E-cache ECC error for ifetch/data";
628static const char CHAFSR_UCC_msg[] =
629 "SW Correctable E-cache ECC error for ifetch/data";
630static const char CHAFSR_UE_msg[] =
631 "Uncorrectable system bus data ECC error for read";
632static const char CHAFSR_EDU_msg[] =
633 "Uncorrectable E-cache ECC error for stmerge/blkld";
634static const char CHAFSR_EMU_msg[] =
635 "Uncorrectable system bus MTAG error";
636static const char CHAFSR_WDU_msg[] =
637 "Uncorrectable E-cache ECC error for writeback";
638static const char CHAFSR_CPU_msg[] =
639 "Uncorrectable ECC error for copyout";
640static const char CHAFSR_CE_msg[] =
641 "HW corrected system bus data ECC error for read";
642static const char CHAFSR_EDC_msg[] =
643 "HW corrected E-cache ECC error for stmerge/blkld";
644static const char CHAFSR_EMC_msg[] =
645 "HW corrected system bus MTAG ECC error";
646static const char CHAFSR_WDC_msg[] =
647 "HW corrected E-cache ECC error for writeback";
648static const char CHAFSR_CPC_msg[] =
649 "HW corrected ECC error for copyout";
650static const char CHAFSR_TO_msg[] =
651 "Unmapped error from system bus";
652static const char CHAFSR_BERR_msg[] =
653 "Bus error response from system bus";
654static const char CHAFSR_IVC_msg[] =
655 "HW corrected system bus data ECC error for ivec read";
656static const char CHAFSR_IVU_msg[] =
657 "Uncorrectable system bus data ECC error for ivec read";
658static struct afsr_error_table __cheetah_error_table[] = {
659 { CHAFSR_PERR, CHAFSR_PERR_msg },
660 { CHAFSR_IERR, CHAFSR_IERR_msg },
661 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
662 { CHAFSR_UCU, CHAFSR_UCU_msg },
663 { CHAFSR_UCC, CHAFSR_UCC_msg },
664 { CHAFSR_UE, CHAFSR_UE_msg },
665 { CHAFSR_EDU, CHAFSR_EDU_msg },
666 { CHAFSR_EMU, CHAFSR_EMU_msg },
667 { CHAFSR_WDU, CHAFSR_WDU_msg },
668 { CHAFSR_CPU, CHAFSR_CPU_msg },
669 { CHAFSR_CE, CHAFSR_CE_msg },
670 { CHAFSR_EDC, CHAFSR_EDC_msg },
671 { CHAFSR_EMC, CHAFSR_EMC_msg },
672 { CHAFSR_WDC, CHAFSR_WDC_msg },
673 { CHAFSR_CPC, CHAFSR_CPC_msg },
674 { CHAFSR_TO, CHAFSR_TO_msg },
675 { CHAFSR_BERR, CHAFSR_BERR_msg },
676 /* These two do not update the AFAR. */
677 { CHAFSR_IVC, CHAFSR_IVC_msg },
678 { CHAFSR_IVU, CHAFSR_IVU_msg },
679 { 0, NULL },
680};
681static const char CHPAFSR_DTO_msg[] =
682 "System bus unmapped error for prefetch/storequeue-read";
683static const char CHPAFSR_DBERR_msg[] =
684 "System bus error for prefetch/storequeue-read";
685static const char CHPAFSR_THCE_msg[] =
686 "Hardware corrected E-cache Tag ECC error";
687static const char CHPAFSR_TSCE_msg[] =
688 "SW handled correctable E-cache Tag ECC error";
689static const char CHPAFSR_TUE_msg[] =
690 "Uncorrectable E-cache Tag ECC error";
691static const char CHPAFSR_DUE_msg[] =
692 "System bus uncorrectable data ECC error due to prefetch/store-fill";
693static struct afsr_error_table __cheetah_plus_error_table[] = {
694 { CHAFSR_PERR, CHAFSR_PERR_msg },
695 { CHAFSR_IERR, CHAFSR_IERR_msg },
696 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
697 { CHAFSR_UCU, CHAFSR_UCU_msg },
698 { CHAFSR_UCC, CHAFSR_UCC_msg },
699 { CHAFSR_UE, CHAFSR_UE_msg },
700 { CHAFSR_EDU, CHAFSR_EDU_msg },
701 { CHAFSR_EMU, CHAFSR_EMU_msg },
702 { CHAFSR_WDU, CHAFSR_WDU_msg },
703 { CHAFSR_CPU, CHAFSR_CPU_msg },
704 { CHAFSR_CE, CHAFSR_CE_msg },
705 { CHAFSR_EDC, CHAFSR_EDC_msg },
706 { CHAFSR_EMC, CHAFSR_EMC_msg },
707 { CHAFSR_WDC, CHAFSR_WDC_msg },
708 { CHAFSR_CPC, CHAFSR_CPC_msg },
709 { CHAFSR_TO, CHAFSR_TO_msg },
710 { CHAFSR_BERR, CHAFSR_BERR_msg },
711 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
712 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
713 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
714 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
715 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
716 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
717 /* These two do not update the AFAR. */
718 { CHAFSR_IVC, CHAFSR_IVC_msg },
719 { CHAFSR_IVU, CHAFSR_IVU_msg },
720 { 0, NULL },
721};
722static const char JPAFSR_JETO_msg[] =
723 "System interface protocol error, hw timeout caused";
724static const char JPAFSR_SCE_msg[] =
725 "Parity error on system snoop results";
726static const char JPAFSR_JEIC_msg[] =
727 "System interface protocol error, illegal command detected";
728static const char JPAFSR_JEIT_msg[] =
729 "System interface protocol error, illegal ADTYPE detected";
730static const char JPAFSR_OM_msg[] =
731 "Out of range memory error has occurred";
732static const char JPAFSR_ETP_msg[] =
733 "Parity error on L2 cache tag SRAM";
734static const char JPAFSR_UMS_msg[] =
735 "Error due to unsupported store";
736static const char JPAFSR_RUE_msg[] =
737 "Uncorrectable ECC error from remote cache/memory";
738static const char JPAFSR_RCE_msg[] =
739 "Correctable ECC error from remote cache/memory";
740static const char JPAFSR_BP_msg[] =
741 "JBUS parity error on returned read data";
742static const char JPAFSR_WBP_msg[] =
743 "JBUS parity error on data for writeback or block store";
744static const char JPAFSR_FRC_msg[] =
745 "Foreign read to DRAM incurring correctable ECC error";
746static const char JPAFSR_FRU_msg[] =
747 "Foreign read to DRAM incurring uncorrectable ECC error";
748static struct afsr_error_table __jalapeno_error_table[] = {
749 { JPAFSR_JETO, JPAFSR_JETO_msg },
750 { JPAFSR_SCE, JPAFSR_SCE_msg },
751 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
752 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
753 { CHAFSR_PERR, CHAFSR_PERR_msg },
754 { CHAFSR_IERR, CHAFSR_IERR_msg },
755 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
756 { CHAFSR_UCU, CHAFSR_UCU_msg },
757 { CHAFSR_UCC, CHAFSR_UCC_msg },
758 { CHAFSR_UE, CHAFSR_UE_msg },
759 { CHAFSR_EDU, CHAFSR_EDU_msg },
760 { JPAFSR_OM, JPAFSR_OM_msg },
761 { CHAFSR_WDU, CHAFSR_WDU_msg },
762 { CHAFSR_CPU, CHAFSR_CPU_msg },
763 { CHAFSR_CE, CHAFSR_CE_msg },
764 { CHAFSR_EDC, CHAFSR_EDC_msg },
765 { JPAFSR_ETP, JPAFSR_ETP_msg },
766 { CHAFSR_WDC, CHAFSR_WDC_msg },
767 { CHAFSR_CPC, CHAFSR_CPC_msg },
768 { CHAFSR_TO, CHAFSR_TO_msg },
769 { CHAFSR_BERR, CHAFSR_BERR_msg },
770 { JPAFSR_UMS, JPAFSR_UMS_msg },
771 { JPAFSR_RUE, JPAFSR_RUE_msg },
772 { JPAFSR_RCE, JPAFSR_RCE_msg },
773 { JPAFSR_BP, JPAFSR_BP_msg },
774 { JPAFSR_WBP, JPAFSR_WBP_msg },
775 { JPAFSR_FRC, JPAFSR_FRC_msg },
776 { JPAFSR_FRU, JPAFSR_FRU_msg },
777 /* These two do not update the AFAR. */
778 { CHAFSR_IVU, CHAFSR_IVU_msg },
779 { 0, NULL },
780};
781static struct afsr_error_table *cheetah_error_table;
782static unsigned long cheetah_afsr_errors;
783
784struct cheetah_err_info *cheetah_error_log;
785
786static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
787{
788 struct cheetah_err_info *p;
789 int cpu = smp_processor_id();
790
791 if (!cheetah_error_log)
792 return NULL;
793
794 p = cheetah_error_log + (cpu * 2);
795 if ((afsr & CHAFSR_TL1) != 0UL)
796 p++;
797
798 return p;
799}
800
801extern unsigned int tl0_icpe[], tl1_icpe[];
802extern unsigned int tl0_dcpe[], tl1_dcpe[];
803extern unsigned int tl0_fecc[], tl1_fecc[];
804extern unsigned int tl0_cee[], tl1_cee[];
805extern unsigned int tl0_iae[], tl1_iae[];
806extern unsigned int tl0_dae[], tl1_dae[];
807extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
808extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
809extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
810extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
811extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
812
813void __init cheetah_ecache_flush_init(void)
814{
815 unsigned long largest_size, smallest_linesize, order, ver;
816 int i, sz;
817
818 /* Scan all cpu device tree nodes, note two values:
819 * 1) largest E-cache size
820 * 2) smallest E-cache line size
821 */
822 largest_size = 0UL;
823 smallest_linesize = ~0UL;
824
825 for (i = 0; i < NR_CPUS; i++) {
826 unsigned long val;
827
828 val = cpu_data(i).ecache_size;
829 if (!val)
830 continue;
831
832 if (val > largest_size)
833 largest_size = val;
834
835 val = cpu_data(i).ecache_line_size;
836 if (val < smallest_linesize)
837 smallest_linesize = val;
838
839 }
840
841 if (largest_size == 0UL || smallest_linesize == ~0UL) {
842 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
843 "parameters.\n");
844 prom_halt();
845 }
846
847 ecache_flush_size = (2 * largest_size);
848 ecache_flush_linesize = smallest_linesize;
849
850 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
851
852 if (ecache_flush_physbase == ~0UL) {
853 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
854 "contiguous physical memory.\n",
855 ecache_flush_size);
856 prom_halt();
857 }
858
859 /* Now allocate error trap reporting scoreboard. */
860 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
861 for (order = 0; order < MAX_ORDER; order++) {
862 if ((PAGE_SIZE << order) >= sz)
863 break;
864 }
865 cheetah_error_log = (struct cheetah_err_info *)
866 __get_free_pages(GFP_KERNEL, order);
867 if (!cheetah_error_log) {
868 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
869 "error logging scoreboard (%d bytes).\n", sz);
870 prom_halt();
871 }
872 memset(cheetah_error_log, 0, PAGE_SIZE << order);
873
874 /* Mark all AFSRs as invalid so that the trap handler will
875 * log new new information there.
876 */
877 for (i = 0; i < 2 * NR_CPUS; i++)
878 cheetah_error_log[i].afsr = CHAFSR_INVALID;
879
880 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
881 if ((ver >> 32) == __JALAPENO_ID ||
882 (ver >> 32) == __SERRANO_ID) {
883 cheetah_error_table = &__jalapeno_error_table[0];
884 cheetah_afsr_errors = JPAFSR_ERRORS;
885 } else if ((ver >> 32) == 0x003e0015) {
886 cheetah_error_table = &__cheetah_plus_error_table[0];
887 cheetah_afsr_errors = CHPAFSR_ERRORS;
888 } else {
889 cheetah_error_table = &__cheetah_error_table[0];
890 cheetah_afsr_errors = CHAFSR_ERRORS;
891 }
892
893 /* Now patch trap tables. */
894 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
895 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
896 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
897 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
898 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
899 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
900 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
901 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
902 if (tlb_type == cheetah_plus) {
903 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
904 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
905 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
906 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
907 }
908 flushi(PAGE_OFFSET);
909}
910
911static void cheetah_flush_ecache(void)
912{
913 unsigned long flush_base = ecache_flush_physbase;
914 unsigned long flush_linesize = ecache_flush_linesize;
915 unsigned long flush_size = ecache_flush_size;
916
917 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
918 " bne,pt %%xcc, 1b\n\t"
919 " ldxa [%2 + %0] %3, %%g0\n\t"
920 : "=&r" (flush_size)
921 : "0" (flush_size), "r" (flush_base),
922 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
923}
924
925static void cheetah_flush_ecache_line(unsigned long physaddr)
926{
927 unsigned long alias;
928
929 physaddr &= ~(8UL - 1UL);
930 physaddr = (ecache_flush_physbase +
931 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
932 alias = physaddr + (ecache_flush_size >> 1UL);
933 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
934 "ldxa [%1] %2, %%g0\n\t"
935 "membar #Sync"
936 : /* no outputs */
937 : "r" (physaddr), "r" (alias),
938 "i" (ASI_PHYS_USE_EC));
939}
940
941/* Unfortunately, the diagnostic access to the I-cache tags we need to
942 * use to clear the thing interferes with I-cache coherency transactions.
943 *
944 * So we must only flush the I-cache when it is disabled.
945 */
946static void __cheetah_flush_icache(void)
947{
948 unsigned int icache_size, icache_line_size;
949 unsigned long addr;
950
951 icache_size = local_cpu_data().icache_size;
952 icache_line_size = local_cpu_data().icache_line_size;
953
954 /* Clear the valid bits in all the tags. */
955 for (addr = 0; addr < icache_size; addr += icache_line_size) {
956 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
957 "membar #Sync"
958 : /* no outputs */
959 : "r" (addr | (2 << 3)),
960 "i" (ASI_IC_TAG));
961 }
962}
963
964static void cheetah_flush_icache(void)
965{
966 unsigned long dcu_save;
967
968 /* Save current DCU, disable I-cache. */
969 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
970 "or %0, %2, %%g1\n\t"
971 "stxa %%g1, [%%g0] %1\n\t"
972 "membar #Sync"
973 : "=r" (dcu_save)
974 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
975 : "g1");
976
977 __cheetah_flush_icache();
978
979 /* Restore DCU register */
980 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
981 "membar #Sync"
982 : /* no outputs */
983 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
984}
985
986static void cheetah_flush_dcache(void)
987{
988 unsigned int dcache_size, dcache_line_size;
989 unsigned long addr;
990
991 dcache_size = local_cpu_data().dcache_size;
992 dcache_line_size = local_cpu_data().dcache_line_size;
993
994 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
995 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
996 "membar #Sync"
997 : /* no outputs */
998 : "r" (addr), "i" (ASI_DCACHE_TAG));
999 }
1000}
1001
1002/* In order to make the even parity correct we must do two things.
1003 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1004 * Next, we clear out all 32-bytes of data for that line. Data of
1005 * all-zero + tag parity value of zero == correct parity.
1006 */
1007static void cheetah_plus_zap_dcache_parity(void)
1008{
1009 unsigned int dcache_size, dcache_line_size;
1010 unsigned long addr;
1011
1012 dcache_size = local_cpu_data().dcache_size;
1013 dcache_line_size = local_cpu_data().dcache_line_size;
1014
1015 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1016 unsigned long tag = (addr >> 14);
1017 unsigned long line;
1018
1019 __asm__ __volatile__("membar #Sync\n\t"
1020 "stxa %0, [%1] %2\n\t"
1021 "membar #Sync"
1022 : /* no outputs */
1023 : "r" (tag), "r" (addr),
1024 "i" (ASI_DCACHE_UTAG));
1025 for (line = addr; line < addr + dcache_line_size; line += 8)
1026 __asm__ __volatile__("membar #Sync\n\t"
1027 "stxa %%g0, [%0] %1\n\t"
1028 "membar #Sync"
1029 : /* no outputs */
1030 : "r" (line),
1031 "i" (ASI_DCACHE_DATA));
1032 }
1033}
1034
1035/* Conversion tables used to frob Cheetah AFSR syndrome values into
1036 * something palatable to the memory controller driver get_unumber
1037 * routine.
1038 */
1039#define MT0 137
1040#define MT1 138
1041#define MT2 139
1042#define NONE 254
1043#define MTC0 140
1044#define MTC1 141
1045#define MTC2 142
1046#define MTC3 143
1047#define C0 128
1048#define C1 129
1049#define C2 130
1050#define C3 131
1051#define C4 132
1052#define C5 133
1053#define C6 134
1054#define C7 135
1055#define C8 136
1056#define M2 144
1057#define M3 145
1058#define M4 146
1059#define M 147
1060static unsigned char cheetah_ecc_syntab[] = {
1061/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1062/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1063/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1064/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1065/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1066/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1067/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1068/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1069/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1070/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1071/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1072/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1073/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1074/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1075/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1076/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1077/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1078/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1079/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1080/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1081/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1082/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1083/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1084/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1085/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1086/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1087/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1088/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1089/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1090/*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1091/*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1092/*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1093};
1094static unsigned char cheetah_mtag_syntab[] = {
1095 NONE, MTC0,
1096 MTC1, NONE,
1097 MTC2, NONE,
1098 NONE, MT0,
1099 MTC3, NONE,
1100 NONE, MT1,
1101 NONE, MT2,
1102 NONE, NONE
1103};
1104
1105/* Return the highest priority error conditon mentioned. */
1106static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1107{
1108 unsigned long tmp = 0;
1109 int i;
1110
1111 for (i = 0; cheetah_error_table[i].mask; i++) {
1112 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1113 return tmp;
1114 }
1115 return tmp;
1116}
1117
1118static const char *cheetah_get_string(unsigned long bit)
1119{
1120 int i;
1121
1122 for (i = 0; cheetah_error_table[i].mask; i++) {
1123 if ((bit & cheetah_error_table[i].mask) != 0UL)
1124 return cheetah_error_table[i].name;
1125 }
1126 return "???";
1127}
1128
1129static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1130 unsigned long afsr, unsigned long afar, int recoverable)
1131{
1132 unsigned long hipri;
1133 char unum[256];
1134
1135 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 afsr, afar,
1138 (afsr & CHAFSR_TL1) ? 1 : 0);
1139 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1140 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1141 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1142 printk("%s" "ERROR(%d): ",
1143 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1144 printk("TPC<%pS>\n", (void *) regs->tpc);
1145 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1146 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1147 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1148 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1149 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1150 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1151 hipri = cheetah_get_hipri(afsr);
1152 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1153 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1154 hipri, cheetah_get_string(hipri));
1155
1156 /* Try to get unumber if relevant. */
1157#define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1158 CHAFSR_CPC | CHAFSR_CPU | \
1159 CHAFSR_UE | CHAFSR_CE | \
1160 CHAFSR_EDC | CHAFSR_EDU | \
1161 CHAFSR_UCC | CHAFSR_UCU | \
1162 CHAFSR_WDU | CHAFSR_WDC)
1163#define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1164 if (afsr & ESYND_ERRORS) {
1165 int syndrome;
1166 int ret;
1167
1168 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1169 syndrome = cheetah_ecc_syntab[syndrome];
1170 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1171 if (ret != -1)
1172 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT),
1174 smp_processor_id(), unum);
1175 } else if (afsr & MSYND_ERRORS) {
1176 int syndrome;
1177 int ret;
1178
1179 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1180 syndrome = cheetah_mtag_syntab[syndrome];
1181 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1182 if (ret != -1)
1183 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1184 (recoverable ? KERN_WARNING : KERN_CRIT),
1185 smp_processor_id(), unum);
1186 }
1187
1188 /* Now dump the cache snapshots. */
1189 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1190 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1191 (int) info->dcache_index,
1192 info->dcache_tag,
1193 info->dcache_utag,
1194 info->dcache_stag);
1195 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1196 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1197 info->dcache_data[0],
1198 info->dcache_data[1],
1199 info->dcache_data[2],
1200 info->dcache_data[3]);
1201 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1202 "u[%016llx] l[%016llx]\n",
1203 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1204 (int) info->icache_index,
1205 info->icache_tag,
1206 info->icache_utag,
1207 info->icache_stag,
1208 info->icache_upper,
1209 info->icache_lower);
1210 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1211 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1212 info->icache_data[0],
1213 info->icache_data[1],
1214 info->icache_data[2],
1215 info->icache_data[3]);
1216 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1217 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1218 info->icache_data[4],
1219 info->icache_data[5],
1220 info->icache_data[6],
1221 info->icache_data[7]);
1222 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1223 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1224 (int) info->ecache_index, info->ecache_tag);
1225 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1226 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1227 info->ecache_data[0],
1228 info->ecache_data[1],
1229 info->ecache_data[2],
1230 info->ecache_data[3]);
1231
1232 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1233 while (afsr != 0UL) {
1234 unsigned long bit = cheetah_get_hipri(afsr);
1235
1236 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1237 (recoverable ? KERN_WARNING : KERN_CRIT),
1238 bit, cheetah_get_string(bit));
1239
1240 afsr &= ~bit;
1241 }
1242
1243 if (!recoverable)
1244 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1245}
1246
1247static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1248{
1249 unsigned long afsr, afar;
1250 int ret = 0;
1251
1252 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1253 : "=r" (afsr)
1254 : "i" (ASI_AFSR));
1255 if ((afsr & cheetah_afsr_errors) != 0) {
1256 if (logp != NULL) {
1257 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1258 : "=r" (afar)
1259 : "i" (ASI_AFAR));
1260 logp->afsr = afsr;
1261 logp->afar = afar;
1262 }
1263 ret = 1;
1264 }
1265 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1266 "membar #Sync\n\t"
1267 : : "r" (afsr), "i" (ASI_AFSR));
1268
1269 return ret;
1270}
1271
1272void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1273{
1274 struct cheetah_err_info local_snapshot, *p;
1275 int recoverable;
1276
1277 /* Flush E-cache */
1278 cheetah_flush_ecache();
1279
1280 p = cheetah_get_error_log(afsr);
1281 if (!p) {
1282 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1283 afsr, afar);
1284 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1285 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1286 prom_halt();
1287 }
1288
1289 /* Grab snapshot of logged error. */
1290 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1291
1292 /* If the current trap snapshot does not match what the
1293 * trap handler passed along into our args, big trouble.
1294 * In such a case, mark the local copy as invalid.
1295 *
1296 * Else, it matches and we mark the afsr in the non-local
1297 * copy as invalid so we may log new error traps there.
1298 */
1299 if (p->afsr != afsr || p->afar != afar)
1300 local_snapshot.afsr = CHAFSR_INVALID;
1301 else
1302 p->afsr = CHAFSR_INVALID;
1303
1304 cheetah_flush_icache();
1305 cheetah_flush_dcache();
1306
1307 /* Re-enable I-cache/D-cache */
1308 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1309 "or %%g1, %1, %%g1\n\t"
1310 "stxa %%g1, [%%g0] %0\n\t"
1311 "membar #Sync"
1312 : /* no outputs */
1313 : "i" (ASI_DCU_CONTROL_REG),
1314 "i" (DCU_DC | DCU_IC)
1315 : "g1");
1316
1317 /* Re-enable error reporting */
1318 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1319 "or %%g1, %1, %%g1\n\t"
1320 "stxa %%g1, [%%g0] %0\n\t"
1321 "membar #Sync"
1322 : /* no outputs */
1323 : "i" (ASI_ESTATE_ERROR_EN),
1324 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1325 : "g1");
1326
1327 /* Decide if we can continue after handling this trap and
1328 * logging the error.
1329 */
1330 recoverable = 1;
1331 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1332 recoverable = 0;
1333
1334 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1335 * error was logged while we had error reporting traps disabled.
1336 */
1337 if (cheetah_recheck_errors(&local_snapshot)) {
1338 unsigned long new_afsr = local_snapshot.afsr;
1339
1340 /* If we got a new asynchronous error, die... */
1341 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1342 CHAFSR_WDU | CHAFSR_CPU |
1343 CHAFSR_IVU | CHAFSR_UE |
1344 CHAFSR_BERR | CHAFSR_TO))
1345 recoverable = 0;
1346 }
1347
1348 /* Log errors. */
1349 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1350
1351 if (!recoverable)
1352 panic("Irrecoverable Fast-ECC error trap.\n");
1353
1354 /* Flush E-cache to kick the error trap handlers out. */
1355 cheetah_flush_ecache();
1356}
1357
1358/* Try to fix a correctable error by pushing the line out from
1359 * the E-cache. Recheck error reporting registers to see if the
1360 * problem is intermittent.
1361 */
1362static int cheetah_fix_ce(unsigned long physaddr)
1363{
1364 unsigned long orig_estate;
1365 unsigned long alias1, alias2;
1366 int ret;
1367
1368 /* Make sure correctable error traps are disabled. */
1369 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1370 "andn %0, %1, %%g1\n\t"
1371 "stxa %%g1, [%%g0] %2\n\t"
1372 "membar #Sync"
1373 : "=&r" (orig_estate)
1374 : "i" (ESTATE_ERROR_CEEN),
1375 "i" (ASI_ESTATE_ERROR_EN)
1376 : "g1");
1377
1378 /* We calculate alias addresses that will force the
1379 * cache line in question out of the E-cache. Then
1380 * we bring it back in with an atomic instruction so
1381 * that we get it in some modified/exclusive state,
1382 * then we displace it again to try and get proper ECC
1383 * pushed back into the system.
1384 */
1385 physaddr &= ~(8UL - 1UL);
1386 alias1 = (ecache_flush_physbase +
1387 (physaddr & ((ecache_flush_size >> 1) - 1)));
1388 alias2 = alias1 + (ecache_flush_size >> 1);
1389 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1390 "ldxa [%1] %3, %%g0\n\t"
1391 "casxa [%2] %3, %%g0, %%g0\n\t"
1392 "ldxa [%0] %3, %%g0\n\t"
1393 "ldxa [%1] %3, %%g0\n\t"
1394 "membar #Sync"
1395 : /* no outputs */
1396 : "r" (alias1), "r" (alias2),
1397 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1398
1399 /* Did that trigger another error? */
1400 if (cheetah_recheck_errors(NULL)) {
1401 /* Try one more time. */
1402 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1403 "membar #Sync"
1404 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1405 if (cheetah_recheck_errors(NULL))
1406 ret = 2;
1407 else
1408 ret = 1;
1409 } else {
1410 /* No new error, intermittent problem. */
1411 ret = 0;
1412 }
1413
1414 /* Restore error enables. */
1415 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1416 "membar #Sync"
1417 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1418
1419 return ret;
1420}
1421
1422/* Return non-zero if PADDR is a valid physical memory address. */
1423static int cheetah_check_main_memory(unsigned long paddr)
1424{
1425 unsigned long vaddr = PAGE_OFFSET + paddr;
1426
1427 if (vaddr > (unsigned long) high_memory)
1428 return 0;
1429
1430 return kern_addr_valid(vaddr);
1431}
1432
1433void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1434{
1435 struct cheetah_err_info local_snapshot, *p;
1436 int recoverable, is_memory;
1437
1438 p = cheetah_get_error_log(afsr);
1439 if (!p) {
1440 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1441 afsr, afar);
1442 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1443 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1444 prom_halt();
1445 }
1446
1447 /* Grab snapshot of logged error. */
1448 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1449
1450 /* If the current trap snapshot does not match what the
1451 * trap handler passed along into our args, big trouble.
1452 * In such a case, mark the local copy as invalid.
1453 *
1454 * Else, it matches and we mark the afsr in the non-local
1455 * copy as invalid so we may log new error traps there.
1456 */
1457 if (p->afsr != afsr || p->afar != afar)
1458 local_snapshot.afsr = CHAFSR_INVALID;
1459 else
1460 p->afsr = CHAFSR_INVALID;
1461
1462 is_memory = cheetah_check_main_memory(afar);
1463
1464 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1465 /* XXX Might want to log the results of this operation
1466 * XXX somewhere... -DaveM
1467 */
1468 cheetah_fix_ce(afar);
1469 }
1470
1471 {
1472 int flush_all, flush_line;
1473
1474 flush_all = flush_line = 0;
1475 if ((afsr & CHAFSR_EDC) != 0UL) {
1476 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1477 flush_line = 1;
1478 else
1479 flush_all = 1;
1480 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1481 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1482 flush_line = 1;
1483 else
1484 flush_all = 1;
1485 }
1486
1487 /* Trap handler only disabled I-cache, flush it. */
1488 cheetah_flush_icache();
1489
1490 /* Re-enable I-cache */
1491 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1492 "or %%g1, %1, %%g1\n\t"
1493 "stxa %%g1, [%%g0] %0\n\t"
1494 "membar #Sync"
1495 : /* no outputs */
1496 : "i" (ASI_DCU_CONTROL_REG),
1497 "i" (DCU_IC)
1498 : "g1");
1499
1500 if (flush_all)
1501 cheetah_flush_ecache();
1502 else if (flush_line)
1503 cheetah_flush_ecache_line(afar);
1504 }
1505
1506 /* Re-enable error reporting */
1507 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1508 "or %%g1, %1, %%g1\n\t"
1509 "stxa %%g1, [%%g0] %0\n\t"
1510 "membar #Sync"
1511 : /* no outputs */
1512 : "i" (ASI_ESTATE_ERROR_EN),
1513 "i" (ESTATE_ERROR_CEEN)
1514 : "g1");
1515
1516 /* Decide if we can continue after handling this trap and
1517 * logging the error.
1518 */
1519 recoverable = 1;
1520 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1521 recoverable = 0;
1522
1523 /* Re-check AFSR/AFAR */
1524 (void) cheetah_recheck_errors(&local_snapshot);
1525
1526 /* Log errors. */
1527 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1528
1529 if (!recoverable)
1530 panic("Irrecoverable Correctable-ECC error trap.\n");
1531}
1532
1533void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1534{
1535 struct cheetah_err_info local_snapshot, *p;
1536 int recoverable, is_memory;
1537
1538#ifdef CONFIG_PCI
1539 /* Check for the special PCI poke sequence. */
1540 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1541 cheetah_flush_icache();
1542 cheetah_flush_dcache();
1543
1544 /* Re-enable I-cache/D-cache */
1545 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1546 "or %%g1, %1, %%g1\n\t"
1547 "stxa %%g1, [%%g0] %0\n\t"
1548 "membar #Sync"
1549 : /* no outputs */
1550 : "i" (ASI_DCU_CONTROL_REG),
1551 "i" (DCU_DC | DCU_IC)
1552 : "g1");
1553
1554 /* Re-enable error reporting */
1555 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1556 "or %%g1, %1, %%g1\n\t"
1557 "stxa %%g1, [%%g0] %0\n\t"
1558 "membar #Sync"
1559 : /* no outputs */
1560 : "i" (ASI_ESTATE_ERROR_EN),
1561 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1562 : "g1");
1563
1564 (void) cheetah_recheck_errors(NULL);
1565
1566 pci_poke_faulted = 1;
1567 regs->tpc += 4;
1568 regs->tnpc = regs->tpc + 4;
1569 return;
1570 }
1571#endif
1572
1573 p = cheetah_get_error_log(afsr);
1574 if (!p) {
1575 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1576 afsr, afar);
1577 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1578 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1579 prom_halt();
1580 }
1581
1582 /* Grab snapshot of logged error. */
1583 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1584
1585 /* If the current trap snapshot does not match what the
1586 * trap handler passed along into our args, big trouble.
1587 * In such a case, mark the local copy as invalid.
1588 *
1589 * Else, it matches and we mark the afsr in the non-local
1590 * copy as invalid so we may log new error traps there.
1591 */
1592 if (p->afsr != afsr || p->afar != afar)
1593 local_snapshot.afsr = CHAFSR_INVALID;
1594 else
1595 p->afsr = CHAFSR_INVALID;
1596
1597 is_memory = cheetah_check_main_memory(afar);
1598
1599 {
1600 int flush_all, flush_line;
1601
1602 flush_all = flush_line = 0;
1603 if ((afsr & CHAFSR_EDU) != 0UL) {
1604 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1605 flush_line = 1;
1606 else
1607 flush_all = 1;
1608 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1609 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1610 flush_line = 1;
1611 else
1612 flush_all = 1;
1613 }
1614
1615 cheetah_flush_icache();
1616 cheetah_flush_dcache();
1617
1618 /* Re-enable I/D caches */
1619 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1620 "or %%g1, %1, %%g1\n\t"
1621 "stxa %%g1, [%%g0] %0\n\t"
1622 "membar #Sync"
1623 : /* no outputs */
1624 : "i" (ASI_DCU_CONTROL_REG),
1625 "i" (DCU_IC | DCU_DC)
1626 : "g1");
1627
1628 if (flush_all)
1629 cheetah_flush_ecache();
1630 else if (flush_line)
1631 cheetah_flush_ecache_line(afar);
1632 }
1633
1634 /* Re-enable error reporting */
1635 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1636 "or %%g1, %1, %%g1\n\t"
1637 "stxa %%g1, [%%g0] %0\n\t"
1638 "membar #Sync"
1639 : /* no outputs */
1640 : "i" (ASI_ESTATE_ERROR_EN),
1641 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1642 : "g1");
1643
1644 /* Decide if we can continue after handling this trap and
1645 * logging the error.
1646 */
1647 recoverable = 1;
1648 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1649 recoverable = 0;
1650
1651 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1652 * error was logged while we had error reporting traps disabled.
1653 */
1654 if (cheetah_recheck_errors(&local_snapshot)) {
1655 unsigned long new_afsr = local_snapshot.afsr;
1656
1657 /* If we got a new asynchronous error, die... */
1658 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1659 CHAFSR_WDU | CHAFSR_CPU |
1660 CHAFSR_IVU | CHAFSR_UE |
1661 CHAFSR_BERR | CHAFSR_TO))
1662 recoverable = 0;
1663 }
1664
1665 /* Log errors. */
1666 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1667
1668 /* "Recoverable" here means we try to yank the page from ever
1669 * being newly used again. This depends upon a few things:
1670 * 1) Must be main memory, and AFAR must be valid.
1671 * 2) If we trapped from user, OK.
1672 * 3) Else, if we trapped from kernel we must find exception
1673 * table entry (ie. we have to have been accessing user
1674 * space).
1675 *
1676 * If AFAR is not in main memory, or we trapped from kernel
1677 * and cannot find an exception table entry, it is unacceptable
1678 * to try and continue.
1679 */
1680 if (recoverable && is_memory) {
1681 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1682 /* OK, usermode access. */
1683 recoverable = 1;
1684 } else {
1685 const struct exception_table_entry *entry;
1686
1687 entry = search_exception_tables(regs->tpc);
1688 if (entry) {
1689 /* OK, kernel access to userspace. */
1690 recoverable = 1;
1691
1692 } else {
1693 /* BAD, privileged state is corrupted. */
1694 recoverable = 0;
1695 }
1696
1697 if (recoverable) {
1698 if (pfn_valid(afar >> PAGE_SHIFT))
1699 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1700 else
1701 recoverable = 0;
1702
1703 /* Only perform fixup if we still have a
1704 * recoverable condition.
1705 */
1706 if (recoverable) {
1707 regs->tpc = entry->fixup;
1708 regs->tnpc = regs->tpc + 4;
1709 }
1710 }
1711 }
1712 } else {
1713 recoverable = 0;
1714 }
1715
1716 if (!recoverable)
1717 panic("Irrecoverable deferred error trap.\n");
1718}
1719
1720/* Handle a D/I cache parity error trap. TYPE is encoded as:
1721 *
1722 * Bit0: 0=dcache,1=icache
1723 * Bit1: 0=recoverable,1=unrecoverable
1724 *
1725 * The hardware has disabled both the I-cache and D-cache in
1726 * the %dcr register.
1727 */
1728void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1729{
1730 if (type & 0x1)
1731 __cheetah_flush_icache();
1732 else
1733 cheetah_plus_zap_dcache_parity();
1734 cheetah_flush_dcache();
1735
1736 /* Re-enable I-cache/D-cache */
1737 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1738 "or %%g1, %1, %%g1\n\t"
1739 "stxa %%g1, [%%g0] %0\n\t"
1740 "membar #Sync"
1741 : /* no outputs */
1742 : "i" (ASI_DCU_CONTROL_REG),
1743 "i" (DCU_DC | DCU_IC)
1744 : "g1");
1745
1746 if (type & 0x2) {
1747 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1748 smp_processor_id(),
1749 (type & 0x1) ? 'I' : 'D',
1750 regs->tpc);
1751 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1752 panic("Irrecoverable Cheetah+ parity error.");
1753 }
1754
1755 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1756 smp_processor_id(),
1757 (type & 0x1) ? 'I' : 'D',
1758 regs->tpc);
1759 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1760}
1761
1762struct sun4v_error_entry {
1763 u64 err_handle;
1764 u64 err_stick;
1765
1766 u32 err_type;
1767#define SUN4V_ERR_TYPE_UNDEFINED 0
1768#define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1769#define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1770#define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1771#define SUN4V_ERR_TYPE_WARNING_RES 4
1772
1773 u32 err_attrs;
1774#define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1775#define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1776#define SUN4V_ERR_ATTRS_PIO 0x00000004
1777#define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1778#define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1779#define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1780#define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1781#define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1782
1783 u64 err_raddr;
1784 u32 err_size;
1785 u16 err_cpu;
1786 u16 err_pad;
1787};
1788
1789static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1790static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1791
1792static const char *sun4v_err_type_to_str(u32 type)
1793{
1794 switch (type) {
1795 case SUN4V_ERR_TYPE_UNDEFINED:
1796 return "undefined";
1797 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1798 return "uncorrected resumable";
1799 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1800 return "precise nonresumable";
1801 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1802 return "deferred nonresumable";
1803 case SUN4V_ERR_TYPE_WARNING_RES:
1804 return "warning resumable";
1805 default:
1806 return "unknown";
1807 }
1808}
1809
1810static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1811{
1812 int cnt;
1813
1814 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1815 printk("%s: err_handle[%llx] err_stick[%llx] err_type[%08x:%s]\n",
1816 pfx,
1817 ent->err_handle, ent->err_stick,
1818 ent->err_type,
1819 sun4v_err_type_to_str(ent->err_type));
1820 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1821 pfx,
1822 ent->err_attrs,
1823 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1824 "processor" : ""),
1825 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1826 "memory" : ""),
1827 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1828 "pio" : ""),
1829 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1830 "integer-regs" : ""),
1831 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1832 "fpu-regs" : ""),
1833 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1834 "user" : ""),
1835 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1836 "privileged" : ""),
1837 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1838 "queue-full" : ""));
1839 printk("%s: err_raddr[%016llx] err_size[%u] err_cpu[%u]\n",
1840 pfx,
1841 ent->err_raddr, ent->err_size, ent->err_cpu);
1842
1843 show_regs(regs);
1844
1845 if ((cnt = atomic_read(ocnt)) != 0) {
1846 atomic_set(ocnt, 0);
1847 wmb();
1848 printk("%s: Queue overflowed %d times.\n",
1849 pfx, cnt);
1850 }
1851}
1852
1853/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1854 * Log the event and clear the first word of the entry.
1855 */
1856void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1857{
1858 struct sun4v_error_entry *ent, local_copy;
1859 struct trap_per_cpu *tb;
1860 unsigned long paddr;
1861 int cpu;
1862
1863 cpu = get_cpu();
1864
1865 tb = &trap_block[cpu];
1866 paddr = tb->resum_kernel_buf_pa + offset;
1867 ent = __va(paddr);
1868
1869 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1870
1871 /* We have a local copy now, so release the entry. */
1872 ent->err_handle = 0;
1873 wmb();
1874
1875 put_cpu();
1876
1877 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1878 /* If err_type is 0x4, it's a powerdown request. Do
1879 * not do the usual resumable error log because that
1880 * makes it look like some abnormal error.
1881 */
1882 printk(KERN_INFO "Power down request...\n");
1883 kill_cad_pid(SIGINT, 1);
1884 return;
1885 }
1886
1887 sun4v_log_error(regs, &local_copy, cpu,
1888 KERN_ERR "RESUMABLE ERROR",
1889 &sun4v_resum_oflow_cnt);
1890}
1891
1892/* If we try to printk() we'll probably make matters worse, by trying
1893 * to retake locks this cpu already holds or causing more errors. So
1894 * just bump a counter, and we'll report these counter bumps above.
1895 */
1896void sun4v_resum_overflow(struct pt_regs *regs)
1897{
1898 atomic_inc(&sun4v_resum_oflow_cnt);
1899}
1900
1901/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
1902 * Log the event, clear the first word of the entry, and die.
1903 */
1904void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1905{
1906 struct sun4v_error_entry *ent, local_copy;
1907 struct trap_per_cpu *tb;
1908 unsigned long paddr;
1909 int cpu;
1910
1911 cpu = get_cpu();
1912
1913 tb = &trap_block[cpu];
1914 paddr = tb->nonresum_kernel_buf_pa + offset;
1915 ent = __va(paddr);
1916
1917 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1918
1919 /* We have a local copy now, so release the entry. */
1920 ent->err_handle = 0;
1921 wmb();
1922
1923 put_cpu();
1924
1925#ifdef CONFIG_PCI
1926 /* Check for the special PCI poke sequence. */
1927 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1928 pci_poke_faulted = 1;
1929 regs->tpc += 4;
1930 regs->tnpc = regs->tpc + 4;
1931 return;
1932 }
1933#endif
1934
1935 sun4v_log_error(regs, &local_copy, cpu,
1936 KERN_EMERG "NON-RESUMABLE ERROR",
1937 &sun4v_nonresum_oflow_cnt);
1938
1939 panic("Non-resumable error.");
1940}
1941
1942/* If we try to printk() we'll probably make matters worse, by trying
1943 * to retake locks this cpu already holds or causing more errors. So
1944 * just bump a counter, and we'll report these counter bumps above.
1945 */
1946void sun4v_nonresum_overflow(struct pt_regs *regs)
1947{
1948 /* XXX Actually even this can make not that much sense. Perhaps
1949 * XXX we should just pull the plug and panic directly from here?
1950 */
1951 atomic_inc(&sun4v_nonresum_oflow_cnt);
1952}
1953
1954unsigned long sun4v_err_itlb_vaddr;
1955unsigned long sun4v_err_itlb_ctx;
1956unsigned long sun4v_err_itlb_pte;
1957unsigned long sun4v_err_itlb_error;
1958
1959void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1960{
1961 if (tl > 1)
1962 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1963
1964 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1965 regs->tpc, tl);
1966 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
1967 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1968 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
1969 (void *) regs->u_regs[UREG_I7]);
1970 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1971 "pte[%lx] error[%lx]\n",
1972 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1973 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1974
1975 prom_halt();
1976}
1977
1978unsigned long sun4v_err_dtlb_vaddr;
1979unsigned long sun4v_err_dtlb_ctx;
1980unsigned long sun4v_err_dtlb_pte;
1981unsigned long sun4v_err_dtlb_error;
1982
1983void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1984{
1985 if (tl > 1)
1986 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1987
1988 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1989 regs->tpc, tl);
1990 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
1991 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
1992 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
1993 (void *) regs->u_regs[UREG_I7]);
1994 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1995 "pte[%lx] error[%lx]\n",
1996 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1997 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1998
1999 prom_halt();
2000}
2001
2002void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2003{
2004 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2005 err, op);
2006}
2007
2008void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2009{
2010 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2011 err, op);
2012}
2013
2014void do_fpe_common(struct pt_regs *regs)
2015{
2016 if (regs->tstate & TSTATE_PRIV) {
2017 regs->tpc = regs->tnpc;
2018 regs->tnpc += 4;
2019 } else {
2020 unsigned long fsr = current_thread_info()->xfsr[0];
2021 siginfo_t info;
2022
2023 if (test_thread_flag(TIF_32BIT)) {
2024 regs->tpc &= 0xffffffff;
2025 regs->tnpc &= 0xffffffff;
2026 }
2027 info.si_signo = SIGFPE;
2028 info.si_errno = 0;
2029 info.si_addr = (void __user *)regs->tpc;
2030 info.si_trapno = 0;
2031 info.si_code = __SI_FAULT;
2032 if ((fsr & 0x1c000) == (1 << 14)) {
2033 if (fsr & 0x10)
2034 info.si_code = FPE_FLTINV;
2035 else if (fsr & 0x08)
2036 info.si_code = FPE_FLTOVF;
2037 else if (fsr & 0x04)
2038 info.si_code = FPE_FLTUND;
2039 else if (fsr & 0x02)
2040 info.si_code = FPE_FLTDIV;
2041 else if (fsr & 0x01)
2042 info.si_code = FPE_FLTRES;
2043 }
2044 force_sig_info(SIGFPE, &info, current);
2045 }
2046}
2047
2048void do_fpieee(struct pt_regs *regs)
2049{
2050 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2051 0, 0x24, SIGFPE) == NOTIFY_STOP)
2052 return;
2053
2054 do_fpe_common(regs);
2055}
2056
2057extern int do_mathemu(struct pt_regs *, struct fpustate *, bool);
2058
2059void do_fpother(struct pt_regs *regs)
2060{
2061 struct fpustate *f = FPUSTATE;
2062 int ret = 0;
2063
2064 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2065 0, 0x25, SIGFPE) == NOTIFY_STOP)
2066 return;
2067
2068 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2069 case (2 << 14): /* unfinished_FPop */
2070 case (3 << 14): /* unimplemented_FPop */
2071 ret = do_mathemu(regs, f, false);
2072 break;
2073 }
2074 if (ret)
2075 return;
2076 do_fpe_common(regs);
2077}
2078
2079void do_tof(struct pt_regs *regs)
2080{
2081 siginfo_t info;
2082
2083 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2084 0, 0x26, SIGEMT) == NOTIFY_STOP)
2085 return;
2086
2087 if (regs->tstate & TSTATE_PRIV)
2088 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2089 if (test_thread_flag(TIF_32BIT)) {
2090 regs->tpc &= 0xffffffff;
2091 regs->tnpc &= 0xffffffff;
2092 }
2093 info.si_signo = SIGEMT;
2094 info.si_errno = 0;
2095 info.si_code = EMT_TAGOVF;
2096 info.si_addr = (void __user *)regs->tpc;
2097 info.si_trapno = 0;
2098 force_sig_info(SIGEMT, &info, current);
2099}
2100
2101void do_div0(struct pt_regs *regs)
2102{
2103 siginfo_t info;
2104
2105 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2106 0, 0x28, SIGFPE) == NOTIFY_STOP)
2107 return;
2108
2109 if (regs->tstate & TSTATE_PRIV)
2110 die_if_kernel("TL0: Kernel divide by zero.", regs);
2111 if (test_thread_flag(TIF_32BIT)) {
2112 regs->tpc &= 0xffffffff;
2113 regs->tnpc &= 0xffffffff;
2114 }
2115 info.si_signo = SIGFPE;
2116 info.si_errno = 0;
2117 info.si_code = FPE_INTDIV;
2118 info.si_addr = (void __user *)regs->tpc;
2119 info.si_trapno = 0;
2120 force_sig_info(SIGFPE, &info, current);
2121}
2122
2123static void instruction_dump(unsigned int *pc)
2124{
2125 int i;
2126
2127 if ((((unsigned long) pc) & 3))
2128 return;
2129
2130 printk("Instruction DUMP:");
2131 for (i = -3; i < 6; i++)
2132 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2133 printk("\n");
2134}
2135
2136static void user_instruction_dump(unsigned int __user *pc)
2137{
2138 int i;
2139 unsigned int buf[9];
2140
2141 if ((((unsigned long) pc) & 3))
2142 return;
2143
2144 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2145 return;
2146
2147 printk("Instruction DUMP:");
2148 for (i = 0; i < 9; i++)
2149 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2150 printk("\n");
2151}
2152
2153void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2154{
2155 unsigned long fp, ksp;
2156 struct thread_info *tp;
2157 int count = 0;
2158#ifdef CONFIG_FUNCTION_GRAPH_TRACER
2159 int graph = 0;
2160#endif
2161
2162 ksp = (unsigned long) _ksp;
2163 if (!tsk)
2164 tsk = current;
2165 tp = task_thread_info(tsk);
2166 if (ksp == 0UL) {
2167 if (tsk == current)
2168 asm("mov %%fp, %0" : "=r" (ksp));
2169 else
2170 ksp = tp->ksp;
2171 }
2172 if (tp == current_thread_info())
2173 flushw_all();
2174
2175 fp = ksp + STACK_BIAS;
2176
2177 printk("Call Trace:\n");
2178 do {
2179 struct sparc_stackf *sf;
2180 struct pt_regs *regs;
2181 unsigned long pc;
2182
2183 if (!kstack_valid(tp, fp))
2184 break;
2185 sf = (struct sparc_stackf *) fp;
2186 regs = (struct pt_regs *) (sf + 1);
2187
2188 if (kstack_is_trap_frame(tp, regs)) {
2189 if (!(regs->tstate & TSTATE_PRIV))
2190 break;
2191 pc = regs->tpc;
2192 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2193 } else {
2194 pc = sf->callers_pc;
2195 fp = (unsigned long)sf->fp + STACK_BIAS;
2196 }
2197
2198 printk(" [%016lx] %pS\n", pc, (void *) pc);
2199#ifdef CONFIG_FUNCTION_GRAPH_TRACER
2200 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2201 int index = tsk->curr_ret_stack;
2202 if (tsk->ret_stack && index >= graph) {
2203 pc = tsk->ret_stack[index - graph].ret;
2204 printk(" [%016lx] %pS\n", pc, (void *) pc);
2205 graph++;
2206 }
2207 }
2208#endif
2209 } while (++count < 16);
2210}
2211
2212void dump_stack(void)
2213{
2214 show_stack(current, NULL);
2215}
2216
2217EXPORT_SYMBOL(dump_stack);
2218
2219static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2220{
2221 unsigned long fp = rw->ins[6];
2222
2223 if (!fp)
2224 return NULL;
2225
2226 return (struct reg_window *) (fp + STACK_BIAS);
2227}
2228
2229void die_if_kernel(char *str, struct pt_regs *regs)
2230{
2231 static int die_counter;
2232 int count = 0;
2233
2234 /* Amuse the user. */
2235 printk(
2236" \\|/ ____ \\|/\n"
2237" \"@'/ .. \\`@\"\n"
2238" /_| \\__/ |_\\\n"
2239" \\__U_/\n");
2240
2241 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2242 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2243 __asm__ __volatile__("flushw");
2244 show_regs(regs);
2245 add_taint(TAINT_DIE);
2246 if (regs->tstate & TSTATE_PRIV) {
2247 struct thread_info *tp = current_thread_info();
2248 struct reg_window *rw = (struct reg_window *)
2249 (regs->u_regs[UREG_FP] + STACK_BIAS);
2250
2251 /* Stop the back trace when we hit userland or we
2252 * find some badly aligned kernel stack.
2253 */
2254 while (rw &&
2255 count++ < 30 &&
2256 kstack_valid(tp, (unsigned long) rw)) {
2257 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2258 (void *) rw->ins[7]);
2259
2260 rw = kernel_stack_up(rw);
2261 }
2262 instruction_dump ((unsigned int *) regs->tpc);
2263 } else {
2264 if (test_thread_flag(TIF_32BIT)) {
2265 regs->tpc &= 0xffffffff;
2266 regs->tnpc &= 0xffffffff;
2267 }
2268 user_instruction_dump ((unsigned int __user *) regs->tpc);
2269 }
2270 if (regs->tstate & TSTATE_PRIV)
2271 do_exit(SIGKILL);
2272 do_exit(SIGSEGV);
2273}
2274EXPORT_SYMBOL(die_if_kernel);
2275
2276#define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2277#define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2278
2279extern int handle_popc(u32 insn, struct pt_regs *regs);
2280extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2281
2282void do_illegal_instruction(struct pt_regs *regs)
2283{
2284 unsigned long pc = regs->tpc;
2285 unsigned long tstate = regs->tstate;
2286 u32 insn;
2287 siginfo_t info;
2288
2289 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2290 0, 0x10, SIGILL) == NOTIFY_STOP)
2291 return;
2292
2293 if (tstate & TSTATE_PRIV)
2294 die_if_kernel("Kernel illegal instruction", regs);
2295 if (test_thread_flag(TIF_32BIT))
2296 pc = (u32)pc;
2297 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2298 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2299 if (handle_popc(insn, regs))
2300 return;
2301 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2302 if (handle_ldf_stq(insn, regs))
2303 return;
2304 } else if (tlb_type == hypervisor) {
2305 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2306 if (!vis_emul(regs, insn))
2307 return;
2308 } else {
2309 struct fpustate *f = FPUSTATE;
2310
2311 /* On UltraSPARC T2 and later, FPU insns which
2312 * are not implemented in HW signal an illegal
2313 * instruction trap and do not set the FP Trap
2314 * Trap in the %fsr to unimplemented_FPop.
2315 */
2316 if (do_mathemu(regs, f, true))
2317 return;
2318 }
2319 }
2320 }
2321 info.si_signo = SIGILL;
2322 info.si_errno = 0;
2323 info.si_code = ILL_ILLOPC;
2324 info.si_addr = (void __user *)pc;
2325 info.si_trapno = 0;
2326 force_sig_info(SIGILL, &info, current);
2327}
2328
2329extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2330
2331void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2332{
2333 siginfo_t info;
2334
2335 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2336 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2337 return;
2338
2339 if (regs->tstate & TSTATE_PRIV) {
2340 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2341 return;
2342 }
2343 info.si_signo = SIGBUS;
2344 info.si_errno = 0;
2345 info.si_code = BUS_ADRALN;
2346 info.si_addr = (void __user *)sfar;
2347 info.si_trapno = 0;
2348 force_sig_info(SIGBUS, &info, current);
2349}
2350
2351void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2352{
2353 siginfo_t info;
2354
2355 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2356 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2357 return;
2358
2359 if (regs->tstate & TSTATE_PRIV) {
2360 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2361 return;
2362 }
2363 info.si_signo = SIGBUS;
2364 info.si_errno = 0;
2365 info.si_code = BUS_ADRALN;
2366 info.si_addr = (void __user *) addr;
2367 info.si_trapno = 0;
2368 force_sig_info(SIGBUS, &info, current);
2369}
2370
2371void do_privop(struct pt_regs *regs)
2372{
2373 siginfo_t info;
2374
2375 if (notify_die(DIE_TRAP, "privileged operation", regs,
2376 0, 0x11, SIGILL) == NOTIFY_STOP)
2377 return;
2378
2379 if (test_thread_flag(TIF_32BIT)) {
2380 regs->tpc &= 0xffffffff;
2381 regs->tnpc &= 0xffffffff;
2382 }
2383 info.si_signo = SIGILL;
2384 info.si_errno = 0;
2385 info.si_code = ILL_PRVOPC;
2386 info.si_addr = (void __user *)regs->tpc;
2387 info.si_trapno = 0;
2388 force_sig_info(SIGILL, &info, current);
2389}
2390
2391void do_privact(struct pt_regs *regs)
2392{
2393 do_privop(regs);
2394}
2395
2396/* Trap level 1 stuff or other traps we should never see... */
2397void do_cee(struct pt_regs *regs)
2398{
2399 die_if_kernel("TL0: Cache Error Exception", regs);
2400}
2401
2402void do_cee_tl1(struct pt_regs *regs)
2403{
2404 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2405 die_if_kernel("TL1: Cache Error Exception", regs);
2406}
2407
2408void do_dae_tl1(struct pt_regs *regs)
2409{
2410 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2411 die_if_kernel("TL1: Data Access Exception", regs);
2412}
2413
2414void do_iae_tl1(struct pt_regs *regs)
2415{
2416 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2417 die_if_kernel("TL1: Instruction Access Exception", regs);
2418}
2419
2420void do_div0_tl1(struct pt_regs *regs)
2421{
2422 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2423 die_if_kernel("TL1: DIV0 Exception", regs);
2424}
2425
2426void do_fpdis_tl1(struct pt_regs *regs)
2427{
2428 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2429 die_if_kernel("TL1: FPU Disabled", regs);
2430}
2431
2432void do_fpieee_tl1(struct pt_regs *regs)
2433{
2434 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2435 die_if_kernel("TL1: FPU IEEE Exception", regs);
2436}
2437
2438void do_fpother_tl1(struct pt_regs *regs)
2439{
2440 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2441 die_if_kernel("TL1: FPU Other Exception", regs);
2442}
2443
2444void do_ill_tl1(struct pt_regs *regs)
2445{
2446 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2447 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2448}
2449
2450void do_irq_tl1(struct pt_regs *regs)
2451{
2452 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2453 die_if_kernel("TL1: IRQ Exception", regs);
2454}
2455
2456void do_lddfmna_tl1(struct pt_regs *regs)
2457{
2458 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2459 die_if_kernel("TL1: LDDF Exception", regs);
2460}
2461
2462void do_stdfmna_tl1(struct pt_regs *regs)
2463{
2464 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2465 die_if_kernel("TL1: STDF Exception", regs);
2466}
2467
2468void do_paw(struct pt_regs *regs)
2469{
2470 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2471}
2472
2473void do_paw_tl1(struct pt_regs *regs)
2474{
2475 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2476 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2477}
2478
2479void do_vaw(struct pt_regs *regs)
2480{
2481 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2482}
2483
2484void do_vaw_tl1(struct pt_regs *regs)
2485{
2486 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2487 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2488}
2489
2490void do_tof_tl1(struct pt_regs *regs)
2491{
2492 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2493 die_if_kernel("TL1: Tag Overflow Exception", regs);
2494}
2495
2496void do_getpsr(struct pt_regs *regs)
2497{
2498 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2499 regs->tpc = regs->tnpc;
2500 regs->tnpc += 4;
2501 if (test_thread_flag(TIF_32BIT)) {
2502 regs->tpc &= 0xffffffff;
2503 regs->tnpc &= 0xffffffff;
2504 }
2505}
2506
2507struct trap_per_cpu trap_block[NR_CPUS];
2508EXPORT_SYMBOL(trap_block);
2509
2510/* This can get invoked before sched_init() so play it super safe
2511 * and use hard_smp_processor_id().
2512 */
2513void notrace init_cur_cpu_trap(struct thread_info *t)
2514{
2515 int cpu = hard_smp_processor_id();
2516 struct trap_per_cpu *p = &trap_block[cpu];
2517
2518 p->thread = t;
2519 p->pgd_paddr = 0;
2520}
2521
2522extern void thread_info_offsets_are_bolixed_dave(void);
2523extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2524extern void tsb_config_offsets_are_bolixed_dave(void);
2525
2526/* Only invoked on boot processor. */
2527void __init trap_init(void)
2528{
2529 /* Compile time sanity check. */
2530 BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2531 TI_FLAGS != offsetof(struct thread_info, flags) ||
2532 TI_CPU != offsetof(struct thread_info, cpu) ||
2533 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2534 TI_KSP != offsetof(struct thread_info, ksp) ||
2535 TI_FAULT_ADDR != offsetof(struct thread_info,
2536 fault_address) ||
2537 TI_KREGS != offsetof(struct thread_info, kregs) ||
2538 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2539 TI_EXEC_DOMAIN != offsetof(struct thread_info,
2540 exec_domain) ||
2541 TI_REG_WINDOW != offsetof(struct thread_info,
2542 reg_window) ||
2543 TI_RWIN_SPTRS != offsetof(struct thread_info,
2544 rwbuf_stkptrs) ||
2545 TI_GSR != offsetof(struct thread_info, gsr) ||
2546 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2547 TI_PRE_COUNT != offsetof(struct thread_info,
2548 preempt_count) ||
2549 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2550 TI_SYS_NOERROR != offsetof(struct thread_info,
2551 syscall_noerror) ||
2552 TI_RESTART_BLOCK != offsetof(struct thread_info,
2553 restart_block) ||
2554 TI_KUNA_REGS != offsetof(struct thread_info,
2555 kern_una_regs) ||
2556 TI_KUNA_INSN != offsetof(struct thread_info,
2557 kern_una_insn) ||
2558 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2559 (TI_FPREGS & (64 - 1)));
2560
2561 BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2562 thread) ||
2563 (TRAP_PER_CPU_PGD_PADDR !=
2564 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2565 (TRAP_PER_CPU_CPU_MONDO_PA !=
2566 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2567 (TRAP_PER_CPU_DEV_MONDO_PA !=
2568 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2569 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2570 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2571 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2572 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2573 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2574 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2575 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2576 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2577 (TRAP_PER_CPU_FAULT_INFO !=
2578 offsetof(struct trap_per_cpu, fault_info)) ||
2579 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2580 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2581 (TRAP_PER_CPU_CPU_LIST_PA !=
2582 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2583 (TRAP_PER_CPU_TSB_HUGE !=
2584 offsetof(struct trap_per_cpu, tsb_huge)) ||
2585 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2586 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2587 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2588 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2589 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2590 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2591 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2592 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2593 (TRAP_PER_CPU_RESUM_QMASK !=
2594 offsetof(struct trap_per_cpu, resum_qmask)) ||
2595 (TRAP_PER_CPU_NONRESUM_QMASK !=
2596 offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2597 (TRAP_PER_CPU_PER_CPU_BASE !=
2598 offsetof(struct trap_per_cpu, __per_cpu_base)));
2599
2600 BUILD_BUG_ON((TSB_CONFIG_TSB !=
2601 offsetof(struct tsb_config, tsb)) ||
2602 (TSB_CONFIG_RSS_LIMIT !=
2603 offsetof(struct tsb_config, tsb_rss_limit)) ||
2604 (TSB_CONFIG_NENTRIES !=
2605 offsetof(struct tsb_config, tsb_nentries)) ||
2606 (TSB_CONFIG_REG_VAL !=
2607 offsetof(struct tsb_config, tsb_reg_val)) ||
2608 (TSB_CONFIG_MAP_VADDR !=
2609 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2610 (TSB_CONFIG_MAP_PTE !=
2611 offsetof(struct tsb_config, tsb_map_pte)));
2612
2613 /* Attach to the address space of init_task. On SMP we
2614 * do this in smp.c:smp_callin for other cpus.
2615 */
2616 atomic_inc(&init_mm.mm_count);
2617 current->active_mm = &init_mm;
2618}
1/* arch/sparc64/kernel/traps.c
2 *
3 * Copyright (C) 1995,1997,2008,2009,2012 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
5 */
6
7/*
8 * I like traps on v9, :))))
9 */
10
11#include <linux/extable.h>
12#include <linux/sched.h>
13#include <linux/linkage.h>
14#include <linux/kernel.h>
15#include <linux/signal.h>
16#include <linux/smp.h>
17#include <linux/mm.h>
18#include <linux/init.h>
19#include <linux/kdebug.h>
20#include <linux/ftrace.h>
21#include <linux/reboot.h>
22#include <linux/gfp.h>
23#include <linux/context_tracking.h>
24
25#include <asm/smp.h>
26#include <asm/delay.h>
27#include <asm/ptrace.h>
28#include <asm/oplib.h>
29#include <asm/page.h>
30#include <asm/pgtable.h>
31#include <asm/unistd.h>
32#include <linux/uaccess.h>
33#include <asm/fpumacro.h>
34#include <asm/lsu.h>
35#include <asm/dcu.h>
36#include <asm/estate.h>
37#include <asm/chafsr.h>
38#include <asm/sfafsr.h>
39#include <asm/psrcompat.h>
40#include <asm/processor.h>
41#include <asm/timer.h>
42#include <asm/head.h>
43#include <asm/prom.h>
44#include <asm/memctrl.h>
45#include <asm/cacheflush.h>
46#include <asm/setup.h>
47
48#include "entry.h"
49#include "kernel.h"
50#include "kstack.h"
51
52/* When an irrecoverable trap occurs at tl > 0, the trap entry
53 * code logs the trap state registers at every level in the trap
54 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
55 * is as follows:
56 */
57struct tl1_traplog {
58 struct {
59 unsigned long tstate;
60 unsigned long tpc;
61 unsigned long tnpc;
62 unsigned long tt;
63 } trapstack[4];
64 unsigned long tl;
65};
66
67static void dump_tl1_traplog(struct tl1_traplog *p)
68{
69 int i, limit;
70
71 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
72 "dumping track stack.\n", p->tl);
73
74 limit = (tlb_type == hypervisor) ? 2 : 4;
75 for (i = 0; i < limit; i++) {
76 printk(KERN_EMERG
77 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
78 "TNPC[%016lx] TT[%lx]\n",
79 i + 1,
80 p->trapstack[i].tstate, p->trapstack[i].tpc,
81 p->trapstack[i].tnpc, p->trapstack[i].tt);
82 printk("TRAPLOG: TPC<%pS>\n", (void *) p->trapstack[i].tpc);
83 }
84}
85
86void bad_trap(struct pt_regs *regs, long lvl)
87{
88 char buffer[36];
89 siginfo_t info;
90
91 if (notify_die(DIE_TRAP, "bad trap", regs,
92 0, lvl, SIGTRAP) == NOTIFY_STOP)
93 return;
94
95 if (lvl < 0x100) {
96 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
97 die_if_kernel(buffer, regs);
98 }
99
100 lvl -= 0x100;
101 if (regs->tstate & TSTATE_PRIV) {
102 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
103 die_if_kernel(buffer, regs);
104 }
105 if (test_thread_flag(TIF_32BIT)) {
106 regs->tpc &= 0xffffffff;
107 regs->tnpc &= 0xffffffff;
108 }
109 info.si_signo = SIGILL;
110 info.si_errno = 0;
111 info.si_code = ILL_ILLTRP;
112 info.si_addr = (void __user *)regs->tpc;
113 info.si_trapno = lvl;
114 force_sig_info(SIGILL, &info, current);
115}
116
117void bad_trap_tl1(struct pt_regs *regs, long lvl)
118{
119 char buffer[36];
120
121 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
122 0, lvl, SIGTRAP) == NOTIFY_STOP)
123 return;
124
125 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
126
127 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
128 die_if_kernel (buffer, regs);
129}
130
131#ifdef CONFIG_DEBUG_BUGVERBOSE
132void do_BUG(const char *file, int line)
133{
134 bust_spinlocks(1);
135 printk("kernel BUG at %s:%d!\n", file, line);
136}
137EXPORT_SYMBOL(do_BUG);
138#endif
139
140static DEFINE_SPINLOCK(dimm_handler_lock);
141static dimm_printer_t dimm_handler;
142
143static int sprintf_dimm(int synd_code, unsigned long paddr, char *buf, int buflen)
144{
145 unsigned long flags;
146 int ret = -ENODEV;
147
148 spin_lock_irqsave(&dimm_handler_lock, flags);
149 if (dimm_handler) {
150 ret = dimm_handler(synd_code, paddr, buf, buflen);
151 } else if (tlb_type == spitfire) {
152 if (prom_getunumber(synd_code, paddr, buf, buflen) == -1)
153 ret = -EINVAL;
154 else
155 ret = 0;
156 } else
157 ret = -ENODEV;
158 spin_unlock_irqrestore(&dimm_handler_lock, flags);
159
160 return ret;
161}
162
163int register_dimm_printer(dimm_printer_t func)
164{
165 unsigned long flags;
166 int ret = 0;
167
168 spin_lock_irqsave(&dimm_handler_lock, flags);
169 if (!dimm_handler)
170 dimm_handler = func;
171 else
172 ret = -EEXIST;
173 spin_unlock_irqrestore(&dimm_handler_lock, flags);
174
175 return ret;
176}
177EXPORT_SYMBOL_GPL(register_dimm_printer);
178
179void unregister_dimm_printer(dimm_printer_t func)
180{
181 unsigned long flags;
182
183 spin_lock_irqsave(&dimm_handler_lock, flags);
184 if (dimm_handler == func)
185 dimm_handler = NULL;
186 spin_unlock_irqrestore(&dimm_handler_lock, flags);
187}
188EXPORT_SYMBOL_GPL(unregister_dimm_printer);
189
190void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
191{
192 enum ctx_state prev_state = exception_enter();
193 siginfo_t info;
194
195 if (notify_die(DIE_TRAP, "instruction access exception", regs,
196 0, 0x8, SIGTRAP) == NOTIFY_STOP)
197 goto out;
198
199 if (regs->tstate & TSTATE_PRIV) {
200 printk("spitfire_insn_access_exception: SFSR[%016lx] "
201 "SFAR[%016lx], going.\n", sfsr, sfar);
202 die_if_kernel("Iax", regs);
203 }
204 if (test_thread_flag(TIF_32BIT)) {
205 regs->tpc &= 0xffffffff;
206 regs->tnpc &= 0xffffffff;
207 }
208 info.si_signo = SIGSEGV;
209 info.si_errno = 0;
210 info.si_code = SEGV_MAPERR;
211 info.si_addr = (void __user *)regs->tpc;
212 info.si_trapno = 0;
213 force_sig_info(SIGSEGV, &info, current);
214out:
215 exception_exit(prev_state);
216}
217
218void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
219{
220 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
221 0, 0x8, SIGTRAP) == NOTIFY_STOP)
222 return;
223
224 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
225 spitfire_insn_access_exception(regs, sfsr, sfar);
226}
227
228void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
229{
230 unsigned short type = (type_ctx >> 16);
231 unsigned short ctx = (type_ctx & 0xffff);
232 siginfo_t info;
233
234 if (notify_die(DIE_TRAP, "instruction access exception", regs,
235 0, 0x8, SIGTRAP) == NOTIFY_STOP)
236 return;
237
238 if (regs->tstate & TSTATE_PRIV) {
239 printk("sun4v_insn_access_exception: ADDR[%016lx] "
240 "CTX[%04x] TYPE[%04x], going.\n",
241 addr, ctx, type);
242 die_if_kernel("Iax", regs);
243 }
244
245 if (test_thread_flag(TIF_32BIT)) {
246 regs->tpc &= 0xffffffff;
247 regs->tnpc &= 0xffffffff;
248 }
249 info.si_signo = SIGSEGV;
250 info.si_errno = 0;
251 info.si_code = SEGV_MAPERR;
252 info.si_addr = (void __user *) addr;
253 info.si_trapno = 0;
254 force_sig_info(SIGSEGV, &info, current);
255}
256
257void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
258{
259 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
260 0, 0x8, SIGTRAP) == NOTIFY_STOP)
261 return;
262
263 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
264 sun4v_insn_access_exception(regs, addr, type_ctx);
265}
266
267void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
268{
269 enum ctx_state prev_state = exception_enter();
270 siginfo_t info;
271
272 if (notify_die(DIE_TRAP, "data access exception", regs,
273 0, 0x30, SIGTRAP) == NOTIFY_STOP)
274 goto out;
275
276 if (regs->tstate & TSTATE_PRIV) {
277 /* Test if this comes from uaccess places. */
278 const struct exception_table_entry *entry;
279
280 entry = search_exception_tables(regs->tpc);
281 if (entry) {
282 /* Ouch, somebody is trying VM hole tricks on us... */
283#ifdef DEBUG_EXCEPTIONS
284 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
285 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
286 regs->tpc, entry->fixup);
287#endif
288 regs->tpc = entry->fixup;
289 regs->tnpc = regs->tpc + 4;
290 goto out;
291 }
292 /* Shit... */
293 printk("spitfire_data_access_exception: SFSR[%016lx] "
294 "SFAR[%016lx], going.\n", sfsr, sfar);
295 die_if_kernel("Dax", regs);
296 }
297
298 info.si_signo = SIGSEGV;
299 info.si_errno = 0;
300 info.si_code = SEGV_MAPERR;
301 info.si_addr = (void __user *)sfar;
302 info.si_trapno = 0;
303 force_sig_info(SIGSEGV, &info, current);
304out:
305 exception_exit(prev_state);
306}
307
308void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
309{
310 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
311 0, 0x30, SIGTRAP) == NOTIFY_STOP)
312 return;
313
314 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
315 spitfire_data_access_exception(regs, sfsr, sfar);
316}
317
318void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
319{
320 unsigned short type = (type_ctx >> 16);
321 unsigned short ctx = (type_ctx & 0xffff);
322 siginfo_t info;
323
324 if (notify_die(DIE_TRAP, "data access exception", regs,
325 0, 0x8, SIGTRAP) == NOTIFY_STOP)
326 return;
327
328 if (regs->tstate & TSTATE_PRIV) {
329 /* Test if this comes from uaccess places. */
330 const struct exception_table_entry *entry;
331
332 entry = search_exception_tables(regs->tpc);
333 if (entry) {
334 /* Ouch, somebody is trying VM hole tricks on us... */
335#ifdef DEBUG_EXCEPTIONS
336 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
337 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
338 regs->tpc, entry->fixup);
339#endif
340 regs->tpc = entry->fixup;
341 regs->tnpc = regs->tpc + 4;
342 return;
343 }
344 printk("sun4v_data_access_exception: ADDR[%016lx] "
345 "CTX[%04x] TYPE[%04x], going.\n",
346 addr, ctx, type);
347 die_if_kernel("Dax", regs);
348 }
349
350 if (test_thread_flag(TIF_32BIT)) {
351 regs->tpc &= 0xffffffff;
352 regs->tnpc &= 0xffffffff;
353 }
354 info.si_signo = SIGSEGV;
355 info.si_errno = 0;
356 info.si_code = SEGV_MAPERR;
357 info.si_addr = (void __user *) addr;
358 info.si_trapno = 0;
359 force_sig_info(SIGSEGV, &info, current);
360}
361
362void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
363{
364 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
365 0, 0x8, SIGTRAP) == NOTIFY_STOP)
366 return;
367
368 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
369 sun4v_data_access_exception(regs, addr, type_ctx);
370}
371
372#ifdef CONFIG_PCI
373#include "pci_impl.h"
374#endif
375
376/* When access exceptions happen, we must do this. */
377static void spitfire_clean_and_reenable_l1_caches(void)
378{
379 unsigned long va;
380
381 if (tlb_type != spitfire)
382 BUG();
383
384 /* Clean 'em. */
385 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
386 spitfire_put_icache_tag(va, 0x0);
387 spitfire_put_dcache_tag(va, 0x0);
388 }
389
390 /* Re-enable in LSU. */
391 __asm__ __volatile__("flush %%g6\n\t"
392 "membar #Sync\n\t"
393 "stxa %0, [%%g0] %1\n\t"
394 "membar #Sync"
395 : /* no outputs */
396 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
397 LSU_CONTROL_IM | LSU_CONTROL_DM),
398 "i" (ASI_LSU_CONTROL)
399 : "memory");
400}
401
402static void spitfire_enable_estate_errors(void)
403{
404 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
405 "membar #Sync"
406 : /* no outputs */
407 : "r" (ESTATE_ERR_ALL),
408 "i" (ASI_ESTATE_ERROR_EN));
409}
410
411static char ecc_syndrome_table[] = {
412 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
413 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
414 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
415 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
416 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
417 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
418 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
419 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
420 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
421 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
422 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
423 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
424 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
425 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
426 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
427 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
428 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
429 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
430 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
431 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
432 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
433 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
434 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
435 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
436 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
437 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
438 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
439 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
440 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
441 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
442 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
443 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
444};
445
446static char *syndrome_unknown = "<Unknown>";
447
448static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
449{
450 unsigned short scode;
451 char memmod_str[64], *p;
452
453 if (udbl & bit) {
454 scode = ecc_syndrome_table[udbl & 0xff];
455 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
456 p = syndrome_unknown;
457 else
458 p = memmod_str;
459 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
460 "Memory Module \"%s\"\n",
461 smp_processor_id(), scode, p);
462 }
463
464 if (udbh & bit) {
465 scode = ecc_syndrome_table[udbh & 0xff];
466 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0)
467 p = syndrome_unknown;
468 else
469 p = memmod_str;
470 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
471 "Memory Module \"%s\"\n",
472 smp_processor_id(), scode, p);
473 }
474
475}
476
477static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
478{
479
480 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
481 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
482 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
483
484 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
485
486 /* We always log it, even if someone is listening for this
487 * trap.
488 */
489 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
490 0, TRAP_TYPE_CEE, SIGTRAP);
491
492 /* The Correctable ECC Error trap does not disable I/D caches. So
493 * we only have to restore the ESTATE Error Enable register.
494 */
495 spitfire_enable_estate_errors();
496}
497
498static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
499{
500 siginfo_t info;
501
502 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
503 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
504 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
505
506 /* XXX add more human friendly logging of the error status
507 * XXX as is implemented for cheetah
508 */
509
510 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
511
512 /* We always log it, even if someone is listening for this
513 * trap.
514 */
515 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
516 0, tt, SIGTRAP);
517
518 if (regs->tstate & TSTATE_PRIV) {
519 if (tl1)
520 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
521 die_if_kernel("UE", regs);
522 }
523
524 /* XXX need more intelligent processing here, such as is implemented
525 * XXX for cheetah errors, in fact if the E-cache still holds the
526 * XXX line with bad parity this will loop
527 */
528
529 spitfire_clean_and_reenable_l1_caches();
530 spitfire_enable_estate_errors();
531
532 if (test_thread_flag(TIF_32BIT)) {
533 regs->tpc &= 0xffffffff;
534 regs->tnpc &= 0xffffffff;
535 }
536 info.si_signo = SIGBUS;
537 info.si_errno = 0;
538 info.si_code = BUS_OBJERR;
539 info.si_addr = (void *)0;
540 info.si_trapno = 0;
541 force_sig_info(SIGBUS, &info, current);
542}
543
544void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
545{
546 unsigned long afsr, tt, udbh, udbl;
547 int tl1;
548
549 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
550 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
551 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
552 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
553 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
554
555#ifdef CONFIG_PCI
556 if (tt == TRAP_TYPE_DAE &&
557 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
558 spitfire_clean_and_reenable_l1_caches();
559 spitfire_enable_estate_errors();
560
561 pci_poke_faulted = 1;
562 regs->tnpc = regs->tpc + 4;
563 return;
564 }
565#endif
566
567 if (afsr & SFAFSR_UE)
568 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
569
570 if (tt == TRAP_TYPE_CEE) {
571 /* Handle the case where we took a CEE trap, but ACK'd
572 * only the UE state in the UDB error registers.
573 */
574 if (afsr & SFAFSR_UE) {
575 if (udbh & UDBE_CE) {
576 __asm__ __volatile__(
577 "stxa %0, [%1] %2\n\t"
578 "membar #Sync"
579 : /* no outputs */
580 : "r" (udbh & UDBE_CE),
581 "r" (0x0), "i" (ASI_UDB_ERROR_W));
582 }
583 if (udbl & UDBE_CE) {
584 __asm__ __volatile__(
585 "stxa %0, [%1] %2\n\t"
586 "membar #Sync"
587 : /* no outputs */
588 : "r" (udbl & UDBE_CE),
589 "r" (0x18), "i" (ASI_UDB_ERROR_W));
590 }
591 }
592
593 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
594 }
595}
596
597int cheetah_pcache_forced_on;
598
599void cheetah_enable_pcache(void)
600{
601 unsigned long dcr;
602
603 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
604 smp_processor_id());
605
606 __asm__ __volatile__("ldxa [%%g0] %1, %0"
607 : "=r" (dcr)
608 : "i" (ASI_DCU_CONTROL_REG));
609 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
610 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
611 "membar #Sync"
612 : /* no outputs */
613 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
614}
615
616/* Cheetah error trap handling. */
617static unsigned long ecache_flush_physbase;
618static unsigned long ecache_flush_linesize;
619static unsigned long ecache_flush_size;
620
621/* This table is ordered in priority of errors and matches the
622 * AFAR overwrite policy as well.
623 */
624
625struct afsr_error_table {
626 unsigned long mask;
627 const char *name;
628};
629
630static const char CHAFSR_PERR_msg[] =
631 "System interface protocol error";
632static const char CHAFSR_IERR_msg[] =
633 "Internal processor error";
634static const char CHAFSR_ISAP_msg[] =
635 "System request parity error on incoming address";
636static const char CHAFSR_UCU_msg[] =
637 "Uncorrectable E-cache ECC error for ifetch/data";
638static const char CHAFSR_UCC_msg[] =
639 "SW Correctable E-cache ECC error for ifetch/data";
640static const char CHAFSR_UE_msg[] =
641 "Uncorrectable system bus data ECC error for read";
642static const char CHAFSR_EDU_msg[] =
643 "Uncorrectable E-cache ECC error for stmerge/blkld";
644static const char CHAFSR_EMU_msg[] =
645 "Uncorrectable system bus MTAG error";
646static const char CHAFSR_WDU_msg[] =
647 "Uncorrectable E-cache ECC error for writeback";
648static const char CHAFSR_CPU_msg[] =
649 "Uncorrectable ECC error for copyout";
650static const char CHAFSR_CE_msg[] =
651 "HW corrected system bus data ECC error for read";
652static const char CHAFSR_EDC_msg[] =
653 "HW corrected E-cache ECC error for stmerge/blkld";
654static const char CHAFSR_EMC_msg[] =
655 "HW corrected system bus MTAG ECC error";
656static const char CHAFSR_WDC_msg[] =
657 "HW corrected E-cache ECC error for writeback";
658static const char CHAFSR_CPC_msg[] =
659 "HW corrected ECC error for copyout";
660static const char CHAFSR_TO_msg[] =
661 "Unmapped error from system bus";
662static const char CHAFSR_BERR_msg[] =
663 "Bus error response from system bus";
664static const char CHAFSR_IVC_msg[] =
665 "HW corrected system bus data ECC error for ivec read";
666static const char CHAFSR_IVU_msg[] =
667 "Uncorrectable system bus data ECC error for ivec read";
668static struct afsr_error_table __cheetah_error_table[] = {
669 { CHAFSR_PERR, CHAFSR_PERR_msg },
670 { CHAFSR_IERR, CHAFSR_IERR_msg },
671 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
672 { CHAFSR_UCU, CHAFSR_UCU_msg },
673 { CHAFSR_UCC, CHAFSR_UCC_msg },
674 { CHAFSR_UE, CHAFSR_UE_msg },
675 { CHAFSR_EDU, CHAFSR_EDU_msg },
676 { CHAFSR_EMU, CHAFSR_EMU_msg },
677 { CHAFSR_WDU, CHAFSR_WDU_msg },
678 { CHAFSR_CPU, CHAFSR_CPU_msg },
679 { CHAFSR_CE, CHAFSR_CE_msg },
680 { CHAFSR_EDC, CHAFSR_EDC_msg },
681 { CHAFSR_EMC, CHAFSR_EMC_msg },
682 { CHAFSR_WDC, CHAFSR_WDC_msg },
683 { CHAFSR_CPC, CHAFSR_CPC_msg },
684 { CHAFSR_TO, CHAFSR_TO_msg },
685 { CHAFSR_BERR, CHAFSR_BERR_msg },
686 /* These two do not update the AFAR. */
687 { CHAFSR_IVC, CHAFSR_IVC_msg },
688 { CHAFSR_IVU, CHAFSR_IVU_msg },
689 { 0, NULL },
690};
691static const char CHPAFSR_DTO_msg[] =
692 "System bus unmapped error for prefetch/storequeue-read";
693static const char CHPAFSR_DBERR_msg[] =
694 "System bus error for prefetch/storequeue-read";
695static const char CHPAFSR_THCE_msg[] =
696 "Hardware corrected E-cache Tag ECC error";
697static const char CHPAFSR_TSCE_msg[] =
698 "SW handled correctable E-cache Tag ECC error";
699static const char CHPAFSR_TUE_msg[] =
700 "Uncorrectable E-cache Tag ECC error";
701static const char CHPAFSR_DUE_msg[] =
702 "System bus uncorrectable data ECC error due to prefetch/store-fill";
703static struct afsr_error_table __cheetah_plus_error_table[] = {
704 { CHAFSR_PERR, CHAFSR_PERR_msg },
705 { CHAFSR_IERR, CHAFSR_IERR_msg },
706 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
707 { CHAFSR_UCU, CHAFSR_UCU_msg },
708 { CHAFSR_UCC, CHAFSR_UCC_msg },
709 { CHAFSR_UE, CHAFSR_UE_msg },
710 { CHAFSR_EDU, CHAFSR_EDU_msg },
711 { CHAFSR_EMU, CHAFSR_EMU_msg },
712 { CHAFSR_WDU, CHAFSR_WDU_msg },
713 { CHAFSR_CPU, CHAFSR_CPU_msg },
714 { CHAFSR_CE, CHAFSR_CE_msg },
715 { CHAFSR_EDC, CHAFSR_EDC_msg },
716 { CHAFSR_EMC, CHAFSR_EMC_msg },
717 { CHAFSR_WDC, CHAFSR_WDC_msg },
718 { CHAFSR_CPC, CHAFSR_CPC_msg },
719 { CHAFSR_TO, CHAFSR_TO_msg },
720 { CHAFSR_BERR, CHAFSR_BERR_msg },
721 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
722 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
723 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
724 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
725 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
726 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
727 /* These two do not update the AFAR. */
728 { CHAFSR_IVC, CHAFSR_IVC_msg },
729 { CHAFSR_IVU, CHAFSR_IVU_msg },
730 { 0, NULL },
731};
732static const char JPAFSR_JETO_msg[] =
733 "System interface protocol error, hw timeout caused";
734static const char JPAFSR_SCE_msg[] =
735 "Parity error on system snoop results";
736static const char JPAFSR_JEIC_msg[] =
737 "System interface protocol error, illegal command detected";
738static const char JPAFSR_JEIT_msg[] =
739 "System interface protocol error, illegal ADTYPE detected";
740static const char JPAFSR_OM_msg[] =
741 "Out of range memory error has occurred";
742static const char JPAFSR_ETP_msg[] =
743 "Parity error on L2 cache tag SRAM";
744static const char JPAFSR_UMS_msg[] =
745 "Error due to unsupported store";
746static const char JPAFSR_RUE_msg[] =
747 "Uncorrectable ECC error from remote cache/memory";
748static const char JPAFSR_RCE_msg[] =
749 "Correctable ECC error from remote cache/memory";
750static const char JPAFSR_BP_msg[] =
751 "JBUS parity error on returned read data";
752static const char JPAFSR_WBP_msg[] =
753 "JBUS parity error on data for writeback or block store";
754static const char JPAFSR_FRC_msg[] =
755 "Foreign read to DRAM incurring correctable ECC error";
756static const char JPAFSR_FRU_msg[] =
757 "Foreign read to DRAM incurring uncorrectable ECC error";
758static struct afsr_error_table __jalapeno_error_table[] = {
759 { JPAFSR_JETO, JPAFSR_JETO_msg },
760 { JPAFSR_SCE, JPAFSR_SCE_msg },
761 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
762 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
763 { CHAFSR_PERR, CHAFSR_PERR_msg },
764 { CHAFSR_IERR, CHAFSR_IERR_msg },
765 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
766 { CHAFSR_UCU, CHAFSR_UCU_msg },
767 { CHAFSR_UCC, CHAFSR_UCC_msg },
768 { CHAFSR_UE, CHAFSR_UE_msg },
769 { CHAFSR_EDU, CHAFSR_EDU_msg },
770 { JPAFSR_OM, JPAFSR_OM_msg },
771 { CHAFSR_WDU, CHAFSR_WDU_msg },
772 { CHAFSR_CPU, CHAFSR_CPU_msg },
773 { CHAFSR_CE, CHAFSR_CE_msg },
774 { CHAFSR_EDC, CHAFSR_EDC_msg },
775 { JPAFSR_ETP, JPAFSR_ETP_msg },
776 { CHAFSR_WDC, CHAFSR_WDC_msg },
777 { CHAFSR_CPC, CHAFSR_CPC_msg },
778 { CHAFSR_TO, CHAFSR_TO_msg },
779 { CHAFSR_BERR, CHAFSR_BERR_msg },
780 { JPAFSR_UMS, JPAFSR_UMS_msg },
781 { JPAFSR_RUE, JPAFSR_RUE_msg },
782 { JPAFSR_RCE, JPAFSR_RCE_msg },
783 { JPAFSR_BP, JPAFSR_BP_msg },
784 { JPAFSR_WBP, JPAFSR_WBP_msg },
785 { JPAFSR_FRC, JPAFSR_FRC_msg },
786 { JPAFSR_FRU, JPAFSR_FRU_msg },
787 /* These two do not update the AFAR. */
788 { CHAFSR_IVU, CHAFSR_IVU_msg },
789 { 0, NULL },
790};
791static struct afsr_error_table *cheetah_error_table;
792static unsigned long cheetah_afsr_errors;
793
794struct cheetah_err_info *cheetah_error_log;
795
796static inline struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
797{
798 struct cheetah_err_info *p;
799 int cpu = smp_processor_id();
800
801 if (!cheetah_error_log)
802 return NULL;
803
804 p = cheetah_error_log + (cpu * 2);
805 if ((afsr & CHAFSR_TL1) != 0UL)
806 p++;
807
808 return p;
809}
810
811extern unsigned int tl0_icpe[], tl1_icpe[];
812extern unsigned int tl0_dcpe[], tl1_dcpe[];
813extern unsigned int tl0_fecc[], tl1_fecc[];
814extern unsigned int tl0_cee[], tl1_cee[];
815extern unsigned int tl0_iae[], tl1_iae[];
816extern unsigned int tl0_dae[], tl1_dae[];
817extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
818extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
819extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
820extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
821extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
822
823void __init cheetah_ecache_flush_init(void)
824{
825 unsigned long largest_size, smallest_linesize, order, ver;
826 int i, sz;
827
828 /* Scan all cpu device tree nodes, note two values:
829 * 1) largest E-cache size
830 * 2) smallest E-cache line size
831 */
832 largest_size = 0UL;
833 smallest_linesize = ~0UL;
834
835 for (i = 0; i < NR_CPUS; i++) {
836 unsigned long val;
837
838 val = cpu_data(i).ecache_size;
839 if (!val)
840 continue;
841
842 if (val > largest_size)
843 largest_size = val;
844
845 val = cpu_data(i).ecache_line_size;
846 if (val < smallest_linesize)
847 smallest_linesize = val;
848
849 }
850
851 if (largest_size == 0UL || smallest_linesize == ~0UL) {
852 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
853 "parameters.\n");
854 prom_halt();
855 }
856
857 ecache_flush_size = (2 * largest_size);
858 ecache_flush_linesize = smallest_linesize;
859
860 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
861
862 if (ecache_flush_physbase == ~0UL) {
863 prom_printf("cheetah_ecache_flush_init: Cannot find %ld byte "
864 "contiguous physical memory.\n",
865 ecache_flush_size);
866 prom_halt();
867 }
868
869 /* Now allocate error trap reporting scoreboard. */
870 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
871 for (order = 0; order < MAX_ORDER; order++) {
872 if ((PAGE_SIZE << order) >= sz)
873 break;
874 }
875 cheetah_error_log = (struct cheetah_err_info *)
876 __get_free_pages(GFP_KERNEL, order);
877 if (!cheetah_error_log) {
878 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
879 "error logging scoreboard (%d bytes).\n", sz);
880 prom_halt();
881 }
882 memset(cheetah_error_log, 0, PAGE_SIZE << order);
883
884 /* Mark all AFSRs as invalid so that the trap handler will
885 * log new new information there.
886 */
887 for (i = 0; i < 2 * NR_CPUS; i++)
888 cheetah_error_log[i].afsr = CHAFSR_INVALID;
889
890 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
891 if ((ver >> 32) == __JALAPENO_ID ||
892 (ver >> 32) == __SERRANO_ID) {
893 cheetah_error_table = &__jalapeno_error_table[0];
894 cheetah_afsr_errors = JPAFSR_ERRORS;
895 } else if ((ver >> 32) == 0x003e0015) {
896 cheetah_error_table = &__cheetah_plus_error_table[0];
897 cheetah_afsr_errors = CHPAFSR_ERRORS;
898 } else {
899 cheetah_error_table = &__cheetah_error_table[0];
900 cheetah_afsr_errors = CHAFSR_ERRORS;
901 }
902
903 /* Now patch trap tables. */
904 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
905 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
906 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
907 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
908 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
909 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
910 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
911 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
912 if (tlb_type == cheetah_plus) {
913 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
914 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
915 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
916 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
917 }
918 flushi(PAGE_OFFSET);
919}
920
921static void cheetah_flush_ecache(void)
922{
923 unsigned long flush_base = ecache_flush_physbase;
924 unsigned long flush_linesize = ecache_flush_linesize;
925 unsigned long flush_size = ecache_flush_size;
926
927 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
928 " bne,pt %%xcc, 1b\n\t"
929 " ldxa [%2 + %0] %3, %%g0\n\t"
930 : "=&r" (flush_size)
931 : "0" (flush_size), "r" (flush_base),
932 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
933}
934
935static void cheetah_flush_ecache_line(unsigned long physaddr)
936{
937 unsigned long alias;
938
939 physaddr &= ~(8UL - 1UL);
940 physaddr = (ecache_flush_physbase +
941 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
942 alias = physaddr + (ecache_flush_size >> 1UL);
943 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
944 "ldxa [%1] %2, %%g0\n\t"
945 "membar #Sync"
946 : /* no outputs */
947 : "r" (physaddr), "r" (alias),
948 "i" (ASI_PHYS_USE_EC));
949}
950
951/* Unfortunately, the diagnostic access to the I-cache tags we need to
952 * use to clear the thing interferes with I-cache coherency transactions.
953 *
954 * So we must only flush the I-cache when it is disabled.
955 */
956static void __cheetah_flush_icache(void)
957{
958 unsigned int icache_size, icache_line_size;
959 unsigned long addr;
960
961 icache_size = local_cpu_data().icache_size;
962 icache_line_size = local_cpu_data().icache_line_size;
963
964 /* Clear the valid bits in all the tags. */
965 for (addr = 0; addr < icache_size; addr += icache_line_size) {
966 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
967 "membar #Sync"
968 : /* no outputs */
969 : "r" (addr | (2 << 3)),
970 "i" (ASI_IC_TAG));
971 }
972}
973
974static void cheetah_flush_icache(void)
975{
976 unsigned long dcu_save;
977
978 /* Save current DCU, disable I-cache. */
979 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
980 "or %0, %2, %%g1\n\t"
981 "stxa %%g1, [%%g0] %1\n\t"
982 "membar #Sync"
983 : "=r" (dcu_save)
984 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
985 : "g1");
986
987 __cheetah_flush_icache();
988
989 /* Restore DCU register */
990 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
991 "membar #Sync"
992 : /* no outputs */
993 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
994}
995
996static void cheetah_flush_dcache(void)
997{
998 unsigned int dcache_size, dcache_line_size;
999 unsigned long addr;
1000
1001 dcache_size = local_cpu_data().dcache_size;
1002 dcache_line_size = local_cpu_data().dcache_line_size;
1003
1004 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1005 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1006 "membar #Sync"
1007 : /* no outputs */
1008 : "r" (addr), "i" (ASI_DCACHE_TAG));
1009 }
1010}
1011
1012/* In order to make the even parity correct we must do two things.
1013 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
1014 * Next, we clear out all 32-bytes of data for that line. Data of
1015 * all-zero + tag parity value of zero == correct parity.
1016 */
1017static void cheetah_plus_zap_dcache_parity(void)
1018{
1019 unsigned int dcache_size, dcache_line_size;
1020 unsigned long addr;
1021
1022 dcache_size = local_cpu_data().dcache_size;
1023 dcache_line_size = local_cpu_data().dcache_line_size;
1024
1025 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
1026 unsigned long tag = (addr >> 14);
1027 unsigned long line;
1028
1029 __asm__ __volatile__("membar #Sync\n\t"
1030 "stxa %0, [%1] %2\n\t"
1031 "membar #Sync"
1032 : /* no outputs */
1033 : "r" (tag), "r" (addr),
1034 "i" (ASI_DCACHE_UTAG));
1035 for (line = addr; line < addr + dcache_line_size; line += 8)
1036 __asm__ __volatile__("membar #Sync\n\t"
1037 "stxa %%g0, [%0] %1\n\t"
1038 "membar #Sync"
1039 : /* no outputs */
1040 : "r" (line),
1041 "i" (ASI_DCACHE_DATA));
1042 }
1043}
1044
1045/* Conversion tables used to frob Cheetah AFSR syndrome values into
1046 * something palatable to the memory controller driver get_unumber
1047 * routine.
1048 */
1049#define MT0 137
1050#define MT1 138
1051#define MT2 139
1052#define NONE 254
1053#define MTC0 140
1054#define MTC1 141
1055#define MTC2 142
1056#define MTC3 143
1057#define C0 128
1058#define C1 129
1059#define C2 130
1060#define C3 131
1061#define C4 132
1062#define C5 133
1063#define C6 134
1064#define C7 135
1065#define C8 136
1066#define M2 144
1067#define M3 145
1068#define M4 146
1069#define M 147
1070static unsigned char cheetah_ecc_syntab[] = {
1071/*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1072/*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1073/*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1074/*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1075/*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1076/*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1077/*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1078/*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1079/*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1080/*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1081/*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1082/*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1083/*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1084/*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1085/*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1086/*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1087/*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1088/*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1089/*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1090/*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1091/*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1092/*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1093/*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1094/*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1095/*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1096/*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1097/*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1098/*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1099/*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1100/*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1101/*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1102/*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1103};
1104static unsigned char cheetah_mtag_syntab[] = {
1105 NONE, MTC0,
1106 MTC1, NONE,
1107 MTC2, NONE,
1108 NONE, MT0,
1109 MTC3, NONE,
1110 NONE, MT1,
1111 NONE, MT2,
1112 NONE, NONE
1113};
1114
1115/* Return the highest priority error conditon mentioned. */
1116static inline unsigned long cheetah_get_hipri(unsigned long afsr)
1117{
1118 unsigned long tmp = 0;
1119 int i;
1120
1121 for (i = 0; cheetah_error_table[i].mask; i++) {
1122 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1123 return tmp;
1124 }
1125 return tmp;
1126}
1127
1128static const char *cheetah_get_string(unsigned long bit)
1129{
1130 int i;
1131
1132 for (i = 0; cheetah_error_table[i].mask; i++) {
1133 if ((bit & cheetah_error_table[i].mask) != 0UL)
1134 return cheetah_error_table[i].name;
1135 }
1136 return "???";
1137}
1138
1139static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1140 unsigned long afsr, unsigned long afar, int recoverable)
1141{
1142 unsigned long hipri;
1143 char unum[256];
1144
1145 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1146 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1147 afsr, afar,
1148 (afsr & CHAFSR_TL1) ? 1 : 0);
1149 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1150 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1151 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1152 printk("%s" "ERROR(%d): ",
1153 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1154 printk("TPC<%pS>\n", (void *) regs->tpc);
1155 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1156 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1157 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1158 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1159 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1160 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1161 hipri = cheetah_get_hipri(afsr);
1162 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1163 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1164 hipri, cheetah_get_string(hipri));
1165
1166 /* Try to get unumber if relevant. */
1167#define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1168 CHAFSR_CPC | CHAFSR_CPU | \
1169 CHAFSR_UE | CHAFSR_CE | \
1170 CHAFSR_EDC | CHAFSR_EDU | \
1171 CHAFSR_UCC | CHAFSR_UCU | \
1172 CHAFSR_WDU | CHAFSR_WDC)
1173#define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1174 if (afsr & ESYND_ERRORS) {
1175 int syndrome;
1176 int ret;
1177
1178 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1179 syndrome = cheetah_ecc_syntab[syndrome];
1180 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1181 if (ret != -1)
1182 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1183 (recoverable ? KERN_WARNING : KERN_CRIT),
1184 smp_processor_id(), unum);
1185 } else if (afsr & MSYND_ERRORS) {
1186 int syndrome;
1187 int ret;
1188
1189 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1190 syndrome = cheetah_mtag_syntab[syndrome];
1191 ret = sprintf_dimm(syndrome, afar, unum, sizeof(unum));
1192 if (ret != -1)
1193 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1194 (recoverable ? KERN_WARNING : KERN_CRIT),
1195 smp_processor_id(), unum);
1196 }
1197
1198 /* Now dump the cache snapshots. */
1199 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx]\n",
1200 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1201 (int) info->dcache_index,
1202 info->dcache_tag,
1203 info->dcache_utag,
1204 info->dcache_stag);
1205 printk("%s" "ERROR(%d): D-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1206 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1207 info->dcache_data[0],
1208 info->dcache_data[1],
1209 info->dcache_data[2],
1210 info->dcache_data[3]);
1211 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016llx] utag[%016llx] stag[%016llx] "
1212 "u[%016llx] l[%016llx]\n",
1213 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1214 (int) info->icache_index,
1215 info->icache_tag,
1216 info->icache_utag,
1217 info->icache_stag,
1218 info->icache_upper,
1219 info->icache_lower);
1220 printk("%s" "ERROR(%d): I-cache INSN0[%016llx] INSN1[%016llx] INSN2[%016llx] INSN3[%016llx]\n",
1221 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1222 info->icache_data[0],
1223 info->icache_data[1],
1224 info->icache_data[2],
1225 info->icache_data[3]);
1226 printk("%s" "ERROR(%d): I-cache INSN4[%016llx] INSN5[%016llx] INSN6[%016llx] INSN7[%016llx]\n",
1227 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1228 info->icache_data[4],
1229 info->icache_data[5],
1230 info->icache_data[6],
1231 info->icache_data[7]);
1232 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016llx]\n",
1233 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1234 (int) info->ecache_index, info->ecache_tag);
1235 printk("%s" "ERROR(%d): E-cache data0[%016llx] data1[%016llx] data2[%016llx] data3[%016llx]\n",
1236 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1237 info->ecache_data[0],
1238 info->ecache_data[1],
1239 info->ecache_data[2],
1240 info->ecache_data[3]);
1241
1242 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1243 while (afsr != 0UL) {
1244 unsigned long bit = cheetah_get_hipri(afsr);
1245
1246 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1247 (recoverable ? KERN_WARNING : KERN_CRIT),
1248 bit, cheetah_get_string(bit));
1249
1250 afsr &= ~bit;
1251 }
1252
1253 if (!recoverable)
1254 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1255}
1256
1257static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1258{
1259 unsigned long afsr, afar;
1260 int ret = 0;
1261
1262 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1263 : "=r" (afsr)
1264 : "i" (ASI_AFSR));
1265 if ((afsr & cheetah_afsr_errors) != 0) {
1266 if (logp != NULL) {
1267 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1268 : "=r" (afar)
1269 : "i" (ASI_AFAR));
1270 logp->afsr = afsr;
1271 logp->afar = afar;
1272 }
1273 ret = 1;
1274 }
1275 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1276 "membar #Sync\n\t"
1277 : : "r" (afsr), "i" (ASI_AFSR));
1278
1279 return ret;
1280}
1281
1282void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1283{
1284 struct cheetah_err_info local_snapshot, *p;
1285 int recoverable;
1286
1287 /* Flush E-cache */
1288 cheetah_flush_ecache();
1289
1290 p = cheetah_get_error_log(afsr);
1291 if (!p) {
1292 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1293 afsr, afar);
1294 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1295 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1296 prom_halt();
1297 }
1298
1299 /* Grab snapshot of logged error. */
1300 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1301
1302 /* If the current trap snapshot does not match what the
1303 * trap handler passed along into our args, big trouble.
1304 * In such a case, mark the local copy as invalid.
1305 *
1306 * Else, it matches and we mark the afsr in the non-local
1307 * copy as invalid so we may log new error traps there.
1308 */
1309 if (p->afsr != afsr || p->afar != afar)
1310 local_snapshot.afsr = CHAFSR_INVALID;
1311 else
1312 p->afsr = CHAFSR_INVALID;
1313
1314 cheetah_flush_icache();
1315 cheetah_flush_dcache();
1316
1317 /* Re-enable I-cache/D-cache */
1318 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1319 "or %%g1, %1, %%g1\n\t"
1320 "stxa %%g1, [%%g0] %0\n\t"
1321 "membar #Sync"
1322 : /* no outputs */
1323 : "i" (ASI_DCU_CONTROL_REG),
1324 "i" (DCU_DC | DCU_IC)
1325 : "g1");
1326
1327 /* Re-enable error reporting */
1328 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1329 "or %%g1, %1, %%g1\n\t"
1330 "stxa %%g1, [%%g0] %0\n\t"
1331 "membar #Sync"
1332 : /* no outputs */
1333 : "i" (ASI_ESTATE_ERROR_EN),
1334 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1335 : "g1");
1336
1337 /* Decide if we can continue after handling this trap and
1338 * logging the error.
1339 */
1340 recoverable = 1;
1341 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1342 recoverable = 0;
1343
1344 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1345 * error was logged while we had error reporting traps disabled.
1346 */
1347 if (cheetah_recheck_errors(&local_snapshot)) {
1348 unsigned long new_afsr = local_snapshot.afsr;
1349
1350 /* If we got a new asynchronous error, die... */
1351 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1352 CHAFSR_WDU | CHAFSR_CPU |
1353 CHAFSR_IVU | CHAFSR_UE |
1354 CHAFSR_BERR | CHAFSR_TO))
1355 recoverable = 0;
1356 }
1357
1358 /* Log errors. */
1359 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1360
1361 if (!recoverable)
1362 panic("Irrecoverable Fast-ECC error trap.\n");
1363
1364 /* Flush E-cache to kick the error trap handlers out. */
1365 cheetah_flush_ecache();
1366}
1367
1368/* Try to fix a correctable error by pushing the line out from
1369 * the E-cache. Recheck error reporting registers to see if the
1370 * problem is intermittent.
1371 */
1372static int cheetah_fix_ce(unsigned long physaddr)
1373{
1374 unsigned long orig_estate;
1375 unsigned long alias1, alias2;
1376 int ret;
1377
1378 /* Make sure correctable error traps are disabled. */
1379 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1380 "andn %0, %1, %%g1\n\t"
1381 "stxa %%g1, [%%g0] %2\n\t"
1382 "membar #Sync"
1383 : "=&r" (orig_estate)
1384 : "i" (ESTATE_ERROR_CEEN),
1385 "i" (ASI_ESTATE_ERROR_EN)
1386 : "g1");
1387
1388 /* We calculate alias addresses that will force the
1389 * cache line in question out of the E-cache. Then
1390 * we bring it back in with an atomic instruction so
1391 * that we get it in some modified/exclusive state,
1392 * then we displace it again to try and get proper ECC
1393 * pushed back into the system.
1394 */
1395 physaddr &= ~(8UL - 1UL);
1396 alias1 = (ecache_flush_physbase +
1397 (physaddr & ((ecache_flush_size >> 1) - 1)));
1398 alias2 = alias1 + (ecache_flush_size >> 1);
1399 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1400 "ldxa [%1] %3, %%g0\n\t"
1401 "casxa [%2] %3, %%g0, %%g0\n\t"
1402 "ldxa [%0] %3, %%g0\n\t"
1403 "ldxa [%1] %3, %%g0\n\t"
1404 "membar #Sync"
1405 : /* no outputs */
1406 : "r" (alias1), "r" (alias2),
1407 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1408
1409 /* Did that trigger another error? */
1410 if (cheetah_recheck_errors(NULL)) {
1411 /* Try one more time. */
1412 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1413 "membar #Sync"
1414 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1415 if (cheetah_recheck_errors(NULL))
1416 ret = 2;
1417 else
1418 ret = 1;
1419 } else {
1420 /* No new error, intermittent problem. */
1421 ret = 0;
1422 }
1423
1424 /* Restore error enables. */
1425 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1426 "membar #Sync"
1427 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1428
1429 return ret;
1430}
1431
1432/* Return non-zero if PADDR is a valid physical memory address. */
1433static int cheetah_check_main_memory(unsigned long paddr)
1434{
1435 unsigned long vaddr = PAGE_OFFSET + paddr;
1436
1437 if (vaddr > (unsigned long) high_memory)
1438 return 0;
1439
1440 return kern_addr_valid(vaddr);
1441}
1442
1443void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1444{
1445 struct cheetah_err_info local_snapshot, *p;
1446 int recoverable, is_memory;
1447
1448 p = cheetah_get_error_log(afsr);
1449 if (!p) {
1450 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1451 afsr, afar);
1452 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1453 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1454 prom_halt();
1455 }
1456
1457 /* Grab snapshot of logged error. */
1458 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1459
1460 /* If the current trap snapshot does not match what the
1461 * trap handler passed along into our args, big trouble.
1462 * In such a case, mark the local copy as invalid.
1463 *
1464 * Else, it matches and we mark the afsr in the non-local
1465 * copy as invalid so we may log new error traps there.
1466 */
1467 if (p->afsr != afsr || p->afar != afar)
1468 local_snapshot.afsr = CHAFSR_INVALID;
1469 else
1470 p->afsr = CHAFSR_INVALID;
1471
1472 is_memory = cheetah_check_main_memory(afar);
1473
1474 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1475 /* XXX Might want to log the results of this operation
1476 * XXX somewhere... -DaveM
1477 */
1478 cheetah_fix_ce(afar);
1479 }
1480
1481 {
1482 int flush_all, flush_line;
1483
1484 flush_all = flush_line = 0;
1485 if ((afsr & CHAFSR_EDC) != 0UL) {
1486 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1487 flush_line = 1;
1488 else
1489 flush_all = 1;
1490 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1491 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1492 flush_line = 1;
1493 else
1494 flush_all = 1;
1495 }
1496
1497 /* Trap handler only disabled I-cache, flush it. */
1498 cheetah_flush_icache();
1499
1500 /* Re-enable I-cache */
1501 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1502 "or %%g1, %1, %%g1\n\t"
1503 "stxa %%g1, [%%g0] %0\n\t"
1504 "membar #Sync"
1505 : /* no outputs */
1506 : "i" (ASI_DCU_CONTROL_REG),
1507 "i" (DCU_IC)
1508 : "g1");
1509
1510 if (flush_all)
1511 cheetah_flush_ecache();
1512 else if (flush_line)
1513 cheetah_flush_ecache_line(afar);
1514 }
1515
1516 /* Re-enable error reporting */
1517 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1518 "or %%g1, %1, %%g1\n\t"
1519 "stxa %%g1, [%%g0] %0\n\t"
1520 "membar #Sync"
1521 : /* no outputs */
1522 : "i" (ASI_ESTATE_ERROR_EN),
1523 "i" (ESTATE_ERROR_CEEN)
1524 : "g1");
1525
1526 /* Decide if we can continue after handling this trap and
1527 * logging the error.
1528 */
1529 recoverable = 1;
1530 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1531 recoverable = 0;
1532
1533 /* Re-check AFSR/AFAR */
1534 (void) cheetah_recheck_errors(&local_snapshot);
1535
1536 /* Log errors. */
1537 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1538
1539 if (!recoverable)
1540 panic("Irrecoverable Correctable-ECC error trap.\n");
1541}
1542
1543void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1544{
1545 struct cheetah_err_info local_snapshot, *p;
1546 int recoverable, is_memory;
1547
1548#ifdef CONFIG_PCI
1549 /* Check for the special PCI poke sequence. */
1550 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1551 cheetah_flush_icache();
1552 cheetah_flush_dcache();
1553
1554 /* Re-enable I-cache/D-cache */
1555 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1556 "or %%g1, %1, %%g1\n\t"
1557 "stxa %%g1, [%%g0] %0\n\t"
1558 "membar #Sync"
1559 : /* no outputs */
1560 : "i" (ASI_DCU_CONTROL_REG),
1561 "i" (DCU_DC | DCU_IC)
1562 : "g1");
1563
1564 /* Re-enable error reporting */
1565 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1566 "or %%g1, %1, %%g1\n\t"
1567 "stxa %%g1, [%%g0] %0\n\t"
1568 "membar #Sync"
1569 : /* no outputs */
1570 : "i" (ASI_ESTATE_ERROR_EN),
1571 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1572 : "g1");
1573
1574 (void) cheetah_recheck_errors(NULL);
1575
1576 pci_poke_faulted = 1;
1577 regs->tpc += 4;
1578 regs->tnpc = regs->tpc + 4;
1579 return;
1580 }
1581#endif
1582
1583 p = cheetah_get_error_log(afsr);
1584 if (!p) {
1585 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1586 afsr, afar);
1587 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1588 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1589 prom_halt();
1590 }
1591
1592 /* Grab snapshot of logged error. */
1593 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1594
1595 /* If the current trap snapshot does not match what the
1596 * trap handler passed along into our args, big trouble.
1597 * In such a case, mark the local copy as invalid.
1598 *
1599 * Else, it matches and we mark the afsr in the non-local
1600 * copy as invalid so we may log new error traps there.
1601 */
1602 if (p->afsr != afsr || p->afar != afar)
1603 local_snapshot.afsr = CHAFSR_INVALID;
1604 else
1605 p->afsr = CHAFSR_INVALID;
1606
1607 is_memory = cheetah_check_main_memory(afar);
1608
1609 {
1610 int flush_all, flush_line;
1611
1612 flush_all = flush_line = 0;
1613 if ((afsr & CHAFSR_EDU) != 0UL) {
1614 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1615 flush_line = 1;
1616 else
1617 flush_all = 1;
1618 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1619 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1620 flush_line = 1;
1621 else
1622 flush_all = 1;
1623 }
1624
1625 cheetah_flush_icache();
1626 cheetah_flush_dcache();
1627
1628 /* Re-enable I/D caches */
1629 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1630 "or %%g1, %1, %%g1\n\t"
1631 "stxa %%g1, [%%g0] %0\n\t"
1632 "membar #Sync"
1633 : /* no outputs */
1634 : "i" (ASI_DCU_CONTROL_REG),
1635 "i" (DCU_IC | DCU_DC)
1636 : "g1");
1637
1638 if (flush_all)
1639 cheetah_flush_ecache();
1640 else if (flush_line)
1641 cheetah_flush_ecache_line(afar);
1642 }
1643
1644 /* Re-enable error reporting */
1645 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1646 "or %%g1, %1, %%g1\n\t"
1647 "stxa %%g1, [%%g0] %0\n\t"
1648 "membar #Sync"
1649 : /* no outputs */
1650 : "i" (ASI_ESTATE_ERROR_EN),
1651 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1652 : "g1");
1653
1654 /* Decide if we can continue after handling this trap and
1655 * logging the error.
1656 */
1657 recoverable = 1;
1658 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1659 recoverable = 0;
1660
1661 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1662 * error was logged while we had error reporting traps disabled.
1663 */
1664 if (cheetah_recheck_errors(&local_snapshot)) {
1665 unsigned long new_afsr = local_snapshot.afsr;
1666
1667 /* If we got a new asynchronous error, die... */
1668 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1669 CHAFSR_WDU | CHAFSR_CPU |
1670 CHAFSR_IVU | CHAFSR_UE |
1671 CHAFSR_BERR | CHAFSR_TO))
1672 recoverable = 0;
1673 }
1674
1675 /* Log errors. */
1676 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1677
1678 /* "Recoverable" here means we try to yank the page from ever
1679 * being newly used again. This depends upon a few things:
1680 * 1) Must be main memory, and AFAR must be valid.
1681 * 2) If we trapped from user, OK.
1682 * 3) Else, if we trapped from kernel we must find exception
1683 * table entry (ie. we have to have been accessing user
1684 * space).
1685 *
1686 * If AFAR is not in main memory, or we trapped from kernel
1687 * and cannot find an exception table entry, it is unacceptable
1688 * to try and continue.
1689 */
1690 if (recoverable && is_memory) {
1691 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1692 /* OK, usermode access. */
1693 recoverable = 1;
1694 } else {
1695 const struct exception_table_entry *entry;
1696
1697 entry = search_exception_tables(regs->tpc);
1698 if (entry) {
1699 /* OK, kernel access to userspace. */
1700 recoverable = 1;
1701
1702 } else {
1703 /* BAD, privileged state is corrupted. */
1704 recoverable = 0;
1705 }
1706
1707 if (recoverable) {
1708 if (pfn_valid(afar >> PAGE_SHIFT))
1709 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1710 else
1711 recoverable = 0;
1712
1713 /* Only perform fixup if we still have a
1714 * recoverable condition.
1715 */
1716 if (recoverable) {
1717 regs->tpc = entry->fixup;
1718 regs->tnpc = regs->tpc + 4;
1719 }
1720 }
1721 }
1722 } else {
1723 recoverable = 0;
1724 }
1725
1726 if (!recoverable)
1727 panic("Irrecoverable deferred error trap.\n");
1728}
1729
1730/* Handle a D/I cache parity error trap. TYPE is encoded as:
1731 *
1732 * Bit0: 0=dcache,1=icache
1733 * Bit1: 0=recoverable,1=unrecoverable
1734 *
1735 * The hardware has disabled both the I-cache and D-cache in
1736 * the %dcr register.
1737 */
1738void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1739{
1740 if (type & 0x1)
1741 __cheetah_flush_icache();
1742 else
1743 cheetah_plus_zap_dcache_parity();
1744 cheetah_flush_dcache();
1745
1746 /* Re-enable I-cache/D-cache */
1747 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1748 "or %%g1, %1, %%g1\n\t"
1749 "stxa %%g1, [%%g0] %0\n\t"
1750 "membar #Sync"
1751 : /* no outputs */
1752 : "i" (ASI_DCU_CONTROL_REG),
1753 "i" (DCU_DC | DCU_IC)
1754 : "g1");
1755
1756 if (type & 0x2) {
1757 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1758 smp_processor_id(),
1759 (type & 0x1) ? 'I' : 'D',
1760 regs->tpc);
1761 printk(KERN_EMERG "TPC<%pS>\n", (void *) regs->tpc);
1762 panic("Irrecoverable Cheetah+ parity error.");
1763 }
1764
1765 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1766 smp_processor_id(),
1767 (type & 0x1) ? 'I' : 'D',
1768 regs->tpc);
1769 printk(KERN_WARNING "TPC<%pS>\n", (void *) regs->tpc);
1770}
1771
1772struct sun4v_error_entry {
1773 /* Unique error handle */
1774/*0x00*/u64 err_handle;
1775
1776 /* %stick value at the time of the error */
1777/*0x08*/u64 err_stick;
1778
1779/*0x10*/u8 reserved_1[3];
1780
1781 /* Error type */
1782/*0x13*/u8 err_type;
1783#define SUN4V_ERR_TYPE_UNDEFINED 0
1784#define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1785#define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1786#define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1787#define SUN4V_ERR_TYPE_SHUTDOWN_RQST 4
1788#define SUN4V_ERR_TYPE_DUMP_CORE 5
1789#define SUN4V_ERR_TYPE_SP_STATE_CHANGE 6
1790#define SUN4V_ERR_TYPE_NUM 7
1791
1792 /* Error attributes */
1793/*0x14*/u32 err_attrs;
1794#define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1795#define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1796#define SUN4V_ERR_ATTRS_PIO 0x00000004
1797#define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1798#define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1799#define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1800#define SUN4V_ERR_ATTRS_ASR 0x00000040
1801#define SUN4V_ERR_ATTRS_ASI 0x00000080
1802#define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1803#define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1804#define SUN4V_ERR_ATTRS_SPSTATE_SHFT 9
1805#define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1806#define SUN4V_ERR_ATTRS_MODE_SHFT 24
1807#define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1808
1809#define SUN4V_ERR_SPSTATE_FAULTED 0
1810#define SUN4V_ERR_SPSTATE_AVAILABLE 1
1811#define SUN4V_ERR_SPSTATE_NOT_PRESENT 2
1812
1813#define SUN4V_ERR_MODE_USER 1
1814#define SUN4V_ERR_MODE_PRIV 2
1815
1816 /* Real address of the memory region or PIO transaction */
1817/*0x18*/u64 err_raddr;
1818
1819 /* Size of the operation triggering the error, in bytes */
1820/*0x20*/u32 err_size;
1821
1822 /* ID of the CPU */
1823/*0x24*/u16 err_cpu;
1824
1825 /* Grace periof for shutdown, in seconds */
1826/*0x26*/u16 err_secs;
1827
1828 /* Value of the %asi register */
1829/*0x28*/u8 err_asi;
1830
1831/*0x29*/u8 reserved_2;
1832
1833 /* Value of the ASR register number */
1834/*0x2a*/u16 err_asr;
1835#define SUN4V_ERR_ASR_VALID 0x8000
1836
1837/*0x2c*/u32 reserved_3;
1838/*0x30*/u64 reserved_4;
1839/*0x38*/u64 reserved_5;
1840};
1841
1842static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1843static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1844
1845static const char *sun4v_err_type_to_str(u8 type)
1846{
1847 static const char *types[SUN4V_ERR_TYPE_NUM] = {
1848 "undefined",
1849 "uncorrected resumable",
1850 "precise nonresumable",
1851 "deferred nonresumable",
1852 "shutdown request",
1853 "dump core",
1854 "SP state change",
1855 };
1856
1857 if (type < SUN4V_ERR_TYPE_NUM)
1858 return types[type];
1859
1860 return "unknown";
1861}
1862
1863static void sun4v_emit_err_attr_strings(u32 attrs)
1864{
1865 static const char *attr_names[] = {
1866 "processor",
1867 "memory",
1868 "PIO",
1869 "int-registers",
1870 "fpu-registers",
1871 "shutdown-request",
1872 "ASR",
1873 "ASI",
1874 "priv-reg",
1875 };
1876 static const char *sp_states[] = {
1877 "sp-faulted",
1878 "sp-available",
1879 "sp-not-present",
1880 "sp-state-reserved",
1881 };
1882 static const char *modes[] = {
1883 "mode-reserved0",
1884 "user",
1885 "priv",
1886 "mode-reserved1",
1887 };
1888 u32 sp_state, mode;
1889 int i;
1890
1891 for (i = 0; i < ARRAY_SIZE(attr_names); i++) {
1892 if (attrs & (1U << i)) {
1893 const char *s = attr_names[i];
1894
1895 pr_cont("%s ", s);
1896 }
1897 }
1898
1899 sp_state = ((attrs & SUN4V_ERR_ATTRS_SPSTATE_MSK) >>
1900 SUN4V_ERR_ATTRS_SPSTATE_SHFT);
1901 pr_cont("%s ", sp_states[sp_state]);
1902
1903 mode = ((attrs & SUN4V_ERR_ATTRS_MODE_MSK) >>
1904 SUN4V_ERR_ATTRS_MODE_SHFT);
1905 pr_cont("%s ", modes[mode]);
1906
1907 if (attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL)
1908 pr_cont("res-queue-full ");
1909}
1910
1911/* When the report contains a real-address of "-1" it means that the
1912 * hardware did not provide the address. So we compute the effective
1913 * address of the load or store instruction at regs->tpc and report
1914 * that. Usually when this happens it's a PIO and in such a case we
1915 * are using physical addresses with bypass ASIs anyways, so what we
1916 * report here is exactly what we want.
1917 */
1918static void sun4v_report_real_raddr(const char *pfx, struct pt_regs *regs)
1919{
1920 unsigned int insn;
1921 u64 addr;
1922
1923 if (!(regs->tstate & TSTATE_PRIV))
1924 return;
1925
1926 insn = *(unsigned int *) regs->tpc;
1927
1928 addr = compute_effective_address(regs, insn, 0);
1929
1930 printk("%s: insn effective address [0x%016llx]\n",
1931 pfx, addr);
1932}
1933
1934static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent,
1935 int cpu, const char *pfx, atomic_t *ocnt)
1936{
1937 u64 *raw_ptr = (u64 *) ent;
1938 u32 attrs;
1939 int cnt;
1940
1941 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1942 printk("%s: TPC [0x%016lx] <%pS>\n",
1943 pfx, regs->tpc, (void *) regs->tpc);
1944
1945 printk("%s: RAW [%016llx:%016llx:%016llx:%016llx\n",
1946 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]);
1947 printk("%s: %016llx:%016llx:%016llx:%016llx]\n",
1948 pfx, raw_ptr[4], raw_ptr[5], raw_ptr[6], raw_ptr[7]);
1949
1950 printk("%s: handle [0x%016llx] stick [0x%016llx]\n",
1951 pfx, ent->err_handle, ent->err_stick);
1952
1953 printk("%s: type [%s]\n", pfx, sun4v_err_type_to_str(ent->err_type));
1954
1955 attrs = ent->err_attrs;
1956 printk("%s: attrs [0x%08x] < ", pfx, attrs);
1957 sun4v_emit_err_attr_strings(attrs);
1958 pr_cont(">\n");
1959
1960 /* Various fields in the error report are only valid if
1961 * certain attribute bits are set.
1962 */
1963 if (attrs & (SUN4V_ERR_ATTRS_MEMORY |
1964 SUN4V_ERR_ATTRS_PIO |
1965 SUN4V_ERR_ATTRS_ASI)) {
1966 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr);
1967
1968 if (ent->err_raddr == ~(u64)0)
1969 sun4v_report_real_raddr(pfx, regs);
1970 }
1971
1972 if (attrs & (SUN4V_ERR_ATTRS_MEMORY | SUN4V_ERR_ATTRS_ASI))
1973 printk("%s: size [0x%x]\n", pfx, ent->err_size);
1974
1975 if (attrs & (SUN4V_ERR_ATTRS_PROCESSOR |
1976 SUN4V_ERR_ATTRS_INT_REGISTERS |
1977 SUN4V_ERR_ATTRS_FPU_REGISTERS |
1978 SUN4V_ERR_ATTRS_PRIV_REG))
1979 printk("%s: cpu[%u]\n", pfx, ent->err_cpu);
1980
1981 if (attrs & SUN4V_ERR_ATTRS_ASI)
1982 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi);
1983
1984 if ((attrs & (SUN4V_ERR_ATTRS_INT_REGISTERS |
1985 SUN4V_ERR_ATTRS_FPU_REGISTERS |
1986 SUN4V_ERR_ATTRS_PRIV_REG)) &&
1987 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0)
1988 printk("%s: reg [0x%04x]\n",
1989 pfx, ent->err_asr & ~SUN4V_ERR_ASR_VALID);
1990
1991 show_regs(regs);
1992
1993 if ((cnt = atomic_read(ocnt)) != 0) {
1994 atomic_set(ocnt, 0);
1995 wmb();
1996 printk("%s: Queue overflowed %d times.\n",
1997 pfx, cnt);
1998 }
1999}
2000
2001/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2002 * Log the event and clear the first word of the entry.
2003 */
2004void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
2005{
2006 enum ctx_state prev_state = exception_enter();
2007 struct sun4v_error_entry *ent, local_copy;
2008 struct trap_per_cpu *tb;
2009 unsigned long paddr;
2010 int cpu;
2011
2012 cpu = get_cpu();
2013
2014 tb = &trap_block[cpu];
2015 paddr = tb->resum_kernel_buf_pa + offset;
2016 ent = __va(paddr);
2017
2018 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2019
2020 /* We have a local copy now, so release the entry. */
2021 ent->err_handle = 0;
2022 wmb();
2023
2024 put_cpu();
2025
2026 if (local_copy.err_type == SUN4V_ERR_TYPE_SHUTDOWN_RQST) {
2027 /* We should really take the seconds field of
2028 * the error report and use it for the shutdown
2029 * invocation, but for now do the same thing we
2030 * do for a DS shutdown request.
2031 */
2032 pr_info("Shutdown request, %u seconds...\n",
2033 local_copy.err_secs);
2034 orderly_poweroff(true);
2035 goto out;
2036 }
2037
2038 sun4v_log_error(regs, &local_copy, cpu,
2039 KERN_ERR "RESUMABLE ERROR",
2040 &sun4v_resum_oflow_cnt);
2041out:
2042 exception_exit(prev_state);
2043}
2044
2045/* If we try to printk() we'll probably make matters worse, by trying
2046 * to retake locks this cpu already holds or causing more errors. So
2047 * just bump a counter, and we'll report these counter bumps above.
2048 */
2049void sun4v_resum_overflow(struct pt_regs *regs)
2050{
2051 atomic_inc(&sun4v_resum_oflow_cnt);
2052}
2053
2054/* Given a set of registers, get the virtual addressi that was being accessed
2055 * by the faulting instructions at tpc.
2056 */
2057static unsigned long sun4v_get_vaddr(struct pt_regs *regs)
2058{
2059 unsigned int insn;
2060
2061 if (!copy_from_user(&insn, (void __user *)regs->tpc, 4)) {
2062 return compute_effective_address(regs, insn,
2063 (insn >> 25) & 0x1f);
2064 }
2065 return 0;
2066}
2067
2068/* Attempt to handle non-resumable errors generated from userspace.
2069 * Returns true if the signal was handled, false otherwise.
2070 */
2071bool sun4v_nonresum_error_user_handled(struct pt_regs *regs,
2072 struct sun4v_error_entry *ent) {
2073
2074 unsigned int attrs = ent->err_attrs;
2075
2076 if (attrs & SUN4V_ERR_ATTRS_MEMORY) {
2077 unsigned long addr = ent->err_raddr;
2078 siginfo_t info;
2079
2080 if (addr == ~(u64)0) {
2081 /* This seems highly unlikely to ever occur */
2082 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory error detected in unknown location!\n");
2083 } else {
2084 unsigned long page_cnt = DIV_ROUND_UP(ent->err_size,
2085 PAGE_SIZE);
2086
2087 /* Break the unfortunate news. */
2088 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Memory failed at %016lX\n",
2089 addr);
2090 pr_emerg("SUN4V NON-RECOVERABLE ERROR: Claiming %lu ages.\n",
2091 page_cnt);
2092
2093 while (page_cnt-- > 0) {
2094 if (pfn_valid(addr >> PAGE_SHIFT))
2095 get_page(pfn_to_page(addr >> PAGE_SHIFT));
2096 addr += PAGE_SIZE;
2097 }
2098 }
2099 info.si_signo = SIGKILL;
2100 info.si_errno = 0;
2101 info.si_trapno = 0;
2102 force_sig_info(info.si_signo, &info, current);
2103
2104 return true;
2105 }
2106 if (attrs & SUN4V_ERR_ATTRS_PIO) {
2107 siginfo_t info;
2108
2109 info.si_signo = SIGBUS;
2110 info.si_code = BUS_ADRERR;
2111 info.si_addr = (void __user *)sun4v_get_vaddr(regs);
2112 force_sig_info(info.si_signo, &info, current);
2113
2114 return true;
2115 }
2116
2117 /* Default to doing nothing */
2118 return false;
2119}
2120
2121/* We run with %pil set to PIL_NORMAL_MAX and PSTATE_IE enabled in %pstate.
2122 * Log the event, clear the first word of the entry, and die.
2123 */
2124void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
2125{
2126 struct sun4v_error_entry *ent, local_copy;
2127 struct trap_per_cpu *tb;
2128 unsigned long paddr;
2129 int cpu;
2130
2131 cpu = get_cpu();
2132
2133 tb = &trap_block[cpu];
2134 paddr = tb->nonresum_kernel_buf_pa + offset;
2135 ent = __va(paddr);
2136
2137 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
2138
2139 /* We have a local copy now, so release the entry. */
2140 ent->err_handle = 0;
2141 wmb();
2142
2143 put_cpu();
2144
2145 if (!(regs->tstate & TSTATE_PRIV) &&
2146 sun4v_nonresum_error_user_handled(regs, &local_copy)) {
2147 /* DON'T PANIC: This userspace error was handled. */
2148 return;
2149 }
2150
2151#ifdef CONFIG_PCI
2152 /* Check for the special PCI poke sequence. */
2153 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
2154 pci_poke_faulted = 1;
2155 regs->tpc += 4;
2156 regs->tnpc = regs->tpc + 4;
2157 return;
2158 }
2159#endif
2160
2161 sun4v_log_error(regs, &local_copy, cpu,
2162 KERN_EMERG "NON-RESUMABLE ERROR",
2163 &sun4v_nonresum_oflow_cnt);
2164
2165 panic("Non-resumable error.");
2166}
2167
2168/* If we try to printk() we'll probably make matters worse, by trying
2169 * to retake locks this cpu already holds or causing more errors. So
2170 * just bump a counter, and we'll report these counter bumps above.
2171 */
2172void sun4v_nonresum_overflow(struct pt_regs *regs)
2173{
2174 /* XXX Actually even this can make not that much sense. Perhaps
2175 * XXX we should just pull the plug and panic directly from here?
2176 */
2177 atomic_inc(&sun4v_nonresum_oflow_cnt);
2178}
2179
2180static void sun4v_tlb_error(struct pt_regs *regs)
2181{
2182 die_if_kernel("TLB/TSB error", regs);
2183}
2184
2185unsigned long sun4v_err_itlb_vaddr;
2186unsigned long sun4v_err_itlb_ctx;
2187unsigned long sun4v_err_itlb_pte;
2188unsigned long sun4v_err_itlb_error;
2189
2190void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
2191{
2192 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2193
2194 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
2195 regs->tpc, tl);
2196 printk(KERN_EMERG "SUN4V-ITLB: TPC<%pS>\n", (void *) regs->tpc);
2197 printk(KERN_EMERG "SUN4V-ITLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2198 printk(KERN_EMERG "SUN4V-ITLB: O7<%pS>\n",
2199 (void *) regs->u_regs[UREG_I7]);
2200 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
2201 "pte[%lx] error[%lx]\n",
2202 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
2203 sun4v_err_itlb_pte, sun4v_err_itlb_error);
2204
2205 sun4v_tlb_error(regs);
2206}
2207
2208unsigned long sun4v_err_dtlb_vaddr;
2209unsigned long sun4v_err_dtlb_ctx;
2210unsigned long sun4v_err_dtlb_pte;
2211unsigned long sun4v_err_dtlb_error;
2212
2213void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
2214{
2215 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2216
2217 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
2218 regs->tpc, tl);
2219 printk(KERN_EMERG "SUN4V-DTLB: TPC<%pS>\n", (void *) regs->tpc);
2220 printk(KERN_EMERG "SUN4V-DTLB: O7[%lx]\n", regs->u_regs[UREG_I7]);
2221 printk(KERN_EMERG "SUN4V-DTLB: O7<%pS>\n",
2222 (void *) regs->u_regs[UREG_I7]);
2223 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
2224 "pte[%lx] error[%lx]\n",
2225 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
2226 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
2227
2228 sun4v_tlb_error(regs);
2229}
2230
2231void hypervisor_tlbop_error(unsigned long err, unsigned long op)
2232{
2233 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
2234 err, op);
2235}
2236
2237void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
2238{
2239 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
2240 err, op);
2241}
2242
2243static void do_fpe_common(struct pt_regs *regs)
2244{
2245 if (regs->tstate & TSTATE_PRIV) {
2246 regs->tpc = regs->tnpc;
2247 regs->tnpc += 4;
2248 } else {
2249 unsigned long fsr = current_thread_info()->xfsr[0];
2250 siginfo_t info;
2251
2252 if (test_thread_flag(TIF_32BIT)) {
2253 regs->tpc &= 0xffffffff;
2254 regs->tnpc &= 0xffffffff;
2255 }
2256 info.si_signo = SIGFPE;
2257 info.si_errno = 0;
2258 info.si_addr = (void __user *)regs->tpc;
2259 info.si_trapno = 0;
2260 info.si_code = __SI_FAULT;
2261 if ((fsr & 0x1c000) == (1 << 14)) {
2262 if (fsr & 0x10)
2263 info.si_code = FPE_FLTINV;
2264 else if (fsr & 0x08)
2265 info.si_code = FPE_FLTOVF;
2266 else if (fsr & 0x04)
2267 info.si_code = FPE_FLTUND;
2268 else if (fsr & 0x02)
2269 info.si_code = FPE_FLTDIV;
2270 else if (fsr & 0x01)
2271 info.si_code = FPE_FLTRES;
2272 }
2273 force_sig_info(SIGFPE, &info, current);
2274 }
2275}
2276
2277void do_fpieee(struct pt_regs *regs)
2278{
2279 enum ctx_state prev_state = exception_enter();
2280
2281 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2282 0, 0x24, SIGFPE) == NOTIFY_STOP)
2283 goto out;
2284
2285 do_fpe_common(regs);
2286out:
2287 exception_exit(prev_state);
2288}
2289
2290void do_fpother(struct pt_regs *regs)
2291{
2292 enum ctx_state prev_state = exception_enter();
2293 struct fpustate *f = FPUSTATE;
2294 int ret = 0;
2295
2296 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2297 0, 0x25, SIGFPE) == NOTIFY_STOP)
2298 goto out;
2299
2300 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2301 case (2 << 14): /* unfinished_FPop */
2302 case (3 << 14): /* unimplemented_FPop */
2303 ret = do_mathemu(regs, f, false);
2304 break;
2305 }
2306 if (ret)
2307 goto out;
2308 do_fpe_common(regs);
2309out:
2310 exception_exit(prev_state);
2311}
2312
2313void do_tof(struct pt_regs *regs)
2314{
2315 enum ctx_state prev_state = exception_enter();
2316 siginfo_t info;
2317
2318 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2319 0, 0x26, SIGEMT) == NOTIFY_STOP)
2320 goto out;
2321
2322 if (regs->tstate & TSTATE_PRIV)
2323 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2324 if (test_thread_flag(TIF_32BIT)) {
2325 regs->tpc &= 0xffffffff;
2326 regs->tnpc &= 0xffffffff;
2327 }
2328 info.si_signo = SIGEMT;
2329 info.si_errno = 0;
2330 info.si_code = EMT_TAGOVF;
2331 info.si_addr = (void __user *)regs->tpc;
2332 info.si_trapno = 0;
2333 force_sig_info(SIGEMT, &info, current);
2334out:
2335 exception_exit(prev_state);
2336}
2337
2338void do_div0(struct pt_regs *regs)
2339{
2340 enum ctx_state prev_state = exception_enter();
2341 siginfo_t info;
2342
2343 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2344 0, 0x28, SIGFPE) == NOTIFY_STOP)
2345 goto out;
2346
2347 if (regs->tstate & TSTATE_PRIV)
2348 die_if_kernel("TL0: Kernel divide by zero.", regs);
2349 if (test_thread_flag(TIF_32BIT)) {
2350 regs->tpc &= 0xffffffff;
2351 regs->tnpc &= 0xffffffff;
2352 }
2353 info.si_signo = SIGFPE;
2354 info.si_errno = 0;
2355 info.si_code = FPE_INTDIV;
2356 info.si_addr = (void __user *)regs->tpc;
2357 info.si_trapno = 0;
2358 force_sig_info(SIGFPE, &info, current);
2359out:
2360 exception_exit(prev_state);
2361}
2362
2363static void instruction_dump(unsigned int *pc)
2364{
2365 int i;
2366
2367 if ((((unsigned long) pc) & 3))
2368 return;
2369
2370 printk("Instruction DUMP:");
2371 for (i = -3; i < 6; i++)
2372 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2373 printk("\n");
2374}
2375
2376static void user_instruction_dump(unsigned int __user *pc)
2377{
2378 int i;
2379 unsigned int buf[9];
2380
2381 if ((((unsigned long) pc) & 3))
2382 return;
2383
2384 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2385 return;
2386
2387 printk("Instruction DUMP:");
2388 for (i = 0; i < 9; i++)
2389 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2390 printk("\n");
2391}
2392
2393void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2394{
2395 unsigned long fp, ksp;
2396 struct thread_info *tp;
2397 int count = 0;
2398#ifdef CONFIG_FUNCTION_GRAPH_TRACER
2399 int graph = 0;
2400#endif
2401
2402 ksp = (unsigned long) _ksp;
2403 if (!tsk)
2404 tsk = current;
2405 tp = task_thread_info(tsk);
2406 if (ksp == 0UL) {
2407 if (tsk == current)
2408 asm("mov %%fp, %0" : "=r" (ksp));
2409 else
2410 ksp = tp->ksp;
2411 }
2412 if (tp == current_thread_info())
2413 flushw_all();
2414
2415 fp = ksp + STACK_BIAS;
2416
2417 printk("Call Trace:\n");
2418 do {
2419 struct sparc_stackf *sf;
2420 struct pt_regs *regs;
2421 unsigned long pc;
2422
2423 if (!kstack_valid(tp, fp))
2424 break;
2425 sf = (struct sparc_stackf *) fp;
2426 regs = (struct pt_regs *) (sf + 1);
2427
2428 if (kstack_is_trap_frame(tp, regs)) {
2429 if (!(regs->tstate & TSTATE_PRIV))
2430 break;
2431 pc = regs->tpc;
2432 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
2433 } else {
2434 pc = sf->callers_pc;
2435 fp = (unsigned long)sf->fp + STACK_BIAS;
2436 }
2437
2438 printk(" [%016lx] %pS\n", pc, (void *) pc);
2439#ifdef CONFIG_FUNCTION_GRAPH_TRACER
2440 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
2441 int index = tsk->curr_ret_stack;
2442 if (tsk->ret_stack && index >= graph) {
2443 pc = tsk->ret_stack[index - graph].ret;
2444 printk(" [%016lx] %pS\n", pc, (void *) pc);
2445 graph++;
2446 }
2447 }
2448#endif
2449 } while (++count < 16);
2450}
2451
2452static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2453{
2454 unsigned long fp = rw->ins[6];
2455
2456 if (!fp)
2457 return NULL;
2458
2459 return (struct reg_window *) (fp + STACK_BIAS);
2460}
2461
2462void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
2463{
2464 static int die_counter;
2465 int count = 0;
2466
2467 /* Amuse the user. */
2468 printk(
2469" \\|/ ____ \\|/\n"
2470" \"@'/ .. \\`@\"\n"
2471" /_| \\__/ |_\\\n"
2472" \\__U_/\n");
2473
2474 printk("%s(%d): %s [#%d]\n", current->comm, task_pid_nr(current), str, ++die_counter);
2475 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2476 __asm__ __volatile__("flushw");
2477 show_regs(regs);
2478 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
2479 if (regs->tstate & TSTATE_PRIV) {
2480 struct thread_info *tp = current_thread_info();
2481 struct reg_window *rw = (struct reg_window *)
2482 (regs->u_regs[UREG_FP] + STACK_BIAS);
2483
2484 /* Stop the back trace when we hit userland or we
2485 * find some badly aligned kernel stack.
2486 */
2487 while (rw &&
2488 count++ < 30 &&
2489 kstack_valid(tp, (unsigned long) rw)) {
2490 printk("Caller[%016lx]: %pS\n", rw->ins[7],
2491 (void *) rw->ins[7]);
2492
2493 rw = kernel_stack_up(rw);
2494 }
2495 instruction_dump ((unsigned int *) regs->tpc);
2496 } else {
2497 if (test_thread_flag(TIF_32BIT)) {
2498 regs->tpc &= 0xffffffff;
2499 regs->tnpc &= 0xffffffff;
2500 }
2501 user_instruction_dump ((unsigned int __user *) regs->tpc);
2502 }
2503 if (panic_on_oops)
2504 panic("Fatal exception");
2505 if (regs->tstate & TSTATE_PRIV)
2506 do_exit(SIGKILL);
2507 do_exit(SIGSEGV);
2508}
2509EXPORT_SYMBOL(die_if_kernel);
2510
2511#define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2512#define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2513
2514void do_illegal_instruction(struct pt_regs *regs)
2515{
2516 enum ctx_state prev_state = exception_enter();
2517 unsigned long pc = regs->tpc;
2518 unsigned long tstate = regs->tstate;
2519 u32 insn;
2520 siginfo_t info;
2521
2522 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2523 0, 0x10, SIGILL) == NOTIFY_STOP)
2524 goto out;
2525
2526 if (tstate & TSTATE_PRIV)
2527 die_if_kernel("Kernel illegal instruction", regs);
2528 if (test_thread_flag(TIF_32BIT))
2529 pc = (u32)pc;
2530 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2531 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2532 if (handle_popc(insn, regs))
2533 goto out;
2534 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2535 if (handle_ldf_stq(insn, regs))
2536 goto out;
2537 } else if (tlb_type == hypervisor) {
2538 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2539 if (!vis_emul(regs, insn))
2540 goto out;
2541 } else {
2542 struct fpustate *f = FPUSTATE;
2543
2544 /* On UltraSPARC T2 and later, FPU insns which
2545 * are not implemented in HW signal an illegal
2546 * instruction trap and do not set the FP Trap
2547 * Trap in the %fsr to unimplemented_FPop.
2548 */
2549 if (do_mathemu(regs, f, true))
2550 goto out;
2551 }
2552 }
2553 }
2554 info.si_signo = SIGILL;
2555 info.si_errno = 0;
2556 info.si_code = ILL_ILLOPC;
2557 info.si_addr = (void __user *)pc;
2558 info.si_trapno = 0;
2559 force_sig_info(SIGILL, &info, current);
2560out:
2561 exception_exit(prev_state);
2562}
2563
2564void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2565{
2566 enum ctx_state prev_state = exception_enter();
2567 siginfo_t info;
2568
2569 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2570 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2571 goto out;
2572
2573 if (regs->tstate & TSTATE_PRIV) {
2574 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2575 goto out;
2576 }
2577 info.si_signo = SIGBUS;
2578 info.si_errno = 0;
2579 info.si_code = BUS_ADRALN;
2580 info.si_addr = (void __user *)sfar;
2581 info.si_trapno = 0;
2582 force_sig_info(SIGBUS, &info, current);
2583out:
2584 exception_exit(prev_state);
2585}
2586
2587void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2588{
2589 siginfo_t info;
2590
2591 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2592 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2593 return;
2594
2595 if (regs->tstate & TSTATE_PRIV) {
2596 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2597 return;
2598 }
2599 info.si_signo = SIGBUS;
2600 info.si_errno = 0;
2601 info.si_code = BUS_ADRALN;
2602 info.si_addr = (void __user *) addr;
2603 info.si_trapno = 0;
2604 force_sig_info(SIGBUS, &info, current);
2605}
2606
2607void do_privop(struct pt_regs *regs)
2608{
2609 enum ctx_state prev_state = exception_enter();
2610 siginfo_t info;
2611
2612 if (notify_die(DIE_TRAP, "privileged operation", regs,
2613 0, 0x11, SIGILL) == NOTIFY_STOP)
2614 goto out;
2615
2616 if (test_thread_flag(TIF_32BIT)) {
2617 regs->tpc &= 0xffffffff;
2618 regs->tnpc &= 0xffffffff;
2619 }
2620 info.si_signo = SIGILL;
2621 info.si_errno = 0;
2622 info.si_code = ILL_PRVOPC;
2623 info.si_addr = (void __user *)regs->tpc;
2624 info.si_trapno = 0;
2625 force_sig_info(SIGILL, &info, current);
2626out:
2627 exception_exit(prev_state);
2628}
2629
2630void do_privact(struct pt_regs *regs)
2631{
2632 do_privop(regs);
2633}
2634
2635/* Trap level 1 stuff or other traps we should never see... */
2636void do_cee(struct pt_regs *regs)
2637{
2638 exception_enter();
2639 die_if_kernel("TL0: Cache Error Exception", regs);
2640}
2641
2642void do_div0_tl1(struct pt_regs *regs)
2643{
2644 exception_enter();
2645 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2646 die_if_kernel("TL1: DIV0 Exception", regs);
2647}
2648
2649void do_fpieee_tl1(struct pt_regs *regs)
2650{
2651 exception_enter();
2652 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2653 die_if_kernel("TL1: FPU IEEE Exception", regs);
2654}
2655
2656void do_fpother_tl1(struct pt_regs *regs)
2657{
2658 exception_enter();
2659 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2660 die_if_kernel("TL1: FPU Other Exception", regs);
2661}
2662
2663void do_ill_tl1(struct pt_regs *regs)
2664{
2665 exception_enter();
2666 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2667 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2668}
2669
2670void do_irq_tl1(struct pt_regs *regs)
2671{
2672 exception_enter();
2673 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2674 die_if_kernel("TL1: IRQ Exception", regs);
2675}
2676
2677void do_lddfmna_tl1(struct pt_regs *regs)
2678{
2679 exception_enter();
2680 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2681 die_if_kernel("TL1: LDDF Exception", regs);
2682}
2683
2684void do_stdfmna_tl1(struct pt_regs *regs)
2685{
2686 exception_enter();
2687 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2688 die_if_kernel("TL1: STDF Exception", regs);
2689}
2690
2691void do_paw(struct pt_regs *regs)
2692{
2693 exception_enter();
2694 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2695}
2696
2697void do_paw_tl1(struct pt_regs *regs)
2698{
2699 exception_enter();
2700 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2701 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2702}
2703
2704void do_vaw(struct pt_regs *regs)
2705{
2706 exception_enter();
2707 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2708}
2709
2710void do_vaw_tl1(struct pt_regs *regs)
2711{
2712 exception_enter();
2713 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2714 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2715}
2716
2717void do_tof_tl1(struct pt_regs *regs)
2718{
2719 exception_enter();
2720 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2721 die_if_kernel("TL1: Tag Overflow Exception", regs);
2722}
2723
2724void do_getpsr(struct pt_regs *regs)
2725{
2726 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2727 regs->tpc = regs->tnpc;
2728 regs->tnpc += 4;
2729 if (test_thread_flag(TIF_32BIT)) {
2730 regs->tpc &= 0xffffffff;
2731 regs->tnpc &= 0xffffffff;
2732 }
2733}
2734
2735struct trap_per_cpu trap_block[NR_CPUS];
2736EXPORT_SYMBOL(trap_block);
2737
2738/* This can get invoked before sched_init() so play it super safe
2739 * and use hard_smp_processor_id().
2740 */
2741void notrace init_cur_cpu_trap(struct thread_info *t)
2742{
2743 int cpu = hard_smp_processor_id();
2744 struct trap_per_cpu *p = &trap_block[cpu];
2745
2746 p->thread = t;
2747 p->pgd_paddr = 0;
2748}
2749
2750extern void thread_info_offsets_are_bolixed_dave(void);
2751extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2752extern void tsb_config_offsets_are_bolixed_dave(void);
2753
2754/* Only invoked on boot processor. */
2755void __init trap_init(void)
2756{
2757 /* Compile time sanity check. */
2758 BUILD_BUG_ON(TI_TASK != offsetof(struct thread_info, task) ||
2759 TI_FLAGS != offsetof(struct thread_info, flags) ||
2760 TI_CPU != offsetof(struct thread_info, cpu) ||
2761 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2762 TI_KSP != offsetof(struct thread_info, ksp) ||
2763 TI_FAULT_ADDR != offsetof(struct thread_info,
2764 fault_address) ||
2765 TI_KREGS != offsetof(struct thread_info, kregs) ||
2766 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2767 TI_REG_WINDOW != offsetof(struct thread_info,
2768 reg_window) ||
2769 TI_RWIN_SPTRS != offsetof(struct thread_info,
2770 rwbuf_stkptrs) ||
2771 TI_GSR != offsetof(struct thread_info, gsr) ||
2772 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2773 TI_PRE_COUNT != offsetof(struct thread_info,
2774 preempt_count) ||
2775 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2776 TI_CURRENT_DS != offsetof(struct thread_info,
2777 current_ds) ||
2778 TI_KUNA_REGS != offsetof(struct thread_info,
2779 kern_una_regs) ||
2780 TI_KUNA_INSN != offsetof(struct thread_info,
2781 kern_una_insn) ||
2782 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2783 (TI_FPREGS & (64 - 1)));
2784
2785 BUILD_BUG_ON(TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu,
2786 thread) ||
2787 (TRAP_PER_CPU_PGD_PADDR !=
2788 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2789 (TRAP_PER_CPU_CPU_MONDO_PA !=
2790 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2791 (TRAP_PER_CPU_DEV_MONDO_PA !=
2792 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2793 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2794 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2795 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2796 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2797 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2798 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2799 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2800 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2801 (TRAP_PER_CPU_FAULT_INFO !=
2802 offsetof(struct trap_per_cpu, fault_info)) ||
2803 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2804 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2805 (TRAP_PER_CPU_CPU_LIST_PA !=
2806 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2807 (TRAP_PER_CPU_TSB_HUGE !=
2808 offsetof(struct trap_per_cpu, tsb_huge)) ||
2809 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2810 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2811 (TRAP_PER_CPU_IRQ_WORKLIST_PA !=
2812 offsetof(struct trap_per_cpu, irq_worklist_pa)) ||
2813 (TRAP_PER_CPU_CPU_MONDO_QMASK !=
2814 offsetof(struct trap_per_cpu, cpu_mondo_qmask)) ||
2815 (TRAP_PER_CPU_DEV_MONDO_QMASK !=
2816 offsetof(struct trap_per_cpu, dev_mondo_qmask)) ||
2817 (TRAP_PER_CPU_RESUM_QMASK !=
2818 offsetof(struct trap_per_cpu, resum_qmask)) ||
2819 (TRAP_PER_CPU_NONRESUM_QMASK !=
2820 offsetof(struct trap_per_cpu, nonresum_qmask)) ||
2821 (TRAP_PER_CPU_PER_CPU_BASE !=
2822 offsetof(struct trap_per_cpu, __per_cpu_base)));
2823
2824 BUILD_BUG_ON((TSB_CONFIG_TSB !=
2825 offsetof(struct tsb_config, tsb)) ||
2826 (TSB_CONFIG_RSS_LIMIT !=
2827 offsetof(struct tsb_config, tsb_rss_limit)) ||
2828 (TSB_CONFIG_NENTRIES !=
2829 offsetof(struct tsb_config, tsb_nentries)) ||
2830 (TSB_CONFIG_REG_VAL !=
2831 offsetof(struct tsb_config, tsb_reg_val)) ||
2832 (TSB_CONFIG_MAP_VADDR !=
2833 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2834 (TSB_CONFIG_MAP_PTE !=
2835 offsetof(struct tsb_config, tsb_map_pte)));
2836
2837 /* Attach to the address space of init_task. On SMP we
2838 * do this in smp.c:smp_callin for other cpus.
2839 */
2840 atomic_inc(&init_mm.mm_count);
2841 current->active_mm = &init_mm;
2842}