Loading...
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
37
38#include "mlx4_en.h"
39#include "en_port.h"
40
41
42static void
43mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
44{
45 struct mlx4_en_priv *priv = netdev_priv(dev);
46 struct mlx4_en_dev *mdev = priv->mdev;
47
48 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
49 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
50 sizeof(drvinfo->version));
51 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
52 "%d.%d.%d",
53 (u16) (mdev->dev->caps.fw_ver >> 32),
54 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
55 (u16) (mdev->dev->caps.fw_ver & 0xffff));
56 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->pdev),
57 sizeof(drvinfo->bus_info));
58 drvinfo->n_stats = 0;
59 drvinfo->regdump_len = 0;
60 drvinfo->eedump_len = 0;
61}
62
63static const char main_strings[][ETH_GSTRING_LEN] = {
64 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
65 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
66 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
67 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
68 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
69 "tx_heartbeat_errors", "tx_window_errors",
70
71 /* port statistics */
72 "tso_packets",
73 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
74 "rx_csum_good", "rx_csum_none", "tx_chksum_offload",
75
76 /* packet statistics */
77 "broadcast", "rx_prio_0", "rx_prio_1", "rx_prio_2", "rx_prio_3",
78 "rx_prio_4", "rx_prio_5", "rx_prio_6", "rx_prio_7", "tx_prio_0",
79 "tx_prio_1", "tx_prio_2", "tx_prio_3", "tx_prio_4", "tx_prio_5",
80 "tx_prio_6", "tx_prio_7",
81};
82#define NUM_MAIN_STATS 21
83#define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + NUM_PERF_STATS)
84
85static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
86 "Interrupt Test",
87 "Link Test",
88 "Speed Test",
89 "Register Test",
90 "Loopback Test",
91};
92
93static u32 mlx4_en_get_msglevel(struct net_device *dev)
94{
95 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
96}
97
98static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
99{
100 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
101}
102
103static void mlx4_en_get_wol(struct net_device *netdev,
104 struct ethtool_wolinfo *wol)
105{
106 struct mlx4_en_priv *priv = netdev_priv(netdev);
107 int err = 0;
108 u64 config = 0;
109 u64 mask;
110
111 if ((priv->port < 1) || (priv->port > 2)) {
112 en_err(priv, "Failed to get WoL information\n");
113 return;
114 }
115
116 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
117 MLX4_DEV_CAP_FLAG_WOL_PORT2;
118
119 if (!(priv->mdev->dev->caps.flags & mask)) {
120 wol->supported = 0;
121 wol->wolopts = 0;
122 return;
123 }
124
125 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
126 if (err) {
127 en_err(priv, "Failed to get WoL information\n");
128 return;
129 }
130
131 if (config & MLX4_EN_WOL_MAGIC)
132 wol->supported = WAKE_MAGIC;
133 else
134 wol->supported = 0;
135
136 if (config & MLX4_EN_WOL_ENABLED)
137 wol->wolopts = WAKE_MAGIC;
138 else
139 wol->wolopts = 0;
140}
141
142static int mlx4_en_set_wol(struct net_device *netdev,
143 struct ethtool_wolinfo *wol)
144{
145 struct mlx4_en_priv *priv = netdev_priv(netdev);
146 u64 config = 0;
147 int err = 0;
148 u64 mask;
149
150 if ((priv->port < 1) || (priv->port > 2))
151 return -EOPNOTSUPP;
152
153 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
154 MLX4_DEV_CAP_FLAG_WOL_PORT2;
155
156 if (!(priv->mdev->dev->caps.flags & mask))
157 return -EOPNOTSUPP;
158
159 if (wol->supported & ~WAKE_MAGIC)
160 return -EINVAL;
161
162 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
163 if (err) {
164 en_err(priv, "Failed to get WoL info, unable to modify\n");
165 return err;
166 }
167
168 if (wol->wolopts & WAKE_MAGIC) {
169 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
170 MLX4_EN_WOL_MAGIC;
171 } else {
172 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
173 config |= MLX4_EN_WOL_DO_MODIFY;
174 }
175
176 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
177 if (err)
178 en_err(priv, "Failed to set WoL information\n");
179
180 return err;
181}
182
183static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
184{
185 struct mlx4_en_priv *priv = netdev_priv(dev);
186 int bit_count = hweight64(priv->stats_bitmap);
187
188 switch (sset) {
189 case ETH_SS_STATS:
190 return (priv->stats_bitmap ? bit_count : NUM_ALL_STATS) +
191 (priv->tx_ring_num + priv->rx_ring_num) * 2;
192 case ETH_SS_TEST:
193 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
194 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
195 default:
196 return -EOPNOTSUPP;
197 }
198}
199
200static void mlx4_en_get_ethtool_stats(struct net_device *dev,
201 struct ethtool_stats *stats, uint64_t *data)
202{
203 struct mlx4_en_priv *priv = netdev_priv(dev);
204 int index = 0;
205 int i, j = 0;
206
207 spin_lock_bh(&priv->stats_lock);
208
209 if (!(priv->stats_bitmap)) {
210 for (i = 0; i < NUM_MAIN_STATS; i++)
211 data[index++] =
212 ((unsigned long *) &priv->stats)[i];
213 for (i = 0; i < NUM_PORT_STATS; i++)
214 data[index++] =
215 ((unsigned long *) &priv->port_stats)[i];
216 for (i = 0; i < NUM_PKT_STATS; i++)
217 data[index++] =
218 ((unsigned long *) &priv->pkstats)[i];
219 } else {
220 for (i = 0; i < NUM_MAIN_STATS; i++) {
221 if ((priv->stats_bitmap >> j) & 1)
222 data[index++] =
223 ((unsigned long *) &priv->stats)[i];
224 j++;
225 }
226 for (i = 0; i < NUM_PORT_STATS; i++) {
227 if ((priv->stats_bitmap >> j) & 1)
228 data[index++] =
229 ((unsigned long *) &priv->port_stats)[i];
230 j++;
231 }
232 }
233 for (i = 0; i < priv->tx_ring_num; i++) {
234 data[index++] = priv->tx_ring[i].packets;
235 data[index++] = priv->tx_ring[i].bytes;
236 }
237 for (i = 0; i < priv->rx_ring_num; i++) {
238 data[index++] = priv->rx_ring[i].packets;
239 data[index++] = priv->rx_ring[i].bytes;
240 }
241 spin_unlock_bh(&priv->stats_lock);
242
243}
244
245static void mlx4_en_self_test(struct net_device *dev,
246 struct ethtool_test *etest, u64 *buf)
247{
248 mlx4_en_ex_selftest(dev, &etest->flags, buf);
249}
250
251static void mlx4_en_get_strings(struct net_device *dev,
252 uint32_t stringset, uint8_t *data)
253{
254 struct mlx4_en_priv *priv = netdev_priv(dev);
255 int index = 0;
256 int i;
257
258 switch (stringset) {
259 case ETH_SS_TEST:
260 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
261 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
262 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
263 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
264 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
265 break;
266
267 case ETH_SS_STATS:
268 /* Add main counters */
269 if (!priv->stats_bitmap) {
270 for (i = 0; i < NUM_MAIN_STATS; i++)
271 strcpy(data + (index++) * ETH_GSTRING_LEN,
272 main_strings[i]);
273 for (i = 0; i < NUM_PORT_STATS; i++)
274 strcpy(data + (index++) * ETH_GSTRING_LEN,
275 main_strings[i +
276 NUM_MAIN_STATS]);
277 for (i = 0; i < NUM_PKT_STATS; i++)
278 strcpy(data + (index++) * ETH_GSTRING_LEN,
279 main_strings[i +
280 NUM_MAIN_STATS +
281 NUM_PORT_STATS]);
282 } else
283 for (i = 0; i < NUM_MAIN_STATS + NUM_PORT_STATS; i++) {
284 if ((priv->stats_bitmap >> i) & 1) {
285 strcpy(data +
286 (index++) * ETH_GSTRING_LEN,
287 main_strings[i]);
288 }
289 if (!(priv->stats_bitmap >> i))
290 break;
291 }
292 for (i = 0; i < priv->tx_ring_num; i++) {
293 sprintf(data + (index++) * ETH_GSTRING_LEN,
294 "tx%d_packets", i);
295 sprintf(data + (index++) * ETH_GSTRING_LEN,
296 "tx%d_bytes", i);
297 }
298 for (i = 0; i < priv->rx_ring_num; i++) {
299 sprintf(data + (index++) * ETH_GSTRING_LEN,
300 "rx%d_packets", i);
301 sprintf(data + (index++) * ETH_GSTRING_LEN,
302 "rx%d_bytes", i);
303 }
304 break;
305 }
306}
307
308static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
309{
310 struct mlx4_en_priv *priv = netdev_priv(dev);
311 int trans_type;
312
313 cmd->autoneg = AUTONEG_DISABLE;
314 cmd->supported = SUPPORTED_10000baseT_Full;
315 cmd->advertising = ADVERTISED_10000baseT_Full;
316
317 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
318 return -ENOMEM;
319
320 trans_type = priv->port_state.transciver;
321 if (netif_carrier_ok(dev)) {
322 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
323 cmd->duplex = DUPLEX_FULL;
324 } else {
325 ethtool_cmd_speed_set(cmd, -1);
326 cmd->duplex = -1;
327 }
328
329 if (trans_type > 0 && trans_type <= 0xC) {
330 cmd->port = PORT_FIBRE;
331 cmd->transceiver = XCVR_EXTERNAL;
332 cmd->supported |= SUPPORTED_FIBRE;
333 cmd->advertising |= ADVERTISED_FIBRE;
334 } else if (trans_type == 0x80 || trans_type == 0) {
335 cmd->port = PORT_TP;
336 cmd->transceiver = XCVR_INTERNAL;
337 cmd->supported |= SUPPORTED_TP;
338 cmd->advertising |= ADVERTISED_TP;
339 } else {
340 cmd->port = -1;
341 cmd->transceiver = -1;
342 }
343 return 0;
344}
345
346static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
347{
348 if ((cmd->autoneg == AUTONEG_ENABLE) ||
349 (ethtool_cmd_speed(cmd) != SPEED_10000) ||
350 (cmd->duplex != DUPLEX_FULL))
351 return -EINVAL;
352
353 /* Nothing to change */
354 return 0;
355}
356
357static int mlx4_en_get_coalesce(struct net_device *dev,
358 struct ethtool_coalesce *coal)
359{
360 struct mlx4_en_priv *priv = netdev_priv(dev);
361
362 coal->tx_coalesce_usecs = priv->tx_usecs;
363 coal->tx_max_coalesced_frames = priv->tx_frames;
364 coal->rx_coalesce_usecs = priv->rx_usecs;
365 coal->rx_max_coalesced_frames = priv->rx_frames;
366
367 coal->pkt_rate_low = priv->pkt_rate_low;
368 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
369 coal->pkt_rate_high = priv->pkt_rate_high;
370 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
371 coal->rate_sample_interval = priv->sample_interval;
372 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
373 return 0;
374}
375
376static int mlx4_en_set_coalesce(struct net_device *dev,
377 struct ethtool_coalesce *coal)
378{
379 struct mlx4_en_priv *priv = netdev_priv(dev);
380 int err, i;
381
382 priv->rx_frames = (coal->rx_max_coalesced_frames ==
383 MLX4_EN_AUTO_CONF) ?
384 MLX4_EN_RX_COAL_TARGET :
385 coal->rx_max_coalesced_frames;
386 priv->rx_usecs = (coal->rx_coalesce_usecs ==
387 MLX4_EN_AUTO_CONF) ?
388 MLX4_EN_RX_COAL_TIME :
389 coal->rx_coalesce_usecs;
390
391 /* Setting TX coalescing parameters */
392 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
393 coal->tx_max_coalesced_frames != priv->tx_frames) {
394 priv->tx_usecs = coal->tx_coalesce_usecs;
395 priv->tx_frames = coal->tx_max_coalesced_frames;
396 for (i = 0; i < priv->tx_ring_num; i++) {
397 priv->tx_cq[i].moder_cnt = priv->tx_frames;
398 priv->tx_cq[i].moder_time = priv->tx_usecs;
399 if (mlx4_en_set_cq_moder(priv, &priv->tx_cq[i])) {
400 en_warn(priv, "Failed changing moderation "
401 "for TX cq %d\n", i);
402 }
403 }
404 }
405
406 /* Set adaptive coalescing params */
407 priv->pkt_rate_low = coal->pkt_rate_low;
408 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
409 priv->pkt_rate_high = coal->pkt_rate_high;
410 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
411 priv->sample_interval = coal->rate_sample_interval;
412 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
413 if (priv->adaptive_rx_coal)
414 return 0;
415
416 for (i = 0; i < priv->rx_ring_num; i++) {
417 priv->rx_cq[i].moder_cnt = priv->rx_frames;
418 priv->rx_cq[i].moder_time = priv->rx_usecs;
419 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
420 err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]);
421 if (err)
422 return err;
423 }
424 return 0;
425}
426
427static int mlx4_en_set_pauseparam(struct net_device *dev,
428 struct ethtool_pauseparam *pause)
429{
430 struct mlx4_en_priv *priv = netdev_priv(dev);
431 struct mlx4_en_dev *mdev = priv->mdev;
432 int err;
433
434 priv->prof->tx_pause = pause->tx_pause != 0;
435 priv->prof->rx_pause = pause->rx_pause != 0;
436 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
437 priv->rx_skb_size + ETH_FCS_LEN,
438 priv->prof->tx_pause,
439 priv->prof->tx_ppp,
440 priv->prof->rx_pause,
441 priv->prof->rx_ppp);
442 if (err)
443 en_err(priv, "Failed setting pause params\n");
444
445 return err;
446}
447
448static void mlx4_en_get_pauseparam(struct net_device *dev,
449 struct ethtool_pauseparam *pause)
450{
451 struct mlx4_en_priv *priv = netdev_priv(dev);
452
453 pause->tx_pause = priv->prof->tx_pause;
454 pause->rx_pause = priv->prof->rx_pause;
455}
456
457static int mlx4_en_set_ringparam(struct net_device *dev,
458 struct ethtool_ringparam *param)
459{
460 struct mlx4_en_priv *priv = netdev_priv(dev);
461 struct mlx4_en_dev *mdev = priv->mdev;
462 u32 rx_size, tx_size;
463 int port_up = 0;
464 int err = 0;
465 int i;
466
467 if (param->rx_jumbo_pending || param->rx_mini_pending)
468 return -EINVAL;
469
470 rx_size = roundup_pow_of_two(param->rx_pending);
471 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
472 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
473 tx_size = roundup_pow_of_two(param->tx_pending);
474 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
475 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
476
477 if (rx_size == (priv->port_up ? priv->rx_ring[0].actual_size :
478 priv->rx_ring[0].size) &&
479 tx_size == priv->tx_ring[0].size)
480 return 0;
481
482 mutex_lock(&mdev->state_lock);
483 if (priv->port_up) {
484 port_up = 1;
485 mlx4_en_stop_port(dev);
486 }
487
488 mlx4_en_free_resources(priv);
489
490 priv->prof->tx_ring_size = tx_size;
491 priv->prof->rx_ring_size = rx_size;
492
493 err = mlx4_en_alloc_resources(priv);
494 if (err) {
495 en_err(priv, "Failed reallocating port resources\n");
496 goto out;
497 }
498 if (port_up) {
499 err = mlx4_en_start_port(dev);
500 if (err)
501 en_err(priv, "Failed starting port\n");
502 }
503
504 for (i = 0; i < priv->rx_ring_num; i++) {
505 priv->rx_cq[i].moder_cnt = priv->rx_frames;
506 priv->rx_cq[i].moder_time = priv->rx_usecs;
507 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
508 err = mlx4_en_set_cq_moder(priv, &priv->rx_cq[i]);
509 if (err)
510 goto out;
511 }
512
513out:
514 mutex_unlock(&mdev->state_lock);
515 return err;
516}
517
518static void mlx4_en_get_ringparam(struct net_device *dev,
519 struct ethtool_ringparam *param)
520{
521 struct mlx4_en_priv *priv = netdev_priv(dev);
522
523 memset(param, 0, sizeof(*param));
524 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
525 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
526 param->rx_pending = priv->port_up ?
527 priv->rx_ring[0].actual_size : priv->rx_ring[0].size;
528 param->tx_pending = priv->tx_ring[0].size;
529}
530
531static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
532{
533 struct mlx4_en_priv *priv = netdev_priv(dev);
534
535 return priv->rx_ring_num;
536}
537
538static int mlx4_en_get_rxfh_indir(struct net_device *dev, u32 *ring_index)
539{
540 struct mlx4_en_priv *priv = netdev_priv(dev);
541 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
542 int rss_rings;
543 size_t n = priv->rx_ring_num;
544 int err = 0;
545
546 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
547
548 while (n--) {
549 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
550 rss_map->base_qpn;
551 }
552
553 return err;
554}
555
556static int mlx4_en_set_rxfh_indir(struct net_device *dev,
557 const u32 *ring_index)
558{
559 struct mlx4_en_priv *priv = netdev_priv(dev);
560 struct mlx4_en_dev *mdev = priv->mdev;
561 int port_up = 0;
562 int err = 0;
563 int i;
564 int rss_rings = 0;
565
566 /* Calculate RSS table size and make sure flows are spread evenly
567 * between rings
568 */
569 for (i = 0; i < priv->rx_ring_num; i++) {
570 if (i > 0 && !ring_index[i] && !rss_rings)
571 rss_rings = i;
572
573 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
574 return -EINVAL;
575 }
576
577 if (!rss_rings)
578 rss_rings = priv->rx_ring_num;
579
580 /* RSS table size must be an order of 2 */
581 if (!is_power_of_2(rss_rings))
582 return -EINVAL;
583
584 mutex_lock(&mdev->state_lock);
585 if (priv->port_up) {
586 port_up = 1;
587 mlx4_en_stop_port(dev);
588 }
589
590 priv->prof->rss_rings = rss_rings;
591
592 if (port_up) {
593 err = mlx4_en_start_port(dev);
594 if (err)
595 en_err(priv, "Failed starting port\n");
596 }
597
598 mutex_unlock(&mdev->state_lock);
599 return err;
600}
601
602static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
603 u32 *rule_locs)
604{
605 struct mlx4_en_priv *priv = netdev_priv(dev);
606 int err = 0;
607
608 switch (cmd->cmd) {
609 case ETHTOOL_GRXRINGS:
610 cmd->data = priv->rx_ring_num;
611 break;
612 default:
613 err = -EOPNOTSUPP;
614 break;
615 }
616
617 return err;
618}
619
620const struct ethtool_ops mlx4_en_ethtool_ops = {
621 .get_drvinfo = mlx4_en_get_drvinfo,
622 .get_settings = mlx4_en_get_settings,
623 .set_settings = mlx4_en_set_settings,
624 .get_link = ethtool_op_get_link,
625 .get_strings = mlx4_en_get_strings,
626 .get_sset_count = mlx4_en_get_sset_count,
627 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
628 .self_test = mlx4_en_self_test,
629 .get_wol = mlx4_en_get_wol,
630 .set_wol = mlx4_en_set_wol,
631 .get_msglevel = mlx4_en_get_msglevel,
632 .set_msglevel = mlx4_en_set_msglevel,
633 .get_coalesce = mlx4_en_get_coalesce,
634 .set_coalesce = mlx4_en_set_coalesce,
635 .get_pauseparam = mlx4_en_get_pauseparam,
636 .set_pauseparam = mlx4_en_set_pauseparam,
637 .get_ringparam = mlx4_en_get_ringparam,
638 .set_ringparam = mlx4_en_set_ringparam,
639 .get_rxnfc = mlx4_en_get_rxnfc,
640 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
641 .get_rxfh_indir = mlx4_en_get_rxfh_indir,
642 .set_rxfh_indir = mlx4_en_set_rxfh_indir,
643};
644
645
646
647
648
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/ethtool.h>
36#include <linux/netdevice.h>
37#include <linux/mlx4/driver.h>
38#include <linux/mlx4/device.h>
39#include <linux/in.h>
40#include <net/ip.h>
41#include <linux/bitmap.h>
42
43#include "mlx4_en.h"
44#include "en_port.h"
45
46#define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47#define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48#define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
49
50static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
51{
52 int i, t;
53 int err = 0;
54
55 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
56 for (i = 0; i < priv->tx_ring_num[t]; i++) {
57 priv->tx_cq[t][i]->moder_cnt = priv->tx_frames;
58 priv->tx_cq[t][i]->moder_time = priv->tx_usecs;
59 if (priv->port_up) {
60 err = mlx4_en_set_cq_moder(priv,
61 priv->tx_cq[t][i]);
62 if (err)
63 return err;
64 }
65 }
66 }
67
68 if (priv->adaptive_rx_coal)
69 return 0;
70
71 for (i = 0; i < priv->rx_ring_num; i++) {
72 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
73 priv->rx_cq[i]->moder_time = priv->rx_usecs;
74 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
75 if (priv->port_up) {
76 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
77 if (err)
78 return err;
79 }
80 }
81
82 return err;
83}
84
85static void
86mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
87{
88 struct mlx4_en_priv *priv = netdev_priv(dev);
89 struct mlx4_en_dev *mdev = priv->mdev;
90
91 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
92 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
93 sizeof(drvinfo->version));
94 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
95 "%d.%d.%d",
96 (u16) (mdev->dev->caps.fw_ver >> 32),
97 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
98 (u16) (mdev->dev->caps.fw_ver & 0xffff));
99 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
100 sizeof(drvinfo->bus_info));
101}
102
103static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
104 "blueflame",
105 "phv-bit"
106};
107
108static const char main_strings[][ETH_GSTRING_LEN] = {
109 /* main statistics */
110 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
111 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
112 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
113 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
114 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
115 "tx_heartbeat_errors", "tx_window_errors",
116
117 /* port statistics */
118 "tso_packets",
119 "xmit_more",
120 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
121 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
122
123 /* pf statistics */
124 "pf_rx_packets",
125 "pf_rx_bytes",
126 "pf_tx_packets",
127 "pf_tx_bytes",
128
129 /* priority flow control statistics rx */
130 "rx_pause_prio_0", "rx_pause_duration_prio_0",
131 "rx_pause_transition_prio_0",
132 "rx_pause_prio_1", "rx_pause_duration_prio_1",
133 "rx_pause_transition_prio_1",
134 "rx_pause_prio_2", "rx_pause_duration_prio_2",
135 "rx_pause_transition_prio_2",
136 "rx_pause_prio_3", "rx_pause_duration_prio_3",
137 "rx_pause_transition_prio_3",
138 "rx_pause_prio_4", "rx_pause_duration_prio_4",
139 "rx_pause_transition_prio_4",
140 "rx_pause_prio_5", "rx_pause_duration_prio_5",
141 "rx_pause_transition_prio_5",
142 "rx_pause_prio_6", "rx_pause_duration_prio_6",
143 "rx_pause_transition_prio_6",
144 "rx_pause_prio_7", "rx_pause_duration_prio_7",
145 "rx_pause_transition_prio_7",
146
147 /* flow control statistics rx */
148 "rx_pause", "rx_pause_duration", "rx_pause_transition",
149
150 /* priority flow control statistics tx */
151 "tx_pause_prio_0", "tx_pause_duration_prio_0",
152 "tx_pause_transition_prio_0",
153 "tx_pause_prio_1", "tx_pause_duration_prio_1",
154 "tx_pause_transition_prio_1",
155 "tx_pause_prio_2", "tx_pause_duration_prio_2",
156 "tx_pause_transition_prio_2",
157 "tx_pause_prio_3", "tx_pause_duration_prio_3",
158 "tx_pause_transition_prio_3",
159 "tx_pause_prio_4", "tx_pause_duration_prio_4",
160 "tx_pause_transition_prio_4",
161 "tx_pause_prio_5", "tx_pause_duration_prio_5",
162 "tx_pause_transition_prio_5",
163 "tx_pause_prio_6", "tx_pause_duration_prio_6",
164 "tx_pause_transition_prio_6",
165 "tx_pause_prio_7", "tx_pause_duration_prio_7",
166 "tx_pause_transition_prio_7",
167
168 /* flow control statistics tx */
169 "tx_pause", "tx_pause_duration", "tx_pause_transition",
170
171 /* packet statistics */
172 "rx_multicast_packets",
173 "rx_broadcast_packets",
174 "rx_jabbers",
175 "rx_in_range_length_error",
176 "rx_out_range_length_error",
177 "tx_multicast_packets",
178 "tx_broadcast_packets",
179 "rx_prio_0_packets", "rx_prio_0_bytes",
180 "rx_prio_1_packets", "rx_prio_1_bytes",
181 "rx_prio_2_packets", "rx_prio_2_bytes",
182 "rx_prio_3_packets", "rx_prio_3_bytes",
183 "rx_prio_4_packets", "rx_prio_4_bytes",
184 "rx_prio_5_packets", "rx_prio_5_bytes",
185 "rx_prio_6_packets", "rx_prio_6_bytes",
186 "rx_prio_7_packets", "rx_prio_7_bytes",
187 "rx_novlan_packets", "rx_novlan_bytes",
188 "tx_prio_0_packets", "tx_prio_0_bytes",
189 "tx_prio_1_packets", "tx_prio_1_bytes",
190 "tx_prio_2_packets", "tx_prio_2_bytes",
191 "tx_prio_3_packets", "tx_prio_3_bytes",
192 "tx_prio_4_packets", "tx_prio_4_bytes",
193 "tx_prio_5_packets", "tx_prio_5_bytes",
194 "tx_prio_6_packets", "tx_prio_6_bytes",
195 "tx_prio_7_packets", "tx_prio_7_bytes",
196 "tx_novlan_packets", "tx_novlan_bytes",
197
198 /* xdp statistics */
199 "rx_xdp_drop",
200 "rx_xdp_tx",
201 "rx_xdp_tx_full",
202};
203
204static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
205 "Interrupt Test",
206 "Link Test",
207 "Speed Test",
208 "Register Test",
209 "Loopback Test",
210};
211
212static u32 mlx4_en_get_msglevel(struct net_device *dev)
213{
214 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
215}
216
217static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
218{
219 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
220}
221
222static void mlx4_en_get_wol(struct net_device *netdev,
223 struct ethtool_wolinfo *wol)
224{
225 struct mlx4_en_priv *priv = netdev_priv(netdev);
226 int err = 0;
227 u64 config = 0;
228 u64 mask;
229
230 if ((priv->port < 1) || (priv->port > 2)) {
231 en_err(priv, "Failed to get WoL information\n");
232 return;
233 }
234
235 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
236 MLX4_DEV_CAP_FLAG_WOL_PORT2;
237
238 if (!(priv->mdev->dev->caps.flags & mask)) {
239 wol->supported = 0;
240 wol->wolopts = 0;
241 return;
242 }
243
244 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
245 if (err) {
246 en_err(priv, "Failed to get WoL information\n");
247 return;
248 }
249
250 if (config & MLX4_EN_WOL_MAGIC)
251 wol->supported = WAKE_MAGIC;
252 else
253 wol->supported = 0;
254
255 if (config & MLX4_EN_WOL_ENABLED)
256 wol->wolopts = WAKE_MAGIC;
257 else
258 wol->wolopts = 0;
259}
260
261static int mlx4_en_set_wol(struct net_device *netdev,
262 struct ethtool_wolinfo *wol)
263{
264 struct mlx4_en_priv *priv = netdev_priv(netdev);
265 u64 config = 0;
266 int err = 0;
267 u64 mask;
268
269 if ((priv->port < 1) || (priv->port > 2))
270 return -EOPNOTSUPP;
271
272 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
273 MLX4_DEV_CAP_FLAG_WOL_PORT2;
274
275 if (!(priv->mdev->dev->caps.flags & mask))
276 return -EOPNOTSUPP;
277
278 if (wol->supported & ~WAKE_MAGIC)
279 return -EINVAL;
280
281 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
282 if (err) {
283 en_err(priv, "Failed to get WoL info, unable to modify\n");
284 return err;
285 }
286
287 if (wol->wolopts & WAKE_MAGIC) {
288 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
289 MLX4_EN_WOL_MAGIC;
290 } else {
291 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
292 config |= MLX4_EN_WOL_DO_MODIFY;
293 }
294
295 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
296 if (err)
297 en_err(priv, "Failed to set WoL information\n");
298
299 return err;
300}
301
302struct bitmap_iterator {
303 unsigned long *stats_bitmap;
304 unsigned int count;
305 unsigned int iterator;
306 bool advance_array; /* if set, force no increments */
307};
308
309static inline void bitmap_iterator_init(struct bitmap_iterator *h,
310 unsigned long *stats_bitmap,
311 int count)
312{
313 h->iterator = 0;
314 h->advance_array = !bitmap_empty(stats_bitmap, count);
315 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
316 : count;
317 h->stats_bitmap = stats_bitmap;
318}
319
320static inline int bitmap_iterator_test(struct bitmap_iterator *h)
321{
322 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
323}
324
325static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
326{
327 return h->iterator++;
328}
329
330static inline unsigned int
331bitmap_iterator_count(struct bitmap_iterator *h)
332{
333 return h->count;
334}
335
336static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
337{
338 struct mlx4_en_priv *priv = netdev_priv(dev);
339 struct bitmap_iterator it;
340
341 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
342
343 switch (sset) {
344 case ETH_SS_STATS:
345 return bitmap_iterator_count(&it) +
346 (priv->tx_ring_num[TX] * 2) +
347 (priv->rx_ring_num * (3 + NUM_XDP_STATS));
348 case ETH_SS_TEST:
349 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
350 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
351 case ETH_SS_PRIV_FLAGS:
352 return ARRAY_SIZE(mlx4_en_priv_flags);
353 default:
354 return -EOPNOTSUPP;
355 }
356}
357
358static void mlx4_en_get_ethtool_stats(struct net_device *dev,
359 struct ethtool_stats *stats, uint64_t *data)
360{
361 struct mlx4_en_priv *priv = netdev_priv(dev);
362 int index = 0;
363 int i;
364 struct bitmap_iterator it;
365
366 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
367
368 spin_lock_bh(&priv->stats_lock);
369
370 mlx4_en_fold_software_stats(dev);
371
372 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
373 if (bitmap_iterator_test(&it))
374 data[index++] = ((unsigned long *)&dev->stats)[i];
375
376 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
377 if (bitmap_iterator_test(&it))
378 data[index++] = ((unsigned long *)&priv->port_stats)[i];
379
380 for (i = 0; i < NUM_PF_STATS; i++, bitmap_iterator_inc(&it))
381 if (bitmap_iterator_test(&it))
382 data[index++] =
383 ((unsigned long *)&priv->pf_stats)[i];
384
385 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
386 i++, bitmap_iterator_inc(&it))
387 if (bitmap_iterator_test(&it))
388 data[index++] =
389 ((u64 *)&priv->rx_priority_flowstats)[i];
390
391 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
392 if (bitmap_iterator_test(&it))
393 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
394
395 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
396 i++, bitmap_iterator_inc(&it))
397 if (bitmap_iterator_test(&it))
398 data[index++] =
399 ((u64 *)&priv->tx_priority_flowstats)[i];
400
401 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
402 if (bitmap_iterator_test(&it))
403 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
404
405 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
406 if (bitmap_iterator_test(&it))
407 data[index++] = ((unsigned long *)&priv->pkstats)[i];
408
409 for (i = 0; i < NUM_XDP_STATS; i++, bitmap_iterator_inc(&it))
410 if (bitmap_iterator_test(&it))
411 data[index++] = ((unsigned long *)&priv->xdp_stats)[i];
412
413 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
414 data[index++] = priv->tx_ring[TX][i]->packets;
415 data[index++] = priv->tx_ring[TX][i]->bytes;
416 }
417 for (i = 0; i < priv->rx_ring_num; i++) {
418 data[index++] = priv->rx_ring[i]->packets;
419 data[index++] = priv->rx_ring[i]->bytes;
420 data[index++] = priv->rx_ring[i]->dropped;
421 data[index++] = priv->rx_ring[i]->xdp_drop;
422 data[index++] = priv->rx_ring[i]->xdp_tx;
423 data[index++] = priv->rx_ring[i]->xdp_tx_full;
424 }
425 spin_unlock_bh(&priv->stats_lock);
426
427}
428
429static void mlx4_en_self_test(struct net_device *dev,
430 struct ethtool_test *etest, u64 *buf)
431{
432 mlx4_en_ex_selftest(dev, &etest->flags, buf);
433}
434
435static void mlx4_en_get_strings(struct net_device *dev,
436 uint32_t stringset, uint8_t *data)
437{
438 struct mlx4_en_priv *priv = netdev_priv(dev);
439 int index = 0;
440 int i, strings = 0;
441 struct bitmap_iterator it;
442
443 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
444
445 switch (stringset) {
446 case ETH_SS_TEST:
447 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
448 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
449 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
450 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
451 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
452 break;
453
454 case ETH_SS_STATS:
455 /* Add main counters */
456 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
457 bitmap_iterator_inc(&it))
458 if (bitmap_iterator_test(&it))
459 strcpy(data + (index++) * ETH_GSTRING_LEN,
460 main_strings[strings]);
461
462 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
463 bitmap_iterator_inc(&it))
464 if (bitmap_iterator_test(&it))
465 strcpy(data + (index++) * ETH_GSTRING_LEN,
466 main_strings[strings]);
467
468 for (i = 0; i < NUM_PF_STATS; i++, strings++,
469 bitmap_iterator_inc(&it))
470 if (bitmap_iterator_test(&it))
471 strcpy(data + (index++) * ETH_GSTRING_LEN,
472 main_strings[strings]);
473
474 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
475 bitmap_iterator_inc(&it))
476 if (bitmap_iterator_test(&it))
477 strcpy(data + (index++) * ETH_GSTRING_LEN,
478 main_strings[strings]);
479
480 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
481 bitmap_iterator_inc(&it))
482 if (bitmap_iterator_test(&it))
483 strcpy(data + (index++) * ETH_GSTRING_LEN,
484 main_strings[strings]);
485
486 for (i = 0; i < NUM_XDP_STATS; i++, strings++,
487 bitmap_iterator_inc(&it))
488 if (bitmap_iterator_test(&it))
489 strcpy(data + (index++) * ETH_GSTRING_LEN,
490 main_strings[strings]);
491
492 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
493 sprintf(data + (index++) * ETH_GSTRING_LEN,
494 "tx%d_packets", i);
495 sprintf(data + (index++) * ETH_GSTRING_LEN,
496 "tx%d_bytes", i);
497 }
498 for (i = 0; i < priv->rx_ring_num; i++) {
499 sprintf(data + (index++) * ETH_GSTRING_LEN,
500 "rx%d_packets", i);
501 sprintf(data + (index++) * ETH_GSTRING_LEN,
502 "rx%d_bytes", i);
503 sprintf(data + (index++) * ETH_GSTRING_LEN,
504 "rx%d_dropped", i);
505 sprintf(data + (index++) * ETH_GSTRING_LEN,
506 "rx%d_xdp_drop", i);
507 sprintf(data + (index++) * ETH_GSTRING_LEN,
508 "rx%d_xdp_tx", i);
509 sprintf(data + (index++) * ETH_GSTRING_LEN,
510 "rx%d_xdp_tx_full", i);
511 }
512 break;
513 case ETH_SS_PRIV_FLAGS:
514 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
515 strcpy(data + i * ETH_GSTRING_LEN,
516 mlx4_en_priv_flags[i]);
517 break;
518
519 }
520}
521
522static u32 mlx4_en_autoneg_get(struct net_device *dev)
523{
524 struct mlx4_en_priv *priv = netdev_priv(dev);
525 struct mlx4_en_dev *mdev = priv->mdev;
526 u32 autoneg = AUTONEG_DISABLE;
527
528 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
529 (priv->port_state.flags & MLX4_EN_PORT_ANE))
530 autoneg = AUTONEG_ENABLE;
531
532 return autoneg;
533}
534
535static void ptys2ethtool_update_supported_port(unsigned long *mask,
536 struct mlx4_ptys_reg *ptys_reg)
537{
538 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
539
540 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
541 | MLX4_PROT_MASK(MLX4_1000BASE_T)
542 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
543 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
544 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
545 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
546 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
547 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
548 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
549 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
550 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask);
551 } else if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
552 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
553 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
554 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
555 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
556 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
557 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask);
558 }
559}
560
561static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
562{
563 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
564
565 if (!eth_proto) /* link down */
566 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
567
568 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
569 | MLX4_PROT_MASK(MLX4_1000BASE_T)
570 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
571 return PORT_TP;
572 }
573
574 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
575 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
576 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
577 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
578 return PORT_FIBRE;
579 }
580
581 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
582 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
583 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
584 return PORT_DA;
585 }
586
587 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
588 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
589 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
590 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
591 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
592 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
593 return PORT_NONE;
594 }
595 return PORT_OTHER;
596}
597
598#define MLX4_LINK_MODES_SZ \
599 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
600
601enum ethtool_report {
602 SUPPORTED = 0,
603 ADVERTISED = 1,
604};
605
606struct ptys2ethtool_config {
607 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
608 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
609 u32 speed;
610};
611
612static unsigned long *ptys2ethtool_link_mode(struct ptys2ethtool_config *cfg,
613 enum ethtool_report report)
614{
615 switch (report) {
616 case SUPPORTED:
617 return cfg->supported;
618 case ADVERTISED:
619 return cfg->advertised;
620 }
621 return NULL;
622}
623
624#define MLX4_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
625 ({ \
626 struct ptys2ethtool_config *cfg; \
627 const unsigned int modes[] = { __VA_ARGS__ }; \
628 unsigned int i; \
629 cfg = &ptys2ethtool_map[reg_]; \
630 cfg->speed = speed_; \
631 bitmap_zero(cfg->supported, \
632 __ETHTOOL_LINK_MODE_MASK_NBITS); \
633 bitmap_zero(cfg->advertised, \
634 __ETHTOOL_LINK_MODE_MASK_NBITS); \
635 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
636 __set_bit(modes[i], cfg->supported); \
637 __set_bit(modes[i], cfg->advertised); \
638 } \
639 })
640
641/* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
642static struct ptys2ethtool_config ptys2ethtool_map[MLX4_LINK_MODES_SZ];
643
644void __init mlx4_en_init_ptys2ethtool_map(void)
645{
646 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_100BASE_TX, SPEED_100,
647 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
648 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_T, SPEED_1000,
649 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
650 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_CX_SGMII, SPEED_1000,
651 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
652 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_1000BASE_KX, SPEED_1000,
653 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
654 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_T, SPEED_10000,
655 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
656 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CX4, SPEED_10000,
657 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
658 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KX4, SPEED_10000,
659 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
660 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_KR, SPEED_10000,
661 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
662 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_CR, SPEED_10000,
663 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
664 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_10GBASE_SR, SPEED_10000,
665 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
666 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_20GBASE_KR2, SPEED_20000,
667 ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT,
668 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
669 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_CR4, SPEED_40000,
670 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
671 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_KR4, SPEED_40000,
672 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
673 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_40GBASE_SR4, SPEED_40000,
674 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
675 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_KR4, SPEED_56000,
676 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
677 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_CR4, SPEED_56000,
678 ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT);
679 MLX4_BUILD_PTYS2ETHTOOL_CONFIG(MLX4_56GBASE_SR4, SPEED_56000,
680 ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT);
681};
682
683static void ptys2ethtool_update_link_modes(unsigned long *link_modes,
684 u32 eth_proto,
685 enum ethtool_report report)
686{
687 int i;
688 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
689 if (eth_proto & MLX4_PROT_MASK(i))
690 bitmap_or(link_modes, link_modes,
691 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
692 report),
693 __ETHTOOL_LINK_MODE_MASK_NBITS);
694 }
695}
696
697static u32 ethtool2ptys_link_modes(const unsigned long *link_modes,
698 enum ethtool_report report)
699{
700 int i;
701 u32 ptys_modes = 0;
702
703 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
704 if (bitmap_intersects(
705 ptys2ethtool_link_mode(&ptys2ethtool_map[i],
706 report),
707 link_modes,
708 __ETHTOOL_LINK_MODE_MASK_NBITS))
709 ptys_modes |= 1 << i;
710 }
711 return ptys_modes;
712}
713
714/* Convert actual speed (SPEED_XXX) to ptys link modes */
715static u32 speed2ptys_link_modes(u32 speed)
716{
717 int i;
718 u32 ptys_modes = 0;
719
720 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
721 if (ptys2ethtool_map[i].speed == speed)
722 ptys_modes |= 1 << i;
723 }
724 return ptys_modes;
725}
726
727static int
728ethtool_get_ptys_link_ksettings(struct net_device *dev,
729 struct ethtool_link_ksettings *link_ksettings)
730{
731 struct mlx4_en_priv *priv = netdev_priv(dev);
732 struct mlx4_ptys_reg ptys_reg;
733 u32 eth_proto;
734 int ret;
735
736 memset(&ptys_reg, 0, sizeof(ptys_reg));
737 ptys_reg.local_port = priv->port;
738 ptys_reg.proto_mask = MLX4_PTYS_EN;
739 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
740 MLX4_ACCESS_REG_QUERY, &ptys_reg);
741 if (ret) {
742 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
743 ret);
744 return ret;
745 }
746 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
747 ptys_reg.proto_mask);
748 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
749 be32_to_cpu(ptys_reg.eth_proto_cap));
750 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
751 be32_to_cpu(ptys_reg.eth_proto_admin));
752 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
753 be32_to_cpu(ptys_reg.eth_proto_oper));
754 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
755 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
756
757 /* reset supported/advertising masks */
758 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
759 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
760
761 ptys2ethtool_update_supported_port(link_ksettings->link_modes.supported,
762 &ptys_reg);
763
764 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
765 ptys2ethtool_update_link_modes(link_ksettings->link_modes.supported,
766 eth_proto, SUPPORTED);
767
768 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
769 ptys2ethtool_update_link_modes(link_ksettings->link_modes.advertising,
770 eth_proto, ADVERTISED);
771
772 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
773 Pause);
774 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
775 Asym_Pause);
776
777 if (priv->prof->tx_pause)
778 ethtool_link_ksettings_add_link_mode(link_ksettings,
779 advertising, Pause);
780 if (priv->prof->tx_pause ^ priv->prof->rx_pause)
781 ethtool_link_ksettings_add_link_mode(link_ksettings,
782 advertising, Asym_Pause);
783
784 link_ksettings->base.port = ptys_get_active_port(&ptys_reg);
785
786 if (mlx4_en_autoneg_get(dev)) {
787 ethtool_link_ksettings_add_link_mode(link_ksettings,
788 supported, Autoneg);
789 ethtool_link_ksettings_add_link_mode(link_ksettings,
790 advertising, Autoneg);
791 }
792
793 link_ksettings->base.autoneg
794 = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
795 AUTONEG_ENABLE : AUTONEG_DISABLE;
796
797 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
798
799 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
800 ptys2ethtool_update_link_modes(
801 link_ksettings->link_modes.lp_advertising,
802 eth_proto, ADVERTISED);
803 if (priv->port_state.flags & MLX4_EN_PORT_ANC)
804 ethtool_link_ksettings_add_link_mode(link_ksettings,
805 lp_advertising, Autoneg);
806
807 link_ksettings->base.phy_address = 0;
808 link_ksettings->base.mdio_support = 0;
809 link_ksettings->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
810 link_ksettings->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
811
812 return ret;
813}
814
815static void
816ethtool_get_default_link_ksettings(
817 struct net_device *dev, struct ethtool_link_ksettings *link_ksettings)
818{
819 struct mlx4_en_priv *priv = netdev_priv(dev);
820 int trans_type;
821
822 link_ksettings->base.autoneg = AUTONEG_DISABLE;
823
824 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
825 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
826 10000baseT_Full);
827
828 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
829 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising,
830 10000baseT_Full);
831
832 trans_type = priv->port_state.transceiver;
833 if (trans_type > 0 && trans_type <= 0xC) {
834 link_ksettings->base.port = PORT_FIBRE;
835 ethtool_link_ksettings_add_link_mode(link_ksettings,
836 supported, FIBRE);
837 ethtool_link_ksettings_add_link_mode(link_ksettings,
838 advertising, FIBRE);
839 } else if (trans_type == 0x80 || trans_type == 0) {
840 link_ksettings->base.port = PORT_TP;
841 ethtool_link_ksettings_add_link_mode(link_ksettings,
842 supported, TP);
843 ethtool_link_ksettings_add_link_mode(link_ksettings,
844 advertising, TP);
845 } else {
846 link_ksettings->base.port = -1;
847 }
848}
849
850static int
851mlx4_en_get_link_ksettings(struct net_device *dev,
852 struct ethtool_link_ksettings *link_ksettings)
853{
854 struct mlx4_en_priv *priv = netdev_priv(dev);
855 int ret = -EINVAL;
856
857 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
858 return -ENOMEM;
859
860 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
861 priv->port_state.flags & MLX4_EN_PORT_ANC,
862 priv->port_state.flags & MLX4_EN_PORT_ANE);
863
864 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
865 ret = ethtool_get_ptys_link_ksettings(dev, link_ksettings);
866 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
867 ethtool_get_default_link_ksettings(dev, link_ksettings);
868
869 if (netif_carrier_ok(dev)) {
870 link_ksettings->base.speed = priv->port_state.link_speed;
871 link_ksettings->base.duplex = DUPLEX_FULL;
872 } else {
873 link_ksettings->base.speed = SPEED_UNKNOWN;
874 link_ksettings->base.duplex = DUPLEX_UNKNOWN;
875 }
876 return 0;
877}
878
879/* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
880static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
881 __be32 proto_cap)
882{
883 __be32 proto_admin = 0;
884
885 if (!speed) { /* Speed = 0 ==> Reset Link modes */
886 proto_admin = proto_cap;
887 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
888 be32_to_cpu(proto_cap));
889 } else {
890 u32 ptys_link_modes = speed2ptys_link_modes(speed);
891
892 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
893 en_info(priv, "Setting Speed to %d\n", speed);
894 }
895 return proto_admin;
896}
897
898static int
899mlx4_en_set_link_ksettings(struct net_device *dev,
900 const struct ethtool_link_ksettings *link_ksettings)
901{
902 struct mlx4_en_priv *priv = netdev_priv(dev);
903 struct mlx4_ptys_reg ptys_reg;
904 __be32 proto_admin;
905 int ret;
906
907 u32 ptys_adv = ethtool2ptys_link_modes(
908 link_ksettings->link_modes.advertising, ADVERTISED);
909 const int speed = link_ksettings->base.speed;
910
911 en_dbg(DRV, priv,
912 "Set Speed=%d adv={%*pbl} autoneg=%d duplex=%d\n",
913 speed, __ETHTOOL_LINK_MODE_MASK_NBITS,
914 link_ksettings->link_modes.advertising,
915 link_ksettings->base.autoneg,
916 link_ksettings->base.duplex);
917
918 if (!(priv->mdev->dev->caps.flags2 &
919 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
920 (link_ksettings->base.duplex == DUPLEX_HALF))
921 return -EINVAL;
922
923 memset(&ptys_reg, 0, sizeof(ptys_reg));
924 ptys_reg.local_port = priv->port;
925 ptys_reg.proto_mask = MLX4_PTYS_EN;
926 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
927 MLX4_ACCESS_REG_QUERY, &ptys_reg);
928 if (ret) {
929 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
930 ret);
931 return 0;
932 }
933
934 proto_admin = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
935 cpu_to_be32(ptys_adv) :
936 speed_set_ptys_admin(priv, speed,
937 ptys_reg.eth_proto_cap);
938
939 proto_admin &= ptys_reg.eth_proto_cap;
940 if (!proto_admin) {
941 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
942 return -EINVAL; /* nothing to change due to bad input */
943 }
944
945 if (proto_admin == ptys_reg.eth_proto_admin)
946 return 0; /* Nothing to change */
947
948 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
949 be32_to_cpu(proto_admin));
950
951 ptys_reg.eth_proto_admin = proto_admin;
952 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
953 &ptys_reg);
954 if (ret) {
955 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
956 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
957 return ret;
958 }
959
960 mutex_lock(&priv->mdev->state_lock);
961 if (priv->port_up) {
962 en_warn(priv, "Port link mode changed, restarting port...\n");
963 mlx4_en_stop_port(dev, 1);
964 if (mlx4_en_start_port(dev))
965 en_err(priv, "Failed restarting port %d\n", priv->port);
966 }
967 mutex_unlock(&priv->mdev->state_lock);
968 return 0;
969}
970
971static int mlx4_en_get_coalesce(struct net_device *dev,
972 struct ethtool_coalesce *coal)
973{
974 struct mlx4_en_priv *priv = netdev_priv(dev);
975
976 coal->tx_coalesce_usecs = priv->tx_usecs;
977 coal->tx_max_coalesced_frames = priv->tx_frames;
978 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
979
980 coal->rx_coalesce_usecs = priv->rx_usecs;
981 coal->rx_max_coalesced_frames = priv->rx_frames;
982
983 coal->pkt_rate_low = priv->pkt_rate_low;
984 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
985 coal->pkt_rate_high = priv->pkt_rate_high;
986 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
987 coal->rate_sample_interval = priv->sample_interval;
988 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
989
990 return 0;
991}
992
993static int mlx4_en_set_coalesce(struct net_device *dev,
994 struct ethtool_coalesce *coal)
995{
996 struct mlx4_en_priv *priv = netdev_priv(dev);
997
998 if (!coal->tx_max_coalesced_frames_irq)
999 return -EINVAL;
1000
1001 priv->rx_frames = (coal->rx_max_coalesced_frames ==
1002 MLX4_EN_AUTO_CONF) ?
1003 MLX4_EN_RX_COAL_TARGET :
1004 coal->rx_max_coalesced_frames;
1005 priv->rx_usecs = (coal->rx_coalesce_usecs ==
1006 MLX4_EN_AUTO_CONF) ?
1007 MLX4_EN_RX_COAL_TIME :
1008 coal->rx_coalesce_usecs;
1009
1010 /* Setting TX coalescing parameters */
1011 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
1012 coal->tx_max_coalesced_frames != priv->tx_frames) {
1013 priv->tx_usecs = coal->tx_coalesce_usecs;
1014 priv->tx_frames = coal->tx_max_coalesced_frames;
1015 }
1016
1017 /* Set adaptive coalescing params */
1018 priv->pkt_rate_low = coal->pkt_rate_low;
1019 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
1020 priv->pkt_rate_high = coal->pkt_rate_high;
1021 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
1022 priv->sample_interval = coal->rate_sample_interval;
1023 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
1024 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
1025
1026 return mlx4_en_moderation_update(priv);
1027}
1028
1029static int mlx4_en_set_pauseparam(struct net_device *dev,
1030 struct ethtool_pauseparam *pause)
1031{
1032 struct mlx4_en_priv *priv = netdev_priv(dev);
1033 struct mlx4_en_dev *mdev = priv->mdev;
1034 int err;
1035
1036 if (pause->autoneg)
1037 return -EINVAL;
1038
1039 priv->prof->tx_pause = pause->tx_pause != 0;
1040 priv->prof->rx_pause = pause->rx_pause != 0;
1041 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1042 priv->rx_skb_size + ETH_FCS_LEN,
1043 priv->prof->tx_pause,
1044 priv->prof->tx_ppp,
1045 priv->prof->rx_pause,
1046 priv->prof->rx_ppp);
1047 if (err)
1048 en_err(priv, "Failed setting pause params\n");
1049 else
1050 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1051 priv->prof->rx_ppp,
1052 priv->prof->rx_pause,
1053 priv->prof->tx_ppp,
1054 priv->prof->tx_pause);
1055
1056 return err;
1057}
1058
1059static void mlx4_en_get_pauseparam(struct net_device *dev,
1060 struct ethtool_pauseparam *pause)
1061{
1062 struct mlx4_en_priv *priv = netdev_priv(dev);
1063
1064 pause->tx_pause = priv->prof->tx_pause;
1065 pause->rx_pause = priv->prof->rx_pause;
1066}
1067
1068static int mlx4_en_set_ringparam(struct net_device *dev,
1069 struct ethtool_ringparam *param)
1070{
1071 struct mlx4_en_priv *priv = netdev_priv(dev);
1072 struct mlx4_en_dev *mdev = priv->mdev;
1073 struct mlx4_en_port_profile new_prof;
1074 struct mlx4_en_priv *tmp;
1075 u32 rx_size, tx_size;
1076 int port_up = 0;
1077 int err = 0;
1078
1079 if (param->rx_jumbo_pending || param->rx_mini_pending)
1080 return -EINVAL;
1081
1082 rx_size = roundup_pow_of_two(param->rx_pending);
1083 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1084 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1085 tx_size = roundup_pow_of_two(param->tx_pending);
1086 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1087 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1088
1089 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1090 priv->rx_ring[0]->size) &&
1091 tx_size == priv->tx_ring[TX][0]->size)
1092 return 0;
1093
1094 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1095 if (!tmp)
1096 return -ENOMEM;
1097
1098 mutex_lock(&mdev->state_lock);
1099 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1100 new_prof.tx_ring_size = tx_size;
1101 new_prof.rx_ring_size = rx_size;
1102 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1103 if (err)
1104 goto out;
1105
1106 if (priv->port_up) {
1107 port_up = 1;
1108 mlx4_en_stop_port(dev, 1);
1109 }
1110
1111 mlx4_en_safe_replace_resources(priv, tmp);
1112
1113 if (port_up) {
1114 err = mlx4_en_start_port(dev);
1115 if (err)
1116 en_err(priv, "Failed starting port\n");
1117 }
1118
1119 err = mlx4_en_moderation_update(priv);
1120out:
1121 kfree(tmp);
1122 mutex_unlock(&mdev->state_lock);
1123 return err;
1124}
1125
1126static void mlx4_en_get_ringparam(struct net_device *dev,
1127 struct ethtool_ringparam *param)
1128{
1129 struct mlx4_en_priv *priv = netdev_priv(dev);
1130
1131 memset(param, 0, sizeof(*param));
1132 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1133 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1134 param->rx_pending = priv->port_up ?
1135 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1136 param->tx_pending = priv->tx_ring[TX][0]->size;
1137}
1138
1139static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1140{
1141 struct mlx4_en_priv *priv = netdev_priv(dev);
1142
1143 return rounddown_pow_of_two(priv->rx_ring_num);
1144}
1145
1146static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1147{
1148 return MLX4_EN_RSS_KEY_SIZE;
1149}
1150
1151static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1152{
1153 struct mlx4_en_priv *priv = netdev_priv(dev);
1154
1155 /* check if requested function is supported by the device */
1156 if (hfunc == ETH_RSS_HASH_TOP) {
1157 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP))
1158 return -EINVAL;
1159 if (!(dev->features & NETIF_F_RXHASH))
1160 en_warn(priv, "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1161 return 0;
1162 } else if (hfunc == ETH_RSS_HASH_XOR) {
1163 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR))
1164 return -EINVAL;
1165 if (dev->features & NETIF_F_RXHASH)
1166 en_warn(priv, "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1167 return 0;
1168 }
1169
1170 return -EINVAL;
1171}
1172
1173static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1174 u8 *hfunc)
1175{
1176 struct mlx4_en_priv *priv = netdev_priv(dev);
1177 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1178 u32 i, rss_rings;
1179 int err = 0;
1180
1181 rss_rings = priv->prof->rss_rings ?: n;
1182 rss_rings = rounddown_pow_of_two(rss_rings);
1183
1184 for (i = 0; i < n; i++) {
1185 if (!ring_index)
1186 break;
1187 ring_index[i] = i % rss_rings;
1188 }
1189 if (key)
1190 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1191 if (hfunc)
1192 *hfunc = priv->rss_hash_fn;
1193 return err;
1194}
1195
1196static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1197 const u8 *key, const u8 hfunc)
1198{
1199 struct mlx4_en_priv *priv = netdev_priv(dev);
1200 u32 n = mlx4_en_get_rxfh_indir_size(dev);
1201 struct mlx4_en_dev *mdev = priv->mdev;
1202 int port_up = 0;
1203 int err = 0;
1204 int i;
1205 int rss_rings = 0;
1206
1207 /* Calculate RSS table size and make sure flows are spread evenly
1208 * between rings
1209 */
1210 for (i = 0; i < n; i++) {
1211 if (!ring_index)
1212 break;
1213 if (i > 0 && !ring_index[i] && !rss_rings)
1214 rss_rings = i;
1215
1216 if (ring_index[i] != (i % (rss_rings ?: n)))
1217 return -EINVAL;
1218 }
1219
1220 if (!rss_rings)
1221 rss_rings = n;
1222
1223 /* RSS table size must be an order of 2 */
1224 if (!is_power_of_2(rss_rings))
1225 return -EINVAL;
1226
1227 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1228 err = mlx4_en_check_rxfh_func(dev, hfunc);
1229 if (err)
1230 return err;
1231 }
1232
1233 mutex_lock(&mdev->state_lock);
1234 if (priv->port_up) {
1235 port_up = 1;
1236 mlx4_en_stop_port(dev, 1);
1237 }
1238
1239 if (ring_index)
1240 priv->prof->rss_rings = rss_rings;
1241 if (key)
1242 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1243 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1244 priv->rss_hash_fn = hfunc;
1245
1246 if (port_up) {
1247 err = mlx4_en_start_port(dev);
1248 if (err)
1249 en_err(priv, "Failed starting port\n");
1250 }
1251
1252 mutex_unlock(&mdev->state_lock);
1253 return err;
1254}
1255
1256#define all_zeros_or_all_ones(field) \
1257 ((field) == 0 || (field) == (__force typeof(field))-1)
1258
1259static int mlx4_en_validate_flow(struct net_device *dev,
1260 struct ethtool_rxnfc *cmd)
1261{
1262 struct ethtool_usrip4_spec *l3_mask;
1263 struct ethtool_tcpip4_spec *l4_mask;
1264 struct ethhdr *eth_mask;
1265
1266 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1267 return -EINVAL;
1268
1269 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1270 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1271 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1272 return -EINVAL;
1273 }
1274
1275 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1276 case TCP_V4_FLOW:
1277 case UDP_V4_FLOW:
1278 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1279 return -EINVAL;
1280 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1281 /* don't allow mask which isn't all 0 or 1 */
1282 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1283 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1284 !all_zeros_or_all_ones(l4_mask->psrc) ||
1285 !all_zeros_or_all_ones(l4_mask->pdst))
1286 return -EINVAL;
1287 break;
1288 case IP_USER_FLOW:
1289 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1290 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1291 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1292 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1293 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1294 !all_zeros_or_all_ones(l3_mask->ip4dst))
1295 return -EINVAL;
1296 break;
1297 case ETHER_FLOW:
1298 eth_mask = &cmd->fs.m_u.ether_spec;
1299 /* source mac mask must not be set */
1300 if (!is_zero_ether_addr(eth_mask->h_source))
1301 return -EINVAL;
1302
1303 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1304 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1305 return -EINVAL;
1306
1307 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1308 return -EINVAL;
1309 break;
1310 default:
1311 return -EINVAL;
1312 }
1313
1314 if ((cmd->fs.flow_type & FLOW_EXT)) {
1315 if (cmd->fs.m_ext.vlan_etype ||
1316 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1317 0 ||
1318 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1319 cpu_to_be16(VLAN_VID_MASK)))
1320 return -EINVAL;
1321
1322 if (cmd->fs.m_ext.vlan_tci) {
1323 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1324 return -EINVAL;
1325
1326 }
1327 }
1328
1329 return 0;
1330}
1331
1332static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1333 struct list_head *rule_list_h,
1334 struct mlx4_spec_list *spec_l2,
1335 unsigned char *mac)
1336{
1337 int err = 0;
1338 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1339
1340 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1341 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1342 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1343
1344 if ((cmd->fs.flow_type & FLOW_EXT) &&
1345 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1346 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1347 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1348 }
1349
1350 list_add_tail(&spec_l2->list, rule_list_h);
1351
1352 return err;
1353}
1354
1355static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1356 struct ethtool_rxnfc *cmd,
1357 struct list_head *rule_list_h,
1358 struct mlx4_spec_list *spec_l2,
1359 __be32 ipv4_dst)
1360{
1361#ifdef CONFIG_INET
1362 unsigned char mac[ETH_ALEN];
1363
1364 if (!ipv4_is_multicast(ipv4_dst)) {
1365 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1366 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1367 else
1368 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1369 } else {
1370 ip_eth_mc_map(ipv4_dst, mac);
1371 }
1372
1373 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1374#else
1375 return -EINVAL;
1376#endif
1377}
1378
1379static int add_ip_rule(struct mlx4_en_priv *priv,
1380 struct ethtool_rxnfc *cmd,
1381 struct list_head *list_h)
1382{
1383 int err;
1384 struct mlx4_spec_list *spec_l2 = NULL;
1385 struct mlx4_spec_list *spec_l3 = NULL;
1386 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1387
1388 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1389 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1390 if (!spec_l2 || !spec_l3) {
1391 err = -ENOMEM;
1392 goto free_spec;
1393 }
1394
1395 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1396 cmd->fs.h_u.
1397 usr_ip4_spec.ip4dst);
1398 if (err)
1399 goto free_spec;
1400 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1401 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1402 if (l3_mask->ip4src)
1403 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1404 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1405 if (l3_mask->ip4dst)
1406 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1407 list_add_tail(&spec_l3->list, list_h);
1408
1409 return 0;
1410
1411free_spec:
1412 kfree(spec_l2);
1413 kfree(spec_l3);
1414 return err;
1415}
1416
1417static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1418 struct ethtool_rxnfc *cmd,
1419 struct list_head *list_h, int proto)
1420{
1421 int err;
1422 struct mlx4_spec_list *spec_l2 = NULL;
1423 struct mlx4_spec_list *spec_l3 = NULL;
1424 struct mlx4_spec_list *spec_l4 = NULL;
1425 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1426
1427 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1428 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1429 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1430 if (!spec_l2 || !spec_l3 || !spec_l4) {
1431 err = -ENOMEM;
1432 goto free_spec;
1433 }
1434
1435 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1436
1437 if (proto == TCP_V4_FLOW) {
1438 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1439 spec_l2,
1440 cmd->fs.h_u.
1441 tcp_ip4_spec.ip4dst);
1442 if (err)
1443 goto free_spec;
1444 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1445 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1446 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1447 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1448 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1449 } else {
1450 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1451 spec_l2,
1452 cmd->fs.h_u.
1453 udp_ip4_spec.ip4dst);
1454 if (err)
1455 goto free_spec;
1456 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1457 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1458 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1459 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1460 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1461 }
1462
1463 if (l4_mask->ip4src)
1464 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1465 if (l4_mask->ip4dst)
1466 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1467
1468 if (l4_mask->psrc)
1469 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1470 if (l4_mask->pdst)
1471 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1472
1473 list_add_tail(&spec_l3->list, list_h);
1474 list_add_tail(&spec_l4->list, list_h);
1475
1476 return 0;
1477
1478free_spec:
1479 kfree(spec_l2);
1480 kfree(spec_l3);
1481 kfree(spec_l4);
1482 return err;
1483}
1484
1485static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1486 struct ethtool_rxnfc *cmd,
1487 struct list_head *rule_list_h)
1488{
1489 int err;
1490 struct ethhdr *eth_spec;
1491 struct mlx4_spec_list *spec_l2;
1492 struct mlx4_en_priv *priv = netdev_priv(dev);
1493
1494 err = mlx4_en_validate_flow(dev, cmd);
1495 if (err)
1496 return err;
1497
1498 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1499 case ETHER_FLOW:
1500 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1501 if (!spec_l2)
1502 return -ENOMEM;
1503
1504 eth_spec = &cmd->fs.h_u.ether_spec;
1505 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1506 ð_spec->h_dest[0]);
1507 spec_l2->eth.ether_type = eth_spec->h_proto;
1508 if (eth_spec->h_proto)
1509 spec_l2->eth.ether_type_enable = 1;
1510 break;
1511 case IP_USER_FLOW:
1512 err = add_ip_rule(priv, cmd, rule_list_h);
1513 break;
1514 case TCP_V4_FLOW:
1515 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1516 break;
1517 case UDP_V4_FLOW:
1518 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1519 break;
1520 }
1521
1522 return err;
1523}
1524
1525static int mlx4_en_flow_replace(struct net_device *dev,
1526 struct ethtool_rxnfc *cmd)
1527{
1528 int err;
1529 struct mlx4_en_priv *priv = netdev_priv(dev);
1530 struct ethtool_flow_id *loc_rule;
1531 struct mlx4_spec_list *spec, *tmp_spec;
1532 u32 qpn;
1533 u64 reg_id;
1534
1535 struct mlx4_net_trans_rule rule = {
1536 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1537 .exclusive = 0,
1538 .allow_loopback = 1,
1539 .promisc_mode = MLX4_FS_REGULAR,
1540 };
1541
1542 rule.port = priv->port;
1543 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1544 INIT_LIST_HEAD(&rule.list);
1545
1546 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1547 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1548 qpn = priv->drop_qp.qpn;
1549 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1550 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1551 } else {
1552 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1553 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1554 cmd->fs.ring_cookie);
1555 return -EINVAL;
1556 }
1557 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1558 if (!qpn) {
1559 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1560 cmd->fs.ring_cookie);
1561 return -EINVAL;
1562 }
1563 }
1564 rule.qpn = qpn;
1565 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1566 if (err)
1567 goto out_free_list;
1568
1569 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1570 if (loc_rule->id) {
1571 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1572 if (err) {
1573 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1574 cmd->fs.location, loc_rule->id);
1575 goto out_free_list;
1576 }
1577 loc_rule->id = 0;
1578 memset(&loc_rule->flow_spec, 0,
1579 sizeof(struct ethtool_rx_flow_spec));
1580 list_del(&loc_rule->list);
1581 }
1582 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1583 if (err) {
1584 en_err(priv, "Fail to attach network rule at location %d\n",
1585 cmd->fs.location);
1586 goto out_free_list;
1587 }
1588 loc_rule->id = reg_id;
1589 memcpy(&loc_rule->flow_spec, &cmd->fs,
1590 sizeof(struct ethtool_rx_flow_spec));
1591 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1592
1593out_free_list:
1594 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1595 list_del(&spec->list);
1596 kfree(spec);
1597 }
1598 return err;
1599}
1600
1601static int mlx4_en_flow_detach(struct net_device *dev,
1602 struct ethtool_rxnfc *cmd)
1603{
1604 int err = 0;
1605 struct ethtool_flow_id *rule;
1606 struct mlx4_en_priv *priv = netdev_priv(dev);
1607
1608 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1609 return -EINVAL;
1610
1611 rule = &priv->ethtool_rules[cmd->fs.location];
1612 if (!rule->id) {
1613 err = -ENOENT;
1614 goto out;
1615 }
1616
1617 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1618 if (err) {
1619 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1620 cmd->fs.location, rule->id);
1621 goto out;
1622 }
1623 rule->id = 0;
1624 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1625 list_del(&rule->list);
1626out:
1627 return err;
1628
1629}
1630
1631static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1632 int loc)
1633{
1634 int err = 0;
1635 struct ethtool_flow_id *rule;
1636 struct mlx4_en_priv *priv = netdev_priv(dev);
1637
1638 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1639 return -EINVAL;
1640
1641 rule = &priv->ethtool_rules[loc];
1642 if (rule->id)
1643 memcpy(&cmd->fs, &rule->flow_spec,
1644 sizeof(struct ethtool_rx_flow_spec));
1645 else
1646 err = -ENOENT;
1647
1648 return err;
1649}
1650
1651static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1652{
1653
1654 int i, res = 0;
1655 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1656 if (priv->ethtool_rules[i].id)
1657 res++;
1658 }
1659 return res;
1660
1661}
1662
1663static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1664 u32 *rule_locs)
1665{
1666 struct mlx4_en_priv *priv = netdev_priv(dev);
1667 struct mlx4_en_dev *mdev = priv->mdev;
1668 int err = 0;
1669 int i = 0, priority = 0;
1670
1671 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1672 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1673 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1674 (mdev->dev->caps.steering_mode !=
1675 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1676 return -EINVAL;
1677
1678 switch (cmd->cmd) {
1679 case ETHTOOL_GRXRINGS:
1680 cmd->data = priv->rx_ring_num;
1681 break;
1682 case ETHTOOL_GRXCLSRLCNT:
1683 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1684 break;
1685 case ETHTOOL_GRXCLSRULE:
1686 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1687 break;
1688 case ETHTOOL_GRXCLSRLALL:
1689 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1690 err = mlx4_en_get_flow(dev, cmd, i);
1691 if (!err)
1692 rule_locs[priority++] = i;
1693 i++;
1694 }
1695 err = 0;
1696 break;
1697 default:
1698 err = -EOPNOTSUPP;
1699 break;
1700 }
1701
1702 return err;
1703}
1704
1705static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1706{
1707 int err = 0;
1708 struct mlx4_en_priv *priv = netdev_priv(dev);
1709 struct mlx4_en_dev *mdev = priv->mdev;
1710
1711 if (mdev->dev->caps.steering_mode !=
1712 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1713 return -EINVAL;
1714
1715 switch (cmd->cmd) {
1716 case ETHTOOL_SRXCLSRLINS:
1717 err = mlx4_en_flow_replace(dev, cmd);
1718 break;
1719 case ETHTOOL_SRXCLSRLDEL:
1720 err = mlx4_en_flow_detach(dev, cmd);
1721 break;
1722 default:
1723 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1724 return -EINVAL;
1725 }
1726
1727 return err;
1728}
1729
1730static void mlx4_en_get_channels(struct net_device *dev,
1731 struct ethtool_channels *channel)
1732{
1733 struct mlx4_en_priv *priv = netdev_priv(dev);
1734
1735 channel->max_rx = MAX_RX_RINGS;
1736 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1737
1738 channel->rx_count = priv->rx_ring_num;
1739 channel->tx_count = priv->tx_ring_num[TX] / MLX4_EN_NUM_UP;
1740}
1741
1742static int mlx4_en_set_channels(struct net_device *dev,
1743 struct ethtool_channels *channel)
1744{
1745 struct mlx4_en_priv *priv = netdev_priv(dev);
1746 struct mlx4_en_dev *mdev = priv->mdev;
1747 struct mlx4_en_port_profile new_prof;
1748 struct mlx4_en_priv *tmp;
1749 int port_up = 0;
1750 int xdp_count;
1751 int err = 0;
1752
1753 if (!channel->tx_count || !channel->rx_count)
1754 return -EINVAL;
1755
1756 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1757 if (!tmp)
1758 return -ENOMEM;
1759
1760 mutex_lock(&mdev->state_lock);
1761 xdp_count = priv->tx_ring_num[TX_XDP] ? channel->rx_count : 0;
1762 if (channel->tx_count * MLX4_EN_NUM_UP + xdp_count > MAX_TX_RINGS) {
1763 err = -EINVAL;
1764 en_err(priv,
1765 "Total number of TX and XDP rings (%d) exceeds the maximum supported (%d)\n",
1766 channel->tx_count * MLX4_EN_NUM_UP + xdp_count,
1767 MAX_TX_RINGS);
1768 goto out;
1769 }
1770
1771 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
1772 new_prof.num_tx_rings_p_up = channel->tx_count;
1773 new_prof.tx_ring_num[TX] = channel->tx_count * MLX4_EN_NUM_UP;
1774 new_prof.tx_ring_num[TX_XDP] = xdp_count;
1775 new_prof.rx_ring_num = channel->rx_count;
1776
1777 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
1778 if (err)
1779 goto out;
1780
1781 if (priv->port_up) {
1782 port_up = 1;
1783 mlx4_en_stop_port(dev, 1);
1784 }
1785
1786 mlx4_en_safe_replace_resources(priv, tmp);
1787
1788 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
1789 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1790
1791 if (dev->num_tc)
1792 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
1793
1794 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num[TX]);
1795 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1796
1797 if (port_up) {
1798 err = mlx4_en_start_port(dev);
1799 if (err)
1800 en_err(priv, "Failed starting port\n");
1801 }
1802
1803 err = mlx4_en_moderation_update(priv);
1804out:
1805 mutex_unlock(&mdev->state_lock);
1806 kfree(tmp);
1807 return err;
1808}
1809
1810static int mlx4_en_get_ts_info(struct net_device *dev,
1811 struct ethtool_ts_info *info)
1812{
1813 struct mlx4_en_priv *priv = netdev_priv(dev);
1814 struct mlx4_en_dev *mdev = priv->mdev;
1815 int ret;
1816
1817 ret = ethtool_op_get_ts_info(dev, info);
1818 if (ret)
1819 return ret;
1820
1821 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1822 info->so_timestamping |=
1823 SOF_TIMESTAMPING_TX_HARDWARE |
1824 SOF_TIMESTAMPING_RX_HARDWARE |
1825 SOF_TIMESTAMPING_RAW_HARDWARE;
1826
1827 info->tx_types =
1828 (1 << HWTSTAMP_TX_OFF) |
1829 (1 << HWTSTAMP_TX_ON);
1830
1831 info->rx_filters =
1832 (1 << HWTSTAMP_FILTER_NONE) |
1833 (1 << HWTSTAMP_FILTER_ALL);
1834
1835 if (mdev->ptp_clock)
1836 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1837 }
1838
1839 return ret;
1840}
1841
1842static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1843{
1844 struct mlx4_en_priv *priv = netdev_priv(dev);
1845 struct mlx4_en_dev *mdev = priv->mdev;
1846 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1847 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1848 bool phv_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_PHV);
1849 bool phv_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_PHV);
1850 int i;
1851 int ret = 0;
1852
1853 if (bf_enabled_new != bf_enabled_old) {
1854 int t;
1855
1856 if (bf_enabled_new) {
1857 bool bf_supported = true;
1858
1859 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1860 for (i = 0; i < priv->tx_ring_num[t]; i++)
1861 bf_supported &=
1862 priv->tx_ring[t][i]->bf_alloced;
1863
1864 if (!bf_supported) {
1865 en_err(priv, "BlueFlame is not supported\n");
1866 return -EINVAL;
1867 }
1868
1869 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1870 } else {
1871 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1872 }
1873
1874 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1875 for (i = 0; i < priv->tx_ring_num[t]; i++)
1876 priv->tx_ring[t][i]->bf_enabled =
1877 bf_enabled_new;
1878
1879 en_info(priv, "BlueFlame %s\n",
1880 bf_enabled_new ? "Enabled" : "Disabled");
1881 }
1882
1883 if (phv_enabled_new != phv_enabled_old) {
1884 ret = set_phv_bit(mdev->dev, priv->port, (int)phv_enabled_new);
1885 if (ret)
1886 return ret;
1887 else if (phv_enabled_new)
1888 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
1889 else
1890 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_PHV;
1891 en_info(priv, "PHV bit %s\n",
1892 phv_enabled_new ? "Enabled" : "Disabled");
1893 }
1894 return 0;
1895}
1896
1897static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1898{
1899 struct mlx4_en_priv *priv = netdev_priv(dev);
1900
1901 return priv->pflags;
1902}
1903
1904static int mlx4_en_get_tunable(struct net_device *dev,
1905 const struct ethtool_tunable *tuna,
1906 void *data)
1907{
1908 const struct mlx4_en_priv *priv = netdev_priv(dev);
1909 int ret = 0;
1910
1911 switch (tuna->id) {
1912 case ETHTOOL_TX_COPYBREAK:
1913 *(u32 *)data = priv->prof->inline_thold;
1914 break;
1915 default:
1916 ret = -EINVAL;
1917 break;
1918 }
1919
1920 return ret;
1921}
1922
1923static int mlx4_en_set_tunable(struct net_device *dev,
1924 const struct ethtool_tunable *tuna,
1925 const void *data)
1926{
1927 struct mlx4_en_priv *priv = netdev_priv(dev);
1928 int val, ret = 0;
1929
1930 switch (tuna->id) {
1931 case ETHTOOL_TX_COPYBREAK:
1932 val = *(u32 *)data;
1933 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1934 ret = -EINVAL;
1935 else
1936 priv->prof->inline_thold = val;
1937 break;
1938 default:
1939 ret = -EINVAL;
1940 break;
1941 }
1942
1943 return ret;
1944}
1945
1946static int mlx4_en_get_module_info(struct net_device *dev,
1947 struct ethtool_modinfo *modinfo)
1948{
1949 struct mlx4_en_priv *priv = netdev_priv(dev);
1950 struct mlx4_en_dev *mdev = priv->mdev;
1951 int ret;
1952 u8 data[4];
1953
1954 /* Read first 2 bytes to get Module & REV ID */
1955 ret = mlx4_get_module_info(mdev->dev, priv->port,
1956 0/*offset*/, 2/*size*/, data);
1957 if (ret < 2)
1958 return -EIO;
1959
1960 switch (data[0] /* identifier */) {
1961 case MLX4_MODULE_ID_QSFP:
1962 modinfo->type = ETH_MODULE_SFF_8436;
1963 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1964 break;
1965 case MLX4_MODULE_ID_QSFP_PLUS:
1966 if (data[1] >= 0x3) { /* revision id */
1967 modinfo->type = ETH_MODULE_SFF_8636;
1968 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1969 } else {
1970 modinfo->type = ETH_MODULE_SFF_8436;
1971 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1972 }
1973 break;
1974 case MLX4_MODULE_ID_QSFP28:
1975 modinfo->type = ETH_MODULE_SFF_8636;
1976 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1977 break;
1978 case MLX4_MODULE_ID_SFP:
1979 modinfo->type = ETH_MODULE_SFF_8472;
1980 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1981 break;
1982 default:
1983 return -ENOSYS;
1984 }
1985
1986 return 0;
1987}
1988
1989static int mlx4_en_get_module_eeprom(struct net_device *dev,
1990 struct ethtool_eeprom *ee,
1991 u8 *data)
1992{
1993 struct mlx4_en_priv *priv = netdev_priv(dev);
1994 struct mlx4_en_dev *mdev = priv->mdev;
1995 int offset = ee->offset;
1996 int i = 0, ret;
1997
1998 if (ee->len == 0)
1999 return -EINVAL;
2000
2001 memset(data, 0, ee->len);
2002
2003 while (i < ee->len) {
2004 en_dbg(DRV, priv,
2005 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
2006 i, offset, ee->len - i);
2007
2008 ret = mlx4_get_module_info(mdev->dev, priv->port,
2009 offset, ee->len - i, data + i);
2010
2011 if (!ret) /* Done reading */
2012 return 0;
2013
2014 if (ret < 0) {
2015 en_err(priv,
2016 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
2017 i, offset, ee->len - i, ret);
2018 return 0;
2019 }
2020
2021 i += ret;
2022 offset += ret;
2023 }
2024 return 0;
2025}
2026
2027static int mlx4_en_set_phys_id(struct net_device *dev,
2028 enum ethtool_phys_id_state state)
2029{
2030 int err;
2031 u16 beacon_duration;
2032 struct mlx4_en_priv *priv = netdev_priv(dev);
2033 struct mlx4_en_dev *mdev = priv->mdev;
2034
2035 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
2036 return -EOPNOTSUPP;
2037
2038 switch (state) {
2039 case ETHTOOL_ID_ACTIVE:
2040 beacon_duration = PORT_BEACON_MAX_LIMIT;
2041 break;
2042 case ETHTOOL_ID_INACTIVE:
2043 beacon_duration = 0;
2044 break;
2045 default:
2046 return -EOPNOTSUPP;
2047 }
2048
2049 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
2050 return err;
2051}
2052
2053const struct ethtool_ops mlx4_en_ethtool_ops = {
2054 .get_drvinfo = mlx4_en_get_drvinfo,
2055 .get_link_ksettings = mlx4_en_get_link_ksettings,
2056 .set_link_ksettings = mlx4_en_set_link_ksettings,
2057 .get_link = ethtool_op_get_link,
2058 .get_strings = mlx4_en_get_strings,
2059 .get_sset_count = mlx4_en_get_sset_count,
2060 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
2061 .self_test = mlx4_en_self_test,
2062 .set_phys_id = mlx4_en_set_phys_id,
2063 .get_wol = mlx4_en_get_wol,
2064 .set_wol = mlx4_en_set_wol,
2065 .get_msglevel = mlx4_en_get_msglevel,
2066 .set_msglevel = mlx4_en_set_msglevel,
2067 .get_coalesce = mlx4_en_get_coalesce,
2068 .set_coalesce = mlx4_en_set_coalesce,
2069 .get_pauseparam = mlx4_en_get_pauseparam,
2070 .set_pauseparam = mlx4_en_set_pauseparam,
2071 .get_ringparam = mlx4_en_get_ringparam,
2072 .set_ringparam = mlx4_en_set_ringparam,
2073 .get_rxnfc = mlx4_en_get_rxnfc,
2074 .set_rxnfc = mlx4_en_set_rxnfc,
2075 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
2076 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
2077 .get_rxfh = mlx4_en_get_rxfh,
2078 .set_rxfh = mlx4_en_set_rxfh,
2079 .get_channels = mlx4_en_get_channels,
2080 .set_channels = mlx4_en_set_channels,
2081 .get_ts_info = mlx4_en_get_ts_info,
2082 .set_priv_flags = mlx4_en_set_priv_flags,
2083 .get_priv_flags = mlx4_en_get_priv_flags,
2084 .get_tunable = mlx4_en_get_tunable,
2085 .set_tunable = mlx4_en_set_tunable,
2086 .get_module_info = mlx4_en_get_module_info,
2087 .get_module_eeprom = mlx4_en_get_module_eeprom
2088};
2089
2090
2091
2092
2093