1/*
  2 * Copyright (c) 2015 Endless Mobile, Inc.
  3 * Author: Carlo Caione <carlo@endlessm.com>
  4 *
  5 * Copyright (c) 2016 BayLibre, Inc.
  6 * Michael Turquette <mturquette@baylibre.com>
  7 *
  8 * This program is free software; you can redistribute it and/or modify it
  9 * under the terms and conditions of the GNU General Public License,
 10 * version 2, as published by the Free Software Foundation.
 11 *
 12 * This program is distributed in the hope it will be useful, but WITHOUT
 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 15 * more details.
 16 *
 17 * You should have received a copy of the GNU General Public License along with
 18 * this program.  If not, see <http://www.gnu.org/licenses/>.
 19 */
 20
 21#ifndef __MESON8B_H
 22#define __MESON8B_H
 23
 24/*
 25 * Clock controller register offsets
 26 *
 27 * Register offsets from the HardKernel[0] data sheet are listed in comment
 28 * blocks below. Those offsets must be multiplied by 4 before adding them to
 29 * the base address to get the right value
 30 *
 31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
 32 */
 33#define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
 34#define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
 35#define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
 36#define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
 37#define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
 38#define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
 39#define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
 40#define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
 41#define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
 42#define HHI_VID_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
 43
 44/*
 45 * CLKID index values
 46 *
 47 * These indices are entirely contrived and do not map onto the hardware.
 48 * Migrate them out of this header and into the DT header file when they need
 49 * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
 50 */
 51
 52/* CLKID_UNUSED */
 53/* CLKID_XTAL */
 54/* CLKID_PLL_FIXED */
 55/* CLKID_PLL_VID */
 56/* CLKID_PLL_SYS */
 57/* CLKID_FCLK_DIV2 */
 58/* CLKID_FCLK_DIV3 */
 59/* CLKID_FCLK_DIV4 */
 60/* CLKID_FCLK_DIV5 */
 61/* CLKID_FCLK_DIV7 */
 62/* CLKID_CLK81 */
 63/* CLKID_MALI */
 64/* CLKID_CPUCLK */
 65/* CLKID_ZERO */
 66/* CLKID_MPEG_SEL */
 67/* CLKID_MPEG_DIV */
 68#define CLKID_DDR		16
 69#define CLKID_DOS		17
 70#define CLKID_ISA		18
 71#define CLKID_PL301		19
 72#define CLKID_PERIPHS		20
 73#define CLKID_SPICC		21
 74#define CLKID_I2C		22
 75#define CLKID_SAR_ADC		23
 76#define CLKID_SMART_CARD	24
 77#define CLKID_RNG0		25
 78#define CLKID_UART0		26
 79#define CLKID_SDHC		27
 80#define CLKID_STREAM		28
 81#define CLKID_ASYNC_FIFO	29
 82#define CLKID_SDIO		30
 83#define CLKID_ABUF		31
 84#define CLKID_HIU_IFACE		32
 85#define CLKID_ASSIST_MISC	33
 86#define CLKID_SPI		34
 87#define CLKID_I2S_SPDIF		35
 88#define CLKID_ETH		36
 89#define CLKID_DEMUX		37
 90#define CLKID_AIU_GLUE		38
 91#define CLKID_IEC958		39
 92#define CLKID_I2S_OUT		40
 93#define CLKID_AMCLK		41
 94#define CLKID_AIFIFO2		42
 95#define CLKID_MIXER		43
 96#define CLKID_MIXER_IFACE	44
 97#define CLKID_ADC		45
 98#define CLKID_BLKMV		46
 99#define CLKID_AIU		47
100#define CLKID_UART1		48
101#define CLKID_G2D		49
102#define CLKID_USB0		50
103#define CLKID_USB1		51
104#define CLKID_RESET		52
105#define CLKID_NAND		53
106#define CLKID_DOS_PARSER	54
107#define CLKID_USB		55
108#define CLKID_VDIN1		56
109#define CLKID_AHB_ARB0		57
110#define CLKID_EFUSE		58
111#define CLKID_BOOT_ROM		59
112#define CLKID_AHB_DATA_BUS	60
113#define CLKID_AHB_CTRL_BUS	61
114#define CLKID_HDMI_INTR_SYNC	62
115#define CLKID_HDMI_PCLK		63
116#define CLKID_USB1_DDR_BRIDGE	64
117#define CLKID_USB0_DDR_BRIDGE	65
118#define CLKID_MMC_PCLK		66
119#define CLKID_DVIN		67
120#define CLKID_UART2		68
121#define CLKID_SANA		69
122#define CLKID_VPU_INTR		70
123#define CLKID_SEC_AHB_AHB3_BRIDGE	71
124#define CLKID_CLK81_A9		72
125#define CLKID_VCLK2_VENCI0	73
126#define CLKID_VCLK2_VENCI1	74
127#define CLKID_VCLK2_VENCP0	75
128#define CLKID_VCLK2_VENCP1	76
129#define CLKID_GCLK_VENCI_INT	77
130#define CLKID_GCLK_VENCP_INT	78
131#define CLKID_DAC_CLK		79
132#define CLKID_AOCLK_GATE	80
133#define CLKID_IEC958_GATE	81
134#define CLKID_ENC480P		82
135#define CLKID_RNG1		83
136#define CLKID_GCLK_VENCL_INT	84
137#define CLKID_VCLK2_VENCLMCC	85
138#define CLKID_VCLK2_VENCL	86
139#define CLKID_VCLK2_OTHER	87
140#define CLKID_EDP		88
141#define CLKID_AO_MEDIA_CPU	89
142#define CLKID_AO_AHB_SRAM	90
143#define CLKID_AO_AHB_BUS	91
144#define CLKID_AO_IFACE		92
145
146#define CLK_NR_CLKS		93
147
148/* include the CLKIDs that have been made part of the stable DT binding */
149#include <dt-bindings/clock/meson8b-clkc.h>
150
151#endif /* __MESON8B_H */