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1/*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/mbus.h>
16#include <linux/msi.h>
17#include <linux/slab.h>
18#include <linux/platform_device.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_gpio.h>
22#include <linux/of_pci.h>
23#include <linux/of_platform.h>
24
25/*
26 * PCIe unit register offsets.
27 */
28#define PCIE_DEV_ID_OFF 0x0000
29#define PCIE_CMD_OFF 0x0004
30#define PCIE_DEV_REV_OFF 0x0008
31#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33#define PCIE_HEADER_LOG_4_OFF 0x0128
34#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38#define PCIE_WIN5_CTRL_OFF 0x1880
39#define PCIE_WIN5_BASE_OFF 0x1884
40#define PCIE_WIN5_REMAP_OFF 0x188c
41#define PCIE_CONF_ADDR_OFF 0x18f8
42#define PCIE_CONF_ADDR_EN 0x80000000
43#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47#define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51#define PCIE_CONF_DATA_OFF 0x18fc
52#define PCIE_MASK_OFF 0x1910
53#define PCIE_MASK_ENABLE_INTS 0x0f000000
54#define PCIE_CTRL_OFF 0x1a00
55#define PCIE_CTRL_X1_MODE 0x0001
56#define PCIE_STAT_OFF 0x1a04
57#define PCIE_STAT_BUS 0xff00
58#define PCIE_STAT_DEV 0x1f0000
59#define PCIE_STAT_LINK_DOWN BIT(0)
60#define PCIE_DEBUG_CTRL 0x1a60
61#define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63/* PCI configuration space of a PCI-to-PCI bridge */
64struct mvebu_sw_pci_bridge {
65 u16 vendor;
66 u16 device;
67 u16 command;
68 u16 class;
69 u8 interface;
70 u8 revision;
71 u8 bist;
72 u8 header_type;
73 u8 latency_timer;
74 u8 cache_line_size;
75 u32 bar[2];
76 u8 primary_bus;
77 u8 secondary_bus;
78 u8 subordinate_bus;
79 u8 secondary_latency_timer;
80 u8 iobase;
81 u8 iolimit;
82 u16 secondary_status;
83 u16 membase;
84 u16 memlimit;
85 u16 iobaseupper;
86 u16 iolimitupper;
87 u8 cappointer;
88 u8 reserved1;
89 u16 reserved2;
90 u32 romaddr;
91 u8 intline;
92 u8 intpin;
93 u16 bridgectrl;
94};
95
96struct mvebu_pcie_port;
97
98/* Structure representing all PCIe interfaces */
99struct mvebu_pcie {
100 struct platform_device *pdev;
101 struct mvebu_pcie_port *ports;
102 struct msi_chip *msi;
103 struct resource io;
104 char io_name[30];
105 struct resource realio;
106 char mem_name[30];
107 struct resource mem;
108 struct resource busn;
109 int nports;
110};
111
112/* Structure representing one PCIe interface */
113struct mvebu_pcie_port {
114 char *name;
115 void __iomem *base;
116 spinlock_t conf_lock;
117 u32 port;
118 u32 lane;
119 int devfn;
120 unsigned int mem_target;
121 unsigned int mem_attr;
122 unsigned int io_target;
123 unsigned int io_attr;
124 struct clk *clk;
125 int reset_gpio;
126 int reset_active_low;
127 char *reset_name;
128 struct mvebu_sw_pci_bridge bridge;
129 struct device_node *dn;
130 struct mvebu_pcie *pcie;
131 phys_addr_t memwin_base;
132 size_t memwin_size;
133 phys_addr_t iowin_base;
134 size_t iowin_size;
135};
136
137static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
138{
139 writel(val, port->base + reg);
140}
141
142static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
143{
144 return readl(port->base + reg);
145}
146
147static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
148{
149 return port->io_target != -1 && port->io_attr != -1;
150}
151
152static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
153{
154 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
155}
156
157static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
158{
159 u32 stat;
160
161 stat = mvebu_readl(port, PCIE_STAT_OFF);
162 stat &= ~PCIE_STAT_BUS;
163 stat |= nr << 8;
164 mvebu_writel(port, stat, PCIE_STAT_OFF);
165}
166
167static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
168{
169 u32 stat;
170
171 stat = mvebu_readl(port, PCIE_STAT_OFF);
172 stat &= ~PCIE_STAT_DEV;
173 stat |= nr << 16;
174 mvebu_writel(port, stat, PCIE_STAT_OFF);
175}
176
177/*
178 * Setup PCIE BARs and Address Decode Wins:
179 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
180 * WIN[0-3] -> DRAM bank[0-3]
181 */
182static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
183{
184 const struct mbus_dram_target_info *dram;
185 u32 size;
186 int i;
187
188 dram = mv_mbus_dram_info();
189
190 /* First, disable and clear BARs and windows. */
191 for (i = 1; i < 3; i++) {
192 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
193 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
194 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
195 }
196
197 for (i = 0; i < 5; i++) {
198 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
199 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
200 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
201 }
202
203 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
204 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
205 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
206
207 /* Setup windows for DDR banks. Count total DDR size on the fly. */
208 size = 0;
209 for (i = 0; i < dram->num_cs; i++) {
210 const struct mbus_dram_window *cs = dram->cs + i;
211
212 mvebu_writel(port, cs->base & 0xffff0000,
213 PCIE_WIN04_BASE_OFF(i));
214 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
215 mvebu_writel(port,
216 ((cs->size - 1) & 0xffff0000) |
217 (cs->mbus_attr << 8) |
218 (dram->mbus_dram_target_id << 4) | 1,
219 PCIE_WIN04_CTRL_OFF(i));
220
221 size += cs->size;
222 }
223
224 /* Round up 'size' to the nearest power of two. */
225 if ((size & (size - 1)) != 0)
226 size = 1 << fls(size);
227
228 /* Setup BAR[1] to all DRAM banks. */
229 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
230 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
231 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
232 PCIE_BAR_CTRL_OFF(1));
233}
234
235static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
236{
237 u32 cmd, mask;
238
239 /* Point PCIe unit MBUS decode windows to DRAM space. */
240 mvebu_pcie_setup_wins(port);
241
242 /* Master + slave enable. */
243 cmd = mvebu_readl(port, PCIE_CMD_OFF);
244 cmd |= PCI_COMMAND_IO;
245 cmd |= PCI_COMMAND_MEMORY;
246 cmd |= PCI_COMMAND_MASTER;
247 mvebu_writel(port, cmd, PCIE_CMD_OFF);
248
249 /* Enable interrupt lines A-D. */
250 mask = mvebu_readl(port, PCIE_MASK_OFF);
251 mask |= PCIE_MASK_ENABLE_INTS;
252 mvebu_writel(port, mask, PCIE_MASK_OFF);
253}
254
255static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
256 struct pci_bus *bus,
257 u32 devfn, int where, int size, u32 *val)
258{
259 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
260 PCIE_CONF_ADDR_OFF);
261
262 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
263
264 if (size == 1)
265 *val = (*val >> (8 * (where & 3))) & 0xff;
266 else if (size == 2)
267 *val = (*val >> (8 * (where & 3))) & 0xffff;
268
269 return PCIBIOS_SUCCESSFUL;
270}
271
272static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
273 struct pci_bus *bus,
274 u32 devfn, int where, int size, u32 val)
275{
276 u32 _val, shift = 8 * (where & 3);
277
278 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
279 PCIE_CONF_ADDR_OFF);
280 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
281
282 if (size == 4)
283 _val = val;
284 else if (size == 2)
285 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
286 else if (size == 1)
287 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
288 else
289 return PCIBIOS_BAD_REGISTER_NUMBER;
290
291 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
292
293 return PCIBIOS_SUCCESSFUL;
294}
295
296/*
297 * Remove windows, starting from the largest ones to the smallest
298 * ones.
299 */
300static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
301 phys_addr_t base, size_t size)
302{
303 while (size) {
304 size_t sz = 1 << (fls(size) - 1);
305
306 mvebu_mbus_del_window(base, sz);
307 base += sz;
308 size -= sz;
309 }
310}
311
312/*
313 * MBus windows can only have a power of two size, but PCI BARs do not
314 * have this constraint. Therefore, we have to split the PCI BAR into
315 * areas each having a power of two size. We start from the largest
316 * one (i.e highest order bit set in the size).
317 */
318static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
319 unsigned int target, unsigned int attribute,
320 phys_addr_t base, size_t size,
321 phys_addr_t remap)
322{
323 size_t size_mapped = 0;
324
325 while (size) {
326 size_t sz = 1 << (fls(size) - 1);
327 int ret;
328
329 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
330 sz, remap);
331 if (ret) {
332 dev_err(&port->pcie->pdev->dev,
333 "Could not create MBus window at 0x%x, size 0x%x: %d\n",
334 base, sz, ret);
335 mvebu_pcie_del_windows(port, base - size_mapped,
336 size_mapped);
337 return;
338 }
339
340 size -= sz;
341 size_mapped += sz;
342 base += sz;
343 if (remap != MVEBU_MBUS_NO_REMAP)
344 remap += sz;
345 }
346}
347
348static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
349{
350 phys_addr_t iobase;
351
352 /* Are the new iobase/iolimit values invalid? */
353 if (port->bridge.iolimit < port->bridge.iobase ||
354 port->bridge.iolimitupper < port->bridge.iobaseupper ||
355 !(port->bridge.command & PCI_COMMAND_IO)) {
356
357 /* If a window was configured, remove it */
358 if (port->iowin_base) {
359 mvebu_pcie_del_windows(port, port->iowin_base,
360 port->iowin_size);
361 port->iowin_base = 0;
362 port->iowin_size = 0;
363 }
364
365 return;
366 }
367
368 if (!mvebu_has_ioport(port)) {
369 dev_WARN(&port->pcie->pdev->dev,
370 "Attempt to set IO when IO is disabled\n");
371 return;
372 }
373
374 /*
375 * We read the PCI-to-PCI bridge emulated registers, and
376 * calculate the base address and size of the address decoding
377 * window to setup, according to the PCI-to-PCI bridge
378 * specifications. iobase is the bus address, port->iowin_base
379 * is the CPU address.
380 */
381 iobase = ((port->bridge.iobase & 0xF0) << 8) |
382 (port->bridge.iobaseupper << 16);
383 port->iowin_base = port->pcie->io.start + iobase;
384 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
385 (port->bridge.iolimitupper << 16)) -
386 iobase) + 1;
387
388 mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
389 port->iowin_base, port->iowin_size,
390 iobase);
391}
392
393static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
394{
395 /* Are the new membase/memlimit values invalid? */
396 if (port->bridge.memlimit < port->bridge.membase ||
397 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
398
399 /* If a window was configured, remove it */
400 if (port->memwin_base) {
401 mvebu_pcie_del_windows(port, port->memwin_base,
402 port->memwin_size);
403 port->memwin_base = 0;
404 port->memwin_size = 0;
405 }
406
407 return;
408 }
409
410 /*
411 * We read the PCI-to-PCI bridge emulated registers, and
412 * calculate the base address and size of the address decoding
413 * window to setup, according to the PCI-to-PCI bridge
414 * specifications.
415 */
416 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
417 port->memwin_size =
418 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
419 port->memwin_base + 1;
420
421 mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
422 port->memwin_base, port->memwin_size,
423 MVEBU_MBUS_NO_REMAP);
424}
425
426/*
427 * Initialize the configuration space of the PCI-to-PCI bridge
428 * associated with the given PCIe interface.
429 */
430static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
431{
432 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
433
434 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
435
436 bridge->class = PCI_CLASS_BRIDGE_PCI;
437 bridge->vendor = PCI_VENDOR_ID_MARVELL;
438 bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
439 bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
440 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
441 bridge->cache_line_size = 0x10;
442
443 /* We support 32 bits I/O addressing */
444 bridge->iobase = PCI_IO_RANGE_TYPE_32;
445 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
446}
447
448/*
449 * Read the configuration space of the PCI-to-PCI bridge associated to
450 * the given PCIe interface.
451 */
452static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
453 unsigned int where, int size, u32 *value)
454{
455 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
456
457 switch (where & ~3) {
458 case PCI_VENDOR_ID:
459 *value = bridge->device << 16 | bridge->vendor;
460 break;
461
462 case PCI_COMMAND:
463 *value = bridge->command;
464 break;
465
466 case PCI_CLASS_REVISION:
467 *value = bridge->class << 16 | bridge->interface << 8 |
468 bridge->revision;
469 break;
470
471 case PCI_CACHE_LINE_SIZE:
472 *value = bridge->bist << 24 | bridge->header_type << 16 |
473 bridge->latency_timer << 8 | bridge->cache_line_size;
474 break;
475
476 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
477 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
478 break;
479
480 case PCI_PRIMARY_BUS:
481 *value = (bridge->secondary_latency_timer << 24 |
482 bridge->subordinate_bus << 16 |
483 bridge->secondary_bus << 8 |
484 bridge->primary_bus);
485 break;
486
487 case PCI_IO_BASE:
488 if (!mvebu_has_ioport(port))
489 *value = bridge->secondary_status << 16;
490 else
491 *value = (bridge->secondary_status << 16 |
492 bridge->iolimit << 8 |
493 bridge->iobase);
494 break;
495
496 case PCI_MEMORY_BASE:
497 *value = (bridge->memlimit << 16 | bridge->membase);
498 break;
499
500 case PCI_PREF_MEMORY_BASE:
501 *value = 0;
502 break;
503
504 case PCI_IO_BASE_UPPER16:
505 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
506 break;
507
508 case PCI_ROM_ADDRESS1:
509 *value = 0;
510 break;
511
512 case PCI_INTERRUPT_LINE:
513 /* LINE PIN MIN_GNT MAX_LAT */
514 *value = 0;
515 break;
516
517 default:
518 *value = 0xffffffff;
519 return PCIBIOS_BAD_REGISTER_NUMBER;
520 }
521
522 if (size == 2)
523 *value = (*value >> (8 * (where & 3))) & 0xffff;
524 else if (size == 1)
525 *value = (*value >> (8 * (where & 3))) & 0xff;
526
527 return PCIBIOS_SUCCESSFUL;
528}
529
530/* Write to the PCI-to-PCI bridge configuration space */
531static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
532 unsigned int where, int size, u32 value)
533{
534 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
535 u32 mask, reg;
536 int err;
537
538 if (size == 4)
539 mask = 0x0;
540 else if (size == 2)
541 mask = ~(0xffff << ((where & 3) * 8));
542 else if (size == 1)
543 mask = ~(0xff << ((where & 3) * 8));
544 else
545 return PCIBIOS_BAD_REGISTER_NUMBER;
546
547 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
548 if (err)
549 return err;
550
551 value = (reg & mask) | value << ((where & 3) * 8);
552
553 switch (where & ~3) {
554 case PCI_COMMAND:
555 {
556 u32 old = bridge->command;
557
558 if (!mvebu_has_ioport(port))
559 value &= ~PCI_COMMAND_IO;
560
561 bridge->command = value & 0xffff;
562 if ((old ^ bridge->command) & PCI_COMMAND_IO)
563 mvebu_pcie_handle_iobase_change(port);
564 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
565 mvebu_pcie_handle_membase_change(port);
566 break;
567 }
568
569 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
570 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
571 break;
572
573 case PCI_IO_BASE:
574 /*
575 * We also keep bit 1 set, it is a read-only bit that
576 * indicates we support 32 bits addressing for the
577 * I/O
578 */
579 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
580 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
581 mvebu_pcie_handle_iobase_change(port);
582 break;
583
584 case PCI_MEMORY_BASE:
585 bridge->membase = value & 0xffff;
586 bridge->memlimit = value >> 16;
587 mvebu_pcie_handle_membase_change(port);
588 break;
589
590 case PCI_IO_BASE_UPPER16:
591 bridge->iobaseupper = value & 0xffff;
592 bridge->iolimitupper = value >> 16;
593 mvebu_pcie_handle_iobase_change(port);
594 break;
595
596 case PCI_PRIMARY_BUS:
597 bridge->primary_bus = value & 0xff;
598 bridge->secondary_bus = (value >> 8) & 0xff;
599 bridge->subordinate_bus = (value >> 16) & 0xff;
600 bridge->secondary_latency_timer = (value >> 24) & 0xff;
601 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
602 break;
603
604 default:
605 break;
606 }
607
608 return PCIBIOS_SUCCESSFUL;
609}
610
611static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
612{
613 return sys->private_data;
614}
615
616static struct mvebu_pcie_port *
617mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
618 int devfn)
619{
620 int i;
621
622 for (i = 0; i < pcie->nports; i++) {
623 struct mvebu_pcie_port *port = &pcie->ports[i];
624 if (bus->number == 0 && port->devfn == devfn)
625 return port;
626 if (bus->number != 0 &&
627 bus->number >= port->bridge.secondary_bus &&
628 bus->number <= port->bridge.subordinate_bus)
629 return port;
630 }
631
632 return NULL;
633}
634
635/* PCI configuration space write function */
636static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
637 int where, int size, u32 val)
638{
639 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
640 struct mvebu_pcie_port *port;
641 unsigned long flags;
642 int ret;
643
644 port = mvebu_pcie_find_port(pcie, bus, devfn);
645 if (!port)
646 return PCIBIOS_DEVICE_NOT_FOUND;
647
648 /* Access the emulated PCI-to-PCI bridge */
649 if (bus->number == 0)
650 return mvebu_sw_pci_bridge_write(port, where, size, val);
651
652 if (!mvebu_pcie_link_up(port))
653 return PCIBIOS_DEVICE_NOT_FOUND;
654
655 /*
656 * On the secondary bus, we don't want to expose any other
657 * device than the device physically connected in the PCIe
658 * slot, visible in slot 0. In slot 1, there's a special
659 * Marvell device that only makes sense when the Armada is
660 * used as a PCIe endpoint.
661 */
662 if (bus->number == port->bridge.secondary_bus &&
663 PCI_SLOT(devfn) != 0)
664 return PCIBIOS_DEVICE_NOT_FOUND;
665
666 /* Access the real PCIe interface */
667 spin_lock_irqsave(&port->conf_lock, flags);
668 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
669 where, size, val);
670 spin_unlock_irqrestore(&port->conf_lock, flags);
671
672 return ret;
673}
674
675/* PCI configuration space read function */
676static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
677 int size, u32 *val)
678{
679 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
680 struct mvebu_pcie_port *port;
681 unsigned long flags;
682 int ret;
683
684 port = mvebu_pcie_find_port(pcie, bus, devfn);
685 if (!port) {
686 *val = 0xffffffff;
687 return PCIBIOS_DEVICE_NOT_FOUND;
688 }
689
690 /* Access the emulated PCI-to-PCI bridge */
691 if (bus->number == 0)
692 return mvebu_sw_pci_bridge_read(port, where, size, val);
693
694 if (!mvebu_pcie_link_up(port)) {
695 *val = 0xffffffff;
696 return PCIBIOS_DEVICE_NOT_FOUND;
697 }
698
699 /*
700 * On the secondary bus, we don't want to expose any other
701 * device than the device physically connected in the PCIe
702 * slot, visible in slot 0. In slot 1, there's a special
703 * Marvell device that only makes sense when the Armada is
704 * used as a PCIe endpoint.
705 */
706 if (bus->number == port->bridge.secondary_bus &&
707 PCI_SLOT(devfn) != 0) {
708 *val = 0xffffffff;
709 return PCIBIOS_DEVICE_NOT_FOUND;
710 }
711
712 /* Access the real PCIe interface */
713 spin_lock_irqsave(&port->conf_lock, flags);
714 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
715 where, size, val);
716 spin_unlock_irqrestore(&port->conf_lock, flags);
717
718 return ret;
719}
720
721static struct pci_ops mvebu_pcie_ops = {
722 .read = mvebu_pcie_rd_conf,
723 .write = mvebu_pcie_wr_conf,
724};
725
726static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
727{
728 struct mvebu_pcie *pcie = sys_to_pcie(sys);
729 int i;
730 int domain = 0;
731
732#ifdef CONFIG_PCI_DOMAINS
733 domain = sys->domain;
734#endif
735
736 snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
737 domain);
738 pcie->mem.name = pcie->mem_name;
739
740 snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
741 pcie->realio.name = pcie->io_name;
742
743 if (request_resource(&iomem_resource, &pcie->mem))
744 return 0;
745
746 if (resource_size(&pcie->realio) != 0) {
747 if (request_resource(&ioport_resource, &pcie->realio)) {
748 release_resource(&pcie->mem);
749 return 0;
750 }
751 pci_add_resource_offset(&sys->resources, &pcie->realio,
752 sys->io_offset);
753 }
754 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
755 pci_add_resource(&sys->resources, &pcie->busn);
756
757 for (i = 0; i < pcie->nports; i++) {
758 struct mvebu_pcie_port *port = &pcie->ports[i];
759 if (!port->base)
760 continue;
761 mvebu_pcie_setup_hw(port);
762 }
763
764 return 1;
765}
766
767static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
768{
769 struct mvebu_pcie *pcie = sys_to_pcie(sys);
770 struct pci_bus *bus;
771
772 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
773 &mvebu_pcie_ops, sys, &sys->resources);
774 if (!bus)
775 return NULL;
776
777 pci_scan_child_bus(bus);
778
779 return bus;
780}
781
782static void mvebu_pcie_add_bus(struct pci_bus *bus)
783{
784 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
785 bus->msi = pcie->msi;
786}
787
788static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
789 const struct resource *res,
790 resource_size_t start,
791 resource_size_t size,
792 resource_size_t align)
793{
794 if (dev->bus->number != 0)
795 return start;
796
797 /*
798 * On the PCI-to-PCI bridge side, the I/O windows must have at
799 * least a 64 KB size and the memory windows must have at
800 * least a 1 MB size. Moreover, MBus windows need to have a
801 * base address aligned on their size, and their size must be
802 * a power of two. This means that if the BAR doesn't have a
803 * power of two size, several MBus windows will actually be
804 * created. We need to ensure that the biggest MBus window
805 * (which will be the first one) is aligned on its size, which
806 * explains the rounddown_pow_of_two() being done here.
807 */
808 if (res->flags & IORESOURCE_IO)
809 return round_up(start, max_t(resource_size_t, SZ_64K,
810 rounddown_pow_of_two(size)));
811 else if (res->flags & IORESOURCE_MEM)
812 return round_up(start, max_t(resource_size_t, SZ_1M,
813 rounddown_pow_of_two(size)));
814 else
815 return start;
816}
817
818static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
819{
820 struct hw_pci hw;
821
822 memset(&hw, 0, sizeof(hw));
823
824 hw.nr_controllers = 1;
825 hw.private_data = (void **)&pcie;
826 hw.setup = mvebu_pcie_setup;
827 hw.scan = mvebu_pcie_scan_bus;
828 hw.map_irq = of_irq_parse_and_map_pci;
829 hw.ops = &mvebu_pcie_ops;
830 hw.align_resource = mvebu_pcie_align_resource;
831 hw.add_bus = mvebu_pcie_add_bus;
832
833 pci_common_init(&hw);
834}
835
836/*
837 * Looks up the list of register addresses encoded into the reg =
838 * <...> property for one that matches the given port/lane. Once
839 * found, maps it.
840 */
841static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
842 struct device_node *np, struct mvebu_pcie_port *port)
843{
844 struct resource regs;
845 int ret = 0;
846
847 ret = of_address_to_resource(np, 0, ®s);
848 if (ret)
849 return ERR_PTR(ret);
850
851 return devm_ioremap_resource(&pdev->dev, ®s);
852}
853
854#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
855#define DT_TYPE_IO 0x1
856#define DT_TYPE_MEM32 0x2
857#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
858#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
859
860static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
861 unsigned long type,
862 unsigned int *tgt,
863 unsigned int *attr)
864{
865 const int na = 3, ns = 2;
866 const __be32 *range;
867 int rlen, nranges, rangesz, pna, i;
868
869 *tgt = -1;
870 *attr = -1;
871
872 range = of_get_property(np, "ranges", &rlen);
873 if (!range)
874 return -EINVAL;
875
876 pna = of_n_addr_cells(np);
877 rangesz = pna + na + ns;
878 nranges = rlen / sizeof(__be32) / rangesz;
879
880 for (i = 0; i < nranges; i++) {
881 u32 flags = of_read_number(range, 1);
882 u32 slot = of_read_number(range + 1, 1);
883 u64 cpuaddr = of_read_number(range + na, pna);
884 unsigned long rtype;
885
886 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
887 rtype = IORESOURCE_IO;
888 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
889 rtype = IORESOURCE_MEM;
890
891 if (slot == PCI_SLOT(devfn) && type == rtype) {
892 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
893 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
894 return 0;
895 }
896
897 range += rangesz;
898 }
899
900 return -ENOENT;
901}
902
903static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
904{
905 struct device_node *msi_node;
906
907 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
908 "msi-parent", 0);
909 if (!msi_node)
910 return;
911
912 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
913
914 if (pcie->msi)
915 pcie->msi->dev = &pcie->pdev->dev;
916}
917
918static int mvebu_pcie_probe(struct platform_device *pdev)
919{
920 struct mvebu_pcie *pcie;
921 struct device_node *np = pdev->dev.of_node;
922 struct device_node *child;
923 int i, ret;
924
925 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
926 GFP_KERNEL);
927 if (!pcie)
928 return -ENOMEM;
929
930 pcie->pdev = pdev;
931 platform_set_drvdata(pdev, pcie);
932
933 /* Get the PCIe memory and I/O aperture */
934 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
935 if (resource_size(&pcie->mem) == 0) {
936 dev_err(&pdev->dev, "invalid memory aperture size\n");
937 return -EINVAL;
938 }
939
940 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
941
942 if (resource_size(&pcie->io) != 0) {
943 pcie->realio.flags = pcie->io.flags;
944 pcie->realio.start = PCIBIOS_MIN_IO;
945 pcie->realio.end = min_t(resource_size_t,
946 IO_SPACE_LIMIT,
947 resource_size(&pcie->io));
948 } else
949 pcie->realio = pcie->io;
950
951 /* Get the bus range */
952 ret = of_pci_parse_bus_range(np, &pcie->busn);
953 if (ret) {
954 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
955 ret);
956 return ret;
957 }
958
959 i = 0;
960 for_each_child_of_node(pdev->dev.of_node, child) {
961 if (!of_device_is_available(child))
962 continue;
963 i++;
964 }
965
966 pcie->ports = devm_kzalloc(&pdev->dev, i *
967 sizeof(struct mvebu_pcie_port),
968 GFP_KERNEL);
969 if (!pcie->ports)
970 return -ENOMEM;
971
972 i = 0;
973 for_each_child_of_node(pdev->dev.of_node, child) {
974 struct mvebu_pcie_port *port = &pcie->ports[i];
975 enum of_gpio_flags flags;
976
977 if (!of_device_is_available(child))
978 continue;
979
980 port->pcie = pcie;
981
982 if (of_property_read_u32(child, "marvell,pcie-port",
983 &port->port)) {
984 dev_warn(&pdev->dev,
985 "ignoring PCIe DT node, missing pcie-port property\n");
986 continue;
987 }
988
989 if (of_property_read_u32(child, "marvell,pcie-lane",
990 &port->lane))
991 port->lane = 0;
992
993 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
994 port->port, port->lane);
995
996 port->devfn = of_pci_get_devfn(child);
997 if (port->devfn < 0)
998 continue;
999
1000 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
1001 &port->mem_target, &port->mem_attr);
1002 if (ret < 0) {
1003 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
1004 port->port, port->lane);
1005 continue;
1006 }
1007
1008 if (resource_size(&pcie->io) != 0)
1009 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
1010 &port->io_target, &port->io_attr);
1011 else {
1012 port->io_target = -1;
1013 port->io_attr = -1;
1014 }
1015
1016 port->reset_gpio = of_get_named_gpio_flags(child,
1017 "reset-gpios", 0, &flags);
1018 if (gpio_is_valid(port->reset_gpio)) {
1019 u32 reset_udelay = 20000;
1020
1021 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
1022 port->reset_name = kasprintf(GFP_KERNEL,
1023 "pcie%d.%d-reset", port->port, port->lane);
1024 of_property_read_u32(child, "reset-delay-us",
1025 &reset_udelay);
1026
1027 ret = devm_gpio_request_one(&pdev->dev,
1028 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
1029 if (ret) {
1030 if (ret == -EPROBE_DEFER)
1031 return ret;
1032 continue;
1033 }
1034
1035 gpio_set_value(port->reset_gpio,
1036 (port->reset_active_low) ? 1 : 0);
1037 msleep(reset_udelay/1000);
1038 }
1039
1040 port->clk = of_clk_get_by_name(child, NULL);
1041 if (IS_ERR(port->clk)) {
1042 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
1043 port->port, port->lane);
1044 continue;
1045 }
1046
1047 ret = clk_prepare_enable(port->clk);
1048 if (ret)
1049 continue;
1050
1051 port->base = mvebu_pcie_map_registers(pdev, child, port);
1052 if (IS_ERR(port->base)) {
1053 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
1054 port->port, port->lane);
1055 port->base = NULL;
1056 clk_disable_unprepare(port->clk);
1057 continue;
1058 }
1059
1060 mvebu_pcie_set_local_dev_nr(port, 1);
1061
1062 port->dn = child;
1063 spin_lock_init(&port->conf_lock);
1064 mvebu_sw_pci_bridge_init(port);
1065 i++;
1066 }
1067
1068 pcie->nports = i;
1069
1070 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
1071 pci_ioremap_io(i, pcie->io.start + i);
1072
1073 mvebu_pcie_msi_enable(pcie);
1074 mvebu_pcie_enable(pcie);
1075
1076 return 0;
1077}
1078
1079static const struct of_device_id mvebu_pcie_of_match_table[] = {
1080 { .compatible = "marvell,armada-xp-pcie", },
1081 { .compatible = "marvell,armada-370-pcie", },
1082 { .compatible = "marvell,dove-pcie", },
1083 { .compatible = "marvell,kirkwood-pcie", },
1084 {},
1085};
1086MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1087
1088static struct platform_driver mvebu_pcie_driver = {
1089 .driver = {
1090 .owner = THIS_MODULE,
1091 .name = "mvebu-pcie",
1092 .of_match_table = mvebu_pcie_of_match_table,
1093 /* driver unloading/unbinding currently not supported */
1094 .suppress_bind_attrs = true,
1095 },
1096 .probe = mvebu_pcie_probe,
1097};
1098module_platform_driver(mvebu_pcie_driver);
1099
1100MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1101MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1102MODULE_LICENSE("GPLv2");