1/*
  2 * System timer for CSR SiRFprimaII
  3 *
  4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5 *
  6 * Licensed under GPLv2 or later.
  7 */
  8
  9#include <linux/kernel.h>
 10#include <linux/interrupt.h>
 11#include <linux/clockchips.h>
 12#include <linux/clocksource.h>
 13#include <linux/cpu.h>
 14#include <linux/bitops.h>
 15#include <linux/irq.h>
 16#include <linux/clk.h>
 17#include <linux/slab.h>
 18#include <linux/of.h>
 19#include <linux/of_irq.h>
 20#include <linux/of_address.h>
 21#include <linux/sched_clock.h>
 22
 23#define MARCO_CLOCK_FREQ 1000000
 24
 25#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
 26#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
 27#define SIRFSOC_TIMER_MATCH_0				0x0018
 28#define SIRFSOC_TIMER_MATCH_1				0x001c
 29#define SIRFSOC_TIMER_COUNTER_0				0x0048
 30#define SIRFSOC_TIMER_COUNTER_1				0x004c
 31#define SIRFSOC_TIMER_INTR_STATUS			0x0060
 32#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
 33#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
 34#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
 35#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
 36#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
 37#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
 38#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
 39#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080
 40
 41#define SIRFSOC_TIMER_REG_CNT 6
 42
 43static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
 44	SIRFSOC_TIMER_WATCHDOG_EN,
 45	SIRFSOC_TIMER_32COUNTER_0_CTRL,
 46	SIRFSOC_TIMER_32COUNTER_1_CTRL,
 47	SIRFSOC_TIMER_64COUNTER_CTRL,
 48	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
 49	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
 50};
 51
 52static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
 53
 54static void __iomem *sirfsoc_timer_base;
 55
 56/* disable count and interrupt */
 57static inline void sirfsoc_timer_count_disable(int idx)
 58{
 59	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
 60		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
 61}
 62
 63/* enable count and interrupt */
 64static inline void sirfsoc_timer_count_enable(int idx)
 65{
 66	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
 67		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
 68}
 69
 70/* timer interrupt handler */
 71static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
 72{
 73	struct clock_event_device *ce = dev_id;
 74	int cpu = smp_processor_id();
 75
 76	/* clear timer interrupt */
 77	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
 78
 79	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
 80		sirfsoc_timer_count_disable(cpu);
 81
 82	ce->event_handler(ce);
 83
 84	return IRQ_HANDLED;
 85}
 86
 87/* read 64-bit timer counter */
 88static cycle_t sirfsoc_timer_read(struct clocksource *cs)
 89{
 90	u64 cycles;
 91
 92	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
 93			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
 94
 95	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
 96	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
 97
 98	return cycles;
 99}
100
101static int sirfsoc_timer_set_next_event(unsigned long delta,
102	struct clock_event_device *ce)
103{
104	int cpu = smp_processor_id();
105
106	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
107		4 * cpu);
108	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
109		4 * cpu);
110
111	/* enable the tick */
112	sirfsoc_timer_count_enable(cpu);
113
114	return 0;
115}
116
117static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
118	struct clock_event_device *ce)
119{
120	switch (mode) {
121	case CLOCK_EVT_MODE_ONESHOT:
122		/* enable in set_next_event */
123		break;
124	default:
125		break;
126	}
127
128	sirfsoc_timer_count_disable(smp_processor_id());
129}
130
131static void sirfsoc_clocksource_suspend(struct clocksource *cs)
132{
133	int i;
134
135	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
136		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
137}
138
139static void sirfsoc_clocksource_resume(struct clocksource *cs)
140{
141	int i;
142
143	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
144		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
145
146	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
147		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
148	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
149		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
150
151	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
152		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
153}
154
155static struct clock_event_device __percpu *sirfsoc_clockevent;
156
157static struct clocksource sirfsoc_clocksource = {
158	.name = "sirfsoc_clocksource",
159	.rating = 200,
160	.mask = CLOCKSOURCE_MASK(64),
161	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
162	.read = sirfsoc_timer_read,
163	.suspend = sirfsoc_clocksource_suspend,
164	.resume = sirfsoc_clocksource_resume,
165};
166
167static struct irqaction sirfsoc_timer_irq = {
168	.name = "sirfsoc_timer0",
169	.flags = IRQF_TIMER | IRQF_NOBALANCING,
170	.handler = sirfsoc_timer_interrupt,
171};
172
173static struct irqaction sirfsoc_timer1_irq = {
174	.name = "sirfsoc_timer1",
175	.flags = IRQF_TIMER | IRQF_NOBALANCING,
176	.handler = sirfsoc_timer_interrupt,
177};
178
179static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
180{
181	int cpu = smp_processor_id();
182	struct irqaction *action;
183
184	if (cpu == 0)
185		action = &sirfsoc_timer_irq;
186	else
187		action = &sirfsoc_timer1_irq;
188
189	ce->irq = action->irq;
190	ce->name = "local_timer";
191	ce->features = CLOCK_EVT_FEAT_ONESHOT;
192	ce->rating = 200;
193	ce->set_mode = sirfsoc_timer_set_mode;
194	ce->set_next_event = sirfsoc_timer_set_next_event;
195	clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60);
196	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
197	ce->min_delta_ns = clockevent_delta2ns(2, ce);
198	ce->cpumask = cpumask_of(cpu);
199
200	action->dev_id = ce;
201	BUG_ON(setup_irq(ce->irq, action));
202	irq_force_affinity(action->irq, cpumask_of(cpu));
203
204	clockevents_register_device(ce);
205	return 0;
206}
207
208static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
209{
210	int cpu = smp_processor_id();
211
212	sirfsoc_timer_count_disable(1);
213
214	if (cpu == 0)
215		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
216	else
217		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
218}
219
220static int sirfsoc_cpu_notify(struct notifier_block *self,
221			      unsigned long action, void *hcpu)
222{
223	/*
224	 * Grab cpu pointer in each case to avoid spurious
225	 * preemptible warnings
226	 */
227	switch (action & ~CPU_TASKS_FROZEN) {
228	case CPU_STARTING:
229		sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
230		break;
231	case CPU_DYING:
232		sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
233		break;
234	}
235
236	return NOTIFY_OK;
237}
238
239static struct notifier_block sirfsoc_cpu_nb = {
240	.notifier_call = sirfsoc_cpu_notify,
241};
242
243static void __init sirfsoc_clockevent_init(void)
244{
245	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
246	BUG_ON(!sirfsoc_clockevent);
247
248	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
249
250	/* Immediately configure the timer on the boot CPU */
251	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
252}
253
254/* initialize the kernel jiffy timer source */
255static void __init sirfsoc_marco_timer_init(void)
256{
257	unsigned long rate;
258	u32 timer_div;
259	struct clk *clk;
260
261	/* timer's input clock is io clock */
262	clk = clk_get_sys("io", NULL);
263
264	BUG_ON(IS_ERR(clk));
265	rate = clk_get_rate(clk);
266
267	BUG_ON(rate < MARCO_CLOCK_FREQ);
268	BUG_ON(rate % MARCO_CLOCK_FREQ);
269
270	/* Initialize the timer dividers */
271	timer_div = rate / MARCO_CLOCK_FREQ - 1;
272	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
273	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
274	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
275
276	/* Initialize timer counters to 0 */
277	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
278	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
279	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
280		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
281	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
282	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
283
284	/* Clear all interrupts */
285	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
286
287	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ));
288
289	sirfsoc_clockevent_init();
290}
291
292static void __init sirfsoc_of_timer_init(struct device_node *np)
293{
294	sirfsoc_timer_base = of_iomap(np, 0);
295	if (!sirfsoc_timer_base)
296		panic("unable to map timer cpu registers\n");
297
298	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
299	if (!sirfsoc_timer_irq.irq)
300		panic("No irq passed for timer0 via DT\n");
301
302	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
303	if (!sirfsoc_timer1_irq.irq)
304		panic("No irq passed for timer1 via DT\n");
305
306	sirfsoc_marco_timer_init();
307}
308CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );