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1/*
2 * Copyright (C) 2008 STMicroelectronics
3 * Copyright (C) 2010 Alessandro Rubini
4 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/io.h>
14#include <linux/clockchips.h>
15#include <linux/clocksource.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/of_platform.h>
19#include <linux/clk.h>
20#include <linux/jiffies.h>
21#include <linux/delay.h>
22#include <linux/err.h>
23#include <linux/sched_clock.h>
24#include <asm/mach/time.h>
25
26/*
27 * The MTU device hosts four different counters, with 4 set of
28 * registers. These are register names.
29 */
30
31#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
32#define MTU_RIS 0x04 /* Raw interrupt status */
33#define MTU_MIS 0x08 /* Masked interrupt status */
34#define MTU_ICR 0x0C /* Interrupt clear register */
35
36/* per-timer registers take 0..3 as argument */
37#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
38#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
39#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
40#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
41
42/* bits for the control register */
43#define MTU_CRn_ENA 0x80
44#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
45#define MTU_CRn_PRESCALE_MASK 0x0c
46#define MTU_CRn_PRESCALE_1 0x00
47#define MTU_CRn_PRESCALE_16 0x04
48#define MTU_CRn_PRESCALE_256 0x08
49#define MTU_CRn_32BITS 0x02
50#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
51
52/* Other registers are usual amba/primecell registers, currently not used */
53#define MTU_ITCR 0xff0
54#define MTU_ITOP 0xff4
55
56#define MTU_PERIPH_ID0 0xfe0
57#define MTU_PERIPH_ID1 0xfe4
58#define MTU_PERIPH_ID2 0xfe8
59#define MTU_PERIPH_ID3 0xfeC
60
61#define MTU_PCELL0 0xff0
62#define MTU_PCELL1 0xff4
63#define MTU_PCELL2 0xff8
64#define MTU_PCELL3 0xffC
65
66static void __iomem *mtu_base;
67static bool clkevt_periodic;
68static u32 clk_prescale;
69static u32 nmdk_cycle; /* write-once */
70static struct delay_timer mtu_delay_timer;
71
72#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
73/*
74 * Override the global weak sched_clock symbol with this
75 * local implementation which uses the clocksource to get some
76 * better resolution when scheduling the kernel.
77 */
78static u64 notrace nomadik_read_sched_clock(void)
79{
80 if (unlikely(!mtu_base))
81 return 0;
82
83 return -readl(mtu_base + MTU_VAL(0));
84}
85#endif
86
87static unsigned long nmdk_timer_read_current_timer(void)
88{
89 return ~readl_relaxed(mtu_base + MTU_VAL(0));
90}
91
92/* Clockevent device: use one-shot mode */
93static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
94{
95 writel(1 << 1, mtu_base + MTU_IMSC);
96 writel(evt, mtu_base + MTU_LR(1));
97 /* Load highest value, enable device, enable interrupts */
98 writel(MTU_CRn_ONESHOT | clk_prescale |
99 MTU_CRn_32BITS | MTU_CRn_ENA,
100 mtu_base + MTU_CR(1));
101
102 return 0;
103}
104
105static void nmdk_clkevt_reset(void)
106{
107 if (clkevt_periodic) {
108 /* Timer: configure load and background-load, and fire it up */
109 writel(nmdk_cycle, mtu_base + MTU_LR(1));
110 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
111
112 writel(MTU_CRn_PERIODIC | clk_prescale |
113 MTU_CRn_32BITS | MTU_CRn_ENA,
114 mtu_base + MTU_CR(1));
115 writel(1 << 1, mtu_base + MTU_IMSC);
116 } else {
117 /* Generate an interrupt to start the clockevent again */
118 (void) nmdk_clkevt_next(nmdk_cycle, NULL);
119 }
120}
121
122static void nmdk_clkevt_mode(enum clock_event_mode mode,
123 struct clock_event_device *dev)
124{
125 switch (mode) {
126 case CLOCK_EVT_MODE_PERIODIC:
127 clkevt_periodic = true;
128 nmdk_clkevt_reset();
129 break;
130 case CLOCK_EVT_MODE_ONESHOT:
131 clkevt_periodic = false;
132 break;
133 case CLOCK_EVT_MODE_SHUTDOWN:
134 case CLOCK_EVT_MODE_UNUSED:
135 writel(0, mtu_base + MTU_IMSC);
136 /* disable timer */
137 writel(0, mtu_base + MTU_CR(1));
138 /* load some high default value */
139 writel(0xffffffff, mtu_base + MTU_LR(1));
140 break;
141 case CLOCK_EVT_MODE_RESUME:
142 break;
143 }
144}
145
146static void nmdk_clksrc_reset(void)
147{
148 /* Disable */
149 writel(0, mtu_base + MTU_CR(0));
150
151 /* ClockSource: configure load and background-load, and fire it up */
152 writel(nmdk_cycle, mtu_base + MTU_LR(0));
153 writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
154
155 writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
156 mtu_base + MTU_CR(0));
157}
158
159static void nmdk_clkevt_resume(struct clock_event_device *cedev)
160{
161 nmdk_clkevt_reset();
162 nmdk_clksrc_reset();
163}
164
165static struct clock_event_device nmdk_clkevt = {
166 .name = "mtu_1",
167 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC |
168 CLOCK_EVT_FEAT_DYNIRQ,
169 .rating = 200,
170 .set_mode = nmdk_clkevt_mode,
171 .set_next_event = nmdk_clkevt_next,
172 .resume = nmdk_clkevt_resume,
173};
174
175/*
176 * IRQ Handler for timer 1 of the MTU block.
177 */
178static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
179{
180 struct clock_event_device *evdev = dev_id;
181
182 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
183 evdev->event_handler(evdev);
184 return IRQ_HANDLED;
185}
186
187static struct irqaction nmdk_timer_irq = {
188 .name = "Nomadik Timer Tick",
189 .flags = IRQF_TIMER,
190 .handler = nmdk_timer_interrupt,
191 .dev_id = &nmdk_clkevt,
192};
193
194static void __init nmdk_timer_init(void __iomem *base, int irq,
195 struct clk *pclk, struct clk *clk)
196{
197 unsigned long rate;
198
199 mtu_base = base;
200
201 BUG_ON(clk_prepare_enable(pclk));
202 BUG_ON(clk_prepare_enable(clk));
203
204 /*
205 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
206 * for ux500.
207 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
208 * At 32 MHz, the timer (with 32 bit counter) can be programmed
209 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
210 * with 16 gives too low timer resolution.
211 */
212 rate = clk_get_rate(clk);
213 if (rate > 32000000) {
214 rate /= 16;
215 clk_prescale = MTU_CRn_PRESCALE_16;
216 } else {
217 clk_prescale = MTU_CRn_PRESCALE_1;
218 }
219
220 /* Cycles for periodic mode */
221 nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
222
223
224 /* Timer 0 is the free running clocksource */
225 nmdk_clksrc_reset();
226
227 if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
228 rate, 200, 32, clocksource_mmio_readl_down))
229 pr_err("timer: failed to initialize clock source %s\n",
230 "mtu_0");
231
232#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK
233 sched_clock_register(nomadik_read_sched_clock, 32, rate);
234#endif
235
236 /* Timer 1 is used for events, register irq and clockevents */
237 setup_irq(irq, &nmdk_timer_irq);
238 nmdk_clkevt.cpumask = cpumask_of(0);
239 nmdk_clkevt.irq = irq;
240 clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
241
242 mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
243 mtu_delay_timer.freq = rate;
244 register_current_timer_delay(&mtu_delay_timer);
245}
246
247static void __init nmdk_timer_of_init(struct device_node *node)
248{
249 struct clk *pclk;
250 struct clk *clk;
251 void __iomem *base;
252 int irq;
253
254 base = of_iomap(node, 0);
255 if (!base)
256 panic("Can't remap registers");
257
258 pclk = of_clk_get_by_name(node, "apb_pclk");
259 if (IS_ERR(pclk))
260 panic("could not get apb_pclk");
261
262 clk = of_clk_get_by_name(node, "timclk");
263 if (IS_ERR(clk))
264 panic("could not get timclk");
265
266 irq = irq_of_parse_and_map(node, 0);
267 if (irq <= 0)
268 panic("Can't parse IRQ");
269
270 nmdk_timer_init(base, irq, pclk, clk);
271}
272CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
273 nmdk_timer_of_init);