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1/*
2 * sun4m irq support
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
12#include <asm/timer.h>
13#include <asm/traps.h>
14#include <asm/pgalloc.h>
15#include <asm/pgtable.h>
16#include <asm/irq.h>
17#include <asm/io.h>
18#include <asm/cacheflush.h>
19
20#include "irq.h"
21#include "kernel.h"
22
23/* Sample sun4m IRQ layout:
24 *
25 * 0x22 - Power
26 * 0x24 - ESP SCSI
27 * 0x26 - Lance ethernet
28 * 0x2b - Floppy
29 * 0x2c - Zilog uart
30 * 0x32 - SBUS level 0
31 * 0x33 - Parallel port, SBUS level 1
32 * 0x35 - SBUS level 2
33 * 0x37 - SBUS level 3
34 * 0x39 - Audio, Graphics card, SBUS level 4
35 * 0x3b - SBUS level 5
36 * 0x3d - SBUS level 6
37 *
38 * Each interrupt source has a mask bit in the interrupt registers.
39 * When the mask bit is set, this blocks interrupt deliver. So you
40 * clear the bit to enable the interrupt.
41 *
42 * Interrupts numbered less than 0x10 are software triggered interrupts
43 * and unused by Linux.
44 *
45 * Interrupt level assignment on sun4m:
46 *
47 * level source
48 * ------------------------------------------------------------
49 * 1 softint-1
50 * 2 softint-2, VME/SBUS level 1
51 * 3 softint-3, VME/SBUS level 2
52 * 4 softint-4, onboard SCSI
53 * 5 softint-5, VME/SBUS level 3
54 * 6 softint-6, onboard ETHERNET
55 * 7 softint-7, VME/SBUS level 4
56 * 8 softint-8, onboard VIDEO
57 * 9 softint-9, VME/SBUS level 5, Module Interrupt
58 * 10 softint-10, system counter/timer
59 * 11 softint-11, VME/SBUS level 6, Floppy
60 * 12 softint-12, Keyboard/Mouse, Serial
61 * 13 softint-13, VME/SBUS level 7, ISDN Audio
62 * 14 softint-14, per-processor counter/timer
63 * 15 softint-15, Asynchronous Errors (broadcast)
64 *
65 * Each interrupt source is masked distinctly in the sun4m interrupt
66 * registers. The PIL level alone is therefore ambiguous, since multiple
67 * interrupt sources map to a single PIL.
68 *
69 * This ambiguity is resolved in the 'intr' property for device nodes
70 * in the OF device tree. Each 'intr' property entry is composed of
71 * two 32-bit words. The first word is the IRQ priority value, which
72 * is what we're intersted in. The second word is the IRQ vector, which
73 * is unused.
74 *
75 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
76 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
77 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
78 *
79 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
80 * whereas a value of 0x33 is SBUS level 2. Here are some sample
81 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
82 * Tadpole S3 GX systems.
83 *
84 * esp: 0x24 onboard ESP SCSI
85 * le: 0x26 onboard Lance ETHERNET
86 * p9100: 0x32 SBUS level 1 P9100 video
87 * bpp: 0x33 SBUS level 2 BPP parallel port device
88 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
89 * SUNW,leo: 0x39 SBUS level 5 LEO video
90 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
91 * uctrl: 0x3b SBUS level 6 UCTRL device
92 * modem: 0x3d SBUS level 7 MODEM
93 * zs: 0x2c onboard keyboard/mouse/serial
94 * floppy: 0x2b onboard Floppy
95 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
96 */
97
98
99/* Code in entry.S needs to get at these register mappings. */
100struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
101struct sun4m_irq_global __iomem *sun4m_irq_global;
102
103struct sun4m_handler_data {
104 bool percpu;
105 long mask;
106};
107
108/* Dave Redman (djhr@tadpole.co.uk)
109 * The sun4m interrupt registers.
110 */
111#define SUN4M_INT_ENABLE 0x80000000
112#define SUN4M_INT_E14 0x00000080
113#define SUN4M_INT_E10 0x00080000
114
115#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
116#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
117#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
118#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
119#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
120#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
121#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
122#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
123#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
124#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
125#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
126#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
127#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
128#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
129#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
130#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
131
132#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
133 SUN4M_INT_M2S_WRITE_ERR | \
134 SUN4M_INT_ECC_ERR | \
135 SUN4M_INT_VME_ERR)
136
137#define SUN4M_INT_SBUS(x) (1 << (x+7))
138#define SUN4M_INT_VME(x) (1 << (x))
139
140/* Interrupt levels used by OBP */
141#define OBP_INT_LEVEL_SOFT 0x10
142#define OBP_INT_LEVEL_ONBOARD 0x20
143#define OBP_INT_LEVEL_SBUS 0x30
144#define OBP_INT_LEVEL_VME 0x40
145
146#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
147#define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
148
149static unsigned long sun4m_imask[0x50] = {
150 /* 0x00 - SMP */
151 0, SUN4M_SOFT_INT(1),
152 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
153 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
154 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
155 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
156 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
157 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
158 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
159 /* 0x10 - soft */
160 0, SUN4M_SOFT_INT(1),
161 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
162 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
163 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
164 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
165 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
166 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
167 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
168 /* 0x20 - onboard */
169 0, 0, 0, 0,
170 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
171 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
172 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
173 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
174 SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
175 /* 0x30 - sbus */
176 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
177 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
178 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
179 0, SUN4M_INT_SBUS(6), 0, 0,
180 /* 0x40 - vme */
181 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
182 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
183 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
184 0, SUN4M_INT_VME(6), 0, 0
185};
186
187static void sun4m_mask_irq(struct irq_data *data)
188{
189 struct sun4m_handler_data *handler_data = data->handler_data;
190 int cpu = smp_processor_id();
191
192 if (handler_data->mask) {
193 unsigned long flags;
194
195 local_irq_save(flags);
196 if (handler_data->percpu) {
197 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
198 } else {
199 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
200 }
201 local_irq_restore(flags);
202 }
203}
204
205static void sun4m_unmask_irq(struct irq_data *data)
206{
207 struct sun4m_handler_data *handler_data = data->handler_data;
208 int cpu = smp_processor_id();
209
210 if (handler_data->mask) {
211 unsigned long flags;
212
213 local_irq_save(flags);
214 if (handler_data->percpu) {
215 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
216 } else {
217 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
218 }
219 local_irq_restore(flags);
220 }
221}
222
223static unsigned int sun4m_startup_irq(struct irq_data *data)
224{
225 irq_link(data->irq);
226 sun4m_unmask_irq(data);
227 return 0;
228}
229
230static void sun4m_shutdown_irq(struct irq_data *data)
231{
232 sun4m_mask_irq(data);
233 irq_unlink(data->irq);
234}
235
236static struct irq_chip sun4m_irq = {
237 .name = "sun4m",
238 .irq_startup = sun4m_startup_irq,
239 .irq_shutdown = sun4m_shutdown_irq,
240 .irq_mask = sun4m_mask_irq,
241 .irq_unmask = sun4m_unmask_irq,
242};
243
244
245static unsigned int sun4m_build_device_irq(struct platform_device *op,
246 unsigned int real_irq)
247{
248 struct sun4m_handler_data *handler_data;
249 unsigned int irq;
250 unsigned int pil;
251
252 if (real_irq >= OBP_INT_LEVEL_VME) {
253 prom_printf("Bogus sun4m IRQ %u\n", real_irq);
254 prom_halt();
255 }
256 pil = (real_irq & 0xf);
257 irq = irq_alloc(real_irq, pil);
258
259 if (irq == 0)
260 goto out;
261
262 handler_data = irq_get_handler_data(irq);
263 if (unlikely(handler_data))
264 goto out;
265
266 handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
267 if (unlikely(!handler_data)) {
268 prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
269 prom_halt();
270 }
271
272 handler_data->mask = sun4m_imask[real_irq];
273 handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
274 irq_set_chip_and_handler_name(irq, &sun4m_irq,
275 handle_level_irq, "level");
276 irq_set_handler_data(irq, handler_data);
277
278out:
279 return irq;
280}
281
282struct sun4m_timer_percpu {
283 u32 l14_limit;
284 u32 l14_count;
285 u32 l14_limit_noclear;
286 u32 user_timer_start_stop;
287};
288
289static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
290
291struct sun4m_timer_global {
292 u32 l10_limit;
293 u32 l10_count;
294 u32 l10_limit_noclear;
295 u32 reserved;
296 u32 timer_config;
297};
298
299static struct sun4m_timer_global __iomem *timers_global;
300
301static void sun4m_clear_clock_irq(void)
302{
303 sbus_readl(&timers_global->l10_limit);
304}
305
306void sun4m_nmi(struct pt_regs *regs)
307{
308 unsigned long afsr, afar, si;
309
310 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
311 /* XXX HyperSparc hack XXX */
312 __asm__ __volatile__("mov 0x500, %%g1\n\t"
313 "lda [%%g1] 0x4, %0\n\t"
314 "mov 0x600, %%g1\n\t"
315 "lda [%%g1] 0x4, %1\n\t" :
316 "=r" (afsr), "=r" (afar));
317 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
318 si = sbus_readl(&sun4m_irq_global->pending);
319 printk(KERN_ERR "si=%08lx\n", si);
320 if (si & SUN4M_INT_MODULE_ERR)
321 printk(KERN_ERR "Module async error\n");
322 if (si & SUN4M_INT_M2S_WRITE_ERR)
323 printk(KERN_ERR "MBus/SBus async error\n");
324 if (si & SUN4M_INT_ECC_ERR)
325 printk(KERN_ERR "ECC memory error\n");
326 if (si & SUN4M_INT_VME_ERR)
327 printk(KERN_ERR "VME async error\n");
328 printk(KERN_ERR "you lose buddy boy...\n");
329 show_regs(regs);
330 prom_halt();
331}
332
333void sun4m_unmask_profile_irq(void)
334{
335 unsigned long flags;
336
337 local_irq_save(flags);
338 sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
339 local_irq_restore(flags);
340}
341
342void sun4m_clear_profile_irq(int cpu)
343{
344 sbus_readl(&timers_percpu[cpu]->l14_limit);
345}
346
347static void sun4m_load_profile_irq(int cpu, unsigned int limit)
348{
349 unsigned int value = limit ? timer_value(limit) : 0;
350 sbus_writel(value, &timers_percpu[cpu]->l14_limit);
351}
352
353static void __init sun4m_init_timers(void)
354{
355 struct device_node *dp = of_find_node_by_name(NULL, "counter");
356 int i, err, len, num_cpu_timers;
357 unsigned int irq;
358 const u32 *addr;
359
360 if (!dp) {
361 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
362 return;
363 }
364
365 addr = of_get_property(dp, "address", &len);
366 of_node_put(dp);
367 if (!addr) {
368 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
369 return;
370 }
371
372 num_cpu_timers = (len / sizeof(u32)) - 1;
373 for (i = 0; i < num_cpu_timers; i++) {
374 timers_percpu[i] = (void __iomem *)
375 (unsigned long) addr[i];
376 }
377 timers_global = (void __iomem *)
378 (unsigned long) addr[num_cpu_timers];
379
380 /* Every per-cpu timer works in timer mode */
381 sbus_writel(0x00000000, &timers_global->timer_config);
382
383#ifdef CONFIG_SMP
384 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
385 sparc_config.features |= FEAT_L14_ONESHOT;
386#else
387 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
388 sparc_config.features |= FEAT_L10_CLOCKEVENT;
389#endif
390 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
391 sbus_writel(timer_value(sparc_config.cs_period),
392 &timers_global->l10_limit);
393
394 master_l10_counter = &timers_global->l10_count;
395
396 irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
397
398 err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
399 if (err) {
400 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
401 err);
402 return;
403 }
404
405 for (i = 0; i < num_cpu_timers; i++)
406 sbus_writel(0, &timers_percpu[i]->l14_limit);
407 if (num_cpu_timers == 4)
408 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
409
410#ifdef CONFIG_SMP
411 {
412 unsigned long flags;
413 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
414
415 /* For SMP we use the level 14 ticker, however the bootup code
416 * has copied the firmware's level 14 vector into the boot cpu's
417 * trap table, we must fix this now or we get squashed.
418 */
419 local_irq_save(flags);
420 trap_table->inst_one = lvl14_save[0];
421 trap_table->inst_two = lvl14_save[1];
422 trap_table->inst_three = lvl14_save[2];
423 trap_table->inst_four = lvl14_save[3];
424 local_ops->cache_all();
425 local_irq_restore(flags);
426 }
427#endif
428}
429
430void __init sun4m_init_IRQ(void)
431{
432 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
433 int len, i, mid, num_cpu_iregs;
434 const u32 *addr;
435
436 if (!dp) {
437 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
438 return;
439 }
440
441 addr = of_get_property(dp, "address", &len);
442 of_node_put(dp);
443 if (!addr) {
444 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
445 return;
446 }
447
448 num_cpu_iregs = (len / sizeof(u32)) - 1;
449 for (i = 0; i < num_cpu_iregs; i++) {
450 sun4m_irq_percpu[i] = (void __iomem *)
451 (unsigned long) addr[i];
452 }
453 sun4m_irq_global = (void __iomem *)
454 (unsigned long) addr[num_cpu_iregs];
455
456 local_irq_disable();
457
458 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
459 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
460 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
461
462 if (num_cpu_iregs == 4)
463 sbus_writel(0, &sun4m_irq_global->interrupt_target);
464
465 sparc_config.init_timers = sun4m_init_timers;
466 sparc_config.build_device_irq = sun4m_build_device_irq;
467 sparc_config.clock_rate = SBUS_CLOCK_RATE;
468 sparc_config.clear_clock_irq = sun4m_clear_clock_irq;
469 sparc_config.load_profile_irq = sun4m_load_profile_irq;
470
471
472 /* Cannot enable interrupts until OBP ticker is disabled. */
473}
1/*
2 * sun4m irq support
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
12#include <linux/slab.h>
13
14#include <asm/timer.h>
15#include <asm/traps.h>
16#include <asm/pgalloc.h>
17#include <asm/pgtable.h>
18#include <asm/irq.h>
19#include <asm/io.h>
20#include <asm/cacheflush.h>
21
22#include "irq.h"
23#include "kernel.h"
24
25/* Sample sun4m IRQ layout:
26 *
27 * 0x22 - Power
28 * 0x24 - ESP SCSI
29 * 0x26 - Lance ethernet
30 * 0x2b - Floppy
31 * 0x2c - Zilog uart
32 * 0x32 - SBUS level 0
33 * 0x33 - Parallel port, SBUS level 1
34 * 0x35 - SBUS level 2
35 * 0x37 - SBUS level 3
36 * 0x39 - Audio, Graphics card, SBUS level 4
37 * 0x3b - SBUS level 5
38 * 0x3d - SBUS level 6
39 *
40 * Each interrupt source has a mask bit in the interrupt registers.
41 * When the mask bit is set, this blocks interrupt deliver. So you
42 * clear the bit to enable the interrupt.
43 *
44 * Interrupts numbered less than 0x10 are software triggered interrupts
45 * and unused by Linux.
46 *
47 * Interrupt level assignment on sun4m:
48 *
49 * level source
50 * ------------------------------------------------------------
51 * 1 softint-1
52 * 2 softint-2, VME/SBUS level 1
53 * 3 softint-3, VME/SBUS level 2
54 * 4 softint-4, onboard SCSI
55 * 5 softint-5, VME/SBUS level 3
56 * 6 softint-6, onboard ETHERNET
57 * 7 softint-7, VME/SBUS level 4
58 * 8 softint-8, onboard VIDEO
59 * 9 softint-9, VME/SBUS level 5, Module Interrupt
60 * 10 softint-10, system counter/timer
61 * 11 softint-11, VME/SBUS level 6, Floppy
62 * 12 softint-12, Keyboard/Mouse, Serial
63 * 13 softint-13, VME/SBUS level 7, ISDN Audio
64 * 14 softint-14, per-processor counter/timer
65 * 15 softint-15, Asynchronous Errors (broadcast)
66 *
67 * Each interrupt source is masked distinctly in the sun4m interrupt
68 * registers. The PIL level alone is therefore ambiguous, since multiple
69 * interrupt sources map to a single PIL.
70 *
71 * This ambiguity is resolved in the 'intr' property for device nodes
72 * in the OF device tree. Each 'intr' property entry is composed of
73 * two 32-bit words. The first word is the IRQ priority value, which
74 * is what we're intersted in. The second word is the IRQ vector, which
75 * is unused.
76 *
77 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
78 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
79 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
80 *
81 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
82 * whereas a value of 0x33 is SBUS level 2. Here are some sample
83 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
84 * Tadpole S3 GX systems.
85 *
86 * esp: 0x24 onboard ESP SCSI
87 * le: 0x26 onboard Lance ETHERNET
88 * p9100: 0x32 SBUS level 1 P9100 video
89 * bpp: 0x33 SBUS level 2 BPP parallel port device
90 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
91 * SUNW,leo: 0x39 SBUS level 5 LEO video
92 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
93 * uctrl: 0x3b SBUS level 6 UCTRL device
94 * modem: 0x3d SBUS level 7 MODEM
95 * zs: 0x2c onboard keyboard/mouse/serial
96 * floppy: 0x2b onboard Floppy
97 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
98 */
99
100
101/* Code in entry.S needs to get at these register mappings. */
102struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
103struct sun4m_irq_global __iomem *sun4m_irq_global;
104
105struct sun4m_handler_data {
106 bool percpu;
107 long mask;
108};
109
110/* Dave Redman (djhr@tadpole.co.uk)
111 * The sun4m interrupt registers.
112 */
113#define SUN4M_INT_ENABLE 0x80000000
114#define SUN4M_INT_E14 0x00000080
115#define SUN4M_INT_E10 0x00080000
116
117#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
118#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
119#define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
120#define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
121#define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
122#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
123#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
124#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
125#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
126#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
127#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
128#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
129#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
130#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
131#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
132#define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
133
134#define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
135 SUN4M_INT_M2S_WRITE_ERR | \
136 SUN4M_INT_ECC_ERR | \
137 SUN4M_INT_VME_ERR)
138
139#define SUN4M_INT_SBUS(x) (1 << (x+7))
140#define SUN4M_INT_VME(x) (1 << (x))
141
142/* Interrupt levels used by OBP */
143#define OBP_INT_LEVEL_SOFT 0x10
144#define OBP_INT_LEVEL_ONBOARD 0x20
145#define OBP_INT_LEVEL_SBUS 0x30
146#define OBP_INT_LEVEL_VME 0x40
147
148#define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
149#define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
150
151static unsigned long sun4m_imask[0x50] = {
152 /* 0x00 - SMP */
153 0, SUN4M_SOFT_INT(1),
154 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
155 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
156 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
157 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
158 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
159 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
160 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
161 /* 0x10 - soft */
162 0, SUN4M_SOFT_INT(1),
163 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
164 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
165 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
166 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
167 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
168 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
169 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
170 /* 0x20 - onboard */
171 0, 0, 0, 0,
172 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
173 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
174 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
175 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
176 SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
177 /* 0x30 - sbus */
178 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
179 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
180 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
181 0, SUN4M_INT_SBUS(6), 0, 0,
182 /* 0x40 - vme */
183 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
184 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
185 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
186 0, SUN4M_INT_VME(6), 0, 0
187};
188
189static void sun4m_mask_irq(struct irq_data *data)
190{
191 struct sun4m_handler_data *handler_data = data->handler_data;
192 int cpu = smp_processor_id();
193
194 if (handler_data->mask) {
195 unsigned long flags;
196
197 local_irq_save(flags);
198 if (handler_data->percpu) {
199 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
200 } else {
201 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
202 }
203 local_irq_restore(flags);
204 }
205}
206
207static void sun4m_unmask_irq(struct irq_data *data)
208{
209 struct sun4m_handler_data *handler_data = data->handler_data;
210 int cpu = smp_processor_id();
211
212 if (handler_data->mask) {
213 unsigned long flags;
214
215 local_irq_save(flags);
216 if (handler_data->percpu) {
217 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
218 } else {
219 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
220 }
221 local_irq_restore(flags);
222 }
223}
224
225static unsigned int sun4m_startup_irq(struct irq_data *data)
226{
227 irq_link(data->irq);
228 sun4m_unmask_irq(data);
229 return 0;
230}
231
232static void sun4m_shutdown_irq(struct irq_data *data)
233{
234 sun4m_mask_irq(data);
235 irq_unlink(data->irq);
236}
237
238static struct irq_chip sun4m_irq = {
239 .name = "sun4m",
240 .irq_startup = sun4m_startup_irq,
241 .irq_shutdown = sun4m_shutdown_irq,
242 .irq_mask = sun4m_mask_irq,
243 .irq_unmask = sun4m_unmask_irq,
244};
245
246
247static unsigned int sun4m_build_device_irq(struct platform_device *op,
248 unsigned int real_irq)
249{
250 struct sun4m_handler_data *handler_data;
251 unsigned int irq;
252 unsigned int pil;
253
254 if (real_irq >= OBP_INT_LEVEL_VME) {
255 prom_printf("Bogus sun4m IRQ %u\n", real_irq);
256 prom_halt();
257 }
258 pil = (real_irq & 0xf);
259 irq = irq_alloc(real_irq, pil);
260
261 if (irq == 0)
262 goto out;
263
264 handler_data = irq_get_handler_data(irq);
265 if (unlikely(handler_data))
266 goto out;
267
268 handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
269 if (unlikely(!handler_data)) {
270 prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
271 prom_halt();
272 }
273
274 handler_data->mask = sun4m_imask[real_irq];
275 handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
276 irq_set_chip_and_handler_name(irq, &sun4m_irq,
277 handle_level_irq, "level");
278 irq_set_handler_data(irq, handler_data);
279
280out:
281 return irq;
282}
283
284struct sun4m_timer_percpu {
285 u32 l14_limit;
286 u32 l14_count;
287 u32 l14_limit_noclear;
288 u32 user_timer_start_stop;
289};
290
291static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
292
293struct sun4m_timer_global {
294 u32 l10_limit;
295 u32 l10_count;
296 u32 l10_limit_noclear;
297 u32 reserved;
298 u32 timer_config;
299};
300
301static struct sun4m_timer_global __iomem *timers_global;
302
303static void sun4m_clear_clock_irq(void)
304{
305 sbus_readl(&timers_global->l10_limit);
306}
307
308void sun4m_nmi(struct pt_regs *regs)
309{
310 unsigned long afsr, afar, si;
311
312 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
313 /* XXX HyperSparc hack XXX */
314 __asm__ __volatile__("mov 0x500, %%g1\n\t"
315 "lda [%%g1] 0x4, %0\n\t"
316 "mov 0x600, %%g1\n\t"
317 "lda [%%g1] 0x4, %1\n\t" :
318 "=r" (afsr), "=r" (afar));
319 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
320 si = sbus_readl(&sun4m_irq_global->pending);
321 printk(KERN_ERR "si=%08lx\n", si);
322 if (si & SUN4M_INT_MODULE_ERR)
323 printk(KERN_ERR "Module async error\n");
324 if (si & SUN4M_INT_M2S_WRITE_ERR)
325 printk(KERN_ERR "MBus/SBus async error\n");
326 if (si & SUN4M_INT_ECC_ERR)
327 printk(KERN_ERR "ECC memory error\n");
328 if (si & SUN4M_INT_VME_ERR)
329 printk(KERN_ERR "VME async error\n");
330 printk(KERN_ERR "you lose buddy boy...\n");
331 show_regs(regs);
332 prom_halt();
333}
334
335void sun4m_unmask_profile_irq(void)
336{
337 unsigned long flags;
338
339 local_irq_save(flags);
340 sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
341 local_irq_restore(flags);
342}
343
344void sun4m_clear_profile_irq(int cpu)
345{
346 sbus_readl(&timers_percpu[cpu]->l14_limit);
347}
348
349static void sun4m_load_profile_irq(int cpu, unsigned int limit)
350{
351 unsigned int value = limit ? timer_value(limit) : 0;
352 sbus_writel(value, &timers_percpu[cpu]->l14_limit);
353}
354
355static void __init sun4m_init_timers(void)
356{
357 struct device_node *dp = of_find_node_by_name(NULL, "counter");
358 int i, err, len, num_cpu_timers;
359 unsigned int irq;
360 const u32 *addr;
361
362 if (!dp) {
363 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
364 return;
365 }
366
367 addr = of_get_property(dp, "address", &len);
368 of_node_put(dp);
369 if (!addr) {
370 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
371 return;
372 }
373
374 num_cpu_timers = (len / sizeof(u32)) - 1;
375 for (i = 0; i < num_cpu_timers; i++) {
376 timers_percpu[i] = (void __iomem *)
377 (unsigned long) addr[i];
378 }
379 timers_global = (void __iomem *)
380 (unsigned long) addr[num_cpu_timers];
381
382 /* Every per-cpu timer works in timer mode */
383 sbus_writel(0x00000000, &timers_global->timer_config);
384
385#ifdef CONFIG_SMP
386 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
387 sparc_config.features |= FEAT_L14_ONESHOT;
388#else
389 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
390 sparc_config.features |= FEAT_L10_CLOCKEVENT;
391#endif
392 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
393 sbus_writel(timer_value(sparc_config.cs_period),
394 &timers_global->l10_limit);
395
396 master_l10_counter = &timers_global->l10_count;
397
398 irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
399
400 err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
401 if (err) {
402 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
403 err);
404 return;
405 }
406
407 for (i = 0; i < num_cpu_timers; i++)
408 sbus_writel(0, &timers_percpu[i]->l14_limit);
409 if (num_cpu_timers == 4)
410 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
411
412#ifdef CONFIG_SMP
413 {
414 unsigned long flags;
415 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
416
417 /* For SMP we use the level 14 ticker, however the bootup code
418 * has copied the firmware's level 14 vector into the boot cpu's
419 * trap table, we must fix this now or we get squashed.
420 */
421 local_irq_save(flags);
422 trap_table->inst_one = lvl14_save[0];
423 trap_table->inst_two = lvl14_save[1];
424 trap_table->inst_three = lvl14_save[2];
425 trap_table->inst_four = lvl14_save[3];
426 local_ops->cache_all();
427 local_irq_restore(flags);
428 }
429#endif
430}
431
432void __init sun4m_init_IRQ(void)
433{
434 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
435 int len, i, mid, num_cpu_iregs;
436 const u32 *addr;
437
438 if (!dp) {
439 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
440 return;
441 }
442
443 addr = of_get_property(dp, "address", &len);
444 of_node_put(dp);
445 if (!addr) {
446 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
447 return;
448 }
449
450 num_cpu_iregs = (len / sizeof(u32)) - 1;
451 for (i = 0; i < num_cpu_iregs; i++) {
452 sun4m_irq_percpu[i] = (void __iomem *)
453 (unsigned long) addr[i];
454 }
455 sun4m_irq_global = (void __iomem *)
456 (unsigned long) addr[num_cpu_iregs];
457
458 local_irq_disable();
459
460 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
461 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
462 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
463
464 if (num_cpu_iregs == 4)
465 sbus_writel(0, &sun4m_irq_global->interrupt_target);
466
467 sparc_config.init_timers = sun4m_init_timers;
468 sparc_config.build_device_irq = sun4m_build_device_irq;
469 sparc_config.clock_rate = SBUS_CLOCK_RATE;
470 sparc_config.clear_clock_irq = sun4m_clear_clock_irq;
471 sparc_config.load_profile_irq = sun4m_load_profile_irq;
472
473
474 /* Cannot enable interrupts until OBP ticker is disabled. */
475}