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1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32#include <linux/ratelimit.h>
33
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/pgtable.h>
38#include <asm/irq.h>
39#include <asm/machdep.h>
40#include <asm/mpic.h>
41#include <asm/smp.h>
42
43#include "mpic.h"
44
45#ifdef DEBUG
46#define DBG(fmt...) printk(fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51static struct mpic *mpics;
52static struct mpic *mpic_primary;
53static DEFINE_RAW_SPINLOCK(mpic_lock);
54
55#ifdef CONFIG_PPC32 /* XXX for now */
56#ifdef CONFIG_IRQ_ALL_CPUS
57#define distribute_irqs (1)
58#else
59#define distribute_irqs (0)
60#endif
61#endif
62
63#ifdef CONFIG_MPIC_WEIRD
64static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
66 MPIC_GREG_BASE,
67 MPIC_GREG_FEATURE_0,
68 MPIC_GREG_GLOBAL_CONF_0,
69 MPIC_GREG_VENDOR_ID,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
71 MPIC_GREG_IPI_STRIDE,
72 MPIC_GREG_SPURIOUS,
73 MPIC_GREG_TIMER_FREQ,
74
75 MPIC_TIMER_BASE,
76 MPIC_TIMER_STRIDE,
77 MPIC_TIMER_CURRENT_CNT,
78 MPIC_TIMER_BASE_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
81
82 MPIC_CPU_BASE,
83 MPIC_CPU_STRIDE,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
87 MPIC_CPU_WHOAMI,
88 MPIC_CPU_INTACK,
89 MPIC_CPU_EOI,
90 MPIC_CPU_MCACK,
91
92 MPIC_IRQ_BASE,
93 MPIC_IRQ_STRIDE,
94 MPIC_IRQ_VECTOR_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
102 MPIC_IRQ_DESTINATION
103 },
104 [1] = { /* Tsi108/109 PIC */
105 TSI108_GREG_BASE,
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
113
114 TSI108_TIMER_BASE,
115 TSI108_TIMER_STRIDE,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
120
121 TSI108_CPU_BASE,
122 TSI108_CPU_STRIDE,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
126 TSI108_CPU_WHOAMI,
127 TSI108_CPU_INTACK,
128 TSI108_CPU_EOI,
129 TSI108_CPU_MCACK,
130
131 TSI108_IRQ_BASE,
132 TSI108_IRQ_STRIDE,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
142 },
143};
144
145#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
146
147#else /* CONFIG_MPIC_WEIRD */
148
149#define MPIC_INFO(name) MPIC_##name
150
151#endif /* CONFIG_MPIC_WEIRD */
152
153static inline unsigned int mpic_processor_id(struct mpic *mpic)
154{
155 unsigned int cpu = 0;
156
157 if (!(mpic->flags & MPIC_SECONDARY))
158 cpu = hard_smp_processor_id();
159
160 return cpu;
161}
162
163/*
164 * Register accessor functions
165 */
166
167
168static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
170 unsigned int reg)
171{
172 switch(type) {
173#ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
176#endif
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
180 default:
181 return in_le32(rb->base + (reg >> 2));
182 }
183}
184
185static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
188{
189 switch(type) {
190#ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
193 break;
194#endif
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
197 break;
198 case mpic_access_mmio_le:
199 default:
200 out_le32(rb->base + (reg >> 2), value);
201 break;
202 }
203}
204
205static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
206{
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
210
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
214}
215
216static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
217{
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
220
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
222}
223
224static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
225{
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
228
229 if (tm >= 4)
230 offset += 0x1000 / 4;
231
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
233}
234
235static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
236{
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
239
240 if (tm >= 4)
241 offset += 0x1000 / 4;
242
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
244}
245
246static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
247{
248 unsigned int cpu = mpic_processor_id(mpic);
249
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
251}
252
253static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
254{
255 unsigned int cpu = mpic_processor_id(mpic);
256
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
258}
259
260static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
261{
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
264 unsigned int val;
265
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268#ifdef CONFIG_MPIC_BROKEN_REGREAD
269 if (reg == 0)
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
272#endif
273 return val;
274}
275
276static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
278{
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
281
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
284
285#ifdef CONFIG_MPIC_BROKEN_REGREAD
286 if (reg == 0)
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
289#endif
290}
291
292#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
302
303
304/*
305 * Low level utility functions
306 */
307
308
309static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
311 unsigned int size)
312{
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
315}
316
317#ifdef CONFIG_PPC_DCR
318static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
319 unsigned int offset, unsigned int size)
320{
321 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
322 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
323 BUG_ON(!DCR_MAP_OK(rb->dhost));
324}
325
326static inline void mpic_map(struct mpic *mpic,
327 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
328 unsigned int offset, unsigned int size)
329{
330 if (mpic->flags & MPIC_USES_DCR)
331 _mpic_map_dcr(mpic, rb, offset, size);
332 else
333 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
334}
335#else /* CONFIG_PPC_DCR */
336#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
337#endif /* !CONFIG_PPC_DCR */
338
339
340
341/* Check if we have one of those nice broken MPICs with a flipped endian on
342 * reads from IPI registers
343 */
344static void __init mpic_test_broken_ipi(struct mpic *mpic)
345{
346 u32 r;
347
348 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
349 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
350
351 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
352 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
353 mpic->flags |= MPIC_BROKEN_IPI;
354 }
355}
356
357#ifdef CONFIG_MPIC_U3_HT_IRQS
358
359/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
360 * to force the edge setting on the MPIC and do the ack workaround.
361 */
362static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
363{
364 if (source >= 128 || !mpic->fixups)
365 return 0;
366 return mpic->fixups[source].base != NULL;
367}
368
369
370static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
371{
372 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
373
374 if (fixup->applebase) {
375 unsigned int soff = (fixup->index >> 3) & ~3;
376 unsigned int mask = 1U << (fixup->index & 0x1f);
377 writel(mask, fixup->applebase + soff);
378 } else {
379 raw_spin_lock(&mpic->fixup_lock);
380 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
381 writel(fixup->data, fixup->base + 4);
382 raw_spin_unlock(&mpic->fixup_lock);
383 }
384}
385
386static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
387 bool level)
388{
389 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
390 unsigned long flags;
391 u32 tmp;
392
393 if (fixup->base == NULL)
394 return;
395
396 DBG("startup_ht_interrupt(0x%x) index: %d\n",
397 source, fixup->index);
398 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
399 /* Enable and configure */
400 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
401 tmp = readl(fixup->base + 4);
402 tmp &= ~(0x23U);
403 if (level)
404 tmp |= 0x22;
405 writel(tmp, fixup->base + 4);
406 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
407
408#ifdef CONFIG_PM
409 /* use the lowest bit inverted to the actual HW,
410 * set if this fixup was enabled, clear otherwise */
411 mpic->save_data[source].fixup_data = tmp | 1;
412#endif
413}
414
415static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
416{
417 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
418 unsigned long flags;
419 u32 tmp;
420
421 if (fixup->base == NULL)
422 return;
423
424 DBG("shutdown_ht_interrupt(0x%x)\n", source);
425
426 /* Disable */
427 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
428 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
429 tmp = readl(fixup->base + 4);
430 tmp |= 1;
431 writel(tmp, fixup->base + 4);
432 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
433
434#ifdef CONFIG_PM
435 /* use the lowest bit inverted to the actual HW,
436 * set if this fixup was enabled, clear otherwise */
437 mpic->save_data[source].fixup_data = tmp & ~1;
438#endif
439}
440
441#ifdef CONFIG_PCI_MSI
442static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
443 unsigned int devfn)
444{
445 u8 __iomem *base;
446 u8 pos, flags;
447 u64 addr = 0;
448
449 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
450 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
451 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
452 if (id == PCI_CAP_ID_HT) {
453 id = readb(devbase + pos + 3);
454 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
455 break;
456 }
457 }
458
459 if (pos == 0)
460 return;
461
462 base = devbase + pos;
463
464 flags = readb(base + HT_MSI_FLAGS);
465 if (!(flags & HT_MSI_FLAGS_FIXED)) {
466 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
467 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
468 }
469
470 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
471 PCI_SLOT(devfn), PCI_FUNC(devfn),
472 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
473
474 if (!(flags & HT_MSI_FLAGS_ENABLE))
475 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
476}
477#else
478static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
479 unsigned int devfn)
480{
481 return;
482}
483#endif
484
485static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
486 unsigned int devfn, u32 vdid)
487{
488 int i, irq, n;
489 u8 __iomem *base;
490 u32 tmp;
491 u8 pos;
492
493 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
494 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
495 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
496 if (id == PCI_CAP_ID_HT) {
497 id = readb(devbase + pos + 3);
498 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
499 break;
500 }
501 }
502 if (pos == 0)
503 return;
504
505 base = devbase + pos;
506 writeb(0x01, base + 2);
507 n = (readl(base + 4) >> 16) & 0xff;
508
509 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
510 " has %d irqs\n",
511 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
512
513 for (i = 0; i <= n; i++) {
514 writeb(0x10 + 2 * i, base + 2);
515 tmp = readl(base + 4);
516 irq = (tmp >> 16) & 0xff;
517 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
518 /* mask it , will be unmasked later */
519 tmp |= 0x1;
520 writel(tmp, base + 4);
521 mpic->fixups[irq].index = i;
522 mpic->fixups[irq].base = base;
523 /* Apple HT PIC has a non-standard way of doing EOIs */
524 if ((vdid & 0xffff) == 0x106b)
525 mpic->fixups[irq].applebase = devbase + 0x60;
526 else
527 mpic->fixups[irq].applebase = NULL;
528 writeb(0x11 + 2 * i, base + 2);
529 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
530 }
531}
532
533
534static void __init mpic_scan_ht_pics(struct mpic *mpic)
535{
536 unsigned int devfn;
537 u8 __iomem *cfgspace;
538
539 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
540
541 /* Allocate fixups array */
542 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
543 BUG_ON(mpic->fixups == NULL);
544
545 /* Init spinlock */
546 raw_spin_lock_init(&mpic->fixup_lock);
547
548 /* Map U3 config space. We assume all IO-APICs are on the primary bus
549 * so we only need to map 64kB.
550 */
551 cfgspace = ioremap(0xf2000000, 0x10000);
552 BUG_ON(cfgspace == NULL);
553
554 /* Now we scan all slots. We do a very quick scan, we read the header
555 * type, vendor ID and device ID only, that's plenty enough
556 */
557 for (devfn = 0; devfn < 0x100; devfn++) {
558 u8 __iomem *devbase = cfgspace + (devfn << 8);
559 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
560 u32 l = readl(devbase + PCI_VENDOR_ID);
561 u16 s;
562
563 DBG("devfn %x, l: %x\n", devfn, l);
564
565 /* If no device, skip */
566 if (l == 0xffffffff || l == 0x00000000 ||
567 l == 0x0000ffff || l == 0xffff0000)
568 goto next;
569 /* Check if is supports capability lists */
570 s = readw(devbase + PCI_STATUS);
571 if (!(s & PCI_STATUS_CAP_LIST))
572 goto next;
573
574 mpic_scan_ht_pic(mpic, devbase, devfn, l);
575 mpic_scan_ht_msi(mpic, devbase, devfn);
576
577 next:
578 /* next device, if function 0 */
579 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
580 devfn += 7;
581 }
582}
583
584#else /* CONFIG_MPIC_U3_HT_IRQS */
585
586static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
587{
588 return 0;
589}
590
591static void __init mpic_scan_ht_pics(struct mpic *mpic)
592{
593}
594
595#endif /* CONFIG_MPIC_U3_HT_IRQS */
596
597/* Find an mpic associated with a given linux interrupt */
598static struct mpic *mpic_find(unsigned int irq)
599{
600 if (irq < NUM_ISA_INTERRUPTS)
601 return NULL;
602
603 return irq_get_chip_data(irq);
604}
605
606/* Determine if the linux irq is an IPI */
607static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
608{
609 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
610}
611
612/* Determine if the linux irq is a timer */
613static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
614{
615 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
616}
617
618/* Convert a cpu mask from logical to physical cpu numbers. */
619static inline u32 mpic_physmask(u32 cpumask)
620{
621 int i;
622 u32 mask = 0;
623
624 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
625 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
626 return mask;
627}
628
629#ifdef CONFIG_SMP
630/* Get the mpic structure from the IPI number */
631static inline struct mpic * mpic_from_ipi(struct irq_data *d)
632{
633 return irq_data_get_irq_chip_data(d);
634}
635#endif
636
637/* Get the mpic structure from the irq number */
638static inline struct mpic * mpic_from_irq(unsigned int irq)
639{
640 return irq_get_chip_data(irq);
641}
642
643/* Get the mpic structure from the irq data */
644static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
645{
646 return irq_data_get_irq_chip_data(d);
647}
648
649/* Send an EOI */
650static inline void mpic_eoi(struct mpic *mpic)
651{
652 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
653 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
654}
655
656/*
657 * Linux descriptor level callbacks
658 */
659
660
661void mpic_unmask_irq(struct irq_data *d)
662{
663 unsigned int loops = 100000;
664 struct mpic *mpic = mpic_from_irq_data(d);
665 unsigned int src = irqd_to_hwirq(d);
666
667 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
668
669 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
670 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
671 ~MPIC_VECPRI_MASK);
672 /* make sure mask gets to controller before we return to user */
673 do {
674 if (!loops--) {
675 printk(KERN_ERR "%s: timeout on hwirq %u\n",
676 __func__, src);
677 break;
678 }
679 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
680}
681
682void mpic_mask_irq(struct irq_data *d)
683{
684 unsigned int loops = 100000;
685 struct mpic *mpic = mpic_from_irq_data(d);
686 unsigned int src = irqd_to_hwirq(d);
687
688 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
689
690 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
691 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
692 MPIC_VECPRI_MASK);
693
694 /* make sure mask gets to controller before we return to user */
695 do {
696 if (!loops--) {
697 printk(KERN_ERR "%s: timeout on hwirq %u\n",
698 __func__, src);
699 break;
700 }
701 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
702}
703
704void mpic_end_irq(struct irq_data *d)
705{
706 struct mpic *mpic = mpic_from_irq_data(d);
707
708#ifdef DEBUG_IRQ
709 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
710#endif
711 /* We always EOI on end_irq() even for edge interrupts since that
712 * should only lower the priority, the MPIC should have properly
713 * latched another edge interrupt coming in anyway
714 */
715
716 mpic_eoi(mpic);
717}
718
719#ifdef CONFIG_MPIC_U3_HT_IRQS
720
721static void mpic_unmask_ht_irq(struct irq_data *d)
722{
723 struct mpic *mpic = mpic_from_irq_data(d);
724 unsigned int src = irqd_to_hwirq(d);
725
726 mpic_unmask_irq(d);
727
728 if (irqd_is_level_type(d))
729 mpic_ht_end_irq(mpic, src);
730}
731
732static unsigned int mpic_startup_ht_irq(struct irq_data *d)
733{
734 struct mpic *mpic = mpic_from_irq_data(d);
735 unsigned int src = irqd_to_hwirq(d);
736
737 mpic_unmask_irq(d);
738 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
739
740 return 0;
741}
742
743static void mpic_shutdown_ht_irq(struct irq_data *d)
744{
745 struct mpic *mpic = mpic_from_irq_data(d);
746 unsigned int src = irqd_to_hwirq(d);
747
748 mpic_shutdown_ht_interrupt(mpic, src);
749 mpic_mask_irq(d);
750}
751
752static void mpic_end_ht_irq(struct irq_data *d)
753{
754 struct mpic *mpic = mpic_from_irq_data(d);
755 unsigned int src = irqd_to_hwirq(d);
756
757#ifdef DEBUG_IRQ
758 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
759#endif
760 /* We always EOI on end_irq() even for edge interrupts since that
761 * should only lower the priority, the MPIC should have properly
762 * latched another edge interrupt coming in anyway
763 */
764
765 if (irqd_is_level_type(d))
766 mpic_ht_end_irq(mpic, src);
767 mpic_eoi(mpic);
768}
769#endif /* !CONFIG_MPIC_U3_HT_IRQS */
770
771#ifdef CONFIG_SMP
772
773static void mpic_unmask_ipi(struct irq_data *d)
774{
775 struct mpic *mpic = mpic_from_ipi(d);
776 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
777
778 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
779 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
780}
781
782static void mpic_mask_ipi(struct irq_data *d)
783{
784 /* NEVER disable an IPI... that's just plain wrong! */
785}
786
787static void mpic_end_ipi(struct irq_data *d)
788{
789 struct mpic *mpic = mpic_from_ipi(d);
790
791 /*
792 * IPIs are marked IRQ_PER_CPU. This has the side effect of
793 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
794 * applying to them. We EOI them late to avoid re-entering.
795 */
796 mpic_eoi(mpic);
797}
798
799#endif /* CONFIG_SMP */
800
801static void mpic_unmask_tm(struct irq_data *d)
802{
803 struct mpic *mpic = mpic_from_irq_data(d);
804 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
805
806 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
807 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
808 mpic_tm_read(src);
809}
810
811static void mpic_mask_tm(struct irq_data *d)
812{
813 struct mpic *mpic = mpic_from_irq_data(d);
814 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
815
816 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
817 mpic_tm_read(src);
818}
819
820int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
821 bool force)
822{
823 struct mpic *mpic = mpic_from_irq_data(d);
824 unsigned int src = irqd_to_hwirq(d);
825
826 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
827 int cpuid = irq_choose_cpu(cpumask);
828
829 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
830 } else {
831 u32 mask = cpumask_bits(cpumask)[0];
832
833 mask &= cpumask_bits(cpu_online_mask)[0];
834
835 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
836 mpic_physmask(mask));
837 }
838
839 return 0;
840}
841
842static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
843{
844 /* Now convert sense value */
845 switch(type & IRQ_TYPE_SENSE_MASK) {
846 case IRQ_TYPE_EDGE_RISING:
847 return MPIC_INFO(VECPRI_SENSE_EDGE) |
848 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
849 case IRQ_TYPE_EDGE_FALLING:
850 case IRQ_TYPE_EDGE_BOTH:
851 return MPIC_INFO(VECPRI_SENSE_EDGE) |
852 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
853 case IRQ_TYPE_LEVEL_HIGH:
854 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
855 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
856 case IRQ_TYPE_LEVEL_LOW:
857 default:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
859 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
860 }
861}
862
863int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
864{
865 struct mpic *mpic = mpic_from_irq_data(d);
866 unsigned int src = irqd_to_hwirq(d);
867 unsigned int vecpri, vold, vnew;
868
869 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
870 mpic, d->irq, src, flow_type);
871
872 if (src >= mpic->num_sources)
873 return -EINVAL;
874
875 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
876
877 /* We don't support "none" type */
878 if (flow_type == IRQ_TYPE_NONE)
879 flow_type = IRQ_TYPE_DEFAULT;
880
881 /* Default: read HW settings */
882 if (flow_type == IRQ_TYPE_DEFAULT) {
883 switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
884 MPIC_INFO(VECPRI_SENSE_MASK))) {
885 case MPIC_INFO(VECPRI_SENSE_EDGE) |
886 MPIC_INFO(VECPRI_POLARITY_POSITIVE):
887 flow_type = IRQ_TYPE_EDGE_RISING;
888 break;
889 case MPIC_INFO(VECPRI_SENSE_EDGE) |
890 MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
891 flow_type = IRQ_TYPE_EDGE_FALLING;
892 break;
893 case MPIC_INFO(VECPRI_SENSE_LEVEL) |
894 MPIC_INFO(VECPRI_POLARITY_POSITIVE):
895 flow_type = IRQ_TYPE_LEVEL_HIGH;
896 break;
897 case MPIC_INFO(VECPRI_SENSE_LEVEL) |
898 MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
899 flow_type = IRQ_TYPE_LEVEL_LOW;
900 break;
901 }
902 }
903
904 /* Apply to irq desc */
905 irqd_set_trigger_type(d, flow_type);
906
907 /* Apply to HW */
908 if (mpic_is_ht_interrupt(mpic, src))
909 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
910 MPIC_VECPRI_SENSE_EDGE;
911 else
912 vecpri = mpic_type_to_vecpri(mpic, flow_type);
913
914 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
915 MPIC_INFO(VECPRI_SENSE_MASK));
916 vnew |= vecpri;
917 if (vold != vnew)
918 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
919
920 return IRQ_SET_MASK_OK_NOCOPY;
921}
922
923void mpic_set_vector(unsigned int virq, unsigned int vector)
924{
925 struct mpic *mpic = mpic_from_irq(virq);
926 unsigned int src = virq_to_hw(virq);
927 unsigned int vecpri;
928
929 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
930 mpic, virq, src, vector);
931
932 if (src >= mpic->num_sources)
933 return;
934
935 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
936 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
937 vecpri |= vector;
938 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
939}
940
941void mpic_set_destination(unsigned int virq, unsigned int cpuid)
942{
943 struct mpic *mpic = mpic_from_irq(virq);
944 unsigned int src = virq_to_hw(virq);
945
946 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
947 mpic, virq, src, cpuid);
948
949 if (src >= mpic->num_sources)
950 return;
951
952 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
953}
954
955static struct irq_chip mpic_irq_chip = {
956 .irq_mask = mpic_mask_irq,
957 .irq_unmask = mpic_unmask_irq,
958 .irq_eoi = mpic_end_irq,
959 .irq_set_type = mpic_set_irq_type,
960};
961
962#ifdef CONFIG_SMP
963static struct irq_chip mpic_ipi_chip = {
964 .irq_mask = mpic_mask_ipi,
965 .irq_unmask = mpic_unmask_ipi,
966 .irq_eoi = mpic_end_ipi,
967};
968#endif /* CONFIG_SMP */
969
970static struct irq_chip mpic_tm_chip = {
971 .irq_mask = mpic_mask_tm,
972 .irq_unmask = mpic_unmask_tm,
973 .irq_eoi = mpic_end_irq,
974};
975
976#ifdef CONFIG_MPIC_U3_HT_IRQS
977static struct irq_chip mpic_irq_ht_chip = {
978 .irq_startup = mpic_startup_ht_irq,
979 .irq_shutdown = mpic_shutdown_ht_irq,
980 .irq_mask = mpic_mask_irq,
981 .irq_unmask = mpic_unmask_ht_irq,
982 .irq_eoi = mpic_end_ht_irq,
983 .irq_set_type = mpic_set_irq_type,
984};
985#endif /* CONFIG_MPIC_U3_HT_IRQS */
986
987
988static int mpic_host_match(struct irq_domain *h, struct device_node *node)
989{
990 /* Exact match, unless mpic node is NULL */
991 return h->of_node == NULL || h->of_node == node;
992}
993
994static int mpic_host_map(struct irq_domain *h, unsigned int virq,
995 irq_hw_number_t hw)
996{
997 struct mpic *mpic = h->host_data;
998 struct irq_chip *chip;
999
1000 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1001
1002 if (hw == mpic->spurious_vec)
1003 return -EINVAL;
1004 if (mpic->protected && test_bit(hw, mpic->protected))
1005 return -EINVAL;
1006
1007#ifdef CONFIG_SMP
1008 else if (hw >= mpic->ipi_vecs[0]) {
1009 WARN_ON(mpic->flags & MPIC_SECONDARY);
1010
1011 DBG("mpic: mapping as IPI\n");
1012 irq_set_chip_data(virq, mpic);
1013 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1014 handle_percpu_irq);
1015 return 0;
1016 }
1017#endif /* CONFIG_SMP */
1018
1019 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1020 WARN_ON(mpic->flags & MPIC_SECONDARY);
1021
1022 DBG("mpic: mapping as timer\n");
1023 irq_set_chip_data(virq, mpic);
1024 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1025 handle_fasteoi_irq);
1026 return 0;
1027 }
1028
1029 if (hw >= mpic->num_sources)
1030 return -EINVAL;
1031
1032 mpic_msi_reserve_hwirq(mpic, hw);
1033
1034 /* Default chip */
1035 chip = &mpic->hc_irq;
1036
1037#ifdef CONFIG_MPIC_U3_HT_IRQS
1038 /* Check for HT interrupts, override vecpri */
1039 if (mpic_is_ht_interrupt(mpic, hw))
1040 chip = &mpic->hc_ht_irq;
1041#endif /* CONFIG_MPIC_U3_HT_IRQS */
1042
1043 DBG("mpic: mapping to irq chip @%p\n", chip);
1044
1045 irq_set_chip_data(virq, mpic);
1046 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1047
1048 /* Set default irq type */
1049 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1050
1051 /* If the MPIC was reset, then all vectors have already been
1052 * initialized. Otherwise, a per source lazy initialization
1053 * is done here.
1054 */
1055 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1056 mpic_set_vector(virq, hw);
1057 mpic_set_destination(virq, mpic_processor_id(mpic));
1058 mpic_irq_set_priority(virq, 8);
1059 }
1060
1061 return 0;
1062}
1063
1064static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1065 const u32 *intspec, unsigned int intsize,
1066 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1067
1068{
1069 struct mpic *mpic = h->host_data;
1070 static unsigned char map_mpic_senses[4] = {
1071 IRQ_TYPE_EDGE_RISING,
1072 IRQ_TYPE_LEVEL_LOW,
1073 IRQ_TYPE_LEVEL_HIGH,
1074 IRQ_TYPE_EDGE_FALLING,
1075 };
1076
1077 *out_hwirq = intspec[0];
1078 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1079 /*
1080 * Freescale MPIC with extended intspec:
1081 * First two cells are as usual. Third specifies
1082 * an "interrupt type". Fourth is type-specific data.
1083 *
1084 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1085 */
1086 switch (intspec[2]) {
1087 case 0:
1088 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1089 break;
1090 case 2:
1091 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1092 return -EINVAL;
1093
1094 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1095 break;
1096 case 3:
1097 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1098 return -EINVAL;
1099
1100 *out_hwirq = mpic->timer_vecs[intspec[0]];
1101 break;
1102 default:
1103 pr_debug("%s: unknown irq type %u\n",
1104 __func__, intspec[2]);
1105 return -EINVAL;
1106 }
1107
1108 *out_flags = map_mpic_senses[intspec[1] & 3];
1109 } else if (intsize > 1) {
1110 u32 mask = 0x3;
1111
1112 /* Apple invented a new race of encoding on machines with
1113 * an HT APIC. They encode, among others, the index within
1114 * the HT APIC. We don't care about it here since thankfully,
1115 * it appears that they have the APIC already properly
1116 * configured, and thus our current fixup code that reads the
1117 * APIC config works fine. However, we still need to mask out
1118 * bits in the specifier to make sure we only get bit 0 which
1119 * is the level/edge bit (the only sense bit exposed by Apple),
1120 * as their bit 1 means something else.
1121 */
1122 if (machine_is(powermac))
1123 mask = 0x1;
1124 *out_flags = map_mpic_senses[intspec[1] & mask];
1125 } else
1126 *out_flags = IRQ_TYPE_NONE;
1127
1128 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1129 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1130
1131 return 0;
1132}
1133
1134/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1135static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1136{
1137 struct irq_chip *chip = irq_desc_get_chip(desc);
1138 struct mpic *mpic = irq_desc_get_handler_data(desc);
1139 unsigned int virq;
1140
1141 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1142
1143 virq = mpic_get_one_irq(mpic);
1144 if (virq)
1145 generic_handle_irq(virq);
1146
1147 chip->irq_eoi(&desc->irq_data);
1148}
1149
1150static struct irq_domain_ops mpic_host_ops = {
1151 .match = mpic_host_match,
1152 .map = mpic_host_map,
1153 .xlate = mpic_host_xlate,
1154};
1155
1156/*
1157 * Exported functions
1158 */
1159
1160struct mpic * __init mpic_alloc(struct device_node *node,
1161 phys_addr_t phys_addr,
1162 unsigned int flags,
1163 unsigned int isu_size,
1164 unsigned int irq_count,
1165 const char *name)
1166{
1167 int i, psize, intvec_top;
1168 struct mpic *mpic;
1169 u32 greg_feature;
1170 const char *vers;
1171 const u32 *psrc;
1172 u32 last_irq;
1173
1174 /* Default MPIC search parameters */
1175 static const struct of_device_id __initconst mpic_device_id[] = {
1176 { .type = "open-pic", },
1177 { .compatible = "open-pic", },
1178 {},
1179 };
1180
1181 /*
1182 * If we were not passed a device-tree node, then perform the default
1183 * search for standardized a standardized OpenPIC.
1184 */
1185 if (node) {
1186 node = of_node_get(node);
1187 } else {
1188 node = of_find_matching_node(NULL, mpic_device_id);
1189 if (!node)
1190 return NULL;
1191 }
1192
1193 /* Pick the physical address from the device tree if unspecified */
1194 if (!phys_addr) {
1195 /* Check if it is DCR-based */
1196 if (of_get_property(node, "dcr-reg", NULL)) {
1197 flags |= MPIC_USES_DCR;
1198 } else {
1199 struct resource r;
1200 if (of_address_to_resource(node, 0, &r))
1201 goto err_of_node_put;
1202 phys_addr = r.start;
1203 }
1204 }
1205
1206 /* Read extra device-tree properties into the flags variable */
1207 if (of_get_property(node, "big-endian", NULL))
1208 flags |= MPIC_BIG_ENDIAN;
1209 if (of_get_property(node, "pic-no-reset", NULL))
1210 flags |= MPIC_NO_RESET;
1211 if (of_get_property(node, "single-cpu-affinity", NULL))
1212 flags |= MPIC_SINGLE_DEST_CPU;
1213 if (of_device_is_compatible(node, "fsl,mpic"))
1214 flags |= MPIC_FSL;
1215
1216 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1217 if (mpic == NULL)
1218 goto err_of_node_put;
1219
1220 mpic->name = name;
1221 mpic->node = node;
1222 mpic->paddr = phys_addr;
1223 mpic->flags = flags;
1224
1225 mpic->hc_irq = mpic_irq_chip;
1226 mpic->hc_irq.name = name;
1227 if (!(mpic->flags & MPIC_SECONDARY))
1228 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1229#ifdef CONFIG_MPIC_U3_HT_IRQS
1230 mpic->hc_ht_irq = mpic_irq_ht_chip;
1231 mpic->hc_ht_irq.name = name;
1232 if (!(mpic->flags & MPIC_SECONDARY))
1233 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1234#endif /* CONFIG_MPIC_U3_HT_IRQS */
1235
1236#ifdef CONFIG_SMP
1237 mpic->hc_ipi = mpic_ipi_chip;
1238 mpic->hc_ipi.name = name;
1239#endif /* CONFIG_SMP */
1240
1241 mpic->hc_tm = mpic_tm_chip;
1242 mpic->hc_tm.name = name;
1243
1244 mpic->num_sources = 0; /* so far */
1245
1246 if (mpic->flags & MPIC_LARGE_VECTORS)
1247 intvec_top = 2047;
1248 else
1249 intvec_top = 255;
1250
1251 mpic->timer_vecs[0] = intvec_top - 12;
1252 mpic->timer_vecs[1] = intvec_top - 11;
1253 mpic->timer_vecs[2] = intvec_top - 10;
1254 mpic->timer_vecs[3] = intvec_top - 9;
1255 mpic->timer_vecs[4] = intvec_top - 8;
1256 mpic->timer_vecs[5] = intvec_top - 7;
1257 mpic->timer_vecs[6] = intvec_top - 6;
1258 mpic->timer_vecs[7] = intvec_top - 5;
1259 mpic->ipi_vecs[0] = intvec_top - 4;
1260 mpic->ipi_vecs[1] = intvec_top - 3;
1261 mpic->ipi_vecs[2] = intvec_top - 2;
1262 mpic->ipi_vecs[3] = intvec_top - 1;
1263 mpic->spurious_vec = intvec_top;
1264
1265 /* Look for protected sources */
1266 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1267 if (psrc) {
1268 /* Allocate a bitmap with one bit per interrupt */
1269 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1270 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1271 BUG_ON(mpic->protected == NULL);
1272 for (i = 0; i < psize/sizeof(u32); i++) {
1273 if (psrc[i] > intvec_top)
1274 continue;
1275 __set_bit(psrc[i], mpic->protected);
1276 }
1277 }
1278
1279#ifdef CONFIG_MPIC_WEIRD
1280 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1281#endif
1282
1283 /* default register type */
1284 if (mpic->flags & MPIC_BIG_ENDIAN)
1285 mpic->reg_type = mpic_access_mmio_be;
1286 else
1287 mpic->reg_type = mpic_access_mmio_le;
1288
1289 /*
1290 * An MPIC with a "dcr-reg" property must be accessed that way, but
1291 * only if the kernel includes DCR support.
1292 */
1293#ifdef CONFIG_PPC_DCR
1294 if (mpic->flags & MPIC_USES_DCR)
1295 mpic->reg_type = mpic_access_dcr;
1296#else
1297 BUG_ON(mpic->flags & MPIC_USES_DCR);
1298#endif
1299
1300 /* Map the global registers */
1301 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1302 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1303
1304 /* Reset */
1305
1306 /* When using a device-node, reset requests are only honored if the MPIC
1307 * is allowed to reset.
1308 */
1309 if (!(mpic->flags & MPIC_NO_RESET)) {
1310 printk(KERN_DEBUG "mpic: Resetting\n");
1311 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1312 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1313 | MPIC_GREG_GCONF_RESET);
1314 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1315 & MPIC_GREG_GCONF_RESET)
1316 mb();
1317 }
1318
1319 /* CoreInt */
1320 if (mpic->flags & MPIC_ENABLE_COREINT)
1321 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1322 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1323 | MPIC_GREG_GCONF_COREINT);
1324
1325 if (mpic->flags & MPIC_ENABLE_MCK)
1326 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1327 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1328 | MPIC_GREG_GCONF_MCK);
1329
1330 /*
1331 * The MPIC driver will crash if there are more cores than we
1332 * can initialize, so we may as well catch that problem here.
1333 */
1334 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1335
1336 /* Map the per-CPU registers */
1337 for_each_possible_cpu(i) {
1338 unsigned int cpu = get_hard_smp_processor_id(i);
1339
1340 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1341 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1342 0x1000);
1343 }
1344
1345 /*
1346 * Read feature register. For non-ISU MPICs, num sources as well. On
1347 * ISU MPICs, sources are counted as ISUs are added
1348 */
1349 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1350
1351 /*
1352 * By default, the last source number comes from the MPIC, but the
1353 * device-tree and board support code can override it on buggy hw.
1354 * If we get passed an isu_size (multi-isu MPIC) then we use that
1355 * as a default instead of the value read from the HW.
1356 */
1357 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1358 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1359 if (isu_size)
1360 last_irq = isu_size * MPIC_MAX_ISU - 1;
1361 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1362 if (irq_count)
1363 last_irq = irq_count - 1;
1364
1365 /* Initialize main ISU if none provided */
1366 if (!isu_size) {
1367 isu_size = last_irq + 1;
1368 mpic->num_sources = isu_size;
1369 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1370 MPIC_INFO(IRQ_BASE),
1371 MPIC_INFO(IRQ_STRIDE) * isu_size);
1372 }
1373
1374 mpic->isu_size = isu_size;
1375 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1376 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1377
1378 mpic->irqhost = irq_domain_add_linear(mpic->node,
1379 last_irq + 1,
1380 &mpic_host_ops, mpic);
1381
1382 /*
1383 * FIXME: The code leaks the MPIC object and mappings here; this
1384 * is very unlikely to fail but it ought to be fixed anyways.
1385 */
1386 if (mpic->irqhost == NULL)
1387 return NULL;
1388
1389 /* Display version */
1390 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1391 case 1:
1392 vers = "1.0";
1393 break;
1394 case 2:
1395 vers = "1.2";
1396 break;
1397 case 3:
1398 vers = "1.3";
1399 break;
1400 default:
1401 vers = "<unknown>";
1402 break;
1403 }
1404 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1405 " max %d CPUs\n",
1406 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1407 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1408 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1409
1410 mpic->next = mpics;
1411 mpics = mpic;
1412
1413 if (!(mpic->flags & MPIC_SECONDARY)) {
1414 mpic_primary = mpic;
1415 irq_set_default_host(mpic->irqhost);
1416 }
1417
1418 return mpic;
1419
1420err_of_node_put:
1421 of_node_put(node);
1422 return NULL;
1423}
1424
1425void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1426 phys_addr_t paddr)
1427{
1428 unsigned int isu_first = isu_num * mpic->isu_size;
1429
1430 BUG_ON(isu_num >= MPIC_MAX_ISU);
1431
1432 mpic_map(mpic,
1433 paddr, &mpic->isus[isu_num], 0,
1434 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1435
1436 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1437 mpic->num_sources = isu_first + mpic->isu_size;
1438}
1439
1440void __init mpic_init(struct mpic *mpic)
1441{
1442 int i, cpu;
1443
1444 BUG_ON(mpic->num_sources == 0);
1445
1446 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1447
1448 /* Set current processor priority to max */
1449 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1450
1451 /* Initialize timers to our reserved vectors and mask them for now */
1452 for (i = 0; i < 4; i++) {
1453 mpic_write(mpic->tmregs,
1454 i * MPIC_INFO(TIMER_STRIDE) +
1455 MPIC_INFO(TIMER_DESTINATION),
1456 1 << hard_smp_processor_id());
1457 mpic_write(mpic->tmregs,
1458 i * MPIC_INFO(TIMER_STRIDE) +
1459 MPIC_INFO(TIMER_VECTOR_PRI),
1460 MPIC_VECPRI_MASK |
1461 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1462 (mpic->timer_vecs[0] + i));
1463 }
1464
1465 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1466 mpic_test_broken_ipi(mpic);
1467 for (i = 0; i < 4; i++) {
1468 mpic_ipi_write(i,
1469 MPIC_VECPRI_MASK |
1470 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1471 (mpic->ipi_vecs[0] + i));
1472 }
1473
1474 /* Do the HT PIC fixups on U3 broken mpic */
1475 DBG("MPIC flags: %x\n", mpic->flags);
1476 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1477 mpic_scan_ht_pics(mpic);
1478 mpic_u3msi_init(mpic);
1479 }
1480
1481 mpic_pasemi_msi_init(mpic);
1482
1483 cpu = mpic_processor_id(mpic);
1484
1485 if (!(mpic->flags & MPIC_NO_RESET)) {
1486 for (i = 0; i < mpic->num_sources; i++) {
1487 /* start with vector = source number, and masked */
1488 u32 vecpri = MPIC_VECPRI_MASK | i |
1489 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1490
1491 /* check if protected */
1492 if (mpic->protected && test_bit(i, mpic->protected))
1493 continue;
1494 /* init hw */
1495 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1496 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1497 }
1498 }
1499
1500 /* Init spurious vector */
1501 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1502
1503 /* Disable 8259 passthrough, if supported */
1504 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1505 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1506 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1507 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1508
1509 if (mpic->flags & MPIC_NO_BIAS)
1510 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1511 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1512 | MPIC_GREG_GCONF_NO_BIAS);
1513
1514 /* Set current processor priority to 0 */
1515 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1516
1517#ifdef CONFIG_PM
1518 /* allocate memory to save mpic state */
1519 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1520 GFP_KERNEL);
1521 BUG_ON(mpic->save_data == NULL);
1522#endif
1523
1524 /* Check if this MPIC is chained from a parent interrupt controller */
1525 if (mpic->flags & MPIC_SECONDARY) {
1526 int virq = irq_of_parse_and_map(mpic->node, 0);
1527 if (virq != NO_IRQ) {
1528 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1529 mpic->node->full_name, virq);
1530 irq_set_handler_data(virq, mpic);
1531 irq_set_chained_handler(virq, &mpic_cascade);
1532 }
1533 }
1534}
1535
1536void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1537{
1538 u32 v;
1539
1540 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1541 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1542 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1543 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1544}
1545
1546void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1547{
1548 unsigned long flags;
1549 u32 v;
1550
1551 raw_spin_lock_irqsave(&mpic_lock, flags);
1552 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1553 if (enable)
1554 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1555 else
1556 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1557 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1558 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1559}
1560
1561void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1562{
1563 struct mpic *mpic = mpic_find(irq);
1564 unsigned int src = virq_to_hw(irq);
1565 unsigned long flags;
1566 u32 reg;
1567
1568 if (!mpic)
1569 return;
1570
1571 raw_spin_lock_irqsave(&mpic_lock, flags);
1572 if (mpic_is_ipi(mpic, src)) {
1573 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1574 ~MPIC_VECPRI_PRIORITY_MASK;
1575 mpic_ipi_write(src - mpic->ipi_vecs[0],
1576 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1577 } else if (mpic_is_tm(mpic, src)) {
1578 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1579 ~MPIC_VECPRI_PRIORITY_MASK;
1580 mpic_tm_write(src - mpic->timer_vecs[0],
1581 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1582 } else {
1583 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1584 & ~MPIC_VECPRI_PRIORITY_MASK;
1585 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1586 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1587 }
1588 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1589}
1590
1591void mpic_setup_this_cpu(void)
1592{
1593#ifdef CONFIG_SMP
1594 struct mpic *mpic = mpic_primary;
1595 unsigned long flags;
1596 u32 msk = 1 << hard_smp_processor_id();
1597 unsigned int i;
1598
1599 BUG_ON(mpic == NULL);
1600
1601 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1602
1603 raw_spin_lock_irqsave(&mpic_lock, flags);
1604
1605 /* let the mpic know we want intrs. default affinity is 0xffffffff
1606 * until changed via /proc. That's how it's done on x86. If we want
1607 * it differently, then we should make sure we also change the default
1608 * values of irq_desc[].affinity in irq.c.
1609 */
1610 if (distribute_irqs) {
1611 for (i = 0; i < mpic->num_sources ; i++)
1612 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1613 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1614 }
1615
1616 /* Set current processor priority to 0 */
1617 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1618
1619 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1620#endif /* CONFIG_SMP */
1621}
1622
1623int mpic_cpu_get_priority(void)
1624{
1625 struct mpic *mpic = mpic_primary;
1626
1627 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1628}
1629
1630void mpic_cpu_set_priority(int prio)
1631{
1632 struct mpic *mpic = mpic_primary;
1633
1634 prio &= MPIC_CPU_TASKPRI_MASK;
1635 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1636}
1637
1638void mpic_teardown_this_cpu(int secondary)
1639{
1640 struct mpic *mpic = mpic_primary;
1641 unsigned long flags;
1642 u32 msk = 1 << hard_smp_processor_id();
1643 unsigned int i;
1644
1645 BUG_ON(mpic == NULL);
1646
1647 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1648 raw_spin_lock_irqsave(&mpic_lock, flags);
1649
1650 /* let the mpic know we don't want intrs. */
1651 for (i = 0; i < mpic->num_sources ; i++)
1652 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1653 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1654
1655 /* Set current processor priority to max */
1656 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1657 /* We need to EOI the IPI since not all platforms reset the MPIC
1658 * on boot and new interrupts wouldn't get delivered otherwise.
1659 */
1660 mpic_eoi(mpic);
1661
1662 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1663}
1664
1665
1666static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1667{
1668 u32 src;
1669
1670 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1671#ifdef DEBUG_LOW
1672 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1673#endif
1674 if (unlikely(src == mpic->spurious_vec)) {
1675 if (mpic->flags & MPIC_SPV_EOI)
1676 mpic_eoi(mpic);
1677 return NO_IRQ;
1678 }
1679 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1680 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1681 mpic->name, (int)src);
1682 mpic_eoi(mpic);
1683 return NO_IRQ;
1684 }
1685
1686 return irq_linear_revmap(mpic->irqhost, src);
1687}
1688
1689unsigned int mpic_get_one_irq(struct mpic *mpic)
1690{
1691 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1692}
1693
1694unsigned int mpic_get_irq(void)
1695{
1696 struct mpic *mpic = mpic_primary;
1697
1698 BUG_ON(mpic == NULL);
1699
1700 return mpic_get_one_irq(mpic);
1701}
1702
1703unsigned int mpic_get_coreint_irq(void)
1704{
1705#ifdef CONFIG_BOOKE
1706 struct mpic *mpic = mpic_primary;
1707 u32 src;
1708
1709 BUG_ON(mpic == NULL);
1710
1711 src = mfspr(SPRN_EPR);
1712
1713 if (unlikely(src == mpic->spurious_vec)) {
1714 if (mpic->flags & MPIC_SPV_EOI)
1715 mpic_eoi(mpic);
1716 return NO_IRQ;
1717 }
1718 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1719 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1720 mpic->name, (int)src);
1721 return NO_IRQ;
1722 }
1723
1724 return irq_linear_revmap(mpic->irqhost, src);
1725#else
1726 return NO_IRQ;
1727#endif
1728}
1729
1730unsigned int mpic_get_mcirq(void)
1731{
1732 struct mpic *mpic = mpic_primary;
1733
1734 BUG_ON(mpic == NULL);
1735
1736 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1737}
1738
1739#ifdef CONFIG_SMP
1740void mpic_request_ipis(void)
1741{
1742 struct mpic *mpic = mpic_primary;
1743 int i;
1744 BUG_ON(mpic == NULL);
1745
1746 printk(KERN_INFO "mpic: requesting IPIs...\n");
1747
1748 for (i = 0; i < 4; i++) {
1749 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1750 mpic->ipi_vecs[0] + i);
1751 if (vipi == NO_IRQ) {
1752 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1753 continue;
1754 }
1755 smp_request_message_ipi(vipi, i);
1756 }
1757}
1758
1759void smp_mpic_message_pass(int cpu, int msg)
1760{
1761 struct mpic *mpic = mpic_primary;
1762 u32 physmask;
1763
1764 BUG_ON(mpic == NULL);
1765
1766 /* make sure we're sending something that translates to an IPI */
1767 if ((unsigned int)msg > 3) {
1768 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1769 smp_processor_id(), msg);
1770 return;
1771 }
1772
1773#ifdef DEBUG_IPI
1774 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1775#endif
1776
1777 physmask = 1 << get_hard_smp_processor_id(cpu);
1778
1779 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1780 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1781}
1782
1783int __init smp_mpic_probe(void)
1784{
1785 int nr_cpus;
1786
1787 DBG("smp_mpic_probe()...\n");
1788
1789 nr_cpus = cpumask_weight(cpu_possible_mask);
1790
1791 DBG("nr_cpus: %d\n", nr_cpus);
1792
1793 if (nr_cpus > 1)
1794 mpic_request_ipis();
1795
1796 return nr_cpus;
1797}
1798
1799void __devinit smp_mpic_setup_cpu(int cpu)
1800{
1801 mpic_setup_this_cpu();
1802}
1803
1804void mpic_reset_core(int cpu)
1805{
1806 struct mpic *mpic = mpic_primary;
1807 u32 pir;
1808 int cpuid = get_hard_smp_processor_id(cpu);
1809 int i;
1810
1811 /* Set target bit for core reset */
1812 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1813 pir |= (1 << cpuid);
1814 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1815 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1816
1817 /* Restore target bit after reset complete */
1818 pir &= ~(1 << cpuid);
1819 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1820 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1821
1822 /* Perform 15 EOI on each reset core to clear pending interrupts.
1823 * This is required for FSL CoreNet based devices */
1824 if (mpic->flags & MPIC_FSL) {
1825 for (i = 0; i < 15; i++) {
1826 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1827 MPIC_CPU_EOI, 0);
1828 }
1829 }
1830}
1831#endif /* CONFIG_SMP */
1832
1833#ifdef CONFIG_PM
1834static void mpic_suspend_one(struct mpic *mpic)
1835{
1836 int i;
1837
1838 for (i = 0; i < mpic->num_sources; i++) {
1839 mpic->save_data[i].vecprio =
1840 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1841 mpic->save_data[i].dest =
1842 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1843 }
1844}
1845
1846static int mpic_suspend(void)
1847{
1848 struct mpic *mpic = mpics;
1849
1850 while (mpic) {
1851 mpic_suspend_one(mpic);
1852 mpic = mpic->next;
1853 }
1854
1855 return 0;
1856}
1857
1858static void mpic_resume_one(struct mpic *mpic)
1859{
1860 int i;
1861
1862 for (i = 0; i < mpic->num_sources; i++) {
1863 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1864 mpic->save_data[i].vecprio);
1865 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1866 mpic->save_data[i].dest);
1867
1868#ifdef CONFIG_MPIC_U3_HT_IRQS
1869 if (mpic->fixups) {
1870 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1871
1872 if (fixup->base) {
1873 /* we use the lowest bit in an inverted meaning */
1874 if ((mpic->save_data[i].fixup_data & 1) == 0)
1875 continue;
1876
1877 /* Enable and configure */
1878 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1879
1880 writel(mpic->save_data[i].fixup_data & ~1,
1881 fixup->base + 4);
1882 }
1883 }
1884#endif
1885 } /* end for loop */
1886}
1887
1888static void mpic_resume(void)
1889{
1890 struct mpic *mpic = mpics;
1891
1892 while (mpic) {
1893 mpic_resume_one(mpic);
1894 mpic = mpic->next;
1895 }
1896}
1897
1898static struct syscore_ops mpic_syscore_ops = {
1899 .resume = mpic_resume,
1900 .suspend = mpic_suspend,
1901};
1902
1903static int mpic_init_sys(void)
1904{
1905 register_syscore_ops(&mpic_syscore_ops);
1906 return 0;
1907}
1908
1909device_initcall(mpic_init_sys);
1910#endif
1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/bootmem.h>
28#include <linux/spinlock.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/syscore_ops.h>
32#include <linux/ratelimit.h>
33
34#include <asm/ptrace.h>
35#include <asm/signal.h>
36#include <asm/io.h>
37#include <asm/pgtable.h>
38#include <asm/irq.h>
39#include <asm/machdep.h>
40#include <asm/mpic.h>
41#include <asm/smp.h>
42
43#include "mpic.h"
44
45#ifdef DEBUG
46#define DBG(fmt...) printk(fmt)
47#else
48#define DBG(fmt...)
49#endif
50
51struct bus_type mpic_subsys = {
52 .name = "mpic",
53 .dev_name = "mpic",
54};
55EXPORT_SYMBOL_GPL(mpic_subsys);
56
57static struct mpic *mpics;
58static struct mpic *mpic_primary;
59static DEFINE_RAW_SPINLOCK(mpic_lock);
60
61#ifdef CONFIG_PPC32 /* XXX for now */
62#ifdef CONFIG_IRQ_ALL_CPUS
63#define distribute_irqs (1)
64#else
65#define distribute_irqs (0)
66#endif
67#endif
68
69#ifdef CONFIG_MPIC_WEIRD
70static u32 mpic_infos[][MPIC_IDX_END] = {
71 [0] = { /* Original OpenPIC compatible MPIC */
72 MPIC_GREG_BASE,
73 MPIC_GREG_FEATURE_0,
74 MPIC_GREG_GLOBAL_CONF_0,
75 MPIC_GREG_VENDOR_ID,
76 MPIC_GREG_IPI_VECTOR_PRI_0,
77 MPIC_GREG_IPI_STRIDE,
78 MPIC_GREG_SPURIOUS,
79 MPIC_GREG_TIMER_FREQ,
80
81 MPIC_TIMER_BASE,
82 MPIC_TIMER_STRIDE,
83 MPIC_TIMER_CURRENT_CNT,
84 MPIC_TIMER_BASE_CNT,
85 MPIC_TIMER_VECTOR_PRI,
86 MPIC_TIMER_DESTINATION,
87
88 MPIC_CPU_BASE,
89 MPIC_CPU_STRIDE,
90 MPIC_CPU_IPI_DISPATCH_0,
91 MPIC_CPU_IPI_DISPATCH_STRIDE,
92 MPIC_CPU_CURRENT_TASK_PRI,
93 MPIC_CPU_WHOAMI,
94 MPIC_CPU_INTACK,
95 MPIC_CPU_EOI,
96 MPIC_CPU_MCACK,
97
98 MPIC_IRQ_BASE,
99 MPIC_IRQ_STRIDE,
100 MPIC_IRQ_VECTOR_PRI,
101 MPIC_VECPRI_VECTOR_MASK,
102 MPIC_VECPRI_POLARITY_POSITIVE,
103 MPIC_VECPRI_POLARITY_NEGATIVE,
104 MPIC_VECPRI_SENSE_LEVEL,
105 MPIC_VECPRI_SENSE_EDGE,
106 MPIC_VECPRI_POLARITY_MASK,
107 MPIC_VECPRI_SENSE_MASK,
108 MPIC_IRQ_DESTINATION
109 },
110 [1] = { /* Tsi108/109 PIC */
111 TSI108_GREG_BASE,
112 TSI108_GREG_FEATURE_0,
113 TSI108_GREG_GLOBAL_CONF_0,
114 TSI108_GREG_VENDOR_ID,
115 TSI108_GREG_IPI_VECTOR_PRI_0,
116 TSI108_GREG_IPI_STRIDE,
117 TSI108_GREG_SPURIOUS,
118 TSI108_GREG_TIMER_FREQ,
119
120 TSI108_TIMER_BASE,
121 TSI108_TIMER_STRIDE,
122 TSI108_TIMER_CURRENT_CNT,
123 TSI108_TIMER_BASE_CNT,
124 TSI108_TIMER_VECTOR_PRI,
125 TSI108_TIMER_DESTINATION,
126
127 TSI108_CPU_BASE,
128 TSI108_CPU_STRIDE,
129 TSI108_CPU_IPI_DISPATCH_0,
130 TSI108_CPU_IPI_DISPATCH_STRIDE,
131 TSI108_CPU_CURRENT_TASK_PRI,
132 TSI108_CPU_WHOAMI,
133 TSI108_CPU_INTACK,
134 TSI108_CPU_EOI,
135 TSI108_CPU_MCACK,
136
137 TSI108_IRQ_BASE,
138 TSI108_IRQ_STRIDE,
139 TSI108_IRQ_VECTOR_PRI,
140 TSI108_VECPRI_VECTOR_MASK,
141 TSI108_VECPRI_POLARITY_POSITIVE,
142 TSI108_VECPRI_POLARITY_NEGATIVE,
143 TSI108_VECPRI_SENSE_LEVEL,
144 TSI108_VECPRI_SENSE_EDGE,
145 TSI108_VECPRI_POLARITY_MASK,
146 TSI108_VECPRI_SENSE_MASK,
147 TSI108_IRQ_DESTINATION
148 },
149};
150
151#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
152
153#else /* CONFIG_MPIC_WEIRD */
154
155#define MPIC_INFO(name) MPIC_##name
156
157#endif /* CONFIG_MPIC_WEIRD */
158
159static inline unsigned int mpic_processor_id(struct mpic *mpic)
160{
161 unsigned int cpu = 0;
162
163 if (!(mpic->flags & MPIC_SECONDARY))
164 cpu = hard_smp_processor_id();
165
166 return cpu;
167}
168
169/*
170 * Register accessor functions
171 */
172
173
174static inline u32 _mpic_read(enum mpic_reg_type type,
175 struct mpic_reg_bank *rb,
176 unsigned int reg)
177{
178 switch(type) {
179#ifdef CONFIG_PPC_DCR
180 case mpic_access_dcr:
181 return dcr_read(rb->dhost, reg);
182#endif
183 case mpic_access_mmio_be:
184 return in_be32(rb->base + (reg >> 2));
185 case mpic_access_mmio_le:
186 default:
187 return in_le32(rb->base + (reg >> 2));
188 }
189}
190
191static inline void _mpic_write(enum mpic_reg_type type,
192 struct mpic_reg_bank *rb,
193 unsigned int reg, u32 value)
194{
195 switch(type) {
196#ifdef CONFIG_PPC_DCR
197 case mpic_access_dcr:
198 dcr_write(rb->dhost, reg, value);
199 break;
200#endif
201 case mpic_access_mmio_be:
202 out_be32(rb->base + (reg >> 2), value);
203 break;
204 case mpic_access_mmio_le:
205 default:
206 out_le32(rb->base + (reg >> 2), value);
207 break;
208 }
209}
210
211static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
212{
213 enum mpic_reg_type type = mpic->reg_type;
214 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
215 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
216
217 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
218 type = mpic_access_mmio_be;
219 return _mpic_read(type, &mpic->gregs, offset);
220}
221
222static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
223{
224 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
225 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
226
227 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
228}
229
230static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
231{
232 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
233 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
234}
235
236static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
237{
238 unsigned int offset = mpic_tm_offset(mpic, tm) +
239 MPIC_INFO(TIMER_VECTOR_PRI);
240
241 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
242}
243
244static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
245{
246 unsigned int offset = mpic_tm_offset(mpic, tm) +
247 MPIC_INFO(TIMER_VECTOR_PRI);
248
249 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
250}
251
252static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
253{
254 unsigned int cpu = mpic_processor_id(mpic);
255
256 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
257}
258
259static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
260{
261 unsigned int cpu = mpic_processor_id(mpic);
262
263 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
264}
265
266static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
267{
268 unsigned int isu = src_no >> mpic->isu_shift;
269 unsigned int idx = src_no & mpic->isu_mask;
270 unsigned int val;
271
272 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
273 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
274#ifdef CONFIG_MPIC_BROKEN_REGREAD
275 if (reg == 0)
276 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
277 mpic->isu_reg0_shadow[src_no];
278#endif
279 return val;
280}
281
282static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
283 unsigned int reg, u32 value)
284{
285 unsigned int isu = src_no >> mpic->isu_shift;
286 unsigned int idx = src_no & mpic->isu_mask;
287
288 _mpic_write(mpic->reg_type, &mpic->isus[isu],
289 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
290
291#ifdef CONFIG_MPIC_BROKEN_REGREAD
292 if (reg == 0)
293 mpic->isu_reg0_shadow[src_no] =
294 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
295#endif
296}
297
298#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
299#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
300#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
301#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
302#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
303#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
304#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
305#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
306#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
307#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
308
309
310/*
311 * Low level utility functions
312 */
313
314
315static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
316 struct mpic_reg_bank *rb, unsigned int offset,
317 unsigned int size)
318{
319 rb->base = ioremap(phys_addr + offset, size);
320 BUG_ON(rb->base == NULL);
321}
322
323#ifdef CONFIG_PPC_DCR
324static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
325 unsigned int offset, unsigned int size)
326{
327 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
328 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
329 BUG_ON(!DCR_MAP_OK(rb->dhost));
330}
331
332static inline void mpic_map(struct mpic *mpic,
333 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
334 unsigned int offset, unsigned int size)
335{
336 if (mpic->flags & MPIC_USES_DCR)
337 _mpic_map_dcr(mpic, rb, offset, size);
338 else
339 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
340}
341#else /* CONFIG_PPC_DCR */
342#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
343#endif /* !CONFIG_PPC_DCR */
344
345
346
347/* Check if we have one of those nice broken MPICs with a flipped endian on
348 * reads from IPI registers
349 */
350static void __init mpic_test_broken_ipi(struct mpic *mpic)
351{
352 u32 r;
353
354 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
355 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
356
357 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
358 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
359 mpic->flags |= MPIC_BROKEN_IPI;
360 }
361}
362
363#ifdef CONFIG_MPIC_U3_HT_IRQS
364
365/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
366 * to force the edge setting on the MPIC and do the ack workaround.
367 */
368static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
369{
370 if (source >= 128 || !mpic->fixups)
371 return 0;
372 return mpic->fixups[source].base != NULL;
373}
374
375
376static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
377{
378 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
379
380 if (fixup->applebase) {
381 unsigned int soff = (fixup->index >> 3) & ~3;
382 unsigned int mask = 1U << (fixup->index & 0x1f);
383 writel(mask, fixup->applebase + soff);
384 } else {
385 raw_spin_lock(&mpic->fixup_lock);
386 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
387 writel(fixup->data, fixup->base + 4);
388 raw_spin_unlock(&mpic->fixup_lock);
389 }
390}
391
392static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
393 bool level)
394{
395 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
396 unsigned long flags;
397 u32 tmp;
398
399 if (fixup->base == NULL)
400 return;
401
402 DBG("startup_ht_interrupt(0x%x) index: %d\n",
403 source, fixup->index);
404 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 /* Enable and configure */
406 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
407 tmp = readl(fixup->base + 4);
408 tmp &= ~(0x23U);
409 if (level)
410 tmp |= 0x22;
411 writel(tmp, fixup->base + 4);
412 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
413
414#ifdef CONFIG_PM
415 /* use the lowest bit inverted to the actual HW,
416 * set if this fixup was enabled, clear otherwise */
417 mpic->save_data[source].fixup_data = tmp | 1;
418#endif
419}
420
421static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
422{
423 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
424 unsigned long flags;
425 u32 tmp;
426
427 if (fixup->base == NULL)
428 return;
429
430 DBG("shutdown_ht_interrupt(0x%x)\n", source);
431
432 /* Disable */
433 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
434 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
435 tmp = readl(fixup->base + 4);
436 tmp |= 1;
437 writel(tmp, fixup->base + 4);
438 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
439
440#ifdef CONFIG_PM
441 /* use the lowest bit inverted to the actual HW,
442 * set if this fixup was enabled, clear otherwise */
443 mpic->save_data[source].fixup_data = tmp & ~1;
444#endif
445}
446
447#ifdef CONFIG_PCI_MSI
448static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
449 unsigned int devfn)
450{
451 u8 __iomem *base;
452 u8 pos, flags;
453 u64 addr = 0;
454
455 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
456 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
457 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
458 if (id == PCI_CAP_ID_HT) {
459 id = readb(devbase + pos + 3);
460 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
461 break;
462 }
463 }
464
465 if (pos == 0)
466 return;
467
468 base = devbase + pos;
469
470 flags = readb(base + HT_MSI_FLAGS);
471 if (!(flags & HT_MSI_FLAGS_FIXED)) {
472 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
473 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
474 }
475
476 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
477 PCI_SLOT(devfn), PCI_FUNC(devfn),
478 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
479
480 if (!(flags & HT_MSI_FLAGS_ENABLE))
481 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
482}
483#else
484static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
485 unsigned int devfn)
486{
487 return;
488}
489#endif
490
491static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
492 unsigned int devfn, u32 vdid)
493{
494 int i, irq, n;
495 u8 __iomem *base;
496 u32 tmp;
497 u8 pos;
498
499 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
500 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
501 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
502 if (id == PCI_CAP_ID_HT) {
503 id = readb(devbase + pos + 3);
504 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
505 break;
506 }
507 }
508 if (pos == 0)
509 return;
510
511 base = devbase + pos;
512 writeb(0x01, base + 2);
513 n = (readl(base + 4) >> 16) & 0xff;
514
515 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
516 " has %d irqs\n",
517 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
518
519 for (i = 0; i <= n; i++) {
520 writeb(0x10 + 2 * i, base + 2);
521 tmp = readl(base + 4);
522 irq = (tmp >> 16) & 0xff;
523 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
524 /* mask it , will be unmasked later */
525 tmp |= 0x1;
526 writel(tmp, base + 4);
527 mpic->fixups[irq].index = i;
528 mpic->fixups[irq].base = base;
529 /* Apple HT PIC has a non-standard way of doing EOIs */
530 if ((vdid & 0xffff) == 0x106b)
531 mpic->fixups[irq].applebase = devbase + 0x60;
532 else
533 mpic->fixups[irq].applebase = NULL;
534 writeb(0x11 + 2 * i, base + 2);
535 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
536 }
537}
538
539
540static void __init mpic_scan_ht_pics(struct mpic *mpic)
541{
542 unsigned int devfn;
543 u8 __iomem *cfgspace;
544
545 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
546
547 /* Allocate fixups array */
548 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
549 BUG_ON(mpic->fixups == NULL);
550
551 /* Init spinlock */
552 raw_spin_lock_init(&mpic->fixup_lock);
553
554 /* Map U3 config space. We assume all IO-APICs are on the primary bus
555 * so we only need to map 64kB.
556 */
557 cfgspace = ioremap(0xf2000000, 0x10000);
558 BUG_ON(cfgspace == NULL);
559
560 /* Now we scan all slots. We do a very quick scan, we read the header
561 * type, vendor ID and device ID only, that's plenty enough
562 */
563 for (devfn = 0; devfn < 0x100; devfn++) {
564 u8 __iomem *devbase = cfgspace + (devfn << 8);
565 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
566 u32 l = readl(devbase + PCI_VENDOR_ID);
567 u16 s;
568
569 DBG("devfn %x, l: %x\n", devfn, l);
570
571 /* If no device, skip */
572 if (l == 0xffffffff || l == 0x00000000 ||
573 l == 0x0000ffff || l == 0xffff0000)
574 goto next;
575 /* Check if is supports capability lists */
576 s = readw(devbase + PCI_STATUS);
577 if (!(s & PCI_STATUS_CAP_LIST))
578 goto next;
579
580 mpic_scan_ht_pic(mpic, devbase, devfn, l);
581 mpic_scan_ht_msi(mpic, devbase, devfn);
582
583 next:
584 /* next device, if function 0 */
585 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
586 devfn += 7;
587 }
588}
589
590#else /* CONFIG_MPIC_U3_HT_IRQS */
591
592static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
593{
594 return 0;
595}
596
597static void __init mpic_scan_ht_pics(struct mpic *mpic)
598{
599}
600
601#endif /* CONFIG_MPIC_U3_HT_IRQS */
602
603/* Find an mpic associated with a given linux interrupt */
604static struct mpic *mpic_find(unsigned int irq)
605{
606 if (irq < NUM_ISA_INTERRUPTS)
607 return NULL;
608
609 return irq_get_chip_data(irq);
610}
611
612/* Determine if the linux irq is an IPI */
613static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
614{
615 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
616}
617
618/* Determine if the linux irq is a timer */
619static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
620{
621 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
622}
623
624/* Convert a cpu mask from logical to physical cpu numbers. */
625static inline u32 mpic_physmask(u32 cpumask)
626{
627 int i;
628 u32 mask = 0;
629
630 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
631 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
632 return mask;
633}
634
635#ifdef CONFIG_SMP
636/* Get the mpic structure from the IPI number */
637static inline struct mpic * mpic_from_ipi(struct irq_data *d)
638{
639 return irq_data_get_irq_chip_data(d);
640}
641#endif
642
643/* Get the mpic structure from the irq number */
644static inline struct mpic * mpic_from_irq(unsigned int irq)
645{
646 return irq_get_chip_data(irq);
647}
648
649/* Get the mpic structure from the irq data */
650static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
651{
652 return irq_data_get_irq_chip_data(d);
653}
654
655/* Send an EOI */
656static inline void mpic_eoi(struct mpic *mpic)
657{
658 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
659 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
660}
661
662/*
663 * Linux descriptor level callbacks
664 */
665
666
667void mpic_unmask_irq(struct irq_data *d)
668{
669 unsigned int loops = 100000;
670 struct mpic *mpic = mpic_from_irq_data(d);
671 unsigned int src = irqd_to_hwirq(d);
672
673 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
674
675 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
676 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
677 ~MPIC_VECPRI_MASK);
678 /* make sure mask gets to controller before we return to user */
679 do {
680 if (!loops--) {
681 printk(KERN_ERR "%s: timeout on hwirq %u\n",
682 __func__, src);
683 break;
684 }
685 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
686}
687
688void mpic_mask_irq(struct irq_data *d)
689{
690 unsigned int loops = 100000;
691 struct mpic *mpic = mpic_from_irq_data(d);
692 unsigned int src = irqd_to_hwirq(d);
693
694 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
695
696 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
697 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
698 MPIC_VECPRI_MASK);
699
700 /* make sure mask gets to controller before we return to user */
701 do {
702 if (!loops--) {
703 printk(KERN_ERR "%s: timeout on hwirq %u\n",
704 __func__, src);
705 break;
706 }
707 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
708}
709
710void mpic_end_irq(struct irq_data *d)
711{
712 struct mpic *mpic = mpic_from_irq_data(d);
713
714#ifdef DEBUG_IRQ
715 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
716#endif
717 /* We always EOI on end_irq() even for edge interrupts since that
718 * should only lower the priority, the MPIC should have properly
719 * latched another edge interrupt coming in anyway
720 */
721
722 mpic_eoi(mpic);
723}
724
725#ifdef CONFIG_MPIC_U3_HT_IRQS
726
727static void mpic_unmask_ht_irq(struct irq_data *d)
728{
729 struct mpic *mpic = mpic_from_irq_data(d);
730 unsigned int src = irqd_to_hwirq(d);
731
732 mpic_unmask_irq(d);
733
734 if (irqd_is_level_type(d))
735 mpic_ht_end_irq(mpic, src);
736}
737
738static unsigned int mpic_startup_ht_irq(struct irq_data *d)
739{
740 struct mpic *mpic = mpic_from_irq_data(d);
741 unsigned int src = irqd_to_hwirq(d);
742
743 mpic_unmask_irq(d);
744 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
745
746 return 0;
747}
748
749static void mpic_shutdown_ht_irq(struct irq_data *d)
750{
751 struct mpic *mpic = mpic_from_irq_data(d);
752 unsigned int src = irqd_to_hwirq(d);
753
754 mpic_shutdown_ht_interrupt(mpic, src);
755 mpic_mask_irq(d);
756}
757
758static void mpic_end_ht_irq(struct irq_data *d)
759{
760 struct mpic *mpic = mpic_from_irq_data(d);
761 unsigned int src = irqd_to_hwirq(d);
762
763#ifdef DEBUG_IRQ
764 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
765#endif
766 /* We always EOI on end_irq() even for edge interrupts since that
767 * should only lower the priority, the MPIC should have properly
768 * latched another edge interrupt coming in anyway
769 */
770
771 if (irqd_is_level_type(d))
772 mpic_ht_end_irq(mpic, src);
773 mpic_eoi(mpic);
774}
775#endif /* !CONFIG_MPIC_U3_HT_IRQS */
776
777#ifdef CONFIG_SMP
778
779static void mpic_unmask_ipi(struct irq_data *d)
780{
781 struct mpic *mpic = mpic_from_ipi(d);
782 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
783
784 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
785 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
786}
787
788static void mpic_mask_ipi(struct irq_data *d)
789{
790 /* NEVER disable an IPI... that's just plain wrong! */
791}
792
793static void mpic_end_ipi(struct irq_data *d)
794{
795 struct mpic *mpic = mpic_from_ipi(d);
796
797 /*
798 * IPIs are marked IRQ_PER_CPU. This has the side effect of
799 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
800 * applying to them. We EOI them late to avoid re-entering.
801 */
802 mpic_eoi(mpic);
803}
804
805#endif /* CONFIG_SMP */
806
807static void mpic_unmask_tm(struct irq_data *d)
808{
809 struct mpic *mpic = mpic_from_irq_data(d);
810 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
811
812 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
813 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
814 mpic_tm_read(src);
815}
816
817static void mpic_mask_tm(struct irq_data *d)
818{
819 struct mpic *mpic = mpic_from_irq_data(d);
820 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
821
822 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
823 mpic_tm_read(src);
824}
825
826int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
827 bool force)
828{
829 struct mpic *mpic = mpic_from_irq_data(d);
830 unsigned int src = irqd_to_hwirq(d);
831
832 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
833 int cpuid = irq_choose_cpu(cpumask);
834
835 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
836 } else {
837 u32 mask = cpumask_bits(cpumask)[0];
838
839 mask &= cpumask_bits(cpu_online_mask)[0];
840
841 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
842 mpic_physmask(mask));
843 }
844
845 return IRQ_SET_MASK_OK;
846}
847
848static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
849{
850 /* Now convert sense value */
851 switch(type & IRQ_TYPE_SENSE_MASK) {
852 case IRQ_TYPE_EDGE_RISING:
853 return MPIC_INFO(VECPRI_SENSE_EDGE) |
854 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855 case IRQ_TYPE_EDGE_FALLING:
856 case IRQ_TYPE_EDGE_BOTH:
857 return MPIC_INFO(VECPRI_SENSE_EDGE) |
858 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
859 case IRQ_TYPE_LEVEL_HIGH:
860 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
861 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
862 case IRQ_TYPE_LEVEL_LOW:
863 default:
864 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
865 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
866 }
867}
868
869int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
870{
871 struct mpic *mpic = mpic_from_irq_data(d);
872 unsigned int src = irqd_to_hwirq(d);
873 unsigned int vecpri, vold, vnew;
874
875 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
876 mpic, d->irq, src, flow_type);
877
878 if (src >= mpic->num_sources)
879 return -EINVAL;
880
881 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
882
883 /* We don't support "none" type */
884 if (flow_type == IRQ_TYPE_NONE)
885 flow_type = IRQ_TYPE_DEFAULT;
886
887 /* Default: read HW settings */
888 if (flow_type == IRQ_TYPE_DEFAULT) {
889 int vold_ps;
890
891 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
892 MPIC_INFO(VECPRI_SENSE_MASK));
893
894 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
895 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
896 flow_type = IRQ_TYPE_EDGE_RISING;
897 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
898 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
899 flow_type = IRQ_TYPE_EDGE_FALLING;
900 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
901 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
902 flow_type = IRQ_TYPE_LEVEL_HIGH;
903 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
904 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
905 flow_type = IRQ_TYPE_LEVEL_LOW;
906 else
907 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
908 }
909
910 /* Apply to irq desc */
911 irqd_set_trigger_type(d, flow_type);
912
913 /* Apply to HW */
914 if (mpic_is_ht_interrupt(mpic, src))
915 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
916 MPIC_VECPRI_SENSE_EDGE;
917 else
918 vecpri = mpic_type_to_vecpri(mpic, flow_type);
919
920 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
921 MPIC_INFO(VECPRI_SENSE_MASK));
922 vnew |= vecpri;
923 if (vold != vnew)
924 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
925
926 return IRQ_SET_MASK_OK_NOCOPY;
927}
928
929static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
930{
931 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
932 struct mpic *mpic = mpic_from_irq_data(d);
933
934 if (!(mpic->flags & MPIC_FSL))
935 return -ENXIO;
936
937 if (on)
938 desc->action->flags |= IRQF_NO_SUSPEND;
939 else
940 desc->action->flags &= ~IRQF_NO_SUSPEND;
941
942 return 0;
943}
944
945void mpic_set_vector(unsigned int virq, unsigned int vector)
946{
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
949 unsigned int vecpri;
950
951 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
952 mpic, virq, src, vector);
953
954 if (src >= mpic->num_sources)
955 return;
956
957 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
958 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
959 vecpri |= vector;
960 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
961}
962
963void mpic_set_destination(unsigned int virq, unsigned int cpuid)
964{
965 struct mpic *mpic = mpic_from_irq(virq);
966 unsigned int src = virq_to_hw(virq);
967
968 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
969 mpic, virq, src, cpuid);
970
971 if (src >= mpic->num_sources)
972 return;
973
974 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
975}
976
977static struct irq_chip mpic_irq_chip = {
978 .irq_mask = mpic_mask_irq,
979 .irq_unmask = mpic_unmask_irq,
980 .irq_eoi = mpic_end_irq,
981 .irq_set_type = mpic_set_irq_type,
982 .irq_set_wake = mpic_irq_set_wake,
983};
984
985#ifdef CONFIG_SMP
986static struct irq_chip mpic_ipi_chip = {
987 .irq_mask = mpic_mask_ipi,
988 .irq_unmask = mpic_unmask_ipi,
989 .irq_eoi = mpic_end_ipi,
990};
991#endif /* CONFIG_SMP */
992
993static struct irq_chip mpic_tm_chip = {
994 .irq_mask = mpic_mask_tm,
995 .irq_unmask = mpic_unmask_tm,
996 .irq_eoi = mpic_end_irq,
997 .irq_set_wake = mpic_irq_set_wake,
998};
999
1000#ifdef CONFIG_MPIC_U3_HT_IRQS
1001static struct irq_chip mpic_irq_ht_chip = {
1002 .irq_startup = mpic_startup_ht_irq,
1003 .irq_shutdown = mpic_shutdown_ht_irq,
1004 .irq_mask = mpic_mask_irq,
1005 .irq_unmask = mpic_unmask_ht_irq,
1006 .irq_eoi = mpic_end_ht_irq,
1007 .irq_set_type = mpic_set_irq_type,
1008};
1009#endif /* CONFIG_MPIC_U3_HT_IRQS */
1010
1011
1012static int mpic_host_match(struct irq_domain *h, struct device_node *node)
1013{
1014 /* Exact match, unless mpic node is NULL */
1015 return h->of_node == NULL || h->of_node == node;
1016}
1017
1018static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1019 irq_hw_number_t hw)
1020{
1021 struct mpic *mpic = h->host_data;
1022 struct irq_chip *chip;
1023
1024 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1025
1026 if (hw == mpic->spurious_vec)
1027 return -EINVAL;
1028 if (mpic->protected && test_bit(hw, mpic->protected)) {
1029 pr_warning("mpic: Mapping of source 0x%x failed, "
1030 "source protected by firmware !\n",\
1031 (unsigned int)hw);
1032 return -EPERM;
1033 }
1034
1035#ifdef CONFIG_SMP
1036 else if (hw >= mpic->ipi_vecs[0]) {
1037 WARN_ON(mpic->flags & MPIC_SECONDARY);
1038
1039 DBG("mpic: mapping as IPI\n");
1040 irq_set_chip_data(virq, mpic);
1041 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1042 handle_percpu_irq);
1043 return 0;
1044 }
1045#endif /* CONFIG_SMP */
1046
1047 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1048 WARN_ON(mpic->flags & MPIC_SECONDARY);
1049
1050 DBG("mpic: mapping as timer\n");
1051 irq_set_chip_data(virq, mpic);
1052 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1053 handle_fasteoi_irq);
1054 return 0;
1055 }
1056
1057 if (mpic_map_error_int(mpic, virq, hw))
1058 return 0;
1059
1060 if (hw >= mpic->num_sources) {
1061 pr_warning("mpic: Mapping of source 0x%x failed, "
1062 "source out of range !\n",\
1063 (unsigned int)hw);
1064 return -EINVAL;
1065 }
1066
1067 mpic_msi_reserve_hwirq(mpic, hw);
1068
1069 /* Default chip */
1070 chip = &mpic->hc_irq;
1071
1072#ifdef CONFIG_MPIC_U3_HT_IRQS
1073 /* Check for HT interrupts, override vecpri */
1074 if (mpic_is_ht_interrupt(mpic, hw))
1075 chip = &mpic->hc_ht_irq;
1076#endif /* CONFIG_MPIC_U3_HT_IRQS */
1077
1078 DBG("mpic: mapping to irq chip @%p\n", chip);
1079
1080 irq_set_chip_data(virq, mpic);
1081 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1082
1083 /* Set default irq type */
1084 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1085
1086 /* If the MPIC was reset, then all vectors have already been
1087 * initialized. Otherwise, a per source lazy initialization
1088 * is done here.
1089 */
1090 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1091 int cpu;
1092
1093 preempt_disable();
1094 cpu = mpic_processor_id(mpic);
1095 preempt_enable();
1096
1097 mpic_set_vector(virq, hw);
1098 mpic_set_destination(virq, cpu);
1099 mpic_irq_set_priority(virq, 8);
1100 }
1101
1102 return 0;
1103}
1104
1105static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1106 const u32 *intspec, unsigned int intsize,
1107 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1108
1109{
1110 struct mpic *mpic = h->host_data;
1111 static unsigned char map_mpic_senses[4] = {
1112 IRQ_TYPE_EDGE_RISING,
1113 IRQ_TYPE_LEVEL_LOW,
1114 IRQ_TYPE_LEVEL_HIGH,
1115 IRQ_TYPE_EDGE_FALLING,
1116 };
1117
1118 *out_hwirq = intspec[0];
1119 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1120 /*
1121 * Freescale MPIC with extended intspec:
1122 * First two cells are as usual. Third specifies
1123 * an "interrupt type". Fourth is type-specific data.
1124 *
1125 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1126 */
1127 switch (intspec[2]) {
1128 case 0:
1129 break;
1130 case 1:
1131 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1132 break;
1133
1134 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1135 return -EINVAL;
1136
1137 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1138
1139 break;
1140 case 2:
1141 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1142 return -EINVAL;
1143
1144 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1145 break;
1146 case 3:
1147 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1148 return -EINVAL;
1149
1150 *out_hwirq = mpic->timer_vecs[intspec[0]];
1151 break;
1152 default:
1153 pr_debug("%s: unknown irq type %u\n",
1154 __func__, intspec[2]);
1155 return -EINVAL;
1156 }
1157
1158 *out_flags = map_mpic_senses[intspec[1] & 3];
1159 } else if (intsize > 1) {
1160 u32 mask = 0x3;
1161
1162 /* Apple invented a new race of encoding on machines with
1163 * an HT APIC. They encode, among others, the index within
1164 * the HT APIC. We don't care about it here since thankfully,
1165 * it appears that they have the APIC already properly
1166 * configured, and thus our current fixup code that reads the
1167 * APIC config works fine. However, we still need to mask out
1168 * bits in the specifier to make sure we only get bit 0 which
1169 * is the level/edge bit (the only sense bit exposed by Apple),
1170 * as their bit 1 means something else.
1171 */
1172 if (machine_is(powermac))
1173 mask = 0x1;
1174 *out_flags = map_mpic_senses[intspec[1] & mask];
1175 } else
1176 *out_flags = IRQ_TYPE_NONE;
1177
1178 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1179 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1180
1181 return 0;
1182}
1183
1184/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1185static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1186{
1187 struct irq_chip *chip = irq_desc_get_chip(desc);
1188 struct mpic *mpic = irq_desc_get_handler_data(desc);
1189 unsigned int virq;
1190
1191 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1192
1193 virq = mpic_get_one_irq(mpic);
1194 if (virq)
1195 generic_handle_irq(virq);
1196
1197 chip->irq_eoi(&desc->irq_data);
1198}
1199
1200static struct irq_domain_ops mpic_host_ops = {
1201 .match = mpic_host_match,
1202 .map = mpic_host_map,
1203 .xlate = mpic_host_xlate,
1204};
1205
1206static u32 fsl_mpic_get_version(struct mpic *mpic)
1207{
1208 u32 brr1;
1209
1210 if (!(mpic->flags & MPIC_FSL))
1211 return 0;
1212
1213 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1214 MPIC_FSL_BRR1);
1215
1216 return brr1 & MPIC_FSL_BRR1_VER;
1217}
1218
1219/*
1220 * Exported functions
1221 */
1222
1223u32 fsl_mpic_primary_get_version(void)
1224{
1225 struct mpic *mpic = mpic_primary;
1226
1227 if (mpic)
1228 return fsl_mpic_get_version(mpic);
1229
1230 return 0;
1231}
1232
1233struct mpic * __init mpic_alloc(struct device_node *node,
1234 phys_addr_t phys_addr,
1235 unsigned int flags,
1236 unsigned int isu_size,
1237 unsigned int irq_count,
1238 const char *name)
1239{
1240 int i, psize, intvec_top;
1241 struct mpic *mpic;
1242 u32 greg_feature;
1243 const char *vers;
1244 const u32 *psrc;
1245 u32 last_irq;
1246 u32 fsl_version = 0;
1247
1248 /* Default MPIC search parameters */
1249 static const struct of_device_id __initconst mpic_device_id[] = {
1250 { .type = "open-pic", },
1251 { .compatible = "open-pic", },
1252 {},
1253 };
1254
1255 /*
1256 * If we were not passed a device-tree node, then perform the default
1257 * search for standardized a standardized OpenPIC.
1258 */
1259 if (node) {
1260 node = of_node_get(node);
1261 } else {
1262 node = of_find_matching_node(NULL, mpic_device_id);
1263 if (!node)
1264 return NULL;
1265 }
1266
1267 /* Pick the physical address from the device tree if unspecified */
1268 if (!phys_addr) {
1269 /* Check if it is DCR-based */
1270 if (of_get_property(node, "dcr-reg", NULL)) {
1271 flags |= MPIC_USES_DCR;
1272 } else {
1273 struct resource r;
1274 if (of_address_to_resource(node, 0, &r))
1275 goto err_of_node_put;
1276 phys_addr = r.start;
1277 }
1278 }
1279
1280 /* Read extra device-tree properties into the flags variable */
1281 if (of_get_property(node, "big-endian", NULL))
1282 flags |= MPIC_BIG_ENDIAN;
1283 if (of_get_property(node, "pic-no-reset", NULL))
1284 flags |= MPIC_NO_RESET;
1285 if (of_get_property(node, "single-cpu-affinity", NULL))
1286 flags |= MPIC_SINGLE_DEST_CPU;
1287 if (of_device_is_compatible(node, "fsl,mpic"))
1288 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1289
1290 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1291 if (mpic == NULL)
1292 goto err_of_node_put;
1293
1294 mpic->name = name;
1295 mpic->node = node;
1296 mpic->paddr = phys_addr;
1297 mpic->flags = flags;
1298
1299 mpic->hc_irq = mpic_irq_chip;
1300 mpic->hc_irq.name = name;
1301 if (!(mpic->flags & MPIC_SECONDARY))
1302 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1303#ifdef CONFIG_MPIC_U3_HT_IRQS
1304 mpic->hc_ht_irq = mpic_irq_ht_chip;
1305 mpic->hc_ht_irq.name = name;
1306 if (!(mpic->flags & MPIC_SECONDARY))
1307 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1308#endif /* CONFIG_MPIC_U3_HT_IRQS */
1309
1310#ifdef CONFIG_SMP
1311 mpic->hc_ipi = mpic_ipi_chip;
1312 mpic->hc_ipi.name = name;
1313#endif /* CONFIG_SMP */
1314
1315 mpic->hc_tm = mpic_tm_chip;
1316 mpic->hc_tm.name = name;
1317
1318 mpic->num_sources = 0; /* so far */
1319
1320 if (mpic->flags & MPIC_LARGE_VECTORS)
1321 intvec_top = 2047;
1322 else
1323 intvec_top = 255;
1324
1325 mpic->timer_vecs[0] = intvec_top - 12;
1326 mpic->timer_vecs[1] = intvec_top - 11;
1327 mpic->timer_vecs[2] = intvec_top - 10;
1328 mpic->timer_vecs[3] = intvec_top - 9;
1329 mpic->timer_vecs[4] = intvec_top - 8;
1330 mpic->timer_vecs[5] = intvec_top - 7;
1331 mpic->timer_vecs[6] = intvec_top - 6;
1332 mpic->timer_vecs[7] = intvec_top - 5;
1333 mpic->ipi_vecs[0] = intvec_top - 4;
1334 mpic->ipi_vecs[1] = intvec_top - 3;
1335 mpic->ipi_vecs[2] = intvec_top - 2;
1336 mpic->ipi_vecs[3] = intvec_top - 1;
1337 mpic->spurious_vec = intvec_top;
1338
1339 /* Look for protected sources */
1340 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1341 if (psrc) {
1342 /* Allocate a bitmap with one bit per interrupt */
1343 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1344 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1345 BUG_ON(mpic->protected == NULL);
1346 for (i = 0; i < psize/sizeof(u32); i++) {
1347 if (psrc[i] > intvec_top)
1348 continue;
1349 __set_bit(psrc[i], mpic->protected);
1350 }
1351 }
1352
1353#ifdef CONFIG_MPIC_WEIRD
1354 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1355#endif
1356
1357 /* default register type */
1358 if (mpic->flags & MPIC_BIG_ENDIAN)
1359 mpic->reg_type = mpic_access_mmio_be;
1360 else
1361 mpic->reg_type = mpic_access_mmio_le;
1362
1363 /*
1364 * An MPIC with a "dcr-reg" property must be accessed that way, but
1365 * only if the kernel includes DCR support.
1366 */
1367#ifdef CONFIG_PPC_DCR
1368 if (mpic->flags & MPIC_USES_DCR)
1369 mpic->reg_type = mpic_access_dcr;
1370#else
1371 BUG_ON(mpic->flags & MPIC_USES_DCR);
1372#endif
1373
1374 /* Map the global registers */
1375 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1376 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1377
1378 if (mpic->flags & MPIC_FSL) {
1379 int ret;
1380
1381 /*
1382 * Yes, Freescale really did put global registers in the
1383 * magic per-cpu area -- and they don't even show up in the
1384 * non-magic per-cpu copies that this driver normally uses.
1385 */
1386 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1387 MPIC_CPU_THISBASE, 0x1000);
1388
1389 fsl_version = fsl_mpic_get_version(mpic);
1390
1391 /* Error interrupt mask register (EIMR) is required for
1392 * handling individual device error interrupts. EIMR
1393 * was added in MPIC version 4.1.
1394 *
1395 * Over here we reserve vector number space for error
1396 * interrupt vectors. This space is stolen from the
1397 * global vector number space, as in case of ipis
1398 * and timer interrupts.
1399 *
1400 * Available vector space = intvec_top - 12, where 12
1401 * is the number of vectors which have been consumed by
1402 * ipis and timer interrupts.
1403 */
1404 if (fsl_version >= 0x401) {
1405 ret = mpic_setup_error_int(mpic, intvec_top - 12);
1406 if (ret)
1407 return NULL;
1408 }
1409
1410 }
1411
1412 /*
1413 * EPR is only available starting with v4.0. To support
1414 * platforms that don't know the MPIC version at compile-time,
1415 * such as qemu-e500, turn off coreint if this MPIC doesn't
1416 * support it. Note that we never enable it if it wasn't
1417 * requested in the first place.
1418 *
1419 * This is done outside the MPIC_FSL check, so that we
1420 * also disable coreint if the MPIC node doesn't have
1421 * an "fsl,mpic" compatible at all. This will be the case
1422 * with device trees generated by older versions of QEMU.
1423 * fsl_version will be zero if MPIC_FSL is not set.
1424 */
1425 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1426 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1427 ppc_md.get_irq = mpic_get_irq;
1428 }
1429
1430 /* Reset */
1431
1432 /* When using a device-node, reset requests are only honored if the MPIC
1433 * is allowed to reset.
1434 */
1435 if (!(mpic->flags & MPIC_NO_RESET)) {
1436 printk(KERN_DEBUG "mpic: Resetting\n");
1437 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1438 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1439 | MPIC_GREG_GCONF_RESET);
1440 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1441 & MPIC_GREG_GCONF_RESET)
1442 mb();
1443 }
1444
1445 /* CoreInt */
1446 if (mpic->flags & MPIC_ENABLE_COREINT)
1447 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1448 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1449 | MPIC_GREG_GCONF_COREINT);
1450
1451 if (mpic->flags & MPIC_ENABLE_MCK)
1452 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1453 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1454 | MPIC_GREG_GCONF_MCK);
1455
1456 /*
1457 * The MPIC driver will crash if there are more cores than we
1458 * can initialize, so we may as well catch that problem here.
1459 */
1460 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1461
1462 /* Map the per-CPU registers */
1463 for_each_possible_cpu(i) {
1464 unsigned int cpu = get_hard_smp_processor_id(i);
1465
1466 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1467 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1468 0x1000);
1469 }
1470
1471 /*
1472 * Read feature register. For non-ISU MPICs, num sources as well. On
1473 * ISU MPICs, sources are counted as ISUs are added
1474 */
1475 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1476
1477 /*
1478 * By default, the last source number comes from the MPIC, but the
1479 * device-tree and board support code can override it on buggy hw.
1480 * If we get passed an isu_size (multi-isu MPIC) then we use that
1481 * as a default instead of the value read from the HW.
1482 */
1483 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1484 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1485 if (isu_size)
1486 last_irq = isu_size * MPIC_MAX_ISU - 1;
1487 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1488 if (irq_count)
1489 last_irq = irq_count - 1;
1490
1491 /* Initialize main ISU if none provided */
1492 if (!isu_size) {
1493 isu_size = last_irq + 1;
1494 mpic->num_sources = isu_size;
1495 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1496 MPIC_INFO(IRQ_BASE),
1497 MPIC_INFO(IRQ_STRIDE) * isu_size);
1498 }
1499
1500 mpic->isu_size = isu_size;
1501 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1502 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1503
1504 mpic->irqhost = irq_domain_add_linear(mpic->node,
1505 intvec_top,
1506 &mpic_host_ops, mpic);
1507
1508 /*
1509 * FIXME: The code leaks the MPIC object and mappings here; this
1510 * is very unlikely to fail but it ought to be fixed anyways.
1511 */
1512 if (mpic->irqhost == NULL)
1513 return NULL;
1514
1515 /* Display version */
1516 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1517 case 1:
1518 vers = "1.0";
1519 break;
1520 case 2:
1521 vers = "1.2";
1522 break;
1523 case 3:
1524 vers = "1.3";
1525 break;
1526 default:
1527 vers = "<unknown>";
1528 break;
1529 }
1530 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1531 " max %d CPUs\n",
1532 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1533 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1534 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1535
1536 mpic->next = mpics;
1537 mpics = mpic;
1538
1539 if (!(mpic->flags & MPIC_SECONDARY)) {
1540 mpic_primary = mpic;
1541 irq_set_default_host(mpic->irqhost);
1542 }
1543
1544 return mpic;
1545
1546err_of_node_put:
1547 of_node_put(node);
1548 return NULL;
1549}
1550
1551void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1552 phys_addr_t paddr)
1553{
1554 unsigned int isu_first = isu_num * mpic->isu_size;
1555
1556 BUG_ON(isu_num >= MPIC_MAX_ISU);
1557
1558 mpic_map(mpic,
1559 paddr, &mpic->isus[isu_num], 0,
1560 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1561
1562 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1563 mpic->num_sources = isu_first + mpic->isu_size;
1564}
1565
1566void __init mpic_init(struct mpic *mpic)
1567{
1568 int i, cpu;
1569 int num_timers = 4;
1570
1571 BUG_ON(mpic->num_sources == 0);
1572
1573 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1574
1575 /* Set current processor priority to max */
1576 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1577
1578 if (mpic->flags & MPIC_FSL) {
1579 u32 version = fsl_mpic_get_version(mpic);
1580
1581 /*
1582 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1583 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1584 * I don't know about the status of intermediate versions (or
1585 * whether they even exist).
1586 */
1587 if (version >= 0x0301)
1588 num_timers = 8;
1589 }
1590
1591 /* FSL mpic error interrupt intialization */
1592 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1593 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1594
1595 /* Initialize timers to our reserved vectors and mask them for now */
1596 for (i = 0; i < num_timers; i++) {
1597 unsigned int offset = mpic_tm_offset(mpic, i);
1598
1599 mpic_write(mpic->tmregs,
1600 offset + MPIC_INFO(TIMER_DESTINATION),
1601 1 << hard_smp_processor_id());
1602 mpic_write(mpic->tmregs,
1603 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1604 MPIC_VECPRI_MASK |
1605 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1606 (mpic->timer_vecs[0] + i));
1607 }
1608
1609 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1610 mpic_test_broken_ipi(mpic);
1611 for (i = 0; i < 4; i++) {
1612 mpic_ipi_write(i,
1613 MPIC_VECPRI_MASK |
1614 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1615 (mpic->ipi_vecs[0] + i));
1616 }
1617
1618 /* Do the HT PIC fixups on U3 broken mpic */
1619 DBG("MPIC flags: %x\n", mpic->flags);
1620 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1621 mpic_scan_ht_pics(mpic);
1622 mpic_u3msi_init(mpic);
1623 }
1624
1625 mpic_pasemi_msi_init(mpic);
1626
1627 cpu = mpic_processor_id(mpic);
1628
1629 if (!(mpic->flags & MPIC_NO_RESET)) {
1630 for (i = 0; i < mpic->num_sources; i++) {
1631 /* start with vector = source number, and masked */
1632 u32 vecpri = MPIC_VECPRI_MASK | i |
1633 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1634
1635 /* check if protected */
1636 if (mpic->protected && test_bit(i, mpic->protected))
1637 continue;
1638 /* init hw */
1639 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1640 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1641 }
1642 }
1643
1644 /* Init spurious vector */
1645 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1646
1647 /* Disable 8259 passthrough, if supported */
1648 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1649 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1650 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1651 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1652
1653 if (mpic->flags & MPIC_NO_BIAS)
1654 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1655 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1656 | MPIC_GREG_GCONF_NO_BIAS);
1657
1658 /* Set current processor priority to 0 */
1659 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1660
1661#ifdef CONFIG_PM
1662 /* allocate memory to save mpic state */
1663 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1664 GFP_KERNEL);
1665 BUG_ON(mpic->save_data == NULL);
1666#endif
1667
1668 /* Check if this MPIC is chained from a parent interrupt controller */
1669 if (mpic->flags & MPIC_SECONDARY) {
1670 int virq = irq_of_parse_and_map(mpic->node, 0);
1671 if (virq != NO_IRQ) {
1672 printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1673 mpic->node->full_name, virq);
1674 irq_set_handler_data(virq, mpic);
1675 irq_set_chained_handler(virq, &mpic_cascade);
1676 }
1677 }
1678}
1679
1680void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1681{
1682 u32 v;
1683
1684 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1685 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1686 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1687 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1688}
1689
1690void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1691{
1692 unsigned long flags;
1693 u32 v;
1694
1695 raw_spin_lock_irqsave(&mpic_lock, flags);
1696 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1697 if (enable)
1698 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1699 else
1700 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1701 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1702 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1703}
1704
1705void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1706{
1707 struct mpic *mpic = mpic_find(irq);
1708 unsigned int src = virq_to_hw(irq);
1709 unsigned long flags;
1710 u32 reg;
1711
1712 if (!mpic)
1713 return;
1714
1715 raw_spin_lock_irqsave(&mpic_lock, flags);
1716 if (mpic_is_ipi(mpic, src)) {
1717 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1718 ~MPIC_VECPRI_PRIORITY_MASK;
1719 mpic_ipi_write(src - mpic->ipi_vecs[0],
1720 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1721 } else if (mpic_is_tm(mpic, src)) {
1722 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1723 ~MPIC_VECPRI_PRIORITY_MASK;
1724 mpic_tm_write(src - mpic->timer_vecs[0],
1725 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1726 } else {
1727 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1728 & ~MPIC_VECPRI_PRIORITY_MASK;
1729 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1730 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1731 }
1732 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1733}
1734
1735void mpic_setup_this_cpu(void)
1736{
1737#ifdef CONFIG_SMP
1738 struct mpic *mpic = mpic_primary;
1739 unsigned long flags;
1740 u32 msk = 1 << hard_smp_processor_id();
1741 unsigned int i;
1742
1743 BUG_ON(mpic == NULL);
1744
1745 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1746
1747 raw_spin_lock_irqsave(&mpic_lock, flags);
1748
1749 /* let the mpic know we want intrs. default affinity is 0xffffffff
1750 * until changed via /proc. That's how it's done on x86. If we want
1751 * it differently, then we should make sure we also change the default
1752 * values of irq_desc[].affinity in irq.c.
1753 */
1754 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1755 for (i = 0; i < mpic->num_sources ; i++)
1756 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1757 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1758 }
1759
1760 /* Set current processor priority to 0 */
1761 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1762
1763 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1764#endif /* CONFIG_SMP */
1765}
1766
1767int mpic_cpu_get_priority(void)
1768{
1769 struct mpic *mpic = mpic_primary;
1770
1771 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1772}
1773
1774void mpic_cpu_set_priority(int prio)
1775{
1776 struct mpic *mpic = mpic_primary;
1777
1778 prio &= MPIC_CPU_TASKPRI_MASK;
1779 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1780}
1781
1782void mpic_teardown_this_cpu(int secondary)
1783{
1784 struct mpic *mpic = mpic_primary;
1785 unsigned long flags;
1786 u32 msk = 1 << hard_smp_processor_id();
1787 unsigned int i;
1788
1789 BUG_ON(mpic == NULL);
1790
1791 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1792 raw_spin_lock_irqsave(&mpic_lock, flags);
1793
1794 /* let the mpic know we don't want intrs. */
1795 for (i = 0; i < mpic->num_sources ; i++)
1796 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1797 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1798
1799 /* Set current processor priority to max */
1800 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1801 /* We need to EOI the IPI since not all platforms reset the MPIC
1802 * on boot and new interrupts wouldn't get delivered otherwise.
1803 */
1804 mpic_eoi(mpic);
1805
1806 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1807}
1808
1809
1810static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1811{
1812 u32 src;
1813
1814 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1815#ifdef DEBUG_LOW
1816 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1817#endif
1818 if (unlikely(src == mpic->spurious_vec)) {
1819 if (mpic->flags & MPIC_SPV_EOI)
1820 mpic_eoi(mpic);
1821 return NO_IRQ;
1822 }
1823 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1824 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1825 mpic->name, (int)src);
1826 mpic_eoi(mpic);
1827 return NO_IRQ;
1828 }
1829
1830 return irq_linear_revmap(mpic->irqhost, src);
1831}
1832
1833unsigned int mpic_get_one_irq(struct mpic *mpic)
1834{
1835 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1836}
1837
1838unsigned int mpic_get_irq(void)
1839{
1840 struct mpic *mpic = mpic_primary;
1841
1842 BUG_ON(mpic == NULL);
1843
1844 return mpic_get_one_irq(mpic);
1845}
1846
1847unsigned int mpic_get_coreint_irq(void)
1848{
1849#ifdef CONFIG_BOOKE
1850 struct mpic *mpic = mpic_primary;
1851 u32 src;
1852
1853 BUG_ON(mpic == NULL);
1854
1855 src = mfspr(SPRN_EPR);
1856
1857 if (unlikely(src == mpic->spurious_vec)) {
1858 if (mpic->flags & MPIC_SPV_EOI)
1859 mpic_eoi(mpic);
1860 return NO_IRQ;
1861 }
1862 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1863 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1864 mpic->name, (int)src);
1865 return NO_IRQ;
1866 }
1867
1868 return irq_linear_revmap(mpic->irqhost, src);
1869#else
1870 return NO_IRQ;
1871#endif
1872}
1873
1874unsigned int mpic_get_mcirq(void)
1875{
1876 struct mpic *mpic = mpic_primary;
1877
1878 BUG_ON(mpic == NULL);
1879
1880 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1881}
1882
1883#ifdef CONFIG_SMP
1884void mpic_request_ipis(void)
1885{
1886 struct mpic *mpic = mpic_primary;
1887 int i;
1888 BUG_ON(mpic == NULL);
1889
1890 printk(KERN_INFO "mpic: requesting IPIs...\n");
1891
1892 for (i = 0; i < 4; i++) {
1893 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1894 mpic->ipi_vecs[0] + i);
1895 if (vipi == NO_IRQ) {
1896 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1897 continue;
1898 }
1899 smp_request_message_ipi(vipi, i);
1900 }
1901}
1902
1903void smp_mpic_message_pass(int cpu, int msg)
1904{
1905 struct mpic *mpic = mpic_primary;
1906 u32 physmask;
1907
1908 BUG_ON(mpic == NULL);
1909
1910 /* make sure we're sending something that translates to an IPI */
1911 if ((unsigned int)msg > 3) {
1912 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1913 smp_processor_id(), msg);
1914 return;
1915 }
1916
1917#ifdef DEBUG_IPI
1918 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1919#endif
1920
1921 physmask = 1 << get_hard_smp_processor_id(cpu);
1922
1923 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1924 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1925}
1926
1927int __init smp_mpic_probe(void)
1928{
1929 int nr_cpus;
1930
1931 DBG("smp_mpic_probe()...\n");
1932
1933 nr_cpus = cpumask_weight(cpu_possible_mask);
1934
1935 DBG("nr_cpus: %d\n", nr_cpus);
1936
1937 if (nr_cpus > 1)
1938 mpic_request_ipis();
1939
1940 return nr_cpus;
1941}
1942
1943void smp_mpic_setup_cpu(int cpu)
1944{
1945 mpic_setup_this_cpu();
1946}
1947
1948void mpic_reset_core(int cpu)
1949{
1950 struct mpic *mpic = mpic_primary;
1951 u32 pir;
1952 int cpuid = get_hard_smp_processor_id(cpu);
1953 int i;
1954
1955 /* Set target bit for core reset */
1956 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1957 pir |= (1 << cpuid);
1958 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1959 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1960
1961 /* Restore target bit after reset complete */
1962 pir &= ~(1 << cpuid);
1963 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1964 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1965
1966 /* Perform 15 EOI on each reset core to clear pending interrupts.
1967 * This is required for FSL CoreNet based devices */
1968 if (mpic->flags & MPIC_FSL) {
1969 for (i = 0; i < 15; i++) {
1970 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1971 MPIC_CPU_EOI, 0);
1972 }
1973 }
1974}
1975#endif /* CONFIG_SMP */
1976
1977#ifdef CONFIG_PM
1978static void mpic_suspend_one(struct mpic *mpic)
1979{
1980 int i;
1981
1982 for (i = 0; i < mpic->num_sources; i++) {
1983 mpic->save_data[i].vecprio =
1984 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1985 mpic->save_data[i].dest =
1986 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1987 }
1988}
1989
1990static int mpic_suspend(void)
1991{
1992 struct mpic *mpic = mpics;
1993
1994 while (mpic) {
1995 mpic_suspend_one(mpic);
1996 mpic = mpic->next;
1997 }
1998
1999 return 0;
2000}
2001
2002static void mpic_resume_one(struct mpic *mpic)
2003{
2004 int i;
2005
2006 for (i = 0; i < mpic->num_sources; i++) {
2007 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
2008 mpic->save_data[i].vecprio);
2009 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
2010 mpic->save_data[i].dest);
2011
2012#ifdef CONFIG_MPIC_U3_HT_IRQS
2013 if (mpic->fixups) {
2014 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
2015
2016 if (fixup->base) {
2017 /* we use the lowest bit in an inverted meaning */
2018 if ((mpic->save_data[i].fixup_data & 1) == 0)
2019 continue;
2020
2021 /* Enable and configure */
2022 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
2023
2024 writel(mpic->save_data[i].fixup_data & ~1,
2025 fixup->base + 4);
2026 }
2027 }
2028#endif
2029 } /* end for loop */
2030}
2031
2032static void mpic_resume(void)
2033{
2034 struct mpic *mpic = mpics;
2035
2036 while (mpic) {
2037 mpic_resume_one(mpic);
2038 mpic = mpic->next;
2039 }
2040}
2041
2042static struct syscore_ops mpic_syscore_ops = {
2043 .resume = mpic_resume,
2044 .suspend = mpic_suspend,
2045};
2046
2047static int mpic_init_sys(void)
2048{
2049 register_syscore_ops(&mpic_syscore_ops);
2050 subsys_system_register(&mpic_subsys, NULL);
2051
2052 return 0;
2053}
2054
2055device_initcall(mpic_init_sys);
2056#endif