1/*
  2 * Copyright (C) 2013 Imagination Technologies
  3 * Author: Paul Burton <paul.burton@imgtec.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License as published by the
  7 * Free Software Foundation;  either version 2 of the  License, or (at your
  8 * option) any later version.
  9 */
 10
 11#ifndef __MIPS_ASM_MIPS_CPC_H__
 12#define __MIPS_ASM_MIPS_CPC_H__
 13
 14#include <linux/io.h>
 15#include <linux/types.h>
 16
 17/* The base address of the CPC registers */
 18extern void __iomem *mips_cpc_base;
 19
 20/**
 21 * mips_cpc_default_phys_base - retrieve the default physical base address of
 22 *                              the CPC
 23 *
 24 * Returns the default physical base address of the Cluster Power Controller
 25 * memory mapped registers. This is platform dependant & must therefore be
 26 * implemented per-platform.
 27 */
 28extern phys_t mips_cpc_default_phys_base(void);
 29
 30/**
 31 * mips_cpc_phys_base - retrieve the physical base address of the CPC
 32 *
 33 * This function returns the physical base address of the Cluster Power
 34 * Controller memory mapped registers, or 0 if no Cluster Power Controller
 35 * is present. It may be overriden by individual platforms which determine
 36 * this address in a different way.
 37 */
 38extern phys_t __weak mips_cpc_phys_base(void);
 39
 40/**
 41 * mips_cpc_probe - probe for a Cluster Power Controller
 42 *
 43 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
 44 * a CPC is successfully detected, else -errno.
 45 */
 46#ifdef CONFIG_MIPS_CPC
 47extern int mips_cpc_probe(void);
 48#else
 49static inline int mips_cpc_probe(void)
 50{
 51	return -ENODEV;
 52}
 53#endif
 54
 55/**
 56 * mips_cpc_present - determine whether a Cluster Power Controller is present
 57 *
 58 * Returns true if a CPC is present in the system, else false.
 59 */
 60static inline bool mips_cpc_present(void)
 61{
 62#ifdef CONFIG_MIPS_CPC
 63	return mips_cpc_base != NULL;
 64#else
 65	return false;
 66#endif
 67}
 68
 69/* Offsets from the CPC base address to various control blocks */
 70#define MIPS_CPC_GCB_OFS	0x0000
 71#define MIPS_CPC_CLCB_OFS	0x2000
 72#define MIPS_CPC_COCB_OFS	0x4000
 73
 74/* Macros to ease the creation of register access functions */
 75#define BUILD_CPC_R_(name, off) \
 76static inline u32 read_cpc_##name(void)				\
 77{								\
 78	return __raw_readl(mips_cpc_base + (off));		\
 79}
 80
 81#define BUILD_CPC__W(name, off) \
 82static inline void write_cpc_##name(u32 value)			\
 83{								\
 84	__raw_writel(value, mips_cpc_base + (off));		\
 85}
 86
 87#define BUILD_CPC_RW(name, off)					\
 88	BUILD_CPC_R_(name, off)					\
 89	BUILD_CPC__W(name, off)
 90
 91#define BUILD_CPC_Cx_R_(name, off)				\
 92	BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off))	\
 93	BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
 94
 95#define BUILD_CPC_Cx__W(name, off)				\
 96	BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off))	\
 97	BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
 98
 99#define BUILD_CPC_Cx_RW(name, off)				\
100	BUILD_CPC_Cx_R_(name, off)				\
101	BUILD_CPC_Cx__W(name, off)
102
103/* GCB register accessor functions */
104BUILD_CPC_RW(access,		MIPS_CPC_GCB_OFS + 0x00)
105BUILD_CPC_RW(seqdel,		MIPS_CPC_GCB_OFS + 0x08)
106BUILD_CPC_RW(rail,		MIPS_CPC_GCB_OFS + 0x10)
107BUILD_CPC_RW(resetlen,		MIPS_CPC_GCB_OFS + 0x18)
108BUILD_CPC_R_(revision,		MIPS_CPC_GCB_OFS + 0x20)
109
110/* Core Local & Core Other accessor functions */
111BUILD_CPC_Cx_RW(cmd,		0x00)
112BUILD_CPC_Cx_RW(stat_conf,	0x08)
113BUILD_CPC_Cx_RW(other,		0x10)
114
115/* CPC_Cx_CMD register fields */
116#define CPC_Cx_CMD_SHF				0
117#define CPC_Cx_CMD_MSK				(_ULCAST_(0xf) << 0)
118#define  CPC_Cx_CMD_CLOCKOFF			(_ULCAST_(0x1) << 0)
119#define  CPC_Cx_CMD_PWRDOWN			(_ULCAST_(0x2) << 0)
120#define  CPC_Cx_CMD_PWRUP			(_ULCAST_(0x3) << 0)
121#define  CPC_Cx_CMD_RESET			(_ULCAST_(0x4) << 0)
122
123/* CPC_Cx_STAT_CONF register fields */
124#define CPC_Cx_STAT_CONF_PWRUPE_SHF		23
125#define CPC_Cx_STAT_CONF_PWRUPE_MSK		(_ULCAST_(0x1) << 23)
126#define CPC_Cx_STAT_CONF_SEQSTATE_SHF		19
127#define CPC_Cx_STAT_CONF_SEQSTATE_MSK		(_ULCAST_(0xf) << 19)
128#define  CPC_Cx_STAT_CONF_SEQSTATE_D0		(_ULCAST_(0x0) << 19)
129#define  CPC_Cx_STAT_CONF_SEQSTATE_U0		(_ULCAST_(0x1) << 19)
130#define  CPC_Cx_STAT_CONF_SEQSTATE_U1		(_ULCAST_(0x2) << 19)
131#define  CPC_Cx_STAT_CONF_SEQSTATE_U2		(_ULCAST_(0x3) << 19)
132#define  CPC_Cx_STAT_CONF_SEQSTATE_U3		(_ULCAST_(0x4) << 19)
133#define  CPC_Cx_STAT_CONF_SEQSTATE_U4		(_ULCAST_(0x5) << 19)
134#define  CPC_Cx_STAT_CONF_SEQSTATE_U5		(_ULCAST_(0x6) << 19)
135#define  CPC_Cx_STAT_CONF_SEQSTATE_U6		(_ULCAST_(0x7) << 19)
136#define  CPC_Cx_STAT_CONF_SEQSTATE_D1		(_ULCAST_(0x8) << 19)
137#define  CPC_Cx_STAT_CONF_SEQSTATE_D3		(_ULCAST_(0x9) << 19)
138#define  CPC_Cx_STAT_CONF_SEQSTATE_D2		(_ULCAST_(0xa) << 19)
139#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF	17
140#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK	(_ULCAST_(0x1) << 17)
141#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF		16
142#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK		(_ULCAST_(0x1) << 16)
143#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF	15
144#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK	(_ULCAST_(0x1) << 15)
145
146/* CPC_Cx_OTHER register fields */
147#define CPC_Cx_OTHER_CORENUM_SHF		16
148#define CPC_Cx_OTHER_CORENUM_MSK		(_ULCAST_(0xff) << 16)
149
150#endif /* __MIPS_ASM_MIPS_CPC_H__ */