1/*
   2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3 *
   4 * Copyright (C) 2009-2011 Nokia Corporation
   5 * Copyright (C) 2012 Texas Instruments, Inc.
   6 * Paul Walmsley
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * The data in this file should be completely autogeneratable from
  13 * the TI hardware database or other technical documentation.
  14 *
  15 * XXX these should be marked initdata for multi-OMAP kernels
  16 */
  17#include <plat/omap_hwmod.h>
  18#include <mach/irqs.h>
  19#include <plat/cpu.h>
  20#include <plat/dma.h>
  21#include <plat/serial.h>
  22#include <plat/l3_3xxx.h>
  23#include <plat/l4_3xxx.h>
  24#include <plat/i2c.h>
  25#include <plat/gpio.h>
  26#include <plat/mmc.h>
  27#include <plat/mcbsp.h>
  28#include <plat/mcspi.h>
  29#include <plat/dmtimer.h>
  30
  31#include "omap_hwmod_common_data.h"
  32
  33#include "smartreflex.h"
 
 
  34#include "prm-regbits-34xx.h"
  35#include "cm-regbits-34xx.h"
 
 
 
  36#include "wd_timer.h"
  37#include <mach/am35xx.h>
  38
  39/*
  40 * OMAP3xxx hardware module integration data
  41 *
  42 * All of the data in this section should be autogeneratable from the
  43 * TI hardware database or other technical documentation.  Data that
  44 * is driver-specific or driver-kernel integration-specific belongs
  45 * elsewhere.
  46 */
  47
  48/*
  49 * IP blocks
  50 */
  51
  52/* L3 */
  53static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  54	{ .irq = INT_34XX_L3_DBG_IRQ },
  55	{ .irq = INT_34XX_L3_APP_IRQ },
  56	{ .irq = -1 }
  57};
  58
  59static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  60	.name		= "l3_main",
  61	.class		= &l3_hwmod_class,
  62	.mpu_irqs	= omap3xxx_l3_main_irqs,
  63	.flags		= HWMOD_NO_IDLEST,
  64};
  65
  66/* L4 CORE */
  67static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  68	.name		= "l4_core",
  69	.class		= &l4_hwmod_class,
  70	.flags		= HWMOD_NO_IDLEST,
  71};
  72
  73/* L4 PER */
  74static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  75	.name		= "l4_per",
  76	.class		= &l4_hwmod_class,
  77	.flags		= HWMOD_NO_IDLEST,
  78};
  79
  80/* L4 WKUP */
  81static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  82	.name		= "l4_wkup",
  83	.class		= &l4_hwmod_class,
  84	.flags		= HWMOD_NO_IDLEST,
  85};
  86
  87/* L4 SEC */
  88static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  89	.name		= "l4_sec",
  90	.class		= &l4_hwmod_class,
  91	.flags		= HWMOD_NO_IDLEST,
  92};
  93
  94/* MPU */
 
 
 
 
 
  95static struct omap_hwmod omap3xxx_mpu_hwmod = {
  96	.name		= "mpu",
 
  97	.class		= &mpu_hwmod_class,
  98	.main_clk	= "arm_fck",
  99};
 100
 101/* IVA2 (IVA2) */
 102static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 103	{ .name = "logic", .rst_shift = 0 },
 104	{ .name = "seq0", .rst_shift = 1 },
 105	{ .name = "seq1", .rst_shift = 2 },
 106};
 107
 108static struct omap_hwmod omap3xxx_iva_hwmod = {
 109	.name		= "iva",
 110	.class		= &iva_hwmod_class,
 111	.clkdm_name	= "iva2_clkdm",
 112	.rst_lines	= omap3xxx_iva_resets,
 113	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
 114	.main_clk	= "iva2_ck",
 
 
 
 
 
 
 
 
 
 115};
 116
 117/* timer class */
 118static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 119	.rev_offs	= 0x0000,
 120	.sysc_offs	= 0x0010,
 121	.syss_offs	= 0x0014,
 122	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 123				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 124				SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 125	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 126	.sysc_fields	= &omap_hwmod_sysc_type1,
 127};
 128
 129static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 130	.name = "timer",
 131	.sysc = &omap3xxx_timer_1ms_sysc,
 132	.rev = OMAP_TIMER_IP_VERSION_1,
 
 
 
 133};
 134
 
 135static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 136	.rev_offs	= 0x0000,
 137	.sysc_offs	= 0x0010,
 138	.syss_offs	= 0x0014,
 139	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 140			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 
 
 141	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 
 142	.sysc_fields	= &omap_hwmod_sysc_type1,
 143};
 144
 145static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 146	.name = "timer",
 147	.sysc = &omap3xxx_timer_sysc,
 148	.rev =  OMAP_TIMER_IP_VERSION_1,
 149};
 150
 151/* secure timers dev attribute */
 152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 153	.timer_capability	= OMAP_TIMER_SECURE,
 154};
 155
 156/* always-on timers dev attribute */
 157static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 158	.timer_capability	= OMAP_TIMER_ALWON,
 159};
 160
 161/* pwm timers dev attribute */
 162static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 163	.timer_capability	= OMAP_TIMER_HAS_PWM,
 164};
 165
 
 
 
 
 
 
 
 
 
 
 166/* timer1 */
 167static struct omap_hwmod omap3xxx_timer1_hwmod = {
 168	.name		= "timer1",
 169	.mpu_irqs	= omap2_timer1_mpu_irqs,
 170	.main_clk	= "gpt1_fck",
 171	.prcm		= {
 172		.omap2 = {
 173			.prcm_reg_id = 1,
 174			.module_bit = OMAP3430_EN_GPT1_SHIFT,
 175			.module_offs = WKUP_MOD,
 176			.idlest_reg_id = 1,
 177			.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 178		},
 179	},
 180	.dev_attr	= &capability_alwon_dev_attr,
 181	.class		= &omap3xxx_timer_1ms_hwmod_class,
 
 182};
 183
 184/* timer2 */
 185static struct omap_hwmod omap3xxx_timer2_hwmod = {
 186	.name		= "timer2",
 187	.mpu_irqs	= omap2_timer2_mpu_irqs,
 188	.main_clk	= "gpt2_fck",
 189	.prcm		= {
 190		.omap2 = {
 191			.prcm_reg_id = 1,
 192			.module_bit = OMAP3430_EN_GPT2_SHIFT,
 193			.module_offs = OMAP3430_PER_MOD,
 194			.idlest_reg_id = 1,
 195			.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 196		},
 197	},
 198	.dev_attr	= &capability_alwon_dev_attr,
 199	.class		= &omap3xxx_timer_1ms_hwmod_class,
 200};
 201
 202/* timer3 */
 203static struct omap_hwmod omap3xxx_timer3_hwmod = {
 204	.name		= "timer3",
 205	.mpu_irqs	= omap2_timer3_mpu_irqs,
 206	.main_clk	= "gpt3_fck",
 207	.prcm		= {
 208		.omap2 = {
 209			.prcm_reg_id = 1,
 210			.module_bit = OMAP3430_EN_GPT3_SHIFT,
 211			.module_offs = OMAP3430_PER_MOD,
 212			.idlest_reg_id = 1,
 213			.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 214		},
 215	},
 216	.dev_attr	= &capability_alwon_dev_attr,
 217	.class		= &omap3xxx_timer_hwmod_class,
 
 218};
 219
 220/* timer4 */
 221static struct omap_hwmod omap3xxx_timer4_hwmod = {
 222	.name		= "timer4",
 223	.mpu_irqs	= omap2_timer4_mpu_irqs,
 224	.main_clk	= "gpt4_fck",
 225	.prcm		= {
 226		.omap2 = {
 227			.prcm_reg_id = 1,
 228			.module_bit = OMAP3430_EN_GPT4_SHIFT,
 229			.module_offs = OMAP3430_PER_MOD,
 230			.idlest_reg_id = 1,
 231			.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 232		},
 233	},
 234	.dev_attr	= &capability_alwon_dev_attr,
 235	.class		= &omap3xxx_timer_hwmod_class,
 
 236};
 237
 238/* timer5 */
 239static struct omap_hwmod omap3xxx_timer5_hwmod = {
 240	.name		= "timer5",
 241	.mpu_irqs	= omap2_timer5_mpu_irqs,
 242	.main_clk	= "gpt5_fck",
 243	.prcm		= {
 244		.omap2 = {
 245			.prcm_reg_id = 1,
 246			.module_bit = OMAP3430_EN_GPT5_SHIFT,
 247			.module_offs = OMAP3430_PER_MOD,
 248			.idlest_reg_id = 1,
 249			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 250		},
 251	},
 252	.dev_attr	= &capability_alwon_dev_attr,
 253	.class		= &omap3xxx_timer_hwmod_class,
 
 254};
 255
 256/* timer6 */
 257static struct omap_hwmod omap3xxx_timer6_hwmod = {
 258	.name		= "timer6",
 259	.mpu_irqs	= omap2_timer6_mpu_irqs,
 260	.main_clk	= "gpt6_fck",
 261	.prcm		= {
 262		.omap2 = {
 263			.prcm_reg_id = 1,
 264			.module_bit = OMAP3430_EN_GPT6_SHIFT,
 265			.module_offs = OMAP3430_PER_MOD,
 266			.idlest_reg_id = 1,
 267			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 268		},
 269	},
 270	.dev_attr	= &capability_alwon_dev_attr,
 271	.class		= &omap3xxx_timer_hwmod_class,
 
 272};
 273
 274/* timer7 */
 275static struct omap_hwmod omap3xxx_timer7_hwmod = {
 276	.name		= "timer7",
 277	.mpu_irqs	= omap2_timer7_mpu_irqs,
 278	.main_clk	= "gpt7_fck",
 279	.prcm		= {
 280		.omap2 = {
 281			.prcm_reg_id = 1,
 282			.module_bit = OMAP3430_EN_GPT7_SHIFT,
 283			.module_offs = OMAP3430_PER_MOD,
 284			.idlest_reg_id = 1,
 285			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 286		},
 287	},
 288	.dev_attr	= &capability_alwon_dev_attr,
 289	.class		= &omap3xxx_timer_hwmod_class,
 
 290};
 291
 292/* timer8 */
 293static struct omap_hwmod omap3xxx_timer8_hwmod = {
 294	.name		= "timer8",
 295	.mpu_irqs	= omap2_timer8_mpu_irqs,
 296	.main_clk	= "gpt8_fck",
 297	.prcm		= {
 298		.omap2 = {
 299			.prcm_reg_id = 1,
 300			.module_bit = OMAP3430_EN_GPT8_SHIFT,
 301			.module_offs = OMAP3430_PER_MOD,
 302			.idlest_reg_id = 1,
 303			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 304		},
 305	},
 306	.dev_attr	= &capability_pwm_dev_attr,
 307	.class		= &omap3xxx_timer_hwmod_class,
 
 308};
 309
 310/* timer9 */
 311static struct omap_hwmod omap3xxx_timer9_hwmod = {
 312	.name		= "timer9",
 313	.mpu_irqs	= omap2_timer9_mpu_irqs,
 314	.main_clk	= "gpt9_fck",
 315	.prcm		= {
 316		.omap2 = {
 317			.prcm_reg_id = 1,
 318			.module_bit = OMAP3430_EN_GPT9_SHIFT,
 319			.module_offs = OMAP3430_PER_MOD,
 320			.idlest_reg_id = 1,
 321			.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 322		},
 323	},
 324	.dev_attr	= &capability_pwm_dev_attr,
 325	.class		= &omap3xxx_timer_hwmod_class,
 
 326};
 327
 328/* timer10 */
 329static struct omap_hwmod omap3xxx_timer10_hwmod = {
 330	.name		= "timer10",
 331	.mpu_irqs	= omap2_timer10_mpu_irqs,
 332	.main_clk	= "gpt10_fck",
 333	.prcm		= {
 334		.omap2 = {
 335			.prcm_reg_id = 1,
 336			.module_bit = OMAP3430_EN_GPT10_SHIFT,
 337			.module_offs = CORE_MOD,
 338			.idlest_reg_id = 1,
 339			.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 340		},
 341	},
 342	.dev_attr	= &capability_pwm_dev_attr,
 343	.class		= &omap3xxx_timer_1ms_hwmod_class,
 
 344};
 345
 346/* timer11 */
 347static struct omap_hwmod omap3xxx_timer11_hwmod = {
 348	.name		= "timer11",
 349	.mpu_irqs	= omap2_timer11_mpu_irqs,
 350	.main_clk	= "gpt11_fck",
 351	.prcm		= {
 352		.omap2 = {
 353			.prcm_reg_id = 1,
 354			.module_bit = OMAP3430_EN_GPT11_SHIFT,
 355			.module_offs = CORE_MOD,
 356			.idlest_reg_id = 1,
 357			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 358		},
 359	},
 360	.dev_attr	= &capability_pwm_dev_attr,
 361	.class		= &omap3xxx_timer_hwmod_class,
 
 362};
 363
 364/* timer12 */
 365static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 366	{ .irq = 95, },
 367	{ .irq = -1 }
 368};
 369
 370static struct omap_hwmod omap3xxx_timer12_hwmod = {
 371	.name		= "timer12",
 372	.mpu_irqs	= omap3xxx_timer12_mpu_irqs,
 373	.main_clk	= "gpt12_fck",
 374	.prcm		= {
 375		.omap2 = {
 376			.prcm_reg_id = 1,
 377			.module_bit = OMAP3430_EN_GPT12_SHIFT,
 378			.module_offs = WKUP_MOD,
 379			.idlest_reg_id = 1,
 380			.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 381		},
 382	},
 383	.dev_attr	= &capability_secure_dev_attr,
 384	.class		= &omap3xxx_timer_hwmod_class,
 
 385};
 386
 387/*
 388 * 'wd_timer' class
 389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 390 * overflow condition
 391 */
 392
 393static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 394	.rev_offs	= 0x0000,
 395	.sysc_offs	= 0x0010,
 396	.syss_offs	= 0x0014,
 397	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 398			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 399			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 400			   SYSS_HAS_RESET_STATUS),
 401	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 402	.sysc_fields    = &omap_hwmod_sysc_type1,
 403};
 404
 405/* I2C common */
 406static struct omap_hwmod_class_sysconfig i2c_sysc = {
 407	.rev_offs	= 0x00,
 408	.sysc_offs	= 0x20,
 409	.syss_offs	= 0x10,
 410	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 411			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 412			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 413	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 414	.clockact	= CLOCKACT_TEST_ICLK,
 415	.sysc_fields    = &omap_hwmod_sysc_type1,
 416};
 417
 418static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 419	.name		= "wd_timer",
 420	.sysc		= &omap3xxx_wd_timer_sysc,
 421	.pre_shutdown	= &omap2_wd_timer_disable,
 422	.reset		= &omap2_wd_timer_reset,
 423};
 424
 425static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 426	.name		= "wd_timer2",
 427	.class		= &omap3xxx_wd_timer_hwmod_class,
 428	.main_clk	= "wdt2_fck",
 429	.prcm		= {
 430		.omap2 = {
 431			.prcm_reg_id = 1,
 432			.module_bit = OMAP3430_EN_WDT2_SHIFT,
 433			.module_offs = WKUP_MOD,
 434			.idlest_reg_id = 1,
 435			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 436		},
 437	},
 438	/*
 439	 * XXX: Use software supervised mode, HW supervised smartidle seems to
 440	 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 441	 */
 442	.flags		= HWMOD_SWSUP_SIDLE,
 443};
 444
 445/* UART1 */
 446static struct omap_hwmod omap3xxx_uart1_hwmod = {
 447	.name		= "uart1",
 448	.mpu_irqs	= omap2_uart1_mpu_irqs,
 449	.sdma_reqs	= omap2_uart1_sdma_reqs,
 450	.main_clk	= "uart1_fck",
 
 451	.prcm		= {
 452		.omap2 = {
 453			.module_offs = CORE_MOD,
 454			.prcm_reg_id = 1,
 455			.module_bit = OMAP3430_EN_UART1_SHIFT,
 456			.idlest_reg_id = 1,
 457			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 458		},
 459	},
 460	.class		= &omap2_uart_class,
 461};
 462
 463/* UART2 */
 464static struct omap_hwmod omap3xxx_uart2_hwmod = {
 465	.name		= "uart2",
 466	.mpu_irqs	= omap2_uart2_mpu_irqs,
 467	.sdma_reqs	= omap2_uart2_sdma_reqs,
 468	.main_clk	= "uart2_fck",
 
 469	.prcm		= {
 470		.omap2 = {
 471			.module_offs = CORE_MOD,
 472			.prcm_reg_id = 1,
 473			.module_bit = OMAP3430_EN_UART2_SHIFT,
 474			.idlest_reg_id = 1,
 475			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 476		},
 477	},
 478	.class		= &omap2_uart_class,
 479};
 480
 481/* UART3 */
 482static struct omap_hwmod omap3xxx_uart3_hwmod = {
 483	.name		= "uart3",
 484	.mpu_irqs	= omap2_uart3_mpu_irqs,
 485	.sdma_reqs	= omap2_uart3_sdma_reqs,
 486	.main_clk	= "uart3_fck",
 
 
 487	.prcm		= {
 488		.omap2 = {
 489			.module_offs = OMAP3430_PER_MOD,
 490			.prcm_reg_id = 1,
 491			.module_bit = OMAP3430_EN_UART3_SHIFT,
 492			.idlest_reg_id = 1,
 493			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 494		},
 495	},
 496	.class		= &omap2_uart_class,
 497};
 498
 499/* UART4 */
 500static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 501	{ .irq = INT_36XX_UART4_IRQ, },
 502	{ .irq = -1 }
 503};
 504
 505static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 506	{ .name = "rx",	.dma_req = OMAP36XX_DMA_UART4_RX, },
 507	{ .name = "tx",	.dma_req = OMAP36XX_DMA_UART4_TX, },
 508	{ .dma_req = -1 }
 509};
 510
 511static struct omap_hwmod omap36xx_uart4_hwmod = {
 512	.name		= "uart4",
 513	.mpu_irqs	= uart4_mpu_irqs,
 514	.sdma_reqs	= uart4_sdma_reqs,
 515	.main_clk	= "uart4_fck",
 
 516	.prcm		= {
 517		.omap2 = {
 518			.module_offs = OMAP3430_PER_MOD,
 519			.prcm_reg_id = 1,
 520			.module_bit = OMAP3630_EN_UART4_SHIFT,
 521			.idlest_reg_id = 1,
 522			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 523		},
 524	},
 525	.class		= &omap2_uart_class,
 526};
 527
 528static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 529	{ .irq = INT_35XX_UART4_IRQ, },
 
 530};
 531
 532static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 533	{ .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 534	{ .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 535};
 536
 537static struct omap_hwmod am35xx_uart4_hwmod = {
 538	.name		= "uart4",
 539	.mpu_irqs	= am35xx_uart4_mpu_irqs,
 540	.sdma_reqs	= am35xx_uart4_sdma_reqs,
 541	.main_clk	= "uart4_fck",
 542	.prcm		= {
 543		.omap2 = {
 544			.module_offs = CORE_MOD,
 545			.prcm_reg_id = 1,
 546			.module_bit = OMAP3430_EN_UART4_SHIFT,
 547			.idlest_reg_id = 1,
 548			.idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
 549		},
 550	},
 
 
 
 551	.class		= &omap2_uart_class,
 552};
 553
 554static struct omap_hwmod_class i2c_class = {
 555	.name	= "i2c",
 556	.sysc	= &i2c_sysc,
 557	.rev	= OMAP_I2C_IP_VERSION_1,
 558	.reset	= &omap_i2c_reset,
 559};
 560
 561static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 562	{ .name = "dispc", .dma_req = 5 },
 563	{ .name = "dsi1", .dma_req = 74 },
 564	{ .dma_req = -1 }
 565};
 566
 567/* dss */
 568static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 569	/*
 570	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 571	 * driver does not use these clocks.
 572	 */
 573	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
 574	{ .role = "tv_clk", .clk = "dss_tv_fck" },
 575	/* required only on OMAP3430 */
 576	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 577};
 578
 579static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 580	.name		= "dss_core",
 581	.class		= &omap2_dss_hwmod_class,
 582	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 583	.sdma_reqs	= omap3xxx_dss_sdma_chs,
 584	.prcm		= {
 585		.omap2 = {
 586			.prcm_reg_id = 1,
 587			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 588			.module_offs = OMAP3430_DSS_MOD,
 589			.idlest_reg_id = 1,
 590			.idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 591		},
 592	},
 593	.opt_clks	= dss_opt_clks,
 594	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 595	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 596};
 597
 598static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 599	.name		= "dss_core",
 600	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 601	.class		= &omap2_dss_hwmod_class,
 602	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
 603	.sdma_reqs	= omap3xxx_dss_sdma_chs,
 604	.prcm		= {
 605		.omap2 = {
 606			.prcm_reg_id = 1,
 607			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 608			.module_offs = OMAP3430_DSS_MOD,
 609			.idlest_reg_id = 1,
 610			.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 611			.idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 612		},
 613	},
 614	.opt_clks	= dss_opt_clks,
 615	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 616};
 617
 618/*
 619 * 'dispc' class
 620 * display controller
 621 */
 622
 623static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 624	.rev_offs	= 0x0000,
 625	.sysc_offs	= 0x0010,
 626	.syss_offs	= 0x0014,
 627	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 628			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 629			   SYSC_HAS_ENAWAKEUP),
 630	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 631			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 632	.sysc_fields	= &omap_hwmod_sysc_type1,
 633};
 634
 635static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 636	.name	= "dispc",
 637	.sysc	= &omap3_dispc_sysc,
 638};
 639
 640static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 641	.name		= "dss_dispc",
 642	.class		= &omap3_dispc_hwmod_class,
 643	.mpu_irqs	= omap2_dispc_irqs,
 644	.main_clk	= "dss1_alwon_fck",
 645	.prcm		= {
 646		.omap2 = {
 647			.prcm_reg_id = 1,
 648			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 649			.module_offs = OMAP3430_DSS_MOD,
 650		},
 651	},
 652	.flags		= HWMOD_NO_IDLEST,
 653	.dev_attr	= &omap2_3_dss_dispc_dev_attr
 654};
 655
 656/*
 657 * 'dsi' class
 658 * display serial interface controller
 659 */
 660
 661static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 662	.name = "dsi",
 663};
 664
 665static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 666	{ .irq = 25 },
 667	{ .irq = -1 }
 668};
 669
 670/* dss_dsi1 */
 671static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 672	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
 673};
 674
 675static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 676	.name		= "dss_dsi1",
 677	.class		= &omap3xxx_dsi_hwmod_class,
 678	.mpu_irqs	= omap3xxx_dsi1_irqs,
 679	.main_clk	= "dss1_alwon_fck",
 680	.prcm		= {
 681		.omap2 = {
 682			.prcm_reg_id = 1,
 683			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 684			.module_offs = OMAP3430_DSS_MOD,
 685		},
 686	},
 687	.opt_clks	= dss_dsi1_opt_clks,
 688	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 689	.flags		= HWMOD_NO_IDLEST,
 690};
 691
 692static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 693	{ .role = "ick", .clk = "dss_ick" },
 694};
 695
 696static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 697	.name		= "dss_rfbi",
 698	.class		= &omap2_rfbi_hwmod_class,
 699	.main_clk	= "dss1_alwon_fck",
 700	.prcm		= {
 701		.omap2 = {
 702			.prcm_reg_id = 1,
 703			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 704			.module_offs = OMAP3430_DSS_MOD,
 705		},
 706	},
 707	.opt_clks	= dss_rfbi_opt_clks,
 708	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 709	.flags		= HWMOD_NO_IDLEST,
 710};
 711
 712static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 713	/* required only on OMAP3430 */
 714	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 715};
 716
 717static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 718	.name		= "dss_venc",
 719	.class		= &omap2_venc_hwmod_class,
 720	.main_clk	= "dss_tv_fck",
 721	.prcm		= {
 722		.omap2 = {
 723			.prcm_reg_id = 1,
 724			.module_bit = OMAP3430_EN_DSS1_SHIFT,
 725			.module_offs = OMAP3430_DSS_MOD,
 726		},
 727	},
 728	.opt_clks	= dss_venc_opt_clks,
 729	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
 730	.flags		= HWMOD_NO_IDLEST,
 731};
 732
 733/* I2C1 */
 734static struct omap_i2c_dev_attr i2c1_dev_attr = {
 735	.fifo_depth	= 8, /* bytes */
 736	.flags		= OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 737			  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 738			  OMAP_I2C_FLAG_BUS_SHIFT_2,
 739};
 740
 741static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 742	.name		= "i2c1",
 743	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 744	.mpu_irqs	= omap2_i2c1_mpu_irqs,
 745	.sdma_reqs	= omap2_i2c1_sdma_reqs,
 746	.main_clk	= "i2c1_fck",
 747	.prcm		= {
 748		.omap2 = {
 749			.module_offs = CORE_MOD,
 750			.prcm_reg_id = 1,
 751			.module_bit = OMAP3430_EN_I2C1_SHIFT,
 752			.idlest_reg_id = 1,
 753			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 754		},
 755	},
 756	.class		= &i2c_class,
 757	.dev_attr	= &i2c1_dev_attr,
 758};
 759
 760/* I2C2 */
 761static struct omap_i2c_dev_attr i2c2_dev_attr = {
 762	.fifo_depth	= 8, /* bytes */
 763	.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 764		 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 765		 OMAP_I2C_FLAG_BUS_SHIFT_2,
 766};
 767
 768static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 769	.name		= "i2c2",
 770	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 771	.mpu_irqs	= omap2_i2c2_mpu_irqs,
 772	.sdma_reqs	= omap2_i2c2_sdma_reqs,
 773	.main_clk	= "i2c2_fck",
 774	.prcm		= {
 775		.omap2 = {
 776			.module_offs = CORE_MOD,
 777			.prcm_reg_id = 1,
 778			.module_bit = OMAP3430_EN_I2C2_SHIFT,
 779			.idlest_reg_id = 1,
 780			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 781		},
 782	},
 783	.class		= &i2c_class,
 784	.dev_attr	= &i2c2_dev_attr,
 785};
 786
 787/* I2C3 */
 788static struct omap_i2c_dev_attr i2c3_dev_attr = {
 789	.fifo_depth	= 64, /* bytes */
 790	.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 791		 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 792		 OMAP_I2C_FLAG_BUS_SHIFT_2,
 793};
 794
 795static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 796	{ .irq = INT_34XX_I2C3_IRQ, },
 797	{ .irq = -1 }
 798};
 799
 800static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 801	{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 802	{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 803	{ .dma_req = -1 }
 804};
 805
 806static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 807	.name		= "i2c3",
 808	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 809	.mpu_irqs	= i2c3_mpu_irqs,
 810	.sdma_reqs	= i2c3_sdma_reqs,
 811	.main_clk	= "i2c3_fck",
 812	.prcm		= {
 813		.omap2 = {
 814			.module_offs = CORE_MOD,
 815			.prcm_reg_id = 1,
 816			.module_bit = OMAP3430_EN_I2C3_SHIFT,
 817			.idlest_reg_id = 1,
 818			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 819		},
 820	},
 821	.class		= &i2c_class,
 822	.dev_attr	= &i2c3_dev_attr,
 823};
 824
 825/*
 826 * 'gpio' class
 827 * general purpose io module
 828 */
 829
 830static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 831	.rev_offs	= 0x0000,
 832	.sysc_offs	= 0x0010,
 833	.syss_offs	= 0x0014,
 834	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 835			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 836			   SYSS_HAS_RESET_STATUS),
 837	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 838	.sysc_fields    = &omap_hwmod_sysc_type1,
 839};
 840
 841static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 842	.name = "gpio",
 843	.sysc = &omap3xxx_gpio_sysc,
 844	.rev = 1,
 845};
 846
 847/* gpio_dev_attr */
 848static struct omap_gpio_dev_attr gpio_dev_attr = {
 849	.bank_width = 32,
 850	.dbck_flag = true,
 851};
 852
 853/* gpio1 */
 854static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 855	{ .role = "dbclk", .clk = "gpio1_dbck", },
 856};
 857
 858static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 859	.name		= "gpio1",
 860	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 861	.mpu_irqs	= omap2_gpio1_irqs,
 862	.main_clk	= "gpio1_ick",
 863	.opt_clks	= gpio1_opt_clks,
 864	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
 865	.prcm		= {
 866		.omap2 = {
 867			.prcm_reg_id = 1,
 868			.module_bit = OMAP3430_EN_GPIO1_SHIFT,
 869			.module_offs = WKUP_MOD,
 870			.idlest_reg_id = 1,
 871			.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 872		},
 873	},
 874	.class		= &omap3xxx_gpio_hwmod_class,
 875	.dev_attr	= &gpio_dev_attr,
 876};
 877
 878/* gpio2 */
 879static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 880	{ .role = "dbclk", .clk = "gpio2_dbck", },
 881};
 882
 883static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 884	.name		= "gpio2",
 885	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 886	.mpu_irqs	= omap2_gpio2_irqs,
 887	.main_clk	= "gpio2_ick",
 888	.opt_clks	= gpio2_opt_clks,
 889	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
 890	.prcm		= {
 891		.omap2 = {
 892			.prcm_reg_id = 1,
 893			.module_bit = OMAP3430_EN_GPIO2_SHIFT,
 894			.module_offs = OMAP3430_PER_MOD,
 895			.idlest_reg_id = 1,
 896			.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 897		},
 898	},
 899	.class		= &omap3xxx_gpio_hwmod_class,
 900	.dev_attr	= &gpio_dev_attr,
 901};
 902
 903/* gpio3 */
 904static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 905	{ .role = "dbclk", .clk = "gpio3_dbck", },
 906};
 907
 908static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 909	.name		= "gpio3",
 910	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 911	.mpu_irqs	= omap2_gpio3_irqs,
 912	.main_clk	= "gpio3_ick",
 913	.opt_clks	= gpio3_opt_clks,
 914	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
 915	.prcm		= {
 916		.omap2 = {
 917			.prcm_reg_id = 1,
 918			.module_bit = OMAP3430_EN_GPIO3_SHIFT,
 919			.module_offs = OMAP3430_PER_MOD,
 920			.idlest_reg_id = 1,
 921			.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 922		},
 923	},
 924	.class		= &omap3xxx_gpio_hwmod_class,
 925	.dev_attr	= &gpio_dev_attr,
 926};
 927
 928/* gpio4 */
 929static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 930	{ .role = "dbclk", .clk = "gpio4_dbck", },
 931};
 932
 933static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 934	.name		= "gpio4",
 935	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 936	.mpu_irqs	= omap2_gpio4_irqs,
 937	.main_clk	= "gpio4_ick",
 938	.opt_clks	= gpio4_opt_clks,
 939	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
 940	.prcm		= {
 941		.omap2 = {
 942			.prcm_reg_id = 1,
 943			.module_bit = OMAP3430_EN_GPIO4_SHIFT,
 944			.module_offs = OMAP3430_PER_MOD,
 945			.idlest_reg_id = 1,
 946			.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 947		},
 948	},
 949	.class		= &omap3xxx_gpio_hwmod_class,
 950	.dev_attr	= &gpio_dev_attr,
 951};
 952
 953/* gpio5 */
 954static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 955	{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
 956	{ .irq = -1 }
 957};
 958
 959static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 960	{ .role = "dbclk", .clk = "gpio5_dbck", },
 961};
 962
 963static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 964	.name		= "gpio5",
 965	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 966	.mpu_irqs	= omap3xxx_gpio5_irqs,
 967	.main_clk	= "gpio5_ick",
 968	.opt_clks	= gpio5_opt_clks,
 969	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
 970	.prcm		= {
 971		.omap2 = {
 972			.prcm_reg_id = 1,
 973			.module_bit = OMAP3430_EN_GPIO5_SHIFT,
 974			.module_offs = OMAP3430_PER_MOD,
 975			.idlest_reg_id = 1,
 976			.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 977		},
 978	},
 979	.class		= &omap3xxx_gpio_hwmod_class,
 980	.dev_attr	= &gpio_dev_attr,
 981};
 982
 983/* gpio6 */
 984static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
 985	{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
 986	{ .irq = -1 }
 987};
 988
 989static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 990	{ .role = "dbclk", .clk = "gpio6_dbck", },
 991};
 992
 993static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 994	.name		= "gpio6",
 995	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 996	.mpu_irqs	= omap3xxx_gpio6_irqs,
 997	.main_clk	= "gpio6_ick",
 998	.opt_clks	= gpio6_opt_clks,
 999	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1000	.prcm		= {
1001		.omap2 = {
1002			.prcm_reg_id = 1,
1003			.module_bit = OMAP3430_EN_GPIO6_SHIFT,
1004			.module_offs = OMAP3430_PER_MOD,
1005			.idlest_reg_id = 1,
1006			.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1007		},
1008	},
1009	.class		= &omap3xxx_gpio_hwmod_class,
1010	.dev_attr	= &gpio_dev_attr,
1011};
1012
1013/* dma attributes */
1014static struct omap_dma_dev_attr dma_dev_attr = {
1015	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1016				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1017	.lch_count = 32,
1018};
1019
1020static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1021	.rev_offs	= 0x0000,
1022	.sysc_offs	= 0x002c,
1023	.syss_offs	= 0x0028,
1024	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1025			   SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1026			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1027			   SYSS_HAS_RESET_STATUS),
1028	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1029			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1030	.sysc_fields	= &omap_hwmod_sysc_type1,
1031};
1032
1033static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1034	.name = "dma",
1035	.sysc = &omap3xxx_dma_sysc,
1036};
1037
1038/* dma_system */
1039static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1040	.name		= "dma",
1041	.class		= &omap3xxx_dma_hwmod_class,
1042	.mpu_irqs	= omap2_dma_system_irqs,
1043	.main_clk	= "core_l3_ick",
1044	.prcm = {
1045		.omap2 = {
1046			.module_offs		= CORE_MOD,
1047			.prcm_reg_id		= 1,
1048			.module_bit		= OMAP3430_ST_SDMA_SHIFT,
1049			.idlest_reg_id		= 1,
1050			.idlest_idle_bit	= OMAP3430_ST_SDMA_SHIFT,
1051		},
1052	},
1053	.dev_attr	= &dma_dev_attr,
1054	.flags		= HWMOD_NO_IDLEST,
1055};
1056
1057/*
1058 * 'mcbsp' class
1059 * multi channel buffered serial port controller
1060 */
1061
1062static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1063	.sysc_offs	= 0x008c,
1064	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1065			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1066	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1067	.sysc_fields	= &omap_hwmod_sysc_type1,
1068	.clockact	= 0x2,
1069};
1070
1071static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1072	.name = "mcbsp",
1073	.sysc = &omap3xxx_mcbsp_sysc,
1074	.rev  = MCBSP_CONFIG_TYPE3,
1075};
1076
 
 
 
 
 
 
 
 
 
 
 
1077/* mcbsp1 */
1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1079	{ .name = "common", .irq = 16 },
1080	{ .name = "tx", .irq = 59 },
1081	{ .name = "rx", .irq = 60 },
1082	{ .irq = -1 }
1083};
1084
1085static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1086	.name		= "mcbsp1",
1087	.class		= &omap3xxx_mcbsp_hwmod_class,
1088	.mpu_irqs	= omap3xxx_mcbsp1_irqs,
1089	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
1090	.main_clk	= "mcbsp1_fck",
1091	.prcm		= {
1092		.omap2 = {
1093			.prcm_reg_id = 1,
1094			.module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1095			.module_offs = CORE_MOD,
1096			.idlest_reg_id = 1,
1097			.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1098		},
1099	},
 
 
1100};
1101
1102/* mcbsp2 */
1103static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1104	{ .name = "common", .irq = 17 },
1105	{ .name = "tx", .irq = 62 },
1106	{ .name = "rx", .irq = 63 },
1107	{ .irq = -1 }
1108};
1109
1110static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1111	.sidetone	= "mcbsp2_sidetone",
1112};
1113
1114static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1115	.name		= "mcbsp2",
1116	.class		= &omap3xxx_mcbsp_hwmod_class,
1117	.mpu_irqs	= omap3xxx_mcbsp2_irqs,
1118	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
1119	.main_clk	= "mcbsp2_fck",
1120	.prcm		= {
1121		.omap2 = {
1122			.prcm_reg_id = 1,
1123			.module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1124			.module_offs = OMAP3430_PER_MOD,
1125			.idlest_reg_id = 1,
1126			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1127		},
1128	},
 
 
1129	.dev_attr	= &omap34xx_mcbsp2_dev_attr,
1130};
1131
1132/* mcbsp3 */
1133static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1134	{ .name = "common", .irq = 22 },
1135	{ .name = "tx", .irq = 89 },
1136	{ .name = "rx", .irq = 90 },
1137	{ .irq = -1 }
1138};
1139
1140static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1141	.sidetone	= "mcbsp3_sidetone",
1142};
1143
1144static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1145	.name		= "mcbsp3",
1146	.class		= &omap3xxx_mcbsp_hwmod_class,
1147	.mpu_irqs	= omap3xxx_mcbsp3_irqs,
1148	.sdma_reqs	= omap2_mcbsp3_sdma_reqs,
1149	.main_clk	= "mcbsp3_fck",
1150	.prcm		= {
1151		.omap2 = {
1152			.prcm_reg_id = 1,
1153			.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1154			.module_offs = OMAP3430_PER_MOD,
1155			.idlest_reg_id = 1,
1156			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1157		},
1158	},
 
 
1159	.dev_attr	= &omap34xx_mcbsp3_dev_attr,
1160};
1161
1162/* mcbsp4 */
1163static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1164	{ .name = "common", .irq = 23 },
1165	{ .name = "tx", .irq = 54 },
1166	{ .name = "rx", .irq = 55 },
1167	{ .irq = -1 }
1168};
1169
1170static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1171	{ .name = "rx", .dma_req = 20 },
1172	{ .name = "tx", .dma_req = 19 },
1173	{ .dma_req = -1 }
1174};
1175
1176static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1177	.name		= "mcbsp4",
1178	.class		= &omap3xxx_mcbsp_hwmod_class,
1179	.mpu_irqs	= omap3xxx_mcbsp4_irqs,
1180	.sdma_reqs	= omap3xxx_mcbsp4_sdma_chs,
1181	.main_clk	= "mcbsp4_fck",
1182	.prcm		= {
1183		.omap2 = {
1184			.prcm_reg_id = 1,
1185			.module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1186			.module_offs = OMAP3430_PER_MOD,
1187			.idlest_reg_id = 1,
1188			.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1189		},
1190	},
 
 
1191};
1192
1193/* mcbsp5 */
1194static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1195	{ .name = "common", .irq = 27 },
1196	{ .name = "tx", .irq = 81 },
1197	{ .name = "rx", .irq = 82 },
1198	{ .irq = -1 }
1199};
1200
1201static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1202	{ .name = "rx", .dma_req = 22 },
1203	{ .name = "tx", .dma_req = 21 },
1204	{ .dma_req = -1 }
1205};
1206
1207static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1208	.name		= "mcbsp5",
1209	.class		= &omap3xxx_mcbsp_hwmod_class,
1210	.mpu_irqs	= omap3xxx_mcbsp5_irqs,
1211	.sdma_reqs	= omap3xxx_mcbsp5_sdma_chs,
1212	.main_clk	= "mcbsp5_fck",
1213	.prcm		= {
1214		.omap2 = {
1215			.prcm_reg_id = 1,
1216			.module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1217			.module_offs = CORE_MOD,
1218			.idlest_reg_id = 1,
1219			.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1220		},
1221	},
 
 
1222};
1223
1224/* 'mcbsp sidetone' class */
1225static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1226	.sysc_offs	= 0x0010,
1227	.sysc_flags	= SYSC_HAS_AUTOIDLE,
1228	.sysc_fields	= &omap_hwmod_sysc_type1,
1229};
1230
1231static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1232	.name = "mcbsp_sidetone",
1233	.sysc = &omap3xxx_mcbsp_sidetone_sysc,
1234};
1235
1236/* mcbsp2_sidetone */
1237static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1238	{ .name = "irq", .irq = 4 },
1239	{ .irq = -1 }
1240};
1241
1242static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1243	.name		= "mcbsp2_sidetone",
1244	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1245	.mpu_irqs	= omap3xxx_mcbsp2_sidetone_irqs,
1246	.main_clk	= "mcbsp2_fck",
1247	.prcm		= {
1248		.omap2 = {
1249			.prcm_reg_id = 1,
1250			 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1251			.module_offs = OMAP3430_PER_MOD,
1252			.idlest_reg_id = 1,
1253			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1254		},
1255	},
1256};
1257
1258/* mcbsp3_sidetone */
1259static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1260	{ .name = "irq", .irq = 5 },
1261	{ .irq = -1 }
1262};
1263
1264static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1265	.name		= "mcbsp3_sidetone",
1266	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1267	.mpu_irqs	= omap3xxx_mcbsp3_sidetone_irqs,
1268	.main_clk	= "mcbsp3_fck",
1269	.prcm		= {
1270		.omap2 = {
1271			.prcm_reg_id = 1,
1272			.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1273			.module_offs = OMAP3430_PER_MOD,
1274			.idlest_reg_id = 1,
1275			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1276		},
1277	},
1278};
1279
1280/* SR common */
1281static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1282	.clkact_shift	= 20,
1283};
1284
1285static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1286	.sysc_offs	= 0x24,
1287	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1288	.clockact	= CLOCKACT_TEST_ICLK,
1289	.sysc_fields	= &omap34xx_sr_sysc_fields,
1290};
1291
1292static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1293	.name = "smartreflex",
1294	.sysc = &omap34xx_sr_sysc,
1295	.rev  = 1,
1296};
1297
1298static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1299	.sidle_shift	= 24,
1300	.enwkup_shift	= 26,
1301};
1302
1303static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1304	.sysc_offs	= 0x38,
1305	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1306	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1307			SYSC_NO_CACHE),
1308	.sysc_fields	= &omap36xx_sr_sysc_fields,
1309};
1310
1311static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1312	.name = "smartreflex",
1313	.sysc = &omap36xx_sr_sysc,
1314	.rev  = 2,
1315};
1316
1317/* SR1 */
1318static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1319	.sensor_voltdm_name   = "mpu_iva",
1320};
1321
1322static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1323	{ .irq = 18 },
1324	{ .irq = -1 }
1325};
1326
1327static struct omap_hwmod omap34xx_sr1_hwmod = {
1328	.name		= "sr1",
1329	.class		= &omap34xx_smartreflex_hwmod_class,
1330	.main_clk	= "sr1_fck",
1331	.prcm		= {
1332		.omap2 = {
1333			.prcm_reg_id = 1,
1334			.module_bit = OMAP3430_EN_SR1_SHIFT,
1335			.module_offs = WKUP_MOD,
1336			.idlest_reg_id = 1,
1337			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1338		},
1339	},
1340	.dev_attr	= &sr1_dev_attr,
1341	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
1342	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1343};
1344
1345static struct omap_hwmod omap36xx_sr1_hwmod = {
1346	.name		= "sr1",
1347	.class		= &omap36xx_smartreflex_hwmod_class,
1348	.main_clk	= "sr1_fck",
1349	.prcm		= {
1350		.omap2 = {
1351			.prcm_reg_id = 1,
1352			.module_bit = OMAP3430_EN_SR1_SHIFT,
1353			.module_offs = WKUP_MOD,
1354			.idlest_reg_id = 1,
1355			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1356		},
1357	},
1358	.dev_attr	= &sr1_dev_attr,
1359	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
1360};
1361
1362/* SR2 */
1363static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1364	.sensor_voltdm_name	= "core",
1365};
1366
1367static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1368	{ .irq = 19 },
1369	{ .irq = -1 }
1370};
1371
1372static struct omap_hwmod omap34xx_sr2_hwmod = {
1373	.name		= "sr2",
1374	.class		= &omap34xx_smartreflex_hwmod_class,
1375	.main_clk	= "sr2_fck",
1376	.prcm		= {
1377		.omap2 = {
1378			.prcm_reg_id = 1,
1379			.module_bit = OMAP3430_EN_SR2_SHIFT,
1380			.module_offs = WKUP_MOD,
1381			.idlest_reg_id = 1,
1382			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1383		},
1384	},
1385	.dev_attr	= &sr2_dev_attr,
1386	.mpu_irqs	= omap3_smartreflex_core_irqs,
1387	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1388};
1389
1390static struct omap_hwmod omap36xx_sr2_hwmod = {
1391	.name		= "sr2",
1392	.class		= &omap36xx_smartreflex_hwmod_class,
1393	.main_clk	= "sr2_fck",
1394	.prcm		= {
1395		.omap2 = {
1396			.prcm_reg_id = 1,
1397			.module_bit = OMAP3430_EN_SR2_SHIFT,
1398			.module_offs = WKUP_MOD,
1399			.idlest_reg_id = 1,
1400			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1401		},
1402	},
1403	.dev_attr	= &sr2_dev_attr,
1404	.mpu_irqs	= omap3_smartreflex_core_irqs,
1405};
1406
1407/*
1408 * 'mailbox' class
1409 * mailbox module allowing communication between the on-chip processors
1410 * using a queued mailbox-interrupt mechanism.
1411 */
1412
1413static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1414	.rev_offs	= 0x000,
1415	.sysc_offs	= 0x010,
1416	.syss_offs	= 0x014,
1417	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1418				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1419	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1420	.sysc_fields	= &omap_hwmod_sysc_type1,
1421};
1422
1423static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1424	.name = "mailbox",
1425	.sysc = &omap3xxx_mailbox_sysc,
1426};
1427
 
 
 
 
 
 
 
 
 
 
 
1428static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1429	{ .irq = 26 },
1430	{ .irq = -1 }
1431};
1432
1433static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1434	.name		= "mailbox",
1435	.class		= &omap3xxx_mailbox_hwmod_class,
1436	.mpu_irqs	= omap3xxx_mailbox_irqs,
1437	.main_clk	= "mailboxes_ick",
1438	.prcm		= {
1439		.omap2 = {
1440			.prcm_reg_id = 1,
1441			.module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1442			.module_offs = CORE_MOD,
1443			.idlest_reg_id = 1,
1444			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1445		},
1446	},
 
1447};
1448
1449/*
1450 * 'mcspi' class
1451 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1452 * bus
1453 */
1454
1455static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1456	.rev_offs	= 0x0000,
1457	.sysc_offs	= 0x0010,
1458	.syss_offs	= 0x0014,
1459	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1460				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1461				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1462	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1463	.sysc_fields    = &omap_hwmod_sysc_type1,
1464};
1465
1466static struct omap_hwmod_class omap34xx_mcspi_class = {
1467	.name = "mcspi",
1468	.sysc = &omap34xx_mcspi_sysc,
1469	.rev = OMAP3_MCSPI_REV,
1470};
1471
1472/* mcspi1 */
1473static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1474	.num_chipselect = 4,
1475};
1476
1477static struct omap_hwmod omap34xx_mcspi1 = {
1478	.name		= "mcspi1",
1479	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
1480	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
1481	.main_clk	= "mcspi1_fck",
1482	.prcm		= {
1483		.omap2 = {
1484			.module_offs = CORE_MOD,
1485			.prcm_reg_id = 1,
1486			.module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1487			.idlest_reg_id = 1,
1488			.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1489		},
1490	},
1491	.class		= &omap34xx_mcspi_class,
1492	.dev_attr       = &omap_mcspi1_dev_attr,
1493};
1494
1495/* mcspi2 */
1496static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1497	.num_chipselect = 2,
1498};
1499
1500static struct omap_hwmod omap34xx_mcspi2 = {
1501	.name		= "mcspi2",
1502	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
1503	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
1504	.main_clk	= "mcspi2_fck",
1505	.prcm		= {
1506		.omap2 = {
1507			.module_offs = CORE_MOD,
1508			.prcm_reg_id = 1,
1509			.module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1510			.idlest_reg_id = 1,
1511			.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1512		},
1513	},
1514	.class		= &omap34xx_mcspi_class,
1515	.dev_attr       = &omap_mcspi2_dev_attr,
1516};
1517
1518/* mcspi3 */
1519static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1520	{ .name = "irq", .irq = 91 }, /* 91 */
1521	{ .irq = -1 }
1522};
1523
1524static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1525	{ .name = "tx0", .dma_req = 15 },
1526	{ .name = "rx0", .dma_req = 16 },
1527	{ .name = "tx1", .dma_req = 23 },
1528	{ .name = "rx1", .dma_req = 24 },
1529	{ .dma_req = -1 }
1530};
1531
1532static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1533	.num_chipselect = 2,
1534};
1535
1536static struct omap_hwmod omap34xx_mcspi3 = {
1537	.name		= "mcspi3",
1538	.mpu_irqs	= omap34xx_mcspi3_mpu_irqs,
1539	.sdma_reqs	= omap34xx_mcspi3_sdma_reqs,
1540	.main_clk	= "mcspi3_fck",
1541	.prcm		= {
1542		.omap2 = {
1543			.module_offs = CORE_MOD,
1544			.prcm_reg_id = 1,
1545			.module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1546			.idlest_reg_id = 1,
1547			.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1548		},
1549	},
1550	.class		= &omap34xx_mcspi_class,
1551	.dev_attr       = &omap_mcspi3_dev_attr,
1552};
1553
1554/* mcspi4 */
1555static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1556	{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1557	{ .irq = -1 }
1558};
1559
1560static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1561	{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1562	{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1563	{ .dma_req = -1 }
1564};
1565
1566static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1567	.num_chipselect = 1,
1568};
1569
1570static struct omap_hwmod omap34xx_mcspi4 = {
1571	.name		= "mcspi4",
1572	.mpu_irqs	= omap34xx_mcspi4_mpu_irqs,
1573	.sdma_reqs	= omap34xx_mcspi4_sdma_reqs,
1574	.main_clk	= "mcspi4_fck",
1575	.prcm		= {
1576		.omap2 = {
1577			.module_offs = CORE_MOD,
1578			.prcm_reg_id = 1,
1579			.module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1580			.idlest_reg_id = 1,
1581			.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1582		},
1583	},
1584	.class		= &omap34xx_mcspi_class,
1585	.dev_attr       = &omap_mcspi4_dev_attr,
1586};
1587
1588/* usbhsotg */
1589static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1590	.rev_offs	= 0x0400,
1591	.sysc_offs	= 0x0404,
1592	.syss_offs	= 0x0408,
1593	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1594			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1595			  SYSC_HAS_AUTOIDLE),
1596	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1597			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1598	.sysc_fields	= &omap_hwmod_sysc_type1,
1599};
1600
1601static struct omap_hwmod_class usbotg_class = {
1602	.name = "usbotg",
1603	.sysc = &omap3xxx_usbhsotg_sysc,
1604};
1605
1606/* usb_otg_hs */
1607static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1608
1609	{ .name = "mc", .irq = 92 },
1610	{ .name = "dma", .irq = 93 },
1611	{ .irq = -1 }
1612};
1613
1614static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1615	.name		= "usb_otg_hs",
1616	.mpu_irqs	= omap3xxx_usbhsotg_mpu_irqs,
1617	.main_clk	= "hsotgusb_ick",
1618	.prcm		= {
1619		.omap2 = {
1620			.prcm_reg_id = 1,
1621			.module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1622			.module_offs = CORE_MOD,
1623			.idlest_reg_id = 1,
1624			.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1625			.idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1626		},
1627	},
1628	.class		= &usbotg_class,
1629
1630	/*
1631	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1632	 * broken when autoidle is enabled
1633	 * workaround is to disable the autoidle bit at module level.
 
 
 
 
 
1634	 */
1635	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1636				| HWMOD_SWSUP_MSTANDBY,
1637};
1638
1639/* usb_otg_hs */
1640static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1641
1642	{ .name = "mc", .irq = 71 },
1643	{ .irq = -1 }
1644};
1645
1646static struct omap_hwmod_class am35xx_usbotg_class = {
1647	.name = "am35xx_usbotg",
1648	.sysc = NULL,
1649};
1650
1651static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1652	.name		= "am35x_otg_hs",
1653	.mpu_irqs	= am35xx_usbhsotg_mpu_irqs,
1654	.main_clk	= NULL,
1655	.prcm = {
1656		.omap2 = {
1657		},
1658	},
1659	.class		= &am35xx_usbotg_class,
 
1660};
1661
1662/* MMC/SD/SDIO common */
1663static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1664	.rev_offs	= 0x1fc,
1665	.sysc_offs	= 0x10,
1666	.syss_offs	= 0x14,
1667	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1668			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1669			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1670	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1671	.sysc_fields    = &omap_hwmod_sysc_type1,
1672};
1673
1674static struct omap_hwmod_class omap34xx_mmc_class = {
1675	.name = "mmc",
1676	.sysc = &omap34xx_mmc_sysc,
1677};
1678
1679/* MMC/SD/SDIO1 */
1680
1681static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1682	{ .irq = 83, },
1683	{ .irq = -1 }
1684};
1685
1686static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1687	{ .name = "tx",	.dma_req = 61, },
1688	{ .name = "rx",	.dma_req = 62, },
1689	{ .dma_req = -1 }
1690};
1691
1692static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1693	{ .role = "dbck", .clk = "omap_32k_fck", },
1694};
1695
1696static struct omap_mmc_dev_attr mmc1_dev_attr = {
1697	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1698};
1699
1700/* See 35xx errata 2.1.1.128 in SPRZ278F */
1701static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1702	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1703		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1704};
1705
1706static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1707	.name		= "mmc1",
1708	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
1709	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
1710	.opt_clks	= omap34xx_mmc1_opt_clks,
1711	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1712	.main_clk	= "mmchs1_fck",
1713	.prcm		= {
1714		.omap2 = {
1715			.module_offs = CORE_MOD,
1716			.prcm_reg_id = 1,
1717			.module_bit = OMAP3430_EN_MMC1_SHIFT,
1718			.idlest_reg_id = 1,
1719			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1720		},
1721	},
1722	.dev_attr	= &mmc1_pre_es3_dev_attr,
1723	.class		= &omap34xx_mmc_class,
1724};
1725
1726static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1727	.name		= "mmc1",
1728	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
1729	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
1730	.opt_clks	= omap34xx_mmc1_opt_clks,
1731	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1732	.main_clk	= "mmchs1_fck",
1733	.prcm		= {
1734		.omap2 = {
1735			.module_offs = CORE_MOD,
1736			.prcm_reg_id = 1,
1737			.module_bit = OMAP3430_EN_MMC1_SHIFT,
1738			.idlest_reg_id = 1,
1739			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1740		},
1741	},
1742	.dev_attr	= &mmc1_dev_attr,
1743	.class		= &omap34xx_mmc_class,
1744};
1745
1746/* MMC/SD/SDIO2 */
1747
1748static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1749	{ .irq = INT_24XX_MMC2_IRQ, },
1750	{ .irq = -1 }
1751};
1752
1753static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1754	{ .name = "tx",	.dma_req = 47, },
1755	{ .name = "rx",	.dma_req = 48, },
1756	{ .dma_req = -1 }
1757};
1758
1759static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1760	{ .role = "dbck", .clk = "omap_32k_fck", },
1761};
1762
1763/* See 35xx errata 2.1.1.128 in SPRZ278F */
1764static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1765	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1766};
1767
1768static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1769	.name		= "mmc2",
1770	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
1771	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
1772	.opt_clks	= omap34xx_mmc2_opt_clks,
1773	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1774	.main_clk	= "mmchs2_fck",
1775	.prcm		= {
1776		.omap2 = {
1777			.module_offs = CORE_MOD,
1778			.prcm_reg_id = 1,
1779			.module_bit = OMAP3430_EN_MMC2_SHIFT,
1780			.idlest_reg_id = 1,
1781			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1782		},
1783	},
1784	.dev_attr	= &mmc2_pre_es3_dev_attr,
1785	.class		= &omap34xx_mmc_class,
1786};
1787
1788static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1789	.name		= "mmc2",
1790	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
1791	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
1792	.opt_clks	= omap34xx_mmc2_opt_clks,
1793	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1794	.main_clk	= "mmchs2_fck",
1795	.prcm		= {
1796		.omap2 = {
1797			.module_offs = CORE_MOD,
1798			.prcm_reg_id = 1,
1799			.module_bit = OMAP3430_EN_MMC2_SHIFT,
1800			.idlest_reg_id = 1,
1801			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1802		},
1803	},
1804	.class		= &omap34xx_mmc_class,
1805};
1806
1807/* MMC/SD/SDIO3 */
1808
1809static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1810	{ .irq = 94, },
1811	{ .irq = -1 }
1812};
1813
1814static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1815	{ .name = "tx",	.dma_req = 77, },
1816	{ .name = "rx",	.dma_req = 78, },
1817	{ .dma_req = -1 }
1818};
1819
1820static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1821	{ .role = "dbck", .clk = "omap_32k_fck", },
1822};
1823
1824static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1825	.name		= "mmc3",
1826	.mpu_irqs	= omap34xx_mmc3_mpu_irqs,
1827	.sdma_reqs	= omap34xx_mmc3_sdma_reqs,
1828	.opt_clks	= omap34xx_mmc3_opt_clks,
1829	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1830	.main_clk	= "mmchs3_fck",
1831	.prcm		= {
1832		.omap2 = {
1833			.prcm_reg_id = 1,
1834			.module_bit = OMAP3430_EN_MMC3_SHIFT,
1835			.idlest_reg_id = 1,
1836			.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1837		},
1838	},
1839	.class		= &omap34xx_mmc_class,
1840};
1841
1842/*
1843 * 'usb_host_hs' class
1844 * high-speed multi-port usb host controller
1845 */
1846
1847static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1848	.rev_offs	= 0x0000,
1849	.sysc_offs	= 0x0010,
1850	.syss_offs	= 0x0014,
1851	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1852			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1853			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 
1854	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1855			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1856	.sysc_fields	= &omap_hwmod_sysc_type1,
1857};
1858
1859static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1860	.name = "usb_host_hs",
1861	.sysc = &omap3xxx_usb_host_hs_sysc,
1862};
1863
1864static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1865	  { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1866};
1867
1868static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1869	{ .name = "ohci-irq", .irq = 76 },
1870	{ .name = "ehci-irq", .irq = 77 },
1871	{ .irq = -1 }
1872};
1873
1874static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1875	.name		= "usb_host_hs",
1876	.class		= &omap3xxx_usb_host_hs_hwmod_class,
1877	.clkdm_name	= "l3_init_clkdm",
1878	.mpu_irqs	= omap3xxx_usb_host_hs_irqs,
1879	.main_clk	= "usbhost_48m_fck",
1880	.prcm = {
1881		.omap2 = {
1882			.module_offs = OMAP3430ES2_USBHOST_MOD,
1883			.prcm_reg_id = 1,
1884			.module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1885			.idlest_reg_id = 1,
1886			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1887			.idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1888		},
1889	},
1890	.opt_clks	= omap3xxx_usb_host_hs_opt_clks,
1891	.opt_clks_cnt	= ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1892
1893	/*
1894	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1895	 * id: i660
1896	 *
1897	 * Description:
1898	 * In the following configuration :
1899	 * - USBHOST module is set to smart-idle mode
1900	 * - PRCM asserts idle_req to the USBHOST module ( This typically
1901	 *   happens when the system is going to a low power mode : all ports
1902	 *   have been suspended, the master part of the USBHOST module has
1903	 *   entered the standby state, and SW has cut the functional clocks)
1904	 * - an USBHOST interrupt occurs before the module is able to answer
1905	 *   idle_ack, typically a remote wakeup IRQ.
1906	 * Then the USB HOST module will enter a deadlock situation where it
1907	 * is no more accessible nor functional.
1908	 *
1909	 * Workaround:
1910	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1911	 */
1912
1913	/*
1914	 * Errata: USB host EHCI may stall when entering smart-standby mode
1915	 * Id: i571
1916	 *
1917	 * Description:
1918	 * When the USBHOST module is set to smart-standby mode, and when it is
1919	 * ready to enter the standby state (i.e. all ports are suspended and
1920	 * all attached devices are in suspend mode), then it can wrongly assert
1921	 * the Mstandby signal too early while there are still some residual OCP
1922	 * transactions ongoing. If this condition occurs, the internal state
1923	 * machine may go to an undefined state and the USB link may be stuck
1924	 * upon the next resume.
1925	 *
1926	 * Workaround:
1927	 * Don't use smart standby; use only force standby,
1928	 * hence HWMOD_SWSUP_MSTANDBY
1929	 */
1930
1931	/*
1932	 * During system boot; If the hwmod framework resets the module
1933	 * the module will have smart idle settings; which can lead to deadlock
1934	 * (above Errata Id:i660); so, dont reset the module during boot;
1935	 * Use HWMOD_INIT_NO_RESET.
1936	 */
1937
1938	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1939			  HWMOD_INIT_NO_RESET,
1940};
1941
1942/*
1943 * 'usb_tll_hs' class
1944 * usb_tll_hs module is the adapter on the usb_host_hs ports
1945 */
1946static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1947	.rev_offs	= 0x0000,
1948	.sysc_offs	= 0x0010,
1949	.syss_offs	= 0x0014,
1950	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1951			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1952			   SYSC_HAS_AUTOIDLE),
1953	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1954	.sysc_fields	= &omap_hwmod_sysc_type1,
1955};
1956
1957static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1958	.name = "usb_tll_hs",
1959	.sysc = &omap3xxx_usb_tll_hs_sysc,
1960};
1961
1962static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1963	{ .name = "tll-irq", .irq = 78 },
1964	{ .irq = -1 }
1965};
1966
1967static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1968	.name		= "usb_tll_hs",
1969	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
1970	.clkdm_name	= "l3_init_clkdm",
1971	.mpu_irqs	= omap3xxx_usb_tll_hs_irqs,
1972	.main_clk	= "usbtll_fck",
1973	.prcm = {
1974		.omap2 = {
1975			.module_offs = CORE_MOD,
1976			.prcm_reg_id = 3,
1977			.module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1978			.idlest_reg_id = 3,
1979			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1980		},
1981	},
1982};
1983
1984static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1985	.name		= "hdq1w",
1986	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
1987	.main_clk	= "hdq_fck",
1988	.prcm		= {
1989		.omap2 = {
1990			.module_offs = CORE_MOD,
1991			.prcm_reg_id = 1,
1992			.module_bit = OMAP3430_EN_HDQ_SHIFT,
1993			.idlest_reg_id = 1,
1994			.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1995		},
1996	},
1997	.class		= &omap2_hdq1w_class,
1998};
1999
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2000/*
2001 * '32K sync counter' class
2002 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2003 */
2004static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2005	.rev_offs	= 0x0000,
2006	.sysc_offs	= 0x0004,
2007	.sysc_flags	= SYSC_HAS_SIDLEMODE,
2008	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
2009	.sysc_fields	= &omap_hwmod_sysc_type1,
2010};
2011
2012static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2013	.name	= "counter",
2014	.sysc	= &omap3xxx_counter_sysc,
2015};
2016
2017static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2018	.name		= "counter_32k",
2019	.class		= &omap3xxx_counter_hwmod_class,
2020	.clkdm_name	= "wkup_clkdm",
2021	.flags		= HWMOD_SWSUP_SIDLE,
2022	.main_clk	= "wkup_32k_fck",
2023	.prcm		= {
2024		.omap2	= {
2025			.module_offs = WKUP_MOD,
2026			.prcm_reg_id = 1,
2027			.module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2028			.idlest_reg_id = 1,
2029			.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2030		},
2031	},
2032};
2033
2034/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2035 * interfaces
2036 */
2037
2038/* L3 -> L4_CORE interface */
2039static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2040	.master	= &omap3xxx_l3_main_hwmod,
2041	.slave	= &omap3xxx_l4_core_hwmod,
2042	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2043};
2044
2045/* L3 -> L4_PER interface */
2046static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2047	.master = &omap3xxx_l3_main_hwmod,
2048	.slave	= &omap3xxx_l4_per_hwmod,
2049	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2050};
2051
2052static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2053	{
2054		.pa_start	= 0x68000000,
2055		.pa_end		= 0x6800ffff,
2056		.flags		= ADDR_TYPE_RT,
2057	},
2058	{ }
2059};
2060
2061/* MPU -> L3 interface */
2062static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2063	.master   = &omap3xxx_mpu_hwmod,
2064	.slave    = &omap3xxx_l3_main_hwmod,
2065	.addr     = omap3xxx_l3_main_addrs,
2066	.user	= OCP_USER_MPU,
2067};
2068
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2069/* DSS -> l3 */
2070static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2071	.master		= &omap3430es1_dss_core_hwmod,
2072	.slave		= &omap3xxx_l3_main_hwmod,
2073	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2074};
2075
2076static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2077	.master		= &omap3xxx_dss_core_hwmod,
2078	.slave		= &omap3xxx_l3_main_hwmod,
2079	.fw = {
2080		.omap2 = {
2081			.l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2082			.flags	= OMAP_FIREWALL_L3,
2083		}
2084	},
2085	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2086};
2087
2088/* l3_core -> usbhsotg interface */
2089static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2090	.master		= &omap3xxx_usbhsotg_hwmod,
2091	.slave		= &omap3xxx_l3_main_hwmod,
2092	.clk		= "core_l3_ick",
2093	.user		= OCP_USER_MPU,
2094};
2095
2096/* l3_core -> am35xx_usbhsotg interface */
2097static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2098	.master		= &am35xx_usbhsotg_hwmod,
2099	.slave		= &omap3xxx_l3_main_hwmod,
 
 
 
 
 
 
 
 
2100	.clk		= "core_l3_ick",
2101	.user		= OCP_USER_MPU,
2102};
 
2103/* L4_CORE -> L4_WKUP interface */
2104static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2105	.master	= &omap3xxx_l4_core_hwmod,
2106	.slave	= &omap3xxx_l4_wkup_hwmod,
2107	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* L4 CORE -> MMC1 interface */
2111static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2112	.master		= &omap3xxx_l4_core_hwmod,
2113	.slave		= &omap3xxx_pre_es3_mmc1_hwmod,
2114	.clk		= "mmchs1_ick",
2115	.addr		= omap2430_mmc1_addr_space,
2116	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2117	.flags		= OMAP_FIREWALL_L4
2118};
2119
2120static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2121	.master		= &omap3xxx_l4_core_hwmod,
2122	.slave		= &omap3xxx_es3plus_mmc1_hwmod,
2123	.clk		= "mmchs1_ick",
2124	.addr		= omap2430_mmc1_addr_space,
2125	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2126	.flags		= OMAP_FIREWALL_L4
2127};
2128
2129/* L4 CORE -> MMC2 interface */
2130static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2131	.master		= &omap3xxx_l4_core_hwmod,
2132	.slave		= &omap3xxx_pre_es3_mmc2_hwmod,
2133	.clk		= "mmchs2_ick",
2134	.addr		= omap2430_mmc2_addr_space,
2135	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2136	.flags		= OMAP_FIREWALL_L4
2137};
2138
2139static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2140	.master		= &omap3xxx_l4_core_hwmod,
2141	.slave		= &omap3xxx_es3plus_mmc2_hwmod,
2142	.clk		= "mmchs2_ick",
2143	.addr		= omap2430_mmc2_addr_space,
2144	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2145	.flags		= OMAP_FIREWALL_L4
2146};
2147
2148/* L4 CORE -> MMC3 interface */
2149static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2150	{
2151		.pa_start	= 0x480ad000,
2152		.pa_end		= 0x480ad1ff,
2153		.flags		= ADDR_TYPE_RT,
2154	},
2155	{ }
2156};
2157
2158static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2159	.master		= &omap3xxx_l4_core_hwmod,
2160	.slave		= &omap3xxx_mmc3_hwmod,
2161	.clk		= "mmchs3_ick",
2162	.addr		= omap3xxx_mmc3_addr_space,
2163	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2164	.flags		= OMAP_FIREWALL_L4
2165};
2166
2167/* L4 CORE -> UART1 interface */
2168static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2169	{
2170		.pa_start	= OMAP3_UART1_BASE,
2171		.pa_end		= OMAP3_UART1_BASE + SZ_8K - 1,
2172		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2173	},
2174	{ }
2175};
2176
2177static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2178	.master		= &omap3xxx_l4_core_hwmod,
2179	.slave		= &omap3xxx_uart1_hwmod,
2180	.clk		= "uart1_ick",
2181	.addr		= omap3xxx_uart1_addr_space,
2182	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2183};
2184
2185/* L4 CORE -> UART2 interface */
2186static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2187	{
2188		.pa_start	= OMAP3_UART2_BASE,
2189		.pa_end		= OMAP3_UART2_BASE + SZ_1K - 1,
2190		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2191	},
2192	{ }
2193};
2194
2195static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2196	.master		= &omap3xxx_l4_core_hwmod,
2197	.slave		= &omap3xxx_uart2_hwmod,
2198	.clk		= "uart2_ick",
2199	.addr		= omap3xxx_uart2_addr_space,
2200	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2201};
2202
2203/* L4 PER -> UART3 interface */
2204static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2205	{
2206		.pa_start	= OMAP3_UART3_BASE,
2207		.pa_end		= OMAP3_UART3_BASE + SZ_1K - 1,
2208		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2209	},
2210	{ }
2211};
2212
2213static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2214	.master		= &omap3xxx_l4_per_hwmod,
2215	.slave		= &omap3xxx_uart3_hwmod,
2216	.clk		= "uart3_ick",
2217	.addr		= omap3xxx_uart3_addr_space,
2218	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2219};
2220
2221/* L4 PER -> UART4 interface */
2222static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2223	{
2224		.pa_start	= OMAP3_UART4_BASE,
2225		.pa_end		= OMAP3_UART4_BASE + SZ_1K - 1,
2226		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2227	},
2228	{ }
2229};
2230
2231static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2232	.master		= &omap3xxx_l4_per_hwmod,
2233	.slave		= &omap36xx_uart4_hwmod,
2234	.clk		= "uart4_ick",
2235	.addr		= omap36xx_uart4_addr_space,
2236	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2237};
2238
2239/* AM35xx: L4 CORE -> UART4 interface */
2240static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2241	{
2242		.pa_start	= OMAP3_UART4_AM35XX_BASE,
2243		.pa_end		= OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2244		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2245	},
 
2246};
2247
2248static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2249	.master		= &omap3xxx_l4_core_hwmod,
2250	.slave		= &am35xx_uart4_hwmod,
2251	.clk		= "uart4_ick",
2252	.addr		= am35xx_uart4_addr_space,
2253	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2254};
2255
2256/* L4 CORE -> I2C1 interface */
2257static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2258	.master		= &omap3xxx_l4_core_hwmod,
2259	.slave		= &omap3xxx_i2c1_hwmod,
2260	.clk		= "i2c1_ick",
2261	.addr		= omap2_i2c1_addr_space,
2262	.fw = {
2263		.omap2 = {
2264			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2265			.l4_prot_group = 7,
2266			.flags	= OMAP_FIREWALL_L4,
2267		}
2268	},
2269	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2270};
2271
2272/* L4 CORE -> I2C2 interface */
2273static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2274	.master		= &omap3xxx_l4_core_hwmod,
2275	.slave		= &omap3xxx_i2c2_hwmod,
2276	.clk		= "i2c2_ick",
2277	.addr		= omap2_i2c2_addr_space,
2278	.fw = {
2279		.omap2 = {
2280			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2281			.l4_prot_group = 7,
2282			.flags = OMAP_FIREWALL_L4,
2283		}
2284	},
2285	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2286};
2287
2288/* L4 CORE -> I2C3 interface */
2289static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2290	{
2291		.pa_start	= 0x48060000,
2292		.pa_end		= 0x48060000 + SZ_128 - 1,
2293		.flags		= ADDR_TYPE_RT,
2294	},
2295	{ }
2296};
2297
2298static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2299	.master		= &omap3xxx_l4_core_hwmod,
2300	.slave		= &omap3xxx_i2c3_hwmod,
2301	.clk		= "i2c3_ick",
2302	.addr		= omap3xxx_i2c3_addr_space,
2303	.fw = {
2304		.omap2 = {
2305			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2306			.l4_prot_group = 7,
2307			.flags = OMAP_FIREWALL_L4,
2308		}
2309	},
2310	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2311};
2312
2313/* L4 CORE -> SR1 interface */
2314static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2315	{
2316		.pa_start	= OMAP34XX_SR1_BASE,
2317		.pa_end		= OMAP34XX_SR1_BASE + SZ_1K - 1,
2318		.flags		= ADDR_TYPE_RT,
2319	},
2320	{ }
2321};
2322
2323static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2324	.master		= &omap3xxx_l4_core_hwmod,
2325	.slave		= &omap34xx_sr1_hwmod,
2326	.clk		= "sr_l4_ick",
2327	.addr		= omap3_sr1_addr_space,
2328	.user		= OCP_USER_MPU,
2329};
2330
2331static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2332	.master		= &omap3xxx_l4_core_hwmod,
2333	.slave		= &omap36xx_sr1_hwmod,
2334	.clk		= "sr_l4_ick",
2335	.addr		= omap3_sr1_addr_space,
2336	.user		= OCP_USER_MPU,
2337};
2338
2339/* L4 CORE -> SR1 interface */
2340static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2341	{
2342		.pa_start	= OMAP34XX_SR2_BASE,
2343		.pa_end		= OMAP34XX_SR2_BASE + SZ_1K - 1,
2344		.flags		= ADDR_TYPE_RT,
2345	},
2346	{ }
2347};
2348
2349static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2350	.master		= &omap3xxx_l4_core_hwmod,
2351	.slave		= &omap34xx_sr2_hwmod,
2352	.clk		= "sr_l4_ick",
2353	.addr		= omap3_sr2_addr_space,
2354	.user		= OCP_USER_MPU,
2355};
2356
2357static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2358	.master		= &omap3xxx_l4_core_hwmod,
2359	.slave		= &omap36xx_sr2_hwmod,
2360	.clk		= "sr_l4_ick",
2361	.addr		= omap3_sr2_addr_space,
2362	.user		= OCP_USER_MPU,
2363};
2364
2365static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2366	{
2367		.pa_start	= OMAP34XX_HSUSB_OTG_BASE,
2368		.pa_end		= OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2369		.flags		= ADDR_TYPE_RT
2370	},
2371	{ }
2372};
2373
2374/* l4_core -> usbhsotg  */
2375static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2376	.master		= &omap3xxx_l4_core_hwmod,
2377	.slave		= &omap3xxx_usbhsotg_hwmod,
2378	.clk		= "l4_ick",
2379	.addr		= omap3xxx_usbhsotg_addrs,
2380	.user		= OCP_USER_MPU,
2381};
2382
2383static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2384	{
2385		.pa_start	= AM35XX_IPSS_USBOTGSS_BASE,
2386		.pa_end		= AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2387		.flags		= ADDR_TYPE_RT
2388	},
2389	{ }
2390};
2391
2392/* l4_core -> usbhsotg  */
2393static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2394	.master		= &omap3xxx_l4_core_hwmod,
2395	.slave		= &am35xx_usbhsotg_hwmod,
2396	.clk		= "l4_ick",
2397	.addr		= am35xx_usbhsotg_addrs,
2398	.user		= OCP_USER_MPU,
2399};
2400
2401/* L4_WKUP -> L4_SEC interface */
2402static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2403	.master = &omap3xxx_l4_wkup_hwmod,
2404	.slave	= &omap3xxx_l4_sec_hwmod,
2405	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2406};
2407
2408/* IVA2 <- L3 interface */
2409static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2410	.master		= &omap3xxx_l3_main_hwmod,
2411	.slave		= &omap3xxx_iva_hwmod,
2412	.clk		= "core_l3_ick",
2413	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2414};
2415
2416static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2417	{
2418		.pa_start	= 0x48318000,
2419		.pa_end		= 0x48318000 + SZ_1K - 1,
2420		.flags		= ADDR_TYPE_RT
2421	},
2422	{ }
2423};
2424
2425/* l4_wkup -> timer1 */
2426static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2427	.master		= &omap3xxx_l4_wkup_hwmod,
2428	.slave		= &omap3xxx_timer1_hwmod,
2429	.clk		= "gpt1_ick",
2430	.addr		= omap3xxx_timer1_addrs,
2431	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2432};
2433
2434static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2435	{
2436		.pa_start	= 0x49032000,
2437		.pa_end		= 0x49032000 + SZ_1K - 1,
2438		.flags		= ADDR_TYPE_RT
2439	},
2440	{ }
2441};
2442
2443/* l4_per -> timer2 */
2444static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2445	.master		= &omap3xxx_l4_per_hwmod,
2446	.slave		= &omap3xxx_timer2_hwmod,
2447	.clk		= "gpt2_ick",
2448	.addr		= omap3xxx_timer2_addrs,
2449	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2450};
2451
2452static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2453	{
2454		.pa_start	= 0x49034000,
2455		.pa_end		= 0x49034000 + SZ_1K - 1,
2456		.flags		= ADDR_TYPE_RT
2457	},
2458	{ }
2459};
2460
2461/* l4_per -> timer3 */
2462static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2463	.master		= &omap3xxx_l4_per_hwmod,
2464	.slave		= &omap3xxx_timer3_hwmod,
2465	.clk		= "gpt3_ick",
2466	.addr		= omap3xxx_timer3_addrs,
2467	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2468};
2469
2470static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2471	{
2472		.pa_start	= 0x49036000,
2473		.pa_end		= 0x49036000 + SZ_1K - 1,
2474		.flags		= ADDR_TYPE_RT
2475	},
2476	{ }
2477};
2478
2479/* l4_per -> timer4 */
2480static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2481	.master		= &omap3xxx_l4_per_hwmod,
2482	.slave		= &omap3xxx_timer4_hwmod,
2483	.clk		= "gpt4_ick",
2484	.addr		= omap3xxx_timer4_addrs,
2485	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2489	{
2490		.pa_start	= 0x49038000,
2491		.pa_end		= 0x49038000 + SZ_1K - 1,
2492		.flags		= ADDR_TYPE_RT
2493	},
2494	{ }
2495};
2496
2497/* l4_per -> timer5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2499	.master		= &omap3xxx_l4_per_hwmod,
2500	.slave		= &omap3xxx_timer5_hwmod,
2501	.clk		= "gpt5_ick",
2502	.addr		= omap3xxx_timer5_addrs,
2503	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2507	{
2508		.pa_start	= 0x4903A000,
2509		.pa_end		= 0x4903A000 + SZ_1K - 1,
2510		.flags		= ADDR_TYPE_RT
2511	},
2512	{ }
2513};
2514
2515/* l4_per -> timer6 */
2516static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2517	.master		= &omap3xxx_l4_per_hwmod,
2518	.slave		= &omap3xxx_timer6_hwmod,
2519	.clk		= "gpt6_ick",
2520	.addr		= omap3xxx_timer6_addrs,
2521	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2522};
2523
2524static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2525	{
2526		.pa_start	= 0x4903C000,
2527		.pa_end		= 0x4903C000 + SZ_1K - 1,
2528		.flags		= ADDR_TYPE_RT
2529	},
2530	{ }
2531};
2532
2533/* l4_per -> timer7 */
2534static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2535	.master		= &omap3xxx_l4_per_hwmod,
2536	.slave		= &omap3xxx_timer7_hwmod,
2537	.clk		= "gpt7_ick",
2538	.addr		= omap3xxx_timer7_addrs,
2539	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
2542static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2543	{
2544		.pa_start	= 0x4903E000,
2545		.pa_end		= 0x4903E000 + SZ_1K - 1,
2546		.flags		= ADDR_TYPE_RT
2547	},
2548	{ }
2549};
2550
2551/* l4_per -> timer8 */
2552static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2553	.master		= &omap3xxx_l4_per_hwmod,
2554	.slave		= &omap3xxx_timer8_hwmod,
2555	.clk		= "gpt8_ick",
2556	.addr		= omap3xxx_timer8_addrs,
2557	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2558};
2559
2560static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2561	{
2562		.pa_start	= 0x49040000,
2563		.pa_end		= 0x49040000 + SZ_1K - 1,
2564		.flags		= ADDR_TYPE_RT
2565	},
2566	{ }
2567};
2568
2569/* l4_per -> timer9 */
2570static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2571	.master		= &omap3xxx_l4_per_hwmod,
2572	.slave		= &omap3xxx_timer9_hwmod,
2573	.clk		= "gpt9_ick",
2574	.addr		= omap3xxx_timer9_addrs,
2575	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2576};
2577
2578/* l4_core -> timer10 */
2579static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2580	.master		= &omap3xxx_l4_core_hwmod,
2581	.slave		= &omap3xxx_timer10_hwmod,
2582	.clk		= "gpt10_ick",
2583	.addr		= omap2_timer10_addrs,
2584	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587/* l4_core -> timer11 */
2588static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2589	.master		= &omap3xxx_l4_core_hwmod,
2590	.slave		= &omap3xxx_timer11_hwmod,
2591	.clk		= "gpt11_ick",
2592	.addr		= omap2_timer11_addrs,
2593	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2594};
2595
2596static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2597	{
2598		.pa_start	= 0x48304000,
2599		.pa_end		= 0x48304000 + SZ_1K - 1,
2600		.flags		= ADDR_TYPE_RT
2601	},
2602	{ }
2603};
2604
2605/* l4_core -> timer12 */
2606static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2607	.master		= &omap3xxx_l4_sec_hwmod,
2608	.slave		= &omap3xxx_timer12_hwmod,
2609	.clk		= "gpt12_ick",
2610	.addr		= omap3xxx_timer12_addrs,
2611	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l4_wkup -> wd_timer2 */
2615static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2616	{
2617		.pa_start	= 0x48314000,
2618		.pa_end		= 0x4831407f,
2619		.flags		= ADDR_TYPE_RT
2620	},
2621	{ }
2622};
2623
2624static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2625	.master		= &omap3xxx_l4_wkup_hwmod,
2626	.slave		= &omap3xxx_wd_timer2_hwmod,
2627	.clk		= "wdt2_ick",
2628	.addr		= omap3xxx_wd_timer2_addrs,
2629	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2630};
2631
2632/* l4_core -> dss */
2633static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2634	.master		= &omap3xxx_l4_core_hwmod,
2635	.slave		= &omap3430es1_dss_core_hwmod,
2636	.clk		= "dss_ick",
2637	.addr		= omap2_dss_addrs,
2638	.fw = {
2639		.omap2 = {
2640			.l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2641			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2642			.flags	= OMAP_FIREWALL_L4,
2643		}
2644	},
2645	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2646};
2647
2648static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2649	.master		= &omap3xxx_l4_core_hwmod,
2650	.slave		= &omap3xxx_dss_core_hwmod,
2651	.clk		= "dss_ick",
2652	.addr		= omap2_dss_addrs,
2653	.fw = {
2654		.omap2 = {
2655			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2656			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2657			.flags	= OMAP_FIREWALL_L4,
2658		}
2659	},
2660	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2661};
2662
2663/* l4_core -> dss_dispc */
2664static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2665	.master		= &omap3xxx_l4_core_hwmod,
2666	.slave		= &omap3xxx_dss_dispc_hwmod,
2667	.clk		= "dss_ick",
2668	.addr		= omap2_dss_dispc_addrs,
2669	.fw = {
2670		.omap2 = {
2671			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2672			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2673			.flags	= OMAP_FIREWALL_L4,
2674		}
2675	},
2676	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2677};
2678
2679static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2680	{
2681		.pa_start	= 0x4804FC00,
2682		.pa_end		= 0x4804FFFF,
2683		.flags		= ADDR_TYPE_RT
2684	},
2685	{ }
2686};
2687
2688/* l4_core -> dss_dsi1 */
2689static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2690	.master		= &omap3xxx_l4_core_hwmod,
2691	.slave		= &omap3xxx_dss_dsi1_hwmod,
2692	.clk		= "dss_ick",
2693	.addr		= omap3xxx_dss_dsi1_addrs,
2694	.fw = {
2695		.omap2 = {
2696			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2697			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2698			.flags	= OMAP_FIREWALL_L4,
2699		}
2700	},
2701	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2702};
2703
2704/* l4_core -> dss_rfbi */
2705static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2706	.master		= &omap3xxx_l4_core_hwmod,
2707	.slave		= &omap3xxx_dss_rfbi_hwmod,
2708	.clk		= "dss_ick",
2709	.addr		= omap2_dss_rfbi_addrs,
2710	.fw = {
2711		.omap2 = {
2712			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2713			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2714			.flags	= OMAP_FIREWALL_L4,
2715		}
2716	},
2717	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_core -> dss_venc */
2721static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2722	.master		= &omap3xxx_l4_core_hwmod,
2723	.slave		= &omap3xxx_dss_venc_hwmod,
2724	.clk		= "dss_ick",
2725	.addr		= omap2_dss_venc_addrs,
2726	.fw = {
2727		.omap2 = {
2728			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2729			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2730			.flags	= OMAP_FIREWALL_L4,
2731		}
2732	},
2733	.flags		= OCPIF_SWSUP_IDLE,
2734	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l4_wkup -> gpio1 */
2738static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2739	{
2740		.pa_start	= 0x48310000,
2741		.pa_end		= 0x483101ff,
2742		.flags		= ADDR_TYPE_RT
2743	},
2744	{ }
2745};
2746
2747static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2748	.master		= &omap3xxx_l4_wkup_hwmod,
2749	.slave		= &omap3xxx_gpio1_hwmod,
2750	.addr		= omap3xxx_gpio1_addrs,
2751	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2752};
2753
2754/* l4_per -> gpio2 */
2755static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2756	{
2757		.pa_start	= 0x49050000,
2758		.pa_end		= 0x490501ff,
2759		.flags		= ADDR_TYPE_RT
2760	},
2761	{ }
2762};
2763
2764static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2765	.master		= &omap3xxx_l4_per_hwmod,
2766	.slave		= &omap3xxx_gpio2_hwmod,
2767	.addr		= omap3xxx_gpio2_addrs,
2768	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2769};
2770
2771/* l4_per -> gpio3 */
2772static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2773	{
2774		.pa_start	= 0x49052000,
2775		.pa_end		= 0x490521ff,
2776		.flags		= ADDR_TYPE_RT
2777	},
2778	{ }
2779};
2780
2781static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2782	.master		= &omap3xxx_l4_per_hwmod,
2783	.slave		= &omap3xxx_gpio3_hwmod,
2784	.addr		= omap3xxx_gpio3_addrs,
2785	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2786};
2787
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2788/* l4_per -> gpio4 */
2789static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2790	{
2791		.pa_start	= 0x49054000,
2792		.pa_end		= 0x490541ff,
2793		.flags		= ADDR_TYPE_RT
2794	},
2795	{ }
2796};
2797
2798static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2799	.master		= &omap3xxx_l4_per_hwmod,
2800	.slave		= &omap3xxx_gpio4_hwmod,
2801	.addr		= omap3xxx_gpio4_addrs,
2802	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2803};
2804
2805/* l4_per -> gpio5 */
2806static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2807	{
2808		.pa_start	= 0x49056000,
2809		.pa_end		= 0x490561ff,
2810		.flags		= ADDR_TYPE_RT
2811	},
2812	{ }
2813};
2814
2815static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2816	.master		= &omap3xxx_l4_per_hwmod,
2817	.slave		= &omap3xxx_gpio5_hwmod,
2818	.addr		= omap3xxx_gpio5_addrs,
2819	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_per -> gpio6 */
2823static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2824	{
2825		.pa_start	= 0x49058000,
2826		.pa_end		= 0x490581ff,
2827		.flags		= ADDR_TYPE_RT
2828	},
2829	{ }
2830};
2831
2832static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2833	.master		= &omap3xxx_l4_per_hwmod,
2834	.slave		= &omap3xxx_gpio6_hwmod,
2835	.addr		= omap3xxx_gpio6_addrs,
2836	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2837};
2838
2839/* dma_system -> L3 */
2840static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2841	.master		= &omap3xxx_dma_system_hwmod,
2842	.slave		= &omap3xxx_l3_main_hwmod,
2843	.clk		= "core_l3_ick",
2844	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2845};
2846
2847static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2848	{
2849		.pa_start	= 0x48056000,
2850		.pa_end		= 0x48056fff,
2851		.flags		= ADDR_TYPE_RT
2852	},
2853	{ }
2854};
2855
2856/* l4_cfg -> dma_system */
2857static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2858	.master		= &omap3xxx_l4_core_hwmod,
2859	.slave		= &omap3xxx_dma_system_hwmod,
2860	.clk		= "core_l4_ick",
2861	.addr		= omap3xxx_dma_system_addrs,
2862	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2863};
2864
2865static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2866	{
2867		.name		= "mpu",
2868		.pa_start	= 0x48074000,
2869		.pa_end		= 0x480740ff,
2870		.flags		= ADDR_TYPE_RT
2871	},
2872	{ }
2873};
2874
2875/* l4_core -> mcbsp1 */
2876static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2877	.master		= &omap3xxx_l4_core_hwmod,
2878	.slave		= &omap3xxx_mcbsp1_hwmod,
2879	.clk		= "mcbsp1_ick",
2880	.addr		= omap3xxx_mcbsp1_addrs,
2881	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2882};
2883
2884static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2885	{
2886		.name		= "mpu",
2887		.pa_start	= 0x49022000,
2888		.pa_end		= 0x490220ff,
2889		.flags		= ADDR_TYPE_RT
2890	},
2891	{ }
2892};
2893
2894/* l4_per -> mcbsp2 */
2895static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2896	.master		= &omap3xxx_l4_per_hwmod,
2897	.slave		= &omap3xxx_mcbsp2_hwmod,
2898	.clk		= "mcbsp2_ick",
2899	.addr		= omap3xxx_mcbsp2_addrs,
2900	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2901};
2902
2903static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2904	{
2905		.name		= "mpu",
2906		.pa_start	= 0x49024000,
2907		.pa_end		= 0x490240ff,
2908		.flags		= ADDR_TYPE_RT
2909	},
2910	{ }
2911};
2912
2913/* l4_per -> mcbsp3 */
2914static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2915	.master		= &omap3xxx_l4_per_hwmod,
2916	.slave		= &omap3xxx_mcbsp3_hwmod,
2917	.clk		= "mcbsp3_ick",
2918	.addr		= omap3xxx_mcbsp3_addrs,
2919	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2920};
2921
2922static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2923	{
2924		.name		= "mpu",
2925		.pa_start	= 0x49026000,
2926		.pa_end		= 0x490260ff,
2927		.flags		= ADDR_TYPE_RT
2928	},
2929	{ }
2930};
2931
2932/* l4_per -> mcbsp4 */
2933static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2934	.master		= &omap3xxx_l4_per_hwmod,
2935	.slave		= &omap3xxx_mcbsp4_hwmod,
2936	.clk		= "mcbsp4_ick",
2937	.addr		= omap3xxx_mcbsp4_addrs,
2938	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2939};
2940
2941static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2942	{
2943		.name		= "mpu",
2944		.pa_start	= 0x48096000,
2945		.pa_end		= 0x480960ff,
2946		.flags		= ADDR_TYPE_RT
2947	},
2948	{ }
2949};
2950
2951/* l4_core -> mcbsp5 */
2952static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2953	.master		= &omap3xxx_l4_core_hwmod,
2954	.slave		= &omap3xxx_mcbsp5_hwmod,
2955	.clk		= "mcbsp5_ick",
2956	.addr		= omap3xxx_mcbsp5_addrs,
2957	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
2960static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2961	{
2962		.name		= "sidetone",
2963		.pa_start	= 0x49028000,
2964		.pa_end		= 0x490280ff,
2965		.flags		= ADDR_TYPE_RT
2966	},
2967	{ }
2968};
2969
2970/* l4_per -> mcbsp2_sidetone */
2971static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2972	.master		= &omap3xxx_l4_per_hwmod,
2973	.slave		= &omap3xxx_mcbsp2_sidetone_hwmod,
2974	.clk		= "mcbsp2_ick",
2975	.addr		= omap3xxx_mcbsp2_sidetone_addrs,
2976	.user		= OCP_USER_MPU,
2977};
2978
2979static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2980	{
2981		.name		= "sidetone",
2982		.pa_start	= 0x4902A000,
2983		.pa_end		= 0x4902A0ff,
2984		.flags		= ADDR_TYPE_RT
2985	},
2986	{ }
2987};
2988
2989/* l4_per -> mcbsp3_sidetone */
2990static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2991	.master		= &omap3xxx_l4_per_hwmod,
2992	.slave		= &omap3xxx_mcbsp3_sidetone_hwmod,
2993	.clk		= "mcbsp3_ick",
2994	.addr		= omap3xxx_mcbsp3_sidetone_addrs,
2995	.user		= OCP_USER_MPU,
2996};
2997
2998static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2999	{
3000		.pa_start	= 0x48094000,
3001		.pa_end		= 0x480941ff,
3002		.flags		= ADDR_TYPE_RT,
3003	},
3004	{ }
3005};
3006
3007/* l4_core -> mailbox */
3008static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3009	.master		= &omap3xxx_l4_core_hwmod,
3010	.slave		= &omap3xxx_mailbox_hwmod,
3011	.addr		= omap3xxx_mailbox_addrs,
3012	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3013};
3014
3015/* l4 core -> mcspi1 interface */
3016static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3017	.master		= &omap3xxx_l4_core_hwmod,
3018	.slave		= &omap34xx_mcspi1,
3019	.clk		= "mcspi1_ick",
3020	.addr		= omap2_mcspi1_addr_space,
3021	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3022};
3023
3024/* l4 core -> mcspi2 interface */
3025static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3026	.master		= &omap3xxx_l4_core_hwmod,
3027	.slave		= &omap34xx_mcspi2,
3028	.clk		= "mcspi2_ick",
3029	.addr		= omap2_mcspi2_addr_space,
3030	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3031};
3032
3033/* l4 core -> mcspi3 interface */
3034static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3035	.master		= &omap3xxx_l4_core_hwmod,
3036	.slave		= &omap34xx_mcspi3,
3037	.clk		= "mcspi3_ick",
3038	.addr		= omap2430_mcspi3_addr_space,
3039	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3040};
3041
3042/* l4 core -> mcspi4 interface */
3043static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3044	{
3045		.pa_start	= 0x480ba000,
3046		.pa_end		= 0x480ba0ff,
3047		.flags		= ADDR_TYPE_RT,
3048	},
3049	{ }
3050};
3051
3052static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3053	.master		= &omap3xxx_l4_core_hwmod,
3054	.slave		= &omap34xx_mcspi4,
3055	.clk		= "mcspi4_ick",
3056	.addr		= omap34xx_mcspi4_addr_space,
3057	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3058};
3059
3060static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3061	.master		= &omap3xxx_usb_host_hs_hwmod,
3062	.slave		= &omap3xxx_l3_main_hwmod,
3063	.clk		= "core_l3_ick",
3064	.user		= OCP_USER_MPU,
3065};
3066
3067static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3068	{
3069		.name		= "uhh",
3070		.pa_start	= 0x48064000,
3071		.pa_end		= 0x480643ff,
3072		.flags		= ADDR_TYPE_RT
3073	},
3074	{
3075		.name		= "ohci",
3076		.pa_start	= 0x48064400,
3077		.pa_end		= 0x480647ff,
3078	},
3079	{
3080		.name		= "ehci",
3081		.pa_start	= 0x48064800,
3082		.pa_end		= 0x48064cff,
3083	},
3084	{}
3085};
3086
3087static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3088	.master		= &omap3xxx_l4_core_hwmod,
3089	.slave		= &omap3xxx_usb_host_hs_hwmod,
3090	.clk		= "usbhost_ick",
3091	.addr		= omap3xxx_usb_host_hs_addrs,
3092	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3093};
3094
3095static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3096	{
3097		.name		= "tll",
3098		.pa_start	= 0x48062000,
3099		.pa_end		= 0x48062fff,
3100		.flags		= ADDR_TYPE_RT
3101	},
3102	{}
3103};
3104
3105static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3106	.master		= &omap3xxx_l4_core_hwmod,
3107	.slave		= &omap3xxx_usb_tll_hs_hwmod,
3108	.clk		= "usbtll_ick",
3109	.addr		= omap3xxx_usb_tll_hs_addrs,
3110	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3111};
3112
3113/* l4_core -> hdq1w interface */
3114static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3115	.master		= &omap3xxx_l4_core_hwmod,
3116	.slave		= &omap3xxx_hdq1w_hwmod,
3117	.clk		= "hdq_ick",
3118	.addr		= omap2_hdq1w_addr_space,
3119	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3120	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3121};
3122
3123/* l4_wkup -> 32ksync_counter */
3124static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3125	{
3126		.pa_start	= 0x48320000,
3127		.pa_end		= 0x4832001f,
3128		.flags		= ADDR_TYPE_RT
3129	},
3130	{ }
3131};
3132
 
 
 
 
 
 
 
 
 
3133static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3134	.master		= &omap3xxx_l4_wkup_hwmod,
3135	.slave		= &omap3xxx_counter_32k_hwmod,
3136	.clk		= "omap_32ksync_ick",
3137	.addr		= omap3xxx_counter_32k_addrs,
3138	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3139};
3140
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3141static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3142	&omap3xxx_l3_main__l4_core,
3143	&omap3xxx_l3_main__l4_per,
3144	&omap3xxx_mpu__l3_main,
 
3145	&omap3xxx_l4_core__l4_wkup,
3146	&omap3xxx_l4_core__mmc3,
3147	&omap3_l4_core__uart1,
3148	&omap3_l4_core__uart2,
3149	&omap3_l4_per__uart3,
3150	&omap3_l4_core__i2c1,
3151	&omap3_l4_core__i2c2,
3152	&omap3_l4_core__i2c3,
3153	&omap3xxx_l4_wkup__l4_sec,
3154	&omap3xxx_l4_wkup__timer1,
3155	&omap3xxx_l4_per__timer2,
3156	&omap3xxx_l4_per__timer3,
3157	&omap3xxx_l4_per__timer4,
3158	&omap3xxx_l4_per__timer5,
3159	&omap3xxx_l4_per__timer6,
3160	&omap3xxx_l4_per__timer7,
3161	&omap3xxx_l4_per__timer8,
3162	&omap3xxx_l4_per__timer9,
3163	&omap3xxx_l4_core__timer10,
3164	&omap3xxx_l4_core__timer11,
3165	&omap3xxx_l4_wkup__wd_timer2,
3166	&omap3xxx_l4_wkup__gpio1,
3167	&omap3xxx_l4_per__gpio2,
3168	&omap3xxx_l4_per__gpio3,
3169	&omap3xxx_l4_per__gpio4,
3170	&omap3xxx_l4_per__gpio5,
3171	&omap3xxx_l4_per__gpio6,
3172	&omap3xxx_dma_system__l3,
3173	&omap3xxx_l4_core__dma_system,
3174	&omap3xxx_l4_core__mcbsp1,
3175	&omap3xxx_l4_per__mcbsp2,
3176	&omap3xxx_l4_per__mcbsp3,
3177	&omap3xxx_l4_per__mcbsp4,
3178	&omap3xxx_l4_core__mcbsp5,
3179	&omap3xxx_l4_per__mcbsp2_sidetone,
3180	&omap3xxx_l4_per__mcbsp3_sidetone,
3181	&omap34xx_l4_core__mcspi1,
3182	&omap34xx_l4_core__mcspi2,
3183	&omap34xx_l4_core__mcspi3,
3184	&omap34xx_l4_core__mcspi4,
3185	&omap3xxx_l4_wkup__counter_32k,
 
3186	NULL,
3187};
3188
3189/* GP-only hwmod links */
3190static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3191	&omap3xxx_l4_sec__timer12,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3192	NULL
3193};
3194
3195/* 3430ES1-only hwmod links */
3196static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3197	&omap3430es1_dss__l3,
3198	&omap3430es1_l4_core__dss,
3199	NULL
3200};
3201
3202/* 3430ES2+-only hwmod links */
3203static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3204	&omap3xxx_dss__l3,
3205	&omap3xxx_l4_core__dss,
3206	&omap3xxx_usbhsotg__l3,
3207	&omap3xxx_l4_core__usbhsotg,
3208	&omap3xxx_usb_host_hs__l3_main_2,
3209	&omap3xxx_l4_core__usb_host_hs,
3210	&omap3xxx_l4_core__usb_tll_hs,
3211	NULL
3212};
3213
3214/* <= 3430ES3-only hwmod links */
3215static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3216	&omap3xxx_l4_core__pre_es3_mmc1,
3217	&omap3xxx_l4_core__pre_es3_mmc2,
3218	NULL
3219};
3220
3221/* 3430ES3+-only hwmod links */
3222static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3223	&omap3xxx_l4_core__es3plus_mmc1,
3224	&omap3xxx_l4_core__es3plus_mmc2,
3225	NULL
3226};
3227
3228/* 34xx-only hwmod links (all ES revisions) */
3229static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3230	&omap3xxx_l3__iva,
3231	&omap34xx_l4_core__sr1,
3232	&omap34xx_l4_core__sr2,
3233	&omap3xxx_l4_core__mailbox,
3234	&omap3xxx_l4_core__hdq1w,
 
 
 
 
3235	NULL
3236};
3237
3238/* 36xx-only hwmod links (all ES revisions) */
3239static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3240	&omap3xxx_l3__iva,
3241	&omap36xx_l4_per__uart4,
3242	&omap3xxx_dss__l3,
3243	&omap3xxx_l4_core__dss,
3244	&omap36xx_l4_core__sr1,
3245	&omap36xx_l4_core__sr2,
3246	&omap3xxx_usbhsotg__l3,
3247	&omap3xxx_l4_core__usbhsotg,
3248	&omap3xxx_l4_core__mailbox,
3249	&omap3xxx_usb_host_hs__l3_main_2,
3250	&omap3xxx_l4_core__usb_host_hs,
3251	&omap3xxx_l4_core__usb_tll_hs,
3252	&omap3xxx_l4_core__es3plus_mmc1,
3253	&omap3xxx_l4_core__es3plus_mmc2,
3254	&omap3xxx_l4_core__hdq1w,
 
 
 
3255	NULL
3256};
3257
3258static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3259	&omap3xxx_dss__l3,
3260	&omap3xxx_l4_core__dss,
3261	&am35xx_usbhsotg__l3,
3262	&am35xx_l4_core__usbhsotg,
3263	&am35xx_l4_core__uart4,
3264	&omap3xxx_usb_host_hs__l3_main_2,
3265	&omap3xxx_l4_core__usb_host_hs,
3266	&omap3xxx_l4_core__usb_tll_hs,
3267	&omap3xxx_l4_core__es3plus_mmc1,
3268	&omap3xxx_l4_core__es3plus_mmc2,
 
 
 
 
 
3269	NULL
3270};
3271
3272static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3273	&omap3xxx_l4_core__dss_dispc,
3274	&omap3xxx_l4_core__dss_dsi1,
3275	&omap3xxx_l4_core__dss_rfbi,
3276	&omap3xxx_l4_core__dss_venc,
3277	NULL
3278};
3279
3280int __init omap3xxx_hwmod_init(void)
3281{
3282	int r;
3283	struct omap_hwmod_ocp_if **h = NULL;
3284	unsigned int rev;
3285
 
 
3286	/* Register hwmod links common to all OMAP3 */
3287	r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3288	if (r < 0)
3289		return r;
3290
3291	/* Register GP-only hwmod links. */
3292	if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3293		r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3294		if (r < 0)
3295			return r;
3296	}
3297
3298	rev = omap_rev();
3299
3300	/*
3301	 * Register hwmod links common to individual OMAP3 families, all
3302	 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3303	 * All possible revisions should be included in this conditional.
3304	 */
3305	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3306	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3307	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3308		h = omap34xx_hwmod_ocp_ifs;
 
3309	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3310		h = am35xx_hwmod_ocp_ifs;
 
3311	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3312		   rev == OMAP3630_REV_ES1_2) {
3313		h = omap36xx_hwmod_ocp_ifs;
 
3314	} else {
3315		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3316		return -EINVAL;
3317	};
3318
3319	r = omap_hwmod_register_links(h);
3320	if (r < 0)
3321		return r;
3322
 
 
 
 
 
 
 
 
3323	/*
3324	 * Register hwmod links specific to certain ES levels of a
3325	 * particular family of silicon (e.g., 34xx ES1.0)
3326	 */
3327	h = NULL;
3328	if (rev == OMAP3430_REV_ES1_0) {
3329		h = omap3430es1_hwmod_ocp_ifs;
3330	} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3331		   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3332		   rev == OMAP3430_REV_ES3_1_2) {
3333		h = omap3430es2plus_hwmod_ocp_ifs;
3334	};
3335
3336	if (h) {
3337		r = omap_hwmod_register_links(h);
3338		if (r < 0)
3339			return r;
3340	}
3341
3342	h = NULL;
3343	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3344	    rev == OMAP3430_REV_ES2_1) {
3345		h = omap3430_pre_es3_hwmod_ocp_ifs;
3346	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3347		   rev == OMAP3430_REV_ES3_1_2) {
3348		h = omap3430_es3plus_hwmod_ocp_ifs;
3349	};
3350
3351	if (h)
3352		r = omap_hwmod_register_links(h);
3353	if (r < 0)
3354		return r;
3355
3356	/*
3357	 * DSS code presumes that dss_core hwmod is handled first,
3358	 * _before_ any other DSS related hwmods so register common
3359	 * DSS hwmod links last to ensure that dss_core is already
3360	 * registered.  Otherwise some change things may happen, for
3361	 * ex. if dispc is handled before dss_core and DSS is enabled
3362	 * in bootloader DISPC will be reset with outputs enabled
3363	 * which sometimes leads to unrecoverable L3 error.  XXX The
3364	 * long-term fix to this is to ensure hwmods are set up in
3365	 * dependency order in the hwmod core code.
3366	 */
3367	r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3368
3369	return r;
3370}