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1/*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/memblock.h>
19
20#include <asm/hardware/gic.h>
21#include <asm/hardware/cache-l2x0.h>
22#include <asm/mach/map.h>
23#include <asm/memblock.h>
24
25#include <plat/irqs.h>
26#include <plat/sram.h>
27#include <plat/omap-secure.h>
28#include <plat/mmc.h>
29
30#include <mach/hardware.h>
31#include <mach/omap-wakeupgen.h>
32
33#include "common.h"
34#include "hsmmc.h"
35#include "omap4-sar-layout.h"
36#include <linux/export.h>
37
38#ifdef CONFIG_CACHE_L2X0
39static void __iomem *l2cache_base;
40#endif
41
42static void __iomem *sar_ram_base;
43
44#ifdef CONFIG_OMAP4_ERRATA_I688
45/* Used to implement memory barrier on DRAM path */
46#define OMAP4_DRAM_BARRIER_VA 0xfe600000
47
48void __iomem *dram_sync, *sram_sync;
49
50static phys_addr_t paddr;
51static u32 size;
52
53void omap_bus_sync(void)
54{
55 if (dram_sync && sram_sync) {
56 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
57 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
58 isb();
59 }
60}
61EXPORT_SYMBOL(omap_bus_sync);
62
63/* Steal one page physical memory for barrier implementation */
64int __init omap_barrier_reserve_memblock(void)
65{
66
67 size = ALIGN(PAGE_SIZE, SZ_1M);
68 paddr = arm_memblock_steal(size, SZ_1M);
69
70 return 0;
71}
72
73void __init omap_barriers_init(void)
74{
75 struct map_desc dram_io_desc[1];
76
77 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
78 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
79 dram_io_desc[0].length = size;
80 dram_io_desc[0].type = MT_MEMORY_SO;
81 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
82 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
83 sram_sync = (void __iomem *) OMAP4_SRAM_VA;
84
85 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
86 (long long) paddr, dram_io_desc[0].virtual);
87
88}
89#else
90void __init omap_barriers_init(void)
91{}
92#endif
93
94void __init gic_init_irq(void)
95{
96 void __iomem *omap_irq_base;
97 void __iomem *gic_dist_base_addr;
98
99 /* Static mapping, never released */
100 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
101 BUG_ON(!gic_dist_base_addr);
102
103 /* Static mapping, never released */
104 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
105 BUG_ON(!omap_irq_base);
106
107 omap_wakeupgen_init();
108
109 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
110}
111
112#ifdef CONFIG_CACHE_L2X0
113
114void __iomem *omap4_get_l2cache_base(void)
115{
116 return l2cache_base;
117}
118
119static void omap4_l2x0_disable(void)
120{
121 /* Disable PL310 L2 Cache controller */
122 omap_smc1(0x102, 0x0);
123}
124
125static void omap4_l2x0_set_debug(unsigned long val)
126{
127 /* Program PL310 L2 Cache controller debug register */
128 omap_smc1(0x100, val);
129}
130
131static int __init omap_l2_cache_init(void)
132{
133 u32 aux_ctrl = 0;
134
135 /*
136 * To avoid code running on other OMAPs in
137 * multi-omap builds
138 */
139 if (!cpu_is_omap44xx())
140 return -ENODEV;
141
142 /* Static mapping, never released */
143 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
144 if (WARN_ON(!l2cache_base))
145 return -ENOMEM;
146
147 /*
148 * 16-way associativity, parity disabled
149 * Way size - 32KB (es1.0)
150 * Way size - 64KB (es2.0 +)
151 */
152 aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
153 (0x1 << 25) |
154 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
155 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
156
157 if (omap_rev() == OMAP4430_REV_ES1_0) {
158 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
159 } else {
160 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
161 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
162 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
163 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
164 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
165 }
166 if (omap_rev() != OMAP4430_REV_ES1_0)
167 omap_smc1(0x109, aux_ctrl);
168
169 /* Enable PL310 L2 Cache controller */
170 omap_smc1(0x102, 0x1);
171
172 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
173
174 /*
175 * Override default outer_cache.disable with a OMAP4
176 * specific one
177 */
178 outer_cache.disable = omap4_l2x0_disable;
179 outer_cache.set_debug = omap4_l2x0_set_debug;
180
181 return 0;
182}
183early_initcall(omap_l2_cache_init);
184#endif
185
186void __iomem *omap4_get_sar_ram_base(void)
187{
188 return sar_ram_base;
189}
190
191/*
192 * SAR RAM used to save and restore the HW
193 * context in low power modes
194 */
195static int __init omap4_sar_ram_init(void)
196{
197 /*
198 * To avoid code running on other OMAPs in
199 * multi-omap builds
200 */
201 if (!cpu_is_omap44xx())
202 return -ENOMEM;
203
204 /* Static mapping, never released */
205 sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
206 if (WARN_ON(!sar_ram_base))
207 return -ENOMEM;
208
209 return 0;
210}
211early_initcall(omap4_sar_ram_init);
212
213#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
214static int omap4_twl6030_hsmmc_late_init(struct device *dev)
215{
216 int irq = 0;
217 struct platform_device *pdev = container_of(dev,
218 struct platform_device, dev);
219 struct omap_mmc_platform_data *pdata = dev->platform_data;
220
221 /* Setting MMC1 Card detect Irq */
222 if (pdev->id == 0) {
223 irq = twl6030_mmc_card_detect_config();
224 if (irq < 0) {
225 dev_err(dev, "%s: Error card detect config(%d)\n",
226 __func__, irq);
227 return irq;
228 }
229 pdata->slots[0].card_detect_irq = irq;
230 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
231 }
232 return 0;
233}
234
235static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
236{
237 struct omap_mmc_platform_data *pdata;
238
239 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
240 if (!dev) {
241 pr_err("Failed %s\n", __func__);
242 return;
243 }
244 pdata = dev->platform_data;
245 pdata->init = omap4_twl6030_hsmmc_late_init;
246}
247
248int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
249{
250 struct omap2_hsmmc_info *c;
251
252 omap_hsmmc_init(controllers);
253 for (c = controllers; c->mmc; c++) {
254 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
255 if (!c->pdev)
256 continue;
257 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
258 }
259
260 return 0;
261}
262#else
263int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
264{
265 return 0;
266}
267#endif
1/*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/irqchip.h>
19#include <linux/platform_device.h>
20#include <linux/memblock.h>
21#include <linux/of_irq.h>
22#include <linux/of_platform.h>
23#include <linux/export.h>
24#include <linux/irqchip/arm-gic.h>
25#include <linux/irqchip/irq-crossbar.h>
26#include <linux/of_address.h>
27#include <linux/reboot.h>
28
29#include <asm/hardware/cache-l2x0.h>
30#include <asm/mach/map.h>
31#include <asm/memblock.h>
32#include <asm/smp_twd.h>
33
34#include "omap-wakeupgen.h"
35#include "soc.h"
36#include "iomap.h"
37#include "common.h"
38#include "mmc.h"
39#include "prminst44xx.h"
40#include "prcm_mpu44xx.h"
41#include "omap4-sar-layout.h"
42#include "omap-secure.h"
43#include "sram.h"
44
45#ifdef CONFIG_CACHE_L2X0
46static void __iomem *l2cache_base;
47#endif
48
49static void __iomem *sar_ram_base;
50static void __iomem *gic_dist_base_addr;
51static void __iomem *twd_base;
52
53#define IRQ_LOCALTIMER 29
54
55#ifdef CONFIG_OMAP4_ERRATA_I688
56/* Used to implement memory barrier on DRAM path */
57#define OMAP4_DRAM_BARRIER_VA 0xfe600000
58
59void __iomem *dram_sync, *sram_sync;
60
61static phys_addr_t paddr;
62static u32 size;
63
64void omap_bus_sync(void)
65{
66 if (dram_sync && sram_sync) {
67 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
68 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
69 isb();
70 }
71}
72EXPORT_SYMBOL(omap_bus_sync);
73
74/* Steal one page physical memory for barrier implementation */
75int __init omap_barrier_reserve_memblock(void)
76{
77
78 size = ALIGN(PAGE_SIZE, SZ_1M);
79 paddr = arm_memblock_steal(size, SZ_1M);
80
81 return 0;
82}
83
84void __init omap_barriers_init(void)
85{
86 struct map_desc dram_io_desc[1];
87
88 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
89 dram_io_desc[0].pfn = __phys_to_pfn(paddr);
90 dram_io_desc[0].length = size;
91 dram_io_desc[0].type = MT_MEMORY_RW_SO;
92 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
93 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
94 sram_sync = (void __iomem *) OMAP4_SRAM_VA;
95
96 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
97 (long long) paddr, dram_io_desc[0].virtual);
98
99}
100#else
101void __init omap_barriers_init(void)
102{}
103#endif
104
105void __init gic_init_irq(void)
106{
107 void __iomem *omap_irq_base;
108
109 /* Static mapping, never released */
110 gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
111 BUG_ON(!gic_dist_base_addr);
112
113 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_4K);
114 BUG_ON(!twd_base);
115
116 /* Static mapping, never released */
117 omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
118 BUG_ON(!omap_irq_base);
119
120 omap_wakeupgen_init();
121
122 gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
123}
124
125void gic_dist_disable(void)
126{
127 if (gic_dist_base_addr)
128 __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
129}
130
131void gic_dist_enable(void)
132{
133 if (gic_dist_base_addr)
134 __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
135}
136
137bool gic_dist_disabled(void)
138{
139 return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
140}
141
142void gic_timer_retrigger(void)
143{
144 u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
145 u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
146 u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
147
148 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
149 /*
150 * The local timer interrupt got lost while the distributor was
151 * disabled. Ack the pending interrupt, and retrigger it.
152 */
153 pr_warn("%s: lost localtimer interrupt\n", __func__);
154 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
155 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
156 __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
157 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
158 __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
159 }
160 }
161}
162
163#ifdef CONFIG_CACHE_L2X0
164
165void __iomem *omap4_get_l2cache_base(void)
166{
167 return l2cache_base;
168}
169
170static void omap4_l2x0_disable(void)
171{
172 outer_flush_all();
173 /* Disable PL310 L2 Cache controller */
174 omap_smc1(0x102, 0x0);
175}
176
177static void omap4_l2x0_set_debug(unsigned long val)
178{
179 /* Program PL310 L2 Cache controller debug register */
180 omap_smc1(0x100, val);
181}
182
183static int __init omap_l2_cache_init(void)
184{
185 u32 aux_ctrl = 0;
186
187 /*
188 * To avoid code running on other OMAPs in
189 * multi-omap builds
190 */
191 if (!cpu_is_omap44xx())
192 return -ENODEV;
193
194 /* Static mapping, never released */
195 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
196 if (WARN_ON(!l2cache_base))
197 return -ENOMEM;
198
199 /*
200 * 16-way associativity, parity disabled
201 * Way size - 32KB (es1.0)
202 * Way size - 64KB (es2.0 +)
203 */
204 aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
205 (0x1 << 25) |
206 (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
207 (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
208
209 if (omap_rev() == OMAP4430_REV_ES1_0) {
210 aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
211 } else {
212 aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
213 (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
214 (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
215 (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
216 (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
217 }
218 if (omap_rev() != OMAP4430_REV_ES1_0)
219 omap_smc1(0x109, aux_ctrl);
220
221 /* Enable PL310 L2 Cache controller */
222 omap_smc1(0x102, 0x1);
223
224 if (of_have_populated_dt())
225 l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
226 else
227 l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
228
229 /*
230 * Override default outer_cache.disable with a OMAP4
231 * specific one
232 */
233 outer_cache.disable = omap4_l2x0_disable;
234 outer_cache.set_debug = omap4_l2x0_set_debug;
235
236 return 0;
237}
238omap_early_initcall(omap_l2_cache_init);
239#endif
240
241void __iomem *omap4_get_sar_ram_base(void)
242{
243 return sar_ram_base;
244}
245
246/*
247 * SAR RAM used to save and restore the HW
248 * context in low power modes
249 */
250static int __init omap4_sar_ram_init(void)
251{
252 unsigned long sar_base;
253
254 /*
255 * To avoid code running on other OMAPs in
256 * multi-omap builds
257 */
258 if (cpu_is_omap44xx())
259 sar_base = OMAP44XX_SAR_RAM_BASE;
260 else if (soc_is_omap54xx())
261 sar_base = OMAP54XX_SAR_RAM_BASE;
262 else
263 return -ENOMEM;
264
265 /* Static mapping, never released */
266 sar_ram_base = ioremap(sar_base, SZ_16K);
267 if (WARN_ON(!sar_ram_base))
268 return -ENOMEM;
269
270 return 0;
271}
272omap_early_initcall(omap4_sar_ram_init);
273
274void __init omap_gic_of_init(void)
275{
276 struct device_node *np;
277
278 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
279 if (!cpu_is_omap446x())
280 goto skip_errata_init;
281
282 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
283 gic_dist_base_addr = of_iomap(np, 0);
284 WARN_ON(!gic_dist_base_addr);
285
286 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
287 twd_base = of_iomap(np, 0);
288 WARN_ON(!twd_base);
289
290skip_errata_init:
291 omap_wakeupgen_init();
292#ifdef CONFIG_IRQ_CROSSBAR
293 irqcrossbar_init();
294#endif
295 irqchip_init();
296}