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1/*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <asm/cputype.h>
23
24#include "common.h"
25#include <plat/cpu.h>
26
27#include <mach/id.h>
28
29#include "control.h"
30
31static unsigned int omap_revision;
32static const char *cpu_rev;
33u32 omap_features;
34
35unsigned int omap_rev(void)
36{
37 return omap_revision;
38}
39EXPORT_SYMBOL(omap_rev);
40
41int omap_type(void)
42{
43 u32 val = 0;
44
45 if (cpu_is_omap24xx()) {
46 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
47 } else if (cpu_is_am33xx()) {
48 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
49 } else if (cpu_is_omap34xx()) {
50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
51 } else if (cpu_is_omap44xx()) {
52 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
53 } else {
54 pr_err("Cannot detect omap type!\n");
55 goto out;
56 }
57
58 val &= OMAP2_DEVICETYPE_MASK;
59 val >>= 8;
60
61out:
62 return val;
63}
64EXPORT_SYMBOL(omap_type);
65
66
67/*----------------------------------------------------------------------------*/
68
69#define OMAP_TAP_IDCODE 0x0204
70#define OMAP_TAP_DIE_ID_0 0x0218
71#define OMAP_TAP_DIE_ID_1 0x021C
72#define OMAP_TAP_DIE_ID_2 0x0220
73#define OMAP_TAP_DIE_ID_3 0x0224
74
75#define OMAP_TAP_DIE_ID_44XX_0 0x0200
76#define OMAP_TAP_DIE_ID_44XX_1 0x0208
77#define OMAP_TAP_DIE_ID_44XX_2 0x020c
78#define OMAP_TAP_DIE_ID_44XX_3 0x0210
79
80#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
81
82struct omap_id {
83 u16 hawkeye; /* Silicon type (Hawkeye id) */
84 u8 dev; /* Device type from production_id reg */
85 u32 type; /* Combined type id copied to omap_revision */
86};
87
88/* Register values to detect the OMAP version */
89static struct omap_id omap_ids[] __initdata = {
90 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
91 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
92 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
93 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
94 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
95 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
96};
97
98static void __iomem *tap_base;
99static u16 tap_prod_id;
100
101void omap_get_die_id(struct omap_die_id *odi)
102{
103 if (cpu_is_omap44xx()) {
104 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
105 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
106 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
107 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
108
109 return;
110 }
111 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
112 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
113 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
114 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
115}
116
117void __init omap2xxx_check_revision(void)
118{
119 int i, j;
120 u32 idcode, prod_id;
121 u16 hawkeye;
122 u8 dev_type, rev;
123 struct omap_die_id odi;
124
125 idcode = read_tap_reg(OMAP_TAP_IDCODE);
126 prod_id = read_tap_reg(tap_prod_id);
127 hawkeye = (idcode >> 12) & 0xffff;
128 rev = (idcode >> 28) & 0x0f;
129 dev_type = (prod_id >> 16) & 0x0f;
130 omap_get_die_id(&odi);
131
132 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
133 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
134 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
135 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
136 odi.id_1, (odi.id_1 >> 28) & 0xf);
137 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
138 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
139 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
140 prod_id, dev_type);
141
142 /* Check hawkeye ids */
143 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
144 if (hawkeye == omap_ids[i].hawkeye)
145 break;
146 }
147
148 if (i == ARRAY_SIZE(omap_ids)) {
149 printk(KERN_ERR "Unknown OMAP CPU id\n");
150 return;
151 }
152
153 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
154 if (dev_type == omap_ids[j].dev)
155 break;
156 }
157
158 if (j == ARRAY_SIZE(omap_ids)) {
159 printk(KERN_ERR "Unknown OMAP device type. "
160 "Handling it as OMAP%04x\n",
161 omap_ids[i].type >> 16);
162 j = i;
163 }
164
165 pr_info("OMAP%04x", omap_rev() >> 16);
166 if ((omap_rev() >> 8) & 0x0f)
167 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
168 pr_info("\n");
169}
170
171#define OMAP3_SHOW_FEATURE(feat) \
172 if (omap3_has_ ##feat()) \
173 printk(#feat" ");
174
175static void __init omap3_cpuinfo(void)
176{
177 const char *cpu_name;
178
179 /*
180 * OMAP3430 and OMAP3530 are assumed to be same.
181 *
182 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
183 * on available features. Upon detection, update the CPU id
184 * and CPU class bits.
185 */
186 if (cpu_is_omap3630()) {
187 cpu_name = "OMAP3630";
188 } else if (soc_is_am35xx()) {
189 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
190 } else if (cpu_is_ti816x()) {
191 cpu_name = "TI816X";
192 } else if (cpu_is_am335x()) {
193 cpu_name = "AM335X";
194 } else if (cpu_is_ti814x()) {
195 cpu_name = "TI814X";
196 } else if (omap3_has_iva() && omap3_has_sgx()) {
197 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
198 cpu_name = "OMAP3430/3530";
199 } else if (omap3_has_iva()) {
200 cpu_name = "OMAP3525";
201 } else if (omap3_has_sgx()) {
202 cpu_name = "OMAP3515";
203 } else {
204 cpu_name = "OMAP3503";
205 }
206
207 /* Print verbose information */
208 pr_info("%s ES%s (", cpu_name, cpu_rev);
209
210 OMAP3_SHOW_FEATURE(l2cache);
211 OMAP3_SHOW_FEATURE(iva);
212 OMAP3_SHOW_FEATURE(sgx);
213 OMAP3_SHOW_FEATURE(neon);
214 OMAP3_SHOW_FEATURE(isp);
215 OMAP3_SHOW_FEATURE(192mhz_clk);
216
217 printk(")\n");
218}
219
220#define OMAP3_CHECK_FEATURE(status,feat) \
221 if (((status & OMAP3_ ##feat## _MASK) \
222 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
223 omap_features |= OMAP3_HAS_ ##feat; \
224 }
225
226void __init omap3xxx_check_features(void)
227{
228 u32 status;
229
230 omap_features = 0;
231
232 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
233
234 OMAP3_CHECK_FEATURE(status, L2CACHE);
235 OMAP3_CHECK_FEATURE(status, IVA);
236 OMAP3_CHECK_FEATURE(status, SGX);
237 OMAP3_CHECK_FEATURE(status, NEON);
238 OMAP3_CHECK_FEATURE(status, ISP);
239 if (cpu_is_omap3630())
240 omap_features |= OMAP3_HAS_192MHZ_CLK;
241 if (cpu_is_omap3430() || cpu_is_omap3630())
242 omap_features |= OMAP3_HAS_IO_WAKEUP;
243 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
244 omap_rev() == OMAP3430_REV_ES3_1_2)
245 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
246
247 omap_features |= OMAP3_HAS_SDRC;
248
249 /*
250 * am35x fixups:
251 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
252 * reserved and therefore return 0 when read. Unfortunately,
253 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
254 * mean that a feature is present even though it isn't so clear
255 * the incorrectly set feature bits.
256 */
257 if (soc_is_am35xx())
258 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
259
260 /*
261 * TODO: Get additional info (where applicable)
262 * e.g. Size of L2 cache.
263 */
264
265 omap3_cpuinfo();
266}
267
268void __init omap4xxx_check_features(void)
269{
270 u32 si_type;
271
272 if (cpu_is_omap443x())
273 omap_features |= OMAP4_HAS_MPU_1GHZ;
274
275
276 if (cpu_is_omap446x()) {
277 si_type =
278 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
279 switch ((si_type & (3 << 16)) >> 16) {
280 case 2:
281 /* High performance device */
282 omap_features |= OMAP4_HAS_MPU_1_5GHZ;
283 break;
284 case 1:
285 default:
286 /* Standard device */
287 omap_features |= OMAP4_HAS_MPU_1_2GHZ;
288 break;
289 }
290 }
291}
292
293void __init ti81xx_check_features(void)
294{
295 omap_features = OMAP3_HAS_NEON;
296 omap3_cpuinfo();
297}
298
299void __init omap3xxx_check_revision(void)
300{
301 u32 cpuid, idcode;
302 u16 hawkeye;
303 u8 rev;
304
305 /*
306 * We cannot access revision registers on ES1.0.
307 * If the processor type is Cortex-A8 and the revision is 0x0
308 * it means its Cortex r0p0 which is 3430 ES1.0.
309 */
310 cpuid = read_cpuid(CPUID_ID);
311 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
312 omap_revision = OMAP3430_REV_ES1_0;
313 cpu_rev = "1.0";
314 return;
315 }
316
317 /*
318 * Detection for 34xx ES2.0 and above can be done with just
319 * hawkeye and rev. See TRM 1.5.2 Device Identification.
320 * Note that rev does not map directly to our defined processor
321 * revision numbers as ES1.0 uses value 0.
322 */
323 idcode = read_tap_reg(OMAP_TAP_IDCODE);
324 hawkeye = (idcode >> 12) & 0xffff;
325 rev = (idcode >> 28) & 0xff;
326
327 switch (hawkeye) {
328 case 0xb7ae:
329 /* Handle 34xx/35xx devices */
330 switch (rev) {
331 case 0: /* Take care of early samples */
332 case 1:
333 omap_revision = OMAP3430_REV_ES2_0;
334 cpu_rev = "2.0";
335 break;
336 case 2:
337 omap_revision = OMAP3430_REV_ES2_1;
338 cpu_rev = "2.1";
339 break;
340 case 3:
341 omap_revision = OMAP3430_REV_ES3_0;
342 cpu_rev = "3.0";
343 break;
344 case 4:
345 omap_revision = OMAP3430_REV_ES3_1;
346 cpu_rev = "3.1";
347 break;
348 case 7:
349 /* FALLTHROUGH */
350 default:
351 /* Use the latest known revision as default */
352 omap_revision = OMAP3430_REV_ES3_1_2;
353 cpu_rev = "3.1.2";
354 }
355 break;
356 case 0xb868:
357 /*
358 * Handle OMAP/AM 3505/3517 devices
359 *
360 * Set the device to be OMAP3517 here. Actual device
361 * is identified later based on the features.
362 */
363 switch (rev) {
364 case 0:
365 omap_revision = AM35XX_REV_ES1_0;
366 cpu_rev = "1.0";
367 break;
368 case 1:
369 /* FALLTHROUGH */
370 default:
371 omap_revision = AM35XX_REV_ES1_1;
372 cpu_rev = "1.1";
373 }
374 break;
375 case 0xb891:
376 /* Handle 36xx devices */
377
378 switch(rev) {
379 case 0: /* Take care of early samples */
380 omap_revision = OMAP3630_REV_ES1_0;
381 cpu_rev = "1.0";
382 break;
383 case 1:
384 omap_revision = OMAP3630_REV_ES1_1;
385 cpu_rev = "1.1";
386 break;
387 case 2:
388 /* FALLTHROUGH */
389 default:
390 omap_revision = OMAP3630_REV_ES1_2;
391 cpu_rev = "1.2";
392 }
393 break;
394 case 0xb81e:
395 switch (rev) {
396 case 0:
397 omap_revision = TI8168_REV_ES1_0;
398 cpu_rev = "1.0";
399 break;
400 case 1:
401 /* FALLTHROUGH */
402 default:
403 omap_revision = TI8168_REV_ES1_1;
404 cpu_rev = "1.1";
405 break;
406 }
407 break;
408 case 0xb944:
409 omap_revision = AM335X_REV_ES1_0;
410 cpu_rev = "1.0";
411 break;
412 case 0xb8f2:
413 switch (rev) {
414 case 0:
415 /* FALLTHROUGH */
416 case 1:
417 omap_revision = TI8148_REV_ES1_0;
418 cpu_rev = "1.0";
419 break;
420 case 2:
421 omap_revision = TI8148_REV_ES2_0;
422 cpu_rev = "2.0";
423 break;
424 case 3:
425 /* FALLTHROUGH */
426 default:
427 omap_revision = TI8148_REV_ES2_1;
428 cpu_rev = "2.1";
429 break;
430 }
431 break;
432 default:
433 /* Unknown default to latest silicon rev as default */
434 omap_revision = OMAP3630_REV_ES1_2;
435 cpu_rev = "1.2";
436 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
437 }
438}
439
440void __init omap4xxx_check_revision(void)
441{
442 u32 idcode;
443 u16 hawkeye;
444 u8 rev;
445
446 /*
447 * The IC rev detection is done with hawkeye and rev.
448 * Note that rev does not map directly to defined processor
449 * revision numbers as ES1.0 uses value 0.
450 */
451 idcode = read_tap_reg(OMAP_TAP_IDCODE);
452 hawkeye = (idcode >> 12) & 0xffff;
453 rev = (idcode >> 28) & 0xf;
454
455 /*
456 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
457 * Use ARM register to detect the correct ES version
458 */
459 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
460 idcode = read_cpuid(CPUID_ID);
461 rev = (idcode & 0xf) - 1;
462 }
463
464 switch (hawkeye) {
465 case 0xb852:
466 switch (rev) {
467 case 0:
468 omap_revision = OMAP4430_REV_ES1_0;
469 break;
470 case 1:
471 default:
472 omap_revision = OMAP4430_REV_ES2_0;
473 }
474 break;
475 case 0xb95c:
476 switch (rev) {
477 case 3:
478 omap_revision = OMAP4430_REV_ES2_1;
479 break;
480 case 4:
481 omap_revision = OMAP4430_REV_ES2_2;
482 break;
483 case 6:
484 default:
485 omap_revision = OMAP4430_REV_ES2_3;
486 }
487 break;
488 case 0xb94e:
489 switch (rev) {
490 case 0:
491 omap_revision = OMAP4460_REV_ES1_0;
492 break;
493 case 2:
494 default:
495 omap_revision = OMAP4460_REV_ES1_1;
496 break;
497 }
498 break;
499 case 0xb975:
500 switch (rev) {
501 case 0:
502 default:
503 omap_revision = OMAP4470_REV_ES1_0;
504 break;
505 }
506 break;
507 default:
508 /* Unknown default to latest silicon rev as default */
509 omap_revision = OMAP4430_REV_ES2_3;
510 }
511
512 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
513 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
514}
515
516/*
517 * Set up things for map_io and processor detection later on. Gets called
518 * pretty much first thing from board init. For multi-omap, this gets
519 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
520 * detect the exact revision later on in omap2_detect_revision() once map_io
521 * is done.
522 */
523void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
524{
525 omap_revision = omap2_globals->class;
526 tap_base = omap2_globals->tap;
527
528 if (cpu_is_omap34xx())
529 tap_prod_id = 0x0210;
530 else
531 tap_prod_id = 0x0208;
532}
1/*
2 * linux/arch/arm/mach-omap2/id.c
3 *
4 * OMAP2 CPU identification code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/random.h>
22#include <linux/slab.h>
23
24#ifdef CONFIG_SOC_BUS
25#include <linux/sys_soc.h>
26#endif
27
28#include <asm/cputype.h>
29
30#include "common.h"
31
32#include "id.h"
33
34#include "soc.h"
35#include "control.h"
36
37#define OMAP4_SILICON_TYPE_STANDARD 0x01
38#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
39
40#define OMAP_SOC_MAX_NAME_LENGTH 16
41
42static unsigned int omap_revision;
43static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
44static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
45u32 omap_features;
46
47unsigned int omap_rev(void)
48{
49 return omap_revision;
50}
51EXPORT_SYMBOL(omap_rev);
52
53int omap_type(void)
54{
55 u32 val = 0;
56
57 if (cpu_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
59 } else if (soc_is_am33xx() || soc_is_am43xx()) {
60 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
61 } else if (cpu_is_omap34xx()) {
62 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
63 } else if (cpu_is_omap44xx()) {
64 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
65 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
66 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
67 val &= OMAP5_DEVICETYPE_MASK;
68 val >>= 6;
69 goto out;
70 } else {
71 pr_err("Cannot detect omap type!\n");
72 goto out;
73 }
74
75 val &= OMAP2_DEVICETYPE_MASK;
76 val >>= 8;
77
78out:
79 return val;
80}
81EXPORT_SYMBOL(omap_type);
82
83
84/*----------------------------------------------------------------------------*/
85
86#define OMAP_TAP_IDCODE 0x0204
87#define OMAP_TAP_DIE_ID_0 0x0218
88#define OMAP_TAP_DIE_ID_1 0x021C
89#define OMAP_TAP_DIE_ID_2 0x0220
90#define OMAP_TAP_DIE_ID_3 0x0224
91
92#define OMAP_TAP_DIE_ID_44XX_0 0x0200
93#define OMAP_TAP_DIE_ID_44XX_1 0x0208
94#define OMAP_TAP_DIE_ID_44XX_2 0x020c
95#define OMAP_TAP_DIE_ID_44XX_3 0x0210
96
97#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
98
99struct omap_id {
100 u16 hawkeye; /* Silicon type (Hawkeye id) */
101 u8 dev; /* Device type from production_id reg */
102 u32 type; /* Combined type id copied to omap_revision */
103};
104
105/* Register values to detect the OMAP version */
106static struct omap_id omap_ids[] __initdata = {
107 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
108 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
109 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
110 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
111 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
112 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
113};
114
115static void __iomem *tap_base;
116static u16 tap_prod_id;
117
118void omap_get_die_id(struct omap_die_id *odi)
119{
120 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
121 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
122 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
123 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
124 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
125
126 return;
127 }
128 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
129 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
130 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
131 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
132}
133
134static int __init omap_feed_randpool(void)
135{
136 struct omap_die_id odi;
137
138 /* Throw the die ID into the entropy pool at boot */
139 omap_get_die_id(&odi);
140 add_device_randomness(&odi, sizeof(odi));
141 return 0;
142}
143omap_device_initcall(omap_feed_randpool);
144
145void __init omap2xxx_check_revision(void)
146{
147 int i, j;
148 u32 idcode, prod_id;
149 u16 hawkeye;
150 u8 dev_type, rev;
151 struct omap_die_id odi;
152
153 idcode = read_tap_reg(OMAP_TAP_IDCODE);
154 prod_id = read_tap_reg(tap_prod_id);
155 hawkeye = (idcode >> 12) & 0xffff;
156 rev = (idcode >> 28) & 0x0f;
157 dev_type = (prod_id >> 16) & 0x0f;
158 omap_get_die_id(&odi);
159
160 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
161 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
162 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
163 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
164 odi.id_1, (odi.id_1 >> 28) & 0xf);
165 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
166 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
167 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
168 prod_id, dev_type);
169
170 /* Check hawkeye ids */
171 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
172 if (hawkeye == omap_ids[i].hawkeye)
173 break;
174 }
175
176 if (i == ARRAY_SIZE(omap_ids)) {
177 printk(KERN_ERR "Unknown OMAP CPU id\n");
178 return;
179 }
180
181 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
182 if (dev_type == omap_ids[j].dev)
183 break;
184 }
185
186 if (j == ARRAY_SIZE(omap_ids)) {
187 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
188 omap_ids[i].type >> 16);
189 j = i;
190 }
191
192 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
193 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
194
195 pr_info("%s", soc_name);
196 if ((omap_rev() >> 8) & 0x0f)
197 pr_info("%s", soc_rev);
198 pr_info("\n");
199}
200
201#define OMAP3_SHOW_FEATURE(feat) \
202 if (omap3_has_ ##feat()) \
203 printk(#feat" ");
204
205static void __init omap3_cpuinfo(void)
206{
207 const char *cpu_name;
208
209 /*
210 * OMAP3430 and OMAP3530 are assumed to be same.
211 *
212 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
213 * on available features. Upon detection, update the CPU id
214 * and CPU class bits.
215 */
216 if (cpu_is_omap3630()) {
217 cpu_name = "OMAP3630";
218 } else if (soc_is_am35xx()) {
219 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
220 } else if (cpu_is_ti816x()) {
221 cpu_name = "TI816X";
222 } else if (soc_is_am335x()) {
223 cpu_name = "AM335X";
224 } else if (soc_is_am437x()) {
225 cpu_name = "AM437x";
226 } else if (cpu_is_ti814x()) {
227 cpu_name = "TI814X";
228 } else if (omap3_has_iva() && omap3_has_sgx()) {
229 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
230 cpu_name = "OMAP3430/3530";
231 } else if (omap3_has_iva()) {
232 cpu_name = "OMAP3525";
233 } else if (omap3_has_sgx()) {
234 cpu_name = "OMAP3515";
235 } else {
236 cpu_name = "OMAP3503";
237 }
238
239 sprintf(soc_name, "%s", cpu_name);
240
241 /* Print verbose information */
242 pr_info("%s %s (", soc_name, soc_rev);
243
244 OMAP3_SHOW_FEATURE(l2cache);
245 OMAP3_SHOW_FEATURE(iva);
246 OMAP3_SHOW_FEATURE(sgx);
247 OMAP3_SHOW_FEATURE(neon);
248 OMAP3_SHOW_FEATURE(isp);
249 OMAP3_SHOW_FEATURE(192mhz_clk);
250
251 printk(")\n");
252}
253
254#define OMAP3_CHECK_FEATURE(status,feat) \
255 if (((status & OMAP3_ ##feat## _MASK) \
256 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
257 omap_features |= OMAP3_HAS_ ##feat; \
258 }
259
260void __init omap3xxx_check_features(void)
261{
262 u32 status;
263
264 omap_features = 0;
265
266 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
267
268 OMAP3_CHECK_FEATURE(status, L2CACHE);
269 OMAP3_CHECK_FEATURE(status, IVA);
270 OMAP3_CHECK_FEATURE(status, SGX);
271 OMAP3_CHECK_FEATURE(status, NEON);
272 OMAP3_CHECK_FEATURE(status, ISP);
273 if (cpu_is_omap3630())
274 omap_features |= OMAP3_HAS_192MHZ_CLK;
275 if (cpu_is_omap3430() || cpu_is_omap3630())
276 omap_features |= OMAP3_HAS_IO_WAKEUP;
277 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
278 omap_rev() == OMAP3430_REV_ES3_1_2)
279 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
280
281 omap_features |= OMAP3_HAS_SDRC;
282
283 /*
284 * am35x fixups:
285 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
286 * reserved and therefore return 0 when read. Unfortunately,
287 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
288 * mean that a feature is present even though it isn't so clear
289 * the incorrectly set feature bits.
290 */
291 if (soc_is_am35xx())
292 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
293
294 /*
295 * TODO: Get additional info (where applicable)
296 * e.g. Size of L2 cache.
297 */
298
299 omap3_cpuinfo();
300}
301
302void __init omap4xxx_check_features(void)
303{
304 u32 si_type;
305
306 si_type =
307 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
308
309 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
310 omap_features = OMAP4_HAS_PERF_SILICON;
311}
312
313void __init ti81xx_check_features(void)
314{
315 omap_features = OMAP3_HAS_NEON;
316 omap3_cpuinfo();
317}
318
319void __init am33xx_check_features(void)
320{
321 u32 status;
322
323 omap_features = OMAP3_HAS_NEON;
324
325 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
326 if (status & AM33XX_SGX_MASK)
327 omap_features |= OMAP3_HAS_SGX;
328
329 omap3_cpuinfo();
330}
331
332void __init omap3xxx_check_revision(void)
333{
334 const char *cpu_rev;
335 u32 cpuid, idcode;
336 u16 hawkeye;
337 u8 rev;
338
339 /*
340 * We cannot access revision registers on ES1.0.
341 * If the processor type is Cortex-A8 and the revision is 0x0
342 * it means its Cortex r0p0 which is 3430 ES1.0.
343 */
344 cpuid = read_cpuid_id();
345 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
346 omap_revision = OMAP3430_REV_ES1_0;
347 cpu_rev = "1.0";
348 return;
349 }
350
351 /*
352 * Detection for 34xx ES2.0 and above can be done with just
353 * hawkeye and rev. See TRM 1.5.2 Device Identification.
354 * Note that rev does not map directly to our defined processor
355 * revision numbers as ES1.0 uses value 0.
356 */
357 idcode = read_tap_reg(OMAP_TAP_IDCODE);
358 hawkeye = (idcode >> 12) & 0xffff;
359 rev = (idcode >> 28) & 0xff;
360
361 switch (hawkeye) {
362 case 0xb7ae:
363 /* Handle 34xx/35xx devices */
364 switch (rev) {
365 case 0: /* Take care of early samples */
366 case 1:
367 omap_revision = OMAP3430_REV_ES2_0;
368 cpu_rev = "2.0";
369 break;
370 case 2:
371 omap_revision = OMAP3430_REV_ES2_1;
372 cpu_rev = "2.1";
373 break;
374 case 3:
375 omap_revision = OMAP3430_REV_ES3_0;
376 cpu_rev = "3.0";
377 break;
378 case 4:
379 omap_revision = OMAP3430_REV_ES3_1;
380 cpu_rev = "3.1";
381 break;
382 case 7:
383 /* FALLTHROUGH */
384 default:
385 /* Use the latest known revision as default */
386 omap_revision = OMAP3430_REV_ES3_1_2;
387 cpu_rev = "3.1.2";
388 }
389 break;
390 case 0xb868:
391 /*
392 * Handle OMAP/AM 3505/3517 devices
393 *
394 * Set the device to be OMAP3517 here. Actual device
395 * is identified later based on the features.
396 */
397 switch (rev) {
398 case 0:
399 omap_revision = AM35XX_REV_ES1_0;
400 cpu_rev = "1.0";
401 break;
402 case 1:
403 /* FALLTHROUGH */
404 default:
405 omap_revision = AM35XX_REV_ES1_1;
406 cpu_rev = "1.1";
407 }
408 break;
409 case 0xb891:
410 /* Handle 36xx devices */
411
412 switch(rev) {
413 case 0: /* Take care of early samples */
414 omap_revision = OMAP3630_REV_ES1_0;
415 cpu_rev = "1.0";
416 break;
417 case 1:
418 omap_revision = OMAP3630_REV_ES1_1;
419 cpu_rev = "1.1";
420 break;
421 case 2:
422 /* FALLTHROUGH */
423 default:
424 omap_revision = OMAP3630_REV_ES1_2;
425 cpu_rev = "1.2";
426 }
427 break;
428 case 0xb81e:
429 switch (rev) {
430 case 0:
431 omap_revision = TI8168_REV_ES1_0;
432 cpu_rev = "1.0";
433 break;
434 case 1:
435 omap_revision = TI8168_REV_ES1_1;
436 cpu_rev = "1.1";
437 break;
438 case 2:
439 omap_revision = TI8168_REV_ES2_0;
440 cpu_rev = "2.0";
441 break;
442 case 3:
443 /* FALLTHROUGH */
444 default:
445 omap_revision = TI8168_REV_ES2_1;
446 cpu_rev = "2.1";
447 }
448 break;
449 case 0xb944:
450 switch (rev) {
451 case 0:
452 omap_revision = AM335X_REV_ES1_0;
453 cpu_rev = "1.0";
454 break;
455 case 1:
456 omap_revision = AM335X_REV_ES2_0;
457 cpu_rev = "2.0";
458 break;
459 case 2:
460 /* FALLTHROUGH */
461 default:
462 omap_revision = AM335X_REV_ES2_1;
463 cpu_rev = "2.1";
464 break;
465 }
466 break;
467 case 0xb98c:
468 switch (rev) {
469 case 0:
470 omap_revision = AM437X_REV_ES1_0;
471 cpu_rev = "1.0";
472 break;
473 case 1:
474 /* FALLTHROUGH */
475 default:
476 omap_revision = AM437X_REV_ES1_1;
477 cpu_rev = "1.1";
478 break;
479 }
480 break;
481 case 0xb8f2:
482 switch (rev) {
483 case 0:
484 /* FALLTHROUGH */
485 case 1:
486 omap_revision = TI8148_REV_ES1_0;
487 cpu_rev = "1.0";
488 break;
489 case 2:
490 omap_revision = TI8148_REV_ES2_0;
491 cpu_rev = "2.0";
492 break;
493 case 3:
494 /* FALLTHROUGH */
495 default:
496 omap_revision = TI8148_REV_ES2_1;
497 cpu_rev = "2.1";
498 break;
499 }
500 break;
501 default:
502 /* Unknown default to latest silicon rev as default */
503 omap_revision = OMAP3630_REV_ES1_2;
504 cpu_rev = "1.2";
505 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
506 }
507 sprintf(soc_rev, "ES%s", cpu_rev);
508}
509
510void __init omap4xxx_check_revision(void)
511{
512 u32 idcode;
513 u16 hawkeye;
514 u8 rev;
515
516 /*
517 * The IC rev detection is done with hawkeye and rev.
518 * Note that rev does not map directly to defined processor
519 * revision numbers as ES1.0 uses value 0.
520 */
521 idcode = read_tap_reg(OMAP_TAP_IDCODE);
522 hawkeye = (idcode >> 12) & 0xffff;
523 rev = (idcode >> 28) & 0xf;
524
525 /*
526 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
527 * Use ARM register to detect the correct ES version
528 */
529 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
530 idcode = read_cpuid_id();
531 rev = (idcode & 0xf) - 1;
532 }
533
534 switch (hawkeye) {
535 case 0xb852:
536 switch (rev) {
537 case 0:
538 omap_revision = OMAP4430_REV_ES1_0;
539 break;
540 case 1:
541 default:
542 omap_revision = OMAP4430_REV_ES2_0;
543 }
544 break;
545 case 0xb95c:
546 switch (rev) {
547 case 3:
548 omap_revision = OMAP4430_REV_ES2_1;
549 break;
550 case 4:
551 omap_revision = OMAP4430_REV_ES2_2;
552 break;
553 case 6:
554 default:
555 omap_revision = OMAP4430_REV_ES2_3;
556 }
557 break;
558 case 0xb94e:
559 switch (rev) {
560 case 0:
561 omap_revision = OMAP4460_REV_ES1_0;
562 break;
563 case 2:
564 default:
565 omap_revision = OMAP4460_REV_ES1_1;
566 break;
567 }
568 break;
569 case 0xb975:
570 switch (rev) {
571 case 0:
572 default:
573 omap_revision = OMAP4470_REV_ES1_0;
574 break;
575 }
576 break;
577 default:
578 /* Unknown default to latest silicon rev as default */
579 omap_revision = OMAP4430_REV_ES2_3;
580 }
581
582 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
583 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
584 (omap_rev() >> 8) & 0xf);
585 pr_info("%s %s\n", soc_name, soc_rev);
586}
587
588void __init omap5xxx_check_revision(void)
589{
590 u32 idcode;
591 u16 hawkeye;
592 u8 rev;
593
594 idcode = read_tap_reg(OMAP_TAP_IDCODE);
595 hawkeye = (idcode >> 12) & 0xffff;
596 rev = (idcode >> 28) & 0xff;
597 switch (hawkeye) {
598 case 0xb942:
599 switch (rev) {
600 case 0:
601 /* No support for ES1.0 Test chip */
602 BUG();
603 case 1:
604 default:
605 omap_revision = OMAP5430_REV_ES2_0;
606 }
607 break;
608
609 case 0xb998:
610 switch (rev) {
611 case 0:
612 /* No support for ES1.0 Test chip */
613 BUG();
614 case 1:
615 default:
616 omap_revision = OMAP5432_REV_ES2_0;
617 }
618 break;
619
620 default:
621 /* Unknown default to latest silicon rev as default*/
622 omap_revision = OMAP5430_REV_ES2_0;
623 }
624
625 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
626 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
627
628 pr_info("%s %s\n", soc_name, soc_rev);
629}
630
631/*
632 * Set up things for map_io and processor detection later on. Gets called
633 * pretty much first thing from board init. For multi-omap, this gets
634 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
635 * detect the exact revision later on in omap2_detect_revision() once map_io
636 * is done.
637 */
638void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
639{
640 omap_revision = class;
641 tap_base = tap;
642
643 /* XXX What is this intended to do? */
644 if (cpu_is_omap34xx())
645 tap_prod_id = 0x0210;
646 else
647 tap_prod_id = 0x0208;
648}
649
650#ifdef CONFIG_SOC_BUS
651
652static const char * const omap_types[] = {
653 [OMAP2_DEVICE_TYPE_TEST] = "TST",
654 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
655 [OMAP2_DEVICE_TYPE_SEC] = "HS",
656 [OMAP2_DEVICE_TYPE_GP] = "GP",
657 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
658};
659
660static const char * __init omap_get_family(void)
661{
662 if (cpu_is_omap24xx())
663 return kasprintf(GFP_KERNEL, "OMAP2");
664 else if (cpu_is_omap34xx())
665 return kasprintf(GFP_KERNEL, "OMAP3");
666 else if (cpu_is_omap44xx())
667 return kasprintf(GFP_KERNEL, "OMAP4");
668 else if (soc_is_omap54xx())
669 return kasprintf(GFP_KERNEL, "OMAP5");
670 else if (soc_is_am43xx())
671 return kasprintf(GFP_KERNEL, "AM43xx");
672 else
673 return kasprintf(GFP_KERNEL, "Unknown");
674}
675
676static ssize_t omap_get_type(struct device *dev,
677 struct device_attribute *attr,
678 char *buf)
679{
680 return sprintf(buf, "%s\n", omap_types[omap_type()]);
681}
682
683static struct device_attribute omap_soc_attr =
684 __ATTR(type, S_IRUGO, omap_get_type, NULL);
685
686void __init omap_soc_device_init(void)
687{
688 struct device *parent;
689 struct soc_device *soc_dev;
690 struct soc_device_attribute *soc_dev_attr;
691
692 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
693 if (!soc_dev_attr)
694 return;
695
696 soc_dev_attr->machine = soc_name;
697 soc_dev_attr->family = omap_get_family();
698 soc_dev_attr->revision = soc_rev;
699
700 soc_dev = soc_device_register(soc_dev_attr);
701 if (IS_ERR(soc_dev)) {
702 kfree(soc_dev_attr);
703 return;
704 }
705
706 parent = soc_device_to_device(soc_dev);
707 device_create_file(parent, &omap_soc_attr);
708}
709#endif /* CONFIG_SOC_BUS */