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1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/ioport.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27
28#include <asm/mach-types.h>
29#include <plat/gpmc.h>
30
31#include <plat/sdrc.h>
32
33/* GPMC register offsets */
34#define GPMC_REVISION 0x00
35#define GPMC_SYSCONFIG 0x10
36#define GPMC_SYSSTATUS 0x14
37#define GPMC_IRQSTATUS 0x18
38#define GPMC_IRQENABLE 0x1c
39#define GPMC_TIMEOUT_CONTROL 0x40
40#define GPMC_ERR_ADDRESS 0x44
41#define GPMC_ERR_TYPE 0x48
42#define GPMC_CONFIG 0x50
43#define GPMC_STATUS 0x54
44#define GPMC_PREFETCH_CONFIG1 0x1e0
45#define GPMC_PREFETCH_CONFIG2 0x1e4
46#define GPMC_PREFETCH_CONTROL 0x1ec
47#define GPMC_PREFETCH_STATUS 0x1f0
48#define GPMC_ECC_CONFIG 0x1f4
49#define GPMC_ECC_CONTROL 0x1f8
50#define GPMC_ECC_SIZE_CONFIG 0x1fc
51#define GPMC_ECC1_RESULT 0x200
52#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
53
54/* GPMC ECC control settings */
55#define GPMC_ECC_CTRL_ECCCLEAR 0x100
56#define GPMC_ECC_CTRL_ECCDISABLE 0x000
57#define GPMC_ECC_CTRL_ECCREG1 0x001
58#define GPMC_ECC_CTRL_ECCREG2 0x002
59#define GPMC_ECC_CTRL_ECCREG3 0x003
60#define GPMC_ECC_CTRL_ECCREG4 0x004
61#define GPMC_ECC_CTRL_ECCREG5 0x005
62#define GPMC_ECC_CTRL_ECCREG6 0x006
63#define GPMC_ECC_CTRL_ECCREG7 0x007
64#define GPMC_ECC_CTRL_ECCREG8 0x008
65#define GPMC_ECC_CTRL_ECCREG9 0x009
66
67#define GPMC_CS0_OFFSET 0x60
68#define GPMC_CS_SIZE 0x30
69
70#define GPMC_MEM_START 0x00000000
71#define GPMC_MEM_END 0x3FFFFFFF
72#define BOOT_ROM_SPACE 0x100000 /* 1MB */
73
74#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
75#define GPMC_SECTION_SHIFT 28 /* 128 MB */
76
77#define CS_NUM_SHIFT 24
78#define ENABLE_PREFETCH (0x1 << 7)
79#define DMA_MPU_MODE 2
80
81/* Structure to save gpmc cs context */
82struct gpmc_cs_config {
83 u32 config1;
84 u32 config2;
85 u32 config3;
86 u32 config4;
87 u32 config5;
88 u32 config6;
89 u32 config7;
90 int is_valid;
91};
92
93/*
94 * Structure to save/restore gpmc context
95 * to support core off on OMAP3
96 */
97struct omap3_gpmc_regs {
98 u32 sysconfig;
99 u32 irqenable;
100 u32 timeout_ctrl;
101 u32 config;
102 u32 prefetch_config1;
103 u32 prefetch_config2;
104 u32 prefetch_control;
105 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
106};
107
108static struct resource gpmc_mem_root;
109static struct resource gpmc_cs_mem[GPMC_CS_NUM];
110static DEFINE_SPINLOCK(gpmc_mem_lock);
111static unsigned int gpmc_cs_map; /* flag for cs which are initialized */
112static int gpmc_ecc_used = -EINVAL; /* cs using ecc engine */
113
114static void __iomem *gpmc_base;
115
116static struct clk *gpmc_l3_clk;
117
118static irqreturn_t gpmc_handle_irq(int irq, void *dev);
119
120static void gpmc_write_reg(int idx, u32 val)
121{
122 __raw_writel(val, gpmc_base + idx);
123}
124
125static u32 gpmc_read_reg(int idx)
126{
127 return __raw_readl(gpmc_base + idx);
128}
129
130static void gpmc_cs_write_byte(int cs, int idx, u8 val)
131{
132 void __iomem *reg_addr;
133
134 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
135 __raw_writeb(val, reg_addr);
136}
137
138static u8 gpmc_cs_read_byte(int cs, int idx)
139{
140 void __iomem *reg_addr;
141
142 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
143 return __raw_readb(reg_addr);
144}
145
146void gpmc_cs_write_reg(int cs, int idx, u32 val)
147{
148 void __iomem *reg_addr;
149
150 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
151 __raw_writel(val, reg_addr);
152}
153
154u32 gpmc_cs_read_reg(int cs, int idx)
155{
156 void __iomem *reg_addr;
157
158 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
159 return __raw_readl(reg_addr);
160}
161
162/* TODO: Add support for gpmc_fck to clock framework and use it */
163unsigned long gpmc_get_fclk_period(void)
164{
165 unsigned long rate = clk_get_rate(gpmc_l3_clk);
166
167 if (rate == 0) {
168 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
169 return 0;
170 }
171
172 rate /= 1000;
173 rate = 1000000000 / rate; /* In picoseconds */
174
175 return rate;
176}
177
178unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
179{
180 unsigned long tick_ps;
181
182 /* Calculate in picosecs to yield more exact results */
183 tick_ps = gpmc_get_fclk_period();
184
185 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
186}
187
188unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
189{
190 unsigned long tick_ps;
191
192 /* Calculate in picosecs to yield more exact results */
193 tick_ps = gpmc_get_fclk_period();
194
195 return (time_ps + tick_ps - 1) / tick_ps;
196}
197
198unsigned int gpmc_ticks_to_ns(unsigned int ticks)
199{
200 return ticks * gpmc_get_fclk_period() / 1000;
201}
202
203unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
204{
205 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
206
207 return ticks * gpmc_get_fclk_period() / 1000;
208}
209
210#ifdef DEBUG
211static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
212 int time, const char *name)
213#else
214static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
215 int time)
216#endif
217{
218 u32 l;
219 int ticks, mask, nr_bits;
220
221 if (time == 0)
222 ticks = 0;
223 else
224 ticks = gpmc_ns_to_ticks(time);
225 nr_bits = end_bit - st_bit + 1;
226 if (ticks >= 1 << nr_bits) {
227#ifdef DEBUG
228 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
229 cs, name, time, ticks, 1 << nr_bits);
230#endif
231 return -1;
232 }
233
234 mask = (1 << nr_bits) - 1;
235 l = gpmc_cs_read_reg(cs, reg);
236#ifdef DEBUG
237 printk(KERN_INFO
238 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
239 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
240 (l >> st_bit) & mask, time);
241#endif
242 l &= ~(mask << st_bit);
243 l |= ticks << st_bit;
244 gpmc_cs_write_reg(cs, reg, l);
245
246 return 0;
247}
248
249#ifdef DEBUG
250#define GPMC_SET_ONE(reg, st, end, field) \
251 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
252 t->field, #field) < 0) \
253 return -1
254#else
255#define GPMC_SET_ONE(reg, st, end, field) \
256 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
257 return -1
258#endif
259
260int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
261{
262 int div;
263 u32 l;
264
265 l = sync_clk + (gpmc_get_fclk_period() - 1);
266 div = l / gpmc_get_fclk_period();
267 if (div > 4)
268 return -1;
269 if (div <= 0)
270 div = 1;
271
272 return div;
273}
274
275int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
276{
277 int div;
278 u32 l;
279
280 div = gpmc_cs_calc_divider(cs, t->sync_clk);
281 if (div < 0)
282 return -1;
283
284 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
285 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
286 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
287
288 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
289 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
290 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
291
292 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
293 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
294 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
295 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
296
297 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
298 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
299 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
300
301 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
302
303 if (cpu_is_omap34xx()) {
304 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
305 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
306 }
307
308 /* caller is expected to have initialized CONFIG1 to cover
309 * at least sync vs async
310 */
311 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
312 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
313#ifdef DEBUG
314 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
315 cs, (div * gpmc_get_fclk_period()) / 1000, div);
316#endif
317 l &= ~0x03;
318 l |= (div - 1);
319 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
320 }
321
322 return 0;
323}
324
325static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
326{
327 u32 l;
328 u32 mask;
329
330 mask = (1 << GPMC_SECTION_SHIFT) - size;
331 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
332 l &= ~0x3f;
333 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
334 l &= ~(0x0f << 8);
335 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
336 l |= GPMC_CONFIG7_CSVALID;
337 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
338}
339
340static void gpmc_cs_disable_mem(int cs)
341{
342 u32 l;
343
344 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
345 l &= ~GPMC_CONFIG7_CSVALID;
346 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
347}
348
349static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
350{
351 u32 l;
352 u32 mask;
353
354 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
355 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
356 mask = (l >> 8) & 0x0f;
357 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
358}
359
360static int gpmc_cs_mem_enabled(int cs)
361{
362 u32 l;
363
364 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
365 return l & GPMC_CONFIG7_CSVALID;
366}
367
368int gpmc_cs_set_reserved(int cs, int reserved)
369{
370 if (cs > GPMC_CS_NUM)
371 return -ENODEV;
372
373 gpmc_cs_map &= ~(1 << cs);
374 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
375
376 return 0;
377}
378
379int gpmc_cs_reserved(int cs)
380{
381 if (cs > GPMC_CS_NUM)
382 return -ENODEV;
383
384 return gpmc_cs_map & (1 << cs);
385}
386
387static unsigned long gpmc_mem_align(unsigned long size)
388{
389 int order;
390
391 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
392 order = GPMC_CHUNK_SHIFT - 1;
393 do {
394 size >>= 1;
395 order++;
396 } while (size);
397 size = 1 << order;
398 return size;
399}
400
401static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
402{
403 struct resource *res = &gpmc_cs_mem[cs];
404 int r;
405
406 size = gpmc_mem_align(size);
407 spin_lock(&gpmc_mem_lock);
408 res->start = base;
409 res->end = base + size - 1;
410 r = request_resource(&gpmc_mem_root, res);
411 spin_unlock(&gpmc_mem_lock);
412
413 return r;
414}
415
416int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
417{
418 struct resource *res = &gpmc_cs_mem[cs];
419 int r = -1;
420
421 if (cs > GPMC_CS_NUM)
422 return -ENODEV;
423
424 size = gpmc_mem_align(size);
425 if (size > (1 << GPMC_SECTION_SHIFT))
426 return -ENOMEM;
427
428 spin_lock(&gpmc_mem_lock);
429 if (gpmc_cs_reserved(cs)) {
430 r = -EBUSY;
431 goto out;
432 }
433 if (gpmc_cs_mem_enabled(cs))
434 r = adjust_resource(res, res->start & ~(size - 1), size);
435 if (r < 0)
436 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
437 size, NULL, NULL);
438 if (r < 0)
439 goto out;
440
441 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
442 *base = res->start;
443 gpmc_cs_set_reserved(cs, 1);
444out:
445 spin_unlock(&gpmc_mem_lock);
446 return r;
447}
448EXPORT_SYMBOL(gpmc_cs_request);
449
450void gpmc_cs_free(int cs)
451{
452 spin_lock(&gpmc_mem_lock);
453 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
454 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
455 BUG();
456 spin_unlock(&gpmc_mem_lock);
457 return;
458 }
459 gpmc_cs_disable_mem(cs);
460 release_resource(&gpmc_cs_mem[cs]);
461 gpmc_cs_set_reserved(cs, 0);
462 spin_unlock(&gpmc_mem_lock);
463}
464EXPORT_SYMBOL(gpmc_cs_free);
465
466/**
467 * gpmc_read_status - read access request to get the different gpmc status
468 * @cmd: command type
469 * @return status
470 */
471int gpmc_read_status(int cmd)
472{
473 int status = -EINVAL;
474 u32 regval = 0;
475
476 switch (cmd) {
477 case GPMC_GET_IRQ_STATUS:
478 status = gpmc_read_reg(GPMC_IRQSTATUS);
479 break;
480
481 case GPMC_PREFETCH_FIFO_CNT:
482 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
483 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
484 break;
485
486 case GPMC_PREFETCH_COUNT:
487 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
488 status = GPMC_PREFETCH_STATUS_COUNT(regval);
489 break;
490
491 case GPMC_STATUS_BUFFER:
492 regval = gpmc_read_reg(GPMC_STATUS);
493 /* 1 : buffer is available to write */
494 status = regval & GPMC_STATUS_BUFF_EMPTY;
495 break;
496
497 default:
498 printk(KERN_ERR "gpmc_read_status: Not supported\n");
499 }
500 return status;
501}
502EXPORT_SYMBOL(gpmc_read_status);
503
504/**
505 * gpmc_cs_configure - write request to configure gpmc
506 * @cs: chip select number
507 * @cmd: command type
508 * @wval: value to write
509 * @return status of the operation
510 */
511int gpmc_cs_configure(int cs, int cmd, int wval)
512{
513 int err = 0;
514 u32 regval = 0;
515
516 switch (cmd) {
517 case GPMC_ENABLE_IRQ:
518 gpmc_write_reg(GPMC_IRQENABLE, wval);
519 break;
520
521 case GPMC_SET_IRQ_STATUS:
522 gpmc_write_reg(GPMC_IRQSTATUS, wval);
523 break;
524
525 case GPMC_CONFIG_WP:
526 regval = gpmc_read_reg(GPMC_CONFIG);
527 if (wval)
528 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
529 else
530 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
531 gpmc_write_reg(GPMC_CONFIG, regval);
532 break;
533
534 case GPMC_CONFIG_RDY_BSY:
535 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
536 if (wval)
537 regval |= WR_RD_PIN_MONITORING;
538 else
539 regval &= ~WR_RD_PIN_MONITORING;
540 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
541 break;
542
543 case GPMC_CONFIG_DEV_SIZE:
544 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
545
546 /* clear 2 target bits */
547 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
548
549 /* set the proper value */
550 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
551
552 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
553 break;
554
555 case GPMC_CONFIG_DEV_TYPE:
556 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
557 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
558 if (wval == GPMC_DEVICETYPE_NOR)
559 regval |= GPMC_CONFIG1_MUXADDDATA;
560 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
561 break;
562
563 default:
564 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
565 err = -EINVAL;
566 }
567
568 return err;
569}
570EXPORT_SYMBOL(gpmc_cs_configure);
571
572/**
573 * gpmc_nand_read - nand specific read access request
574 * @cs: chip select number
575 * @cmd: command type
576 */
577int gpmc_nand_read(int cs, int cmd)
578{
579 int rval = -EINVAL;
580
581 switch (cmd) {
582 case GPMC_NAND_DATA:
583 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
584 break;
585
586 default:
587 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
588 }
589 return rval;
590}
591EXPORT_SYMBOL(gpmc_nand_read);
592
593/**
594 * gpmc_nand_write - nand specific write request
595 * @cs: chip select number
596 * @cmd: command type
597 * @wval: value to write
598 */
599int gpmc_nand_write(int cs, int cmd, int wval)
600{
601 int err = 0;
602
603 switch (cmd) {
604 case GPMC_NAND_COMMAND:
605 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
606 break;
607
608 case GPMC_NAND_ADDRESS:
609 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
610 break;
611
612 case GPMC_NAND_DATA:
613 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
614
615 default:
616 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
617 err = -EINVAL;
618 }
619 return err;
620}
621EXPORT_SYMBOL(gpmc_nand_write);
622
623
624
625/**
626 * gpmc_prefetch_enable - configures and starts prefetch transfer
627 * @cs: cs (chip select) number
628 * @fifo_th: fifo threshold to be used for read/ write
629 * @dma_mode: dma mode enable (1) or disable (0)
630 * @u32_count: number of bytes to be transferred
631 * @is_write: prefetch read(0) or write post(1) mode
632 */
633int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
634 unsigned int u32_count, int is_write)
635{
636
637 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
638 pr_err("gpmc: fifo threshold is not supported\n");
639 return -1;
640 } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
641 /* Set the amount of bytes to be prefetched */
642 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
643
644 /* Set dma/mpu mode, the prefetch read / post write and
645 * enable the engine. Set which cs is has requested for.
646 */
647 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
648 PREFETCH_FIFOTHRESHOLD(fifo_th) |
649 ENABLE_PREFETCH |
650 (dma_mode << DMA_MPU_MODE) |
651 (0x1 & is_write)));
652
653 /* Start the prefetch engine */
654 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
655 } else {
656 return -EBUSY;
657 }
658
659 return 0;
660}
661EXPORT_SYMBOL(gpmc_prefetch_enable);
662
663/**
664 * gpmc_prefetch_reset - disables and stops the prefetch engine
665 */
666int gpmc_prefetch_reset(int cs)
667{
668 u32 config1;
669
670 /* check if the same module/cs is trying to reset */
671 config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
672 if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
673 return -EINVAL;
674
675 /* Stop the PFPW engine */
676 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
677
678 /* Reset/disable the PFPW engine */
679 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
680
681 return 0;
682}
683EXPORT_SYMBOL(gpmc_prefetch_reset);
684
685static void __init gpmc_mem_init(void)
686{
687 int cs;
688 unsigned long boot_rom_space = 0;
689
690 /* never allocate the first page, to facilitate bug detection;
691 * even if we didn't boot from ROM.
692 */
693 boot_rom_space = BOOT_ROM_SPACE;
694 /* In apollon the CS0 is mapped as 0x0000 0000 */
695 if (machine_is_omap_apollon())
696 boot_rom_space = 0;
697 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
698 gpmc_mem_root.end = GPMC_MEM_END;
699
700 /* Reserve all regions that has been set up by bootloader */
701 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
702 u32 base, size;
703
704 if (!gpmc_cs_mem_enabled(cs))
705 continue;
706 gpmc_cs_get_memconf(cs, &base, &size);
707 if (gpmc_cs_insert_mem(cs, base, size) < 0)
708 BUG();
709 }
710}
711
712static int __init gpmc_init(void)
713{
714 u32 l, irq;
715 int cs, ret = -EINVAL;
716 int gpmc_irq;
717 char *ck = NULL;
718
719 if (cpu_is_omap24xx()) {
720 ck = "core_l3_ck";
721 if (cpu_is_omap2420())
722 l = OMAP2420_GPMC_BASE;
723 else
724 l = OMAP34XX_GPMC_BASE;
725 gpmc_irq = INT_34XX_GPMC_IRQ;
726 } else if (cpu_is_omap34xx()) {
727 ck = "gpmc_fck";
728 l = OMAP34XX_GPMC_BASE;
729 gpmc_irq = INT_34XX_GPMC_IRQ;
730 } else if (cpu_is_omap44xx()) {
731 ck = "gpmc_ck";
732 l = OMAP44XX_GPMC_BASE;
733 gpmc_irq = OMAP44XX_IRQ_GPMC;
734 }
735
736 if (WARN_ON(!ck))
737 return ret;
738
739 gpmc_l3_clk = clk_get(NULL, ck);
740 if (IS_ERR(gpmc_l3_clk)) {
741 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
742 BUG();
743 }
744
745 gpmc_base = ioremap(l, SZ_4K);
746 if (!gpmc_base) {
747 clk_put(gpmc_l3_clk);
748 printk(KERN_ERR "Could not get GPMC register memory\n");
749 BUG();
750 }
751
752 clk_enable(gpmc_l3_clk);
753
754 l = gpmc_read_reg(GPMC_REVISION);
755 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
756 /* Set smart idle mode and automatic L3 clock gating */
757 l = gpmc_read_reg(GPMC_SYSCONFIG);
758 l &= 0x03 << 3;
759 l |= (0x02 << 3) | (1 << 0);
760 gpmc_write_reg(GPMC_SYSCONFIG, l);
761 gpmc_mem_init();
762
763 /* initalize the irq_chained */
764 irq = OMAP_GPMC_IRQ_BASE;
765 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
766 irq_set_chip_and_handler(irq, &dummy_irq_chip,
767 handle_simple_irq);
768 set_irq_flags(irq, IRQF_VALID);
769 irq++;
770 }
771
772 ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
773 if (ret)
774 pr_err("gpmc: irq-%d could not claim: err %d\n",
775 gpmc_irq, ret);
776 return ret;
777}
778postcore_initcall(gpmc_init);
779
780static irqreturn_t gpmc_handle_irq(int irq, void *dev)
781{
782 u8 cs;
783
784 /* check cs to invoke the irq */
785 cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
786 if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
787 generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
788
789 return IRQ_HANDLED;
790}
791
792#ifdef CONFIG_ARCH_OMAP3
793static struct omap3_gpmc_regs gpmc_context;
794
795void omap3_gpmc_save_context(void)
796{
797 int i;
798
799 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
800 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
801 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
802 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
803 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
804 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
805 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
806 for (i = 0; i < GPMC_CS_NUM; i++) {
807 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
808 if (gpmc_context.cs_context[i].is_valid) {
809 gpmc_context.cs_context[i].config1 =
810 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
811 gpmc_context.cs_context[i].config2 =
812 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
813 gpmc_context.cs_context[i].config3 =
814 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
815 gpmc_context.cs_context[i].config4 =
816 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
817 gpmc_context.cs_context[i].config5 =
818 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
819 gpmc_context.cs_context[i].config6 =
820 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
821 gpmc_context.cs_context[i].config7 =
822 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
823 }
824 }
825}
826
827void omap3_gpmc_restore_context(void)
828{
829 int i;
830
831 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
832 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
833 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
834 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
835 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
836 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
837 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
838 for (i = 0; i < GPMC_CS_NUM; i++) {
839 if (gpmc_context.cs_context[i].is_valid) {
840 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
841 gpmc_context.cs_context[i].config1);
842 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
843 gpmc_context.cs_context[i].config2);
844 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
845 gpmc_context.cs_context[i].config3);
846 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
847 gpmc_context.cs_context[i].config4);
848 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
849 gpmc_context.cs_context[i].config5);
850 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
851 gpmc_context.cs_context[i].config6);
852 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
853 gpmc_context.cs_context[i].config7);
854 }
855 }
856}
857#endif /* CONFIG_ARCH_OMAP3 */
858
859/**
860 * gpmc_enable_hwecc - enable hardware ecc functionality
861 * @cs: chip select number
862 * @mode: read/write mode
863 * @dev_width: device bus width(1 for x16, 0 for x8)
864 * @ecc_size: bytes for which ECC will be generated
865 */
866int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
867{
868 unsigned int val;
869
870 /* check if ecc module is in used */
871 if (gpmc_ecc_used != -EINVAL)
872 return -EINVAL;
873
874 gpmc_ecc_used = cs;
875
876 /* clear ecc and enable bits */
877 gpmc_write_reg(GPMC_ECC_CONTROL,
878 GPMC_ECC_CTRL_ECCCLEAR |
879 GPMC_ECC_CTRL_ECCREG1);
880
881 /* program ecc and result sizes */
882 val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
883 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
884
885 switch (mode) {
886 case GPMC_ECC_READ:
887 case GPMC_ECC_WRITE:
888 gpmc_write_reg(GPMC_ECC_CONTROL,
889 GPMC_ECC_CTRL_ECCCLEAR |
890 GPMC_ECC_CTRL_ECCREG1);
891 break;
892 case GPMC_ECC_READSYN:
893 gpmc_write_reg(GPMC_ECC_CONTROL,
894 GPMC_ECC_CTRL_ECCCLEAR |
895 GPMC_ECC_CTRL_ECCDISABLE);
896 break;
897 default:
898 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
899 break;
900 }
901
902 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
903 val = (dev_width << 7) | (cs << 1) | (0x1);
904 gpmc_write_reg(GPMC_ECC_CONFIG, val);
905 return 0;
906}
907EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
908
909/**
910 * gpmc_calculate_ecc - generate non-inverted ecc bytes
911 * @cs: chip select number
912 * @dat: data pointer over which ecc is computed
913 * @ecc_code: ecc code buffer
914 *
915 * Using non-inverted ECC is considered ugly since writing a blank
916 * page (padding) will clear the ECC bytes. This is not a problem as long
917 * no one is trying to write data on the seemingly unused page. Reading
918 * an erased page will produce an ECC mismatch between generated and read
919 * ECC bytes that has to be dealt with separately.
920 */
921int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
922{
923 unsigned int val = 0x0;
924
925 if (gpmc_ecc_used != cs)
926 return -EINVAL;
927
928 /* read ecc result */
929 val = gpmc_read_reg(GPMC_ECC1_RESULT);
930 *ecc_code++ = val; /* P128e, ..., P1e */
931 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
932 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
933 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
934
935 gpmc_ecc_used = -EINVAL;
936 return 0;
937}
938EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
939
940#ifdef CONFIG_ARCH_OMAP3
941
942/**
943 * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
944 * @cs: chip select number
945 * @nsectors: how many 512-byte sectors to process
946 * @nerrors: how many errors to correct per sector (4 or 8)
947 *
948 * This function must be executed before any call to gpmc_enable_hwecc_bch.
949 */
950int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
951{
952 /* check if ecc module is in use */
953 if (gpmc_ecc_used != -EINVAL)
954 return -EINVAL;
955
956 /* support only OMAP3 class */
957 if (!cpu_is_omap34xx()) {
958 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
959 return -EINVAL;
960 }
961
962 /*
963 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
964 * Other chips may be added if confirmed to work.
965 */
966 if ((nerrors == 4) &&
967 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
968 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
969 return -EINVAL;
970 }
971
972 /* sanity check */
973 if (nsectors > 8) {
974 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
975 nsectors);
976 return -EINVAL;
977 }
978
979 return 0;
980}
981EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
982
983/**
984 * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
985 * @cs: chip select number
986 * @mode: read/write mode
987 * @dev_width: device bus width(1 for x16, 0 for x8)
988 * @nsectors: how many 512-byte sectors to process
989 * @nerrors: how many errors to correct per sector (4 or 8)
990 */
991int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
992 int nerrors)
993{
994 unsigned int val;
995
996 /* check if ecc module is in use */
997 if (gpmc_ecc_used != -EINVAL)
998 return -EINVAL;
999
1000 gpmc_ecc_used = cs;
1001
1002 /* clear ecc and enable bits */
1003 gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1004
1005 /*
1006 * When using BCH, sector size is hardcoded to 512 bytes.
1007 * Here we are using wrapping mode 6 both for reading and writing, with:
1008 * size0 = 0 (no additional protected byte in spare area)
1009 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1010 */
1011 gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1012
1013 /* BCH configuration */
1014 val = ((1 << 16) | /* enable BCH */
1015 (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1016 (0x06 << 8) | /* wrap mode = 6 */
1017 (dev_width << 7) | /* bus width */
1018 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1019 (cs << 1) | /* ECC CS */
1020 (0x1)); /* enable ECC */
1021
1022 gpmc_write_reg(GPMC_ECC_CONFIG, val);
1023 gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1024 return 0;
1025}
1026EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1027
1028/**
1029 * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1030 * @cs: chip select number
1031 * @dat: The pointer to data on which ecc is computed
1032 * @ecc: The ecc output buffer
1033 */
1034int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1035{
1036 int i;
1037 unsigned long nsectors, reg, val1, val2;
1038
1039 if (gpmc_ecc_used != cs)
1040 return -EINVAL;
1041
1042 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1043
1044 for (i = 0; i < nsectors; i++) {
1045
1046 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1047
1048 /* Read hw-computed remainder */
1049 val1 = gpmc_read_reg(reg + 0);
1050 val2 = gpmc_read_reg(reg + 4);
1051
1052 /*
1053 * Add constant polynomial to remainder, in order to get an ecc
1054 * sequence of 0xFFs for a buffer filled with 0xFFs; and
1055 * left-justify the resulting polynomial.
1056 */
1057 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1058 *ecc++ = 0x13 ^ ((val2 >> 4) & 0xFF);
1059 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1060 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1061 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1062 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1063 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1064 }
1065
1066 gpmc_ecc_used = -EINVAL;
1067 return 0;
1068}
1069EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1070
1071/**
1072 * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1073 * @cs: chip select number
1074 * @dat: The pointer to data on which ecc is computed
1075 * @ecc: The ecc output buffer
1076 */
1077int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1078{
1079 int i;
1080 unsigned long nsectors, reg, val1, val2, val3, val4;
1081
1082 if (gpmc_ecc_used != cs)
1083 return -EINVAL;
1084
1085 nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1086
1087 for (i = 0; i < nsectors; i++) {
1088
1089 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1090
1091 /* Read hw-computed remainder */
1092 val1 = gpmc_read_reg(reg + 0);
1093 val2 = gpmc_read_reg(reg + 4);
1094 val3 = gpmc_read_reg(reg + 8);
1095 val4 = gpmc_read_reg(reg + 12);
1096
1097 /*
1098 * Add constant polynomial to remainder, in order to get an ecc
1099 * sequence of 0xFFs for a buffer filled with 0xFFs.
1100 */
1101 *ecc++ = 0xef ^ (val4 & 0xFF);
1102 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1103 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1104 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1105 *ecc++ = 0xed ^ (val3 & 0xFF);
1106 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1107 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1108 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1109 *ecc++ = 0x97 ^ (val2 & 0xFF);
1110 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1111 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1112 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1113 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1114 }
1115
1116 gpmc_ecc_used = -EINVAL;
1117 return 0;
1118}
1119EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1120
1121#endif /* CONFIG_ARCH_OMAP3 */
1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/irq.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/ioport.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_mtd.h>
31#include <linux/of_device.h>
32#include <linux/mtd/nand.h>
33#include <linux/pm_runtime.h>
34
35#include <linux/platform_data/mtd-nand-omap2.h>
36
37#include <asm/mach-types.h>
38
39#include "soc.h"
40#include "common.h"
41#include "omap_device.h"
42#include "gpmc.h"
43#include "gpmc-nand.h"
44#include "gpmc-onenand.h"
45
46#define DEVICE_NAME "omap-gpmc"
47
48/* GPMC register offsets */
49#define GPMC_REVISION 0x00
50#define GPMC_SYSCONFIG 0x10
51#define GPMC_SYSSTATUS 0x14
52#define GPMC_IRQSTATUS 0x18
53#define GPMC_IRQENABLE 0x1c
54#define GPMC_TIMEOUT_CONTROL 0x40
55#define GPMC_ERR_ADDRESS 0x44
56#define GPMC_ERR_TYPE 0x48
57#define GPMC_CONFIG 0x50
58#define GPMC_STATUS 0x54
59#define GPMC_PREFETCH_CONFIG1 0x1e0
60#define GPMC_PREFETCH_CONFIG2 0x1e4
61#define GPMC_PREFETCH_CONTROL 0x1ec
62#define GPMC_PREFETCH_STATUS 0x1f0
63#define GPMC_ECC_CONFIG 0x1f4
64#define GPMC_ECC_CONTROL 0x1f8
65#define GPMC_ECC_SIZE_CONFIG 0x1fc
66#define GPMC_ECC1_RESULT 0x200
67#define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
68#define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
69#define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
70#define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
71
72/* GPMC ECC control settings */
73#define GPMC_ECC_CTRL_ECCCLEAR 0x100
74#define GPMC_ECC_CTRL_ECCDISABLE 0x000
75#define GPMC_ECC_CTRL_ECCREG1 0x001
76#define GPMC_ECC_CTRL_ECCREG2 0x002
77#define GPMC_ECC_CTRL_ECCREG3 0x003
78#define GPMC_ECC_CTRL_ECCREG4 0x004
79#define GPMC_ECC_CTRL_ECCREG5 0x005
80#define GPMC_ECC_CTRL_ECCREG6 0x006
81#define GPMC_ECC_CTRL_ECCREG7 0x007
82#define GPMC_ECC_CTRL_ECCREG8 0x008
83#define GPMC_ECC_CTRL_ECCREG9 0x009
84
85#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88#define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89#define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90#define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91
92#define GPMC_CS0_OFFSET 0x60
93#define GPMC_CS_SIZE 0x30
94#define GPMC_BCH_SIZE 0x10
95
96#define GPMC_MEM_END 0x3FFFFFFF
97
98#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99#define GPMC_SECTION_SHIFT 28 /* 128 MB */
100
101#define CS_NUM_SHIFT 24
102#define ENABLE_PREFETCH (0x1 << 7)
103#define DMA_MPU_MODE 2
104
105#define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106#define GPMC_REVISION_MINOR(l) (l & 0xf)
107
108#define GPMC_HAS_WR_ACCESS 0x1
109#define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110#define GPMC_HAS_MUX_AAD 0x4
111
112#define GPMC_NR_WAITPINS 4
113
114/* XXX: Only NAND irq has been considered,currently these are the only ones used
115 */
116#define GPMC_NR_IRQ 2
117
118struct gpmc_client_irq {
119 unsigned irq;
120 u32 bitmask;
121};
122
123/* Structure to save gpmc cs context */
124struct gpmc_cs_config {
125 u32 config1;
126 u32 config2;
127 u32 config3;
128 u32 config4;
129 u32 config5;
130 u32 config6;
131 u32 config7;
132 int is_valid;
133};
134
135/*
136 * Structure to save/restore gpmc context
137 * to support core off on OMAP3
138 */
139struct omap3_gpmc_regs {
140 u32 sysconfig;
141 u32 irqenable;
142 u32 timeout_ctrl;
143 u32 config;
144 u32 prefetch_config1;
145 u32 prefetch_config2;
146 u32 prefetch_control;
147 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
148};
149
150static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
151static struct irq_chip gpmc_irq_chip;
152static int gpmc_irq_start;
153
154static struct resource gpmc_mem_root;
155static struct resource gpmc_cs_mem[GPMC_CS_NUM];
156static DEFINE_SPINLOCK(gpmc_mem_lock);
157/* Define chip-selects as reserved by default until probe completes */
158static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
159static unsigned int gpmc_cs_num = GPMC_CS_NUM;
160static unsigned int gpmc_nr_waitpins;
161static struct device *gpmc_dev;
162static int gpmc_irq;
163static resource_size_t phys_base, mem_size;
164static unsigned gpmc_capability;
165static void __iomem *gpmc_base;
166
167static struct clk *gpmc_l3_clk;
168
169static irqreturn_t gpmc_handle_irq(int irq, void *dev);
170
171static void gpmc_write_reg(int idx, u32 val)
172{
173 __raw_writel(val, gpmc_base + idx);
174}
175
176static u32 gpmc_read_reg(int idx)
177{
178 return __raw_readl(gpmc_base + idx);
179}
180
181void gpmc_cs_write_reg(int cs, int idx, u32 val)
182{
183 void __iomem *reg_addr;
184
185 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
186 __raw_writel(val, reg_addr);
187}
188
189static u32 gpmc_cs_read_reg(int cs, int idx)
190{
191 void __iomem *reg_addr;
192
193 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
194 return __raw_readl(reg_addr);
195}
196
197/* TODO: Add support for gpmc_fck to clock framework and use it */
198static unsigned long gpmc_get_fclk_period(void)
199{
200 unsigned long rate = clk_get_rate(gpmc_l3_clk);
201
202 if (rate == 0) {
203 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
204 return 0;
205 }
206
207 rate /= 1000;
208 rate = 1000000000 / rate; /* In picoseconds */
209
210 return rate;
211}
212
213static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
214{
215 unsigned long tick_ps;
216
217 /* Calculate in picosecs to yield more exact results */
218 tick_ps = gpmc_get_fclk_period();
219
220 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
221}
222
223static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
224{
225 unsigned long tick_ps;
226
227 /* Calculate in picosecs to yield more exact results */
228 tick_ps = gpmc_get_fclk_period();
229
230 return (time_ps + tick_ps - 1) / tick_ps;
231}
232
233unsigned int gpmc_ticks_to_ns(unsigned int ticks)
234{
235 return ticks * gpmc_get_fclk_period() / 1000;
236}
237
238static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
239{
240 return ticks * gpmc_get_fclk_period();
241}
242
243static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
244{
245 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
246
247 return ticks * gpmc_get_fclk_period();
248}
249
250static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
251{
252 u32 l;
253
254 l = gpmc_cs_read_reg(cs, reg);
255 if (value)
256 l |= mask;
257 else
258 l &= ~mask;
259 gpmc_cs_write_reg(cs, reg, l);
260}
261
262static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
263{
264 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
265 GPMC_CONFIG1_TIME_PARA_GRAN,
266 p->time_para_granularity);
267 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
268 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
270 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
272 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
274 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
275 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
276 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
277 p->cycle2cyclesamecsen);
278 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
279 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
280 p->cycle2cyclediffcsen);
281}
282
283#ifdef DEBUG
284static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
285 int time, const char *name)
286#else
287static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
288 int time)
289#endif
290{
291 u32 l;
292 int ticks, mask, nr_bits;
293
294 if (time == 0)
295 ticks = 0;
296 else
297 ticks = gpmc_ns_to_ticks(time);
298 nr_bits = end_bit - st_bit + 1;
299 if (ticks >= 1 << nr_bits) {
300#ifdef DEBUG
301 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
302 cs, name, time, ticks, 1 << nr_bits);
303#endif
304 return -1;
305 }
306
307 mask = (1 << nr_bits) - 1;
308 l = gpmc_cs_read_reg(cs, reg);
309#ifdef DEBUG
310 printk(KERN_INFO
311 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
312 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
313 (l >> st_bit) & mask, time);
314#endif
315 l &= ~(mask << st_bit);
316 l |= ticks << st_bit;
317 gpmc_cs_write_reg(cs, reg, l);
318
319 return 0;
320}
321
322#ifdef DEBUG
323#define GPMC_SET_ONE(reg, st, end, field) \
324 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
325 t->field, #field) < 0) \
326 return -1
327#else
328#define GPMC_SET_ONE(reg, st, end, field) \
329 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
330 return -1
331#endif
332
333int gpmc_calc_divider(unsigned int sync_clk)
334{
335 int div;
336 u32 l;
337
338 l = sync_clk + (gpmc_get_fclk_period() - 1);
339 div = l / gpmc_get_fclk_period();
340 if (div > 4)
341 return -1;
342 if (div <= 0)
343 div = 1;
344
345 return div;
346}
347
348int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
349{
350 int div;
351 u32 l;
352
353 div = gpmc_calc_divider(t->sync_clk);
354 if (div < 0)
355 return div;
356
357 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
358 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
360
361 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
362 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
364
365 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
366 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
369
370 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
371 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
373
374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
375
376 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
377 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
378
379 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
380 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
381
382 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
383 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
384 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
386
387 /* caller is expected to have initialized CONFIG1 to cover
388 * at least sync vs async
389 */
390 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
391 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
392#ifdef DEBUG
393 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
394 cs, (div * gpmc_get_fclk_period()) / 1000, div);
395#endif
396 l &= ~0x03;
397 l |= (div - 1);
398 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
399 }
400
401 gpmc_cs_bool_timings(cs, &t->bool_timings);
402
403 return 0;
404}
405
406static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
407{
408 u32 l;
409 u32 mask;
410
411 /*
412 * Ensure that base address is aligned on a
413 * boundary equal to or greater than size.
414 */
415 if (base & (size - 1))
416 return -EINVAL;
417
418 mask = (1 << GPMC_SECTION_SHIFT) - size;
419 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
420 l &= ~0x3f;
421 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
422 l &= ~(0x0f << 8);
423 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
424 l |= GPMC_CONFIG7_CSVALID;
425 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
426
427 return 0;
428}
429
430static void gpmc_cs_disable_mem(int cs)
431{
432 u32 l;
433
434 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
435 l &= ~GPMC_CONFIG7_CSVALID;
436 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
437}
438
439static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
440{
441 u32 l;
442 u32 mask;
443
444 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
445 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
446 mask = (l >> 8) & 0x0f;
447 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
448}
449
450static int gpmc_cs_mem_enabled(int cs)
451{
452 u32 l;
453
454 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
455 return l & GPMC_CONFIG7_CSVALID;
456}
457
458static void gpmc_cs_set_reserved(int cs, int reserved)
459{
460 gpmc_cs_map &= ~(1 << cs);
461 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
462}
463
464static bool gpmc_cs_reserved(int cs)
465{
466 return gpmc_cs_map & (1 << cs);
467}
468
469static unsigned long gpmc_mem_align(unsigned long size)
470{
471 int order;
472
473 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
474 order = GPMC_CHUNK_SHIFT - 1;
475 do {
476 size >>= 1;
477 order++;
478 } while (size);
479 size = 1 << order;
480 return size;
481}
482
483static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
484{
485 struct resource *res = &gpmc_cs_mem[cs];
486 int r;
487
488 size = gpmc_mem_align(size);
489 spin_lock(&gpmc_mem_lock);
490 res->start = base;
491 res->end = base + size - 1;
492 r = request_resource(&gpmc_mem_root, res);
493 spin_unlock(&gpmc_mem_lock);
494
495 return r;
496}
497
498static int gpmc_cs_delete_mem(int cs)
499{
500 struct resource *res = &gpmc_cs_mem[cs];
501 int r;
502
503 spin_lock(&gpmc_mem_lock);
504 r = release_resource(res);
505 res->start = 0;
506 res->end = 0;
507 spin_unlock(&gpmc_mem_lock);
508
509 return r;
510}
511
512/**
513 * gpmc_cs_remap - remaps a chip-select physical base address
514 * @cs: chip-select to remap
515 * @base: physical base address to re-map chip-select to
516 *
517 * Re-maps a chip-select to a new physical base address specified by
518 * "base". Returns 0 on success and appropriate negative error code
519 * on failure.
520 */
521static int gpmc_cs_remap(int cs, u32 base)
522{
523 int ret;
524 u32 old_base, size;
525
526 if (cs > gpmc_cs_num) {
527 pr_err("%s: requested chip-select is disabled\n", __func__);
528 return -ENODEV;
529 }
530
531 /*
532 * Make sure we ignore any device offsets from the GPMC partition
533 * allocated for the chip select and that the new base confirms
534 * to the GPMC 16MB minimum granularity.
535 */
536 base &= ~(SZ_16M - 1);
537
538 gpmc_cs_get_memconf(cs, &old_base, &size);
539 if (base == old_base)
540 return 0;
541 gpmc_cs_disable_mem(cs);
542 ret = gpmc_cs_delete_mem(cs);
543 if (ret < 0)
544 return ret;
545 ret = gpmc_cs_insert_mem(cs, base, size);
546 if (ret < 0)
547 return ret;
548 ret = gpmc_cs_enable_mem(cs, base, size);
549 if (ret < 0)
550 return ret;
551
552 return 0;
553}
554
555int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
556{
557 struct resource *res = &gpmc_cs_mem[cs];
558 int r = -1;
559
560 if (cs > gpmc_cs_num) {
561 pr_err("%s: requested chip-select is disabled\n", __func__);
562 return -ENODEV;
563 }
564 size = gpmc_mem_align(size);
565 if (size > (1 << GPMC_SECTION_SHIFT))
566 return -ENOMEM;
567
568 spin_lock(&gpmc_mem_lock);
569 if (gpmc_cs_reserved(cs)) {
570 r = -EBUSY;
571 goto out;
572 }
573 if (gpmc_cs_mem_enabled(cs))
574 r = adjust_resource(res, res->start & ~(size - 1), size);
575 if (r < 0)
576 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
577 size, NULL, NULL);
578 if (r < 0)
579 goto out;
580
581 r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
582 if (r < 0) {
583 release_resource(res);
584 goto out;
585 }
586
587 *base = res->start;
588 gpmc_cs_set_reserved(cs, 1);
589out:
590 spin_unlock(&gpmc_mem_lock);
591 return r;
592}
593EXPORT_SYMBOL(gpmc_cs_request);
594
595void gpmc_cs_free(int cs)
596{
597 struct resource *res = &gpmc_cs_mem[cs];
598
599 spin_lock(&gpmc_mem_lock);
600 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
601 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
602 BUG();
603 spin_unlock(&gpmc_mem_lock);
604 return;
605 }
606 gpmc_cs_disable_mem(cs);
607 if (res->flags)
608 release_resource(res);
609 gpmc_cs_set_reserved(cs, 0);
610 spin_unlock(&gpmc_mem_lock);
611}
612EXPORT_SYMBOL(gpmc_cs_free);
613
614/**
615 * gpmc_configure - write request to configure gpmc
616 * @cmd: command type
617 * @wval: value to write
618 * @return status of the operation
619 */
620int gpmc_configure(int cmd, int wval)
621{
622 u32 regval;
623
624 switch (cmd) {
625 case GPMC_ENABLE_IRQ:
626 gpmc_write_reg(GPMC_IRQENABLE, wval);
627 break;
628
629 case GPMC_SET_IRQ_STATUS:
630 gpmc_write_reg(GPMC_IRQSTATUS, wval);
631 break;
632
633 case GPMC_CONFIG_WP:
634 regval = gpmc_read_reg(GPMC_CONFIG);
635 if (wval)
636 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
637 else
638 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
639 gpmc_write_reg(GPMC_CONFIG, regval);
640 break;
641
642 default:
643 pr_err("%s: command not supported\n", __func__);
644 return -EINVAL;
645 }
646
647 return 0;
648}
649EXPORT_SYMBOL(gpmc_configure);
650
651void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
652{
653 int i;
654
655 reg->gpmc_status = gpmc_base + GPMC_STATUS;
656 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
657 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
658 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
659 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
660 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
661 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
662 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
663 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
664 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
665 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
666 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
667 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
668 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
669 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
670
671 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
672 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
673 GPMC_BCH_SIZE * i;
674 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
675 GPMC_BCH_SIZE * i;
676 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
677 GPMC_BCH_SIZE * i;
678 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
679 GPMC_BCH_SIZE * i;
680 }
681}
682
683int gpmc_get_client_irq(unsigned irq_config)
684{
685 int i;
686
687 if (hweight32(irq_config) > 1)
688 return 0;
689
690 for (i = 0; i < GPMC_NR_IRQ; i++)
691 if (gpmc_client_irq[i].bitmask & irq_config)
692 return gpmc_client_irq[i].irq;
693
694 return 0;
695}
696
697static int gpmc_irq_endis(unsigned irq, bool endis)
698{
699 int i;
700 u32 regval;
701
702 for (i = 0; i < GPMC_NR_IRQ; i++)
703 if (irq == gpmc_client_irq[i].irq) {
704 regval = gpmc_read_reg(GPMC_IRQENABLE);
705 if (endis)
706 regval |= gpmc_client_irq[i].bitmask;
707 else
708 regval &= ~gpmc_client_irq[i].bitmask;
709 gpmc_write_reg(GPMC_IRQENABLE, regval);
710 break;
711 }
712
713 return 0;
714}
715
716static void gpmc_irq_disable(struct irq_data *p)
717{
718 gpmc_irq_endis(p->irq, false);
719}
720
721static void gpmc_irq_enable(struct irq_data *p)
722{
723 gpmc_irq_endis(p->irq, true);
724}
725
726static void gpmc_irq_noop(struct irq_data *data) { }
727
728static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
729
730static int gpmc_setup_irq(void)
731{
732 int i;
733 u32 regval;
734
735 if (!gpmc_irq)
736 return -EINVAL;
737
738 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
739 if (gpmc_irq_start < 0) {
740 pr_err("irq_alloc_descs failed\n");
741 return gpmc_irq_start;
742 }
743
744 gpmc_irq_chip.name = "gpmc";
745 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
746 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
747 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
748 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
749 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
750 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
751 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
752
753 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
754 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
755
756 for (i = 0; i < GPMC_NR_IRQ; i++) {
757 gpmc_client_irq[i].irq = gpmc_irq_start + i;
758 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
759 &gpmc_irq_chip, handle_simple_irq);
760 set_irq_flags(gpmc_client_irq[i].irq,
761 IRQF_VALID | IRQF_NOAUTOEN);
762 }
763
764 /* Disable interrupts */
765 gpmc_write_reg(GPMC_IRQENABLE, 0);
766
767 /* clear interrupts */
768 regval = gpmc_read_reg(GPMC_IRQSTATUS);
769 gpmc_write_reg(GPMC_IRQSTATUS, regval);
770
771 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
772}
773
774static int gpmc_free_irq(void)
775{
776 int i;
777
778 if (gpmc_irq)
779 free_irq(gpmc_irq, NULL);
780
781 for (i = 0; i < GPMC_NR_IRQ; i++) {
782 irq_set_handler(gpmc_client_irq[i].irq, NULL);
783 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
784 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
785 }
786
787 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
788
789 return 0;
790}
791
792static void gpmc_mem_exit(void)
793{
794 int cs;
795
796 for (cs = 0; cs < gpmc_cs_num; cs++) {
797 if (!gpmc_cs_mem_enabled(cs))
798 continue;
799 gpmc_cs_delete_mem(cs);
800 }
801
802}
803
804static void gpmc_mem_init(void)
805{
806 int cs;
807
808 /*
809 * The first 1MB of GPMC address space is typically mapped to
810 * the internal ROM. Never allocate the first page, to
811 * facilitate bug detection; even if we didn't boot from ROM.
812 */
813 gpmc_mem_root.start = SZ_1M;
814 gpmc_mem_root.end = GPMC_MEM_END;
815
816 /* Reserve all regions that has been set up by bootloader */
817 for (cs = 0; cs < gpmc_cs_num; cs++) {
818 u32 base, size;
819
820 if (!gpmc_cs_mem_enabled(cs))
821 continue;
822 gpmc_cs_get_memconf(cs, &base, &size);
823 if (gpmc_cs_insert_mem(cs, base, size)) {
824 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
825 __func__, cs, base, base + size);
826 gpmc_cs_disable_mem(cs);
827 }
828 }
829}
830
831static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
832{
833 u32 temp;
834 int div;
835
836 div = gpmc_calc_divider(sync_clk);
837 temp = gpmc_ps_to_ticks(time_ps);
838 temp = (temp + div - 1) / div;
839 return gpmc_ticks_to_ps(temp * div);
840}
841
842/* XXX: can the cycles be avoided ? */
843static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
844 struct gpmc_device_timings *dev_t,
845 bool mux)
846{
847 u32 temp;
848
849 /* adv_rd_off */
850 temp = dev_t->t_avdp_r;
851 /* XXX: mux check required ? */
852 if (mux) {
853 /* XXX: t_avdp not to be required for sync, only added for tusb
854 * this indirectly necessitates requirement of t_avdp_r and
855 * t_avdp_w instead of having a single t_avdp
856 */
857 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
858 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
859 }
860 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
861
862 /* oe_on */
863 temp = dev_t->t_oeasu; /* XXX: remove this ? */
864 if (mux) {
865 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
866 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
867 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
868 }
869 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
870
871 /* access */
872 /* XXX: any scope for improvement ?, by combining oe_on
873 * and clk_activation, need to check whether
874 * access = clk_activation + round to sync clk ?
875 */
876 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
877 temp += gpmc_t->clk_activation;
878 if (dev_t->cyc_oe)
879 temp = max_t(u32, temp, gpmc_t->oe_on +
880 gpmc_ticks_to_ps(dev_t->cyc_oe));
881 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
882
883 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
884 gpmc_t->cs_rd_off = gpmc_t->oe_off;
885
886 /* rd_cycle */
887 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
888 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
889 gpmc_t->access;
890 /* XXX: barter t_ce_rdyz with t_cez_r ? */
891 if (dev_t->t_ce_rdyz)
892 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
893 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
894
895 return 0;
896}
897
898static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
899 struct gpmc_device_timings *dev_t,
900 bool mux)
901{
902 u32 temp;
903
904 /* adv_wr_off */
905 temp = dev_t->t_avdp_w;
906 if (mux) {
907 temp = max_t(u32, temp,
908 gpmc_t->clk_activation + dev_t->t_avdh);
909 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
910 }
911 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
912
913 /* wr_data_mux_bus */
914 temp = max_t(u32, dev_t->t_weasu,
915 gpmc_t->clk_activation + dev_t->t_rdyo);
916 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
917 * and in that case remember to handle we_on properly
918 */
919 if (mux) {
920 temp = max_t(u32, temp,
921 gpmc_t->adv_wr_off + dev_t->t_aavdh);
922 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
923 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
924 }
925 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
926
927 /* we_on */
928 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
929 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
930 else
931 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
932
933 /* wr_access */
934 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
935 gpmc_t->wr_access = gpmc_t->access;
936
937 /* we_off */
938 temp = gpmc_t->we_on + dev_t->t_wpl;
939 temp = max_t(u32, temp,
940 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
941 temp = max_t(u32, temp,
942 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
943 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
944
945 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
946 dev_t->t_wph);
947
948 /* wr_cycle */
949 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
950 temp += gpmc_t->wr_access;
951 /* XXX: barter t_ce_rdyz with t_cez_w ? */
952 if (dev_t->t_ce_rdyz)
953 temp = max_t(u32, temp,
954 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
955 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
956
957 return 0;
958}
959
960static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
961 struct gpmc_device_timings *dev_t,
962 bool mux)
963{
964 u32 temp;
965
966 /* adv_rd_off */
967 temp = dev_t->t_avdp_r;
968 if (mux)
969 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
970 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
971
972 /* oe_on */
973 temp = dev_t->t_oeasu;
974 if (mux)
975 temp = max_t(u32, temp,
976 gpmc_t->adv_rd_off + dev_t->t_aavdh);
977 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
978
979 /* access */
980 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
981 gpmc_t->oe_on + dev_t->t_oe);
982 temp = max_t(u32, temp,
983 gpmc_t->cs_on + dev_t->t_ce);
984 temp = max_t(u32, temp,
985 gpmc_t->adv_on + dev_t->t_aa);
986 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
987
988 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
989 gpmc_t->cs_rd_off = gpmc_t->oe_off;
990
991 /* rd_cycle */
992 temp = max_t(u32, dev_t->t_rd_cycle,
993 gpmc_t->cs_rd_off + dev_t->t_cez_r);
994 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
995 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
996
997 return 0;
998}
999
1000static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1001 struct gpmc_device_timings *dev_t,
1002 bool mux)
1003{
1004 u32 temp;
1005
1006 /* adv_wr_off */
1007 temp = dev_t->t_avdp_w;
1008 if (mux)
1009 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1010 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1011
1012 /* wr_data_mux_bus */
1013 temp = dev_t->t_weasu;
1014 if (mux) {
1015 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1016 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1017 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1018 }
1019 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1020
1021 /* we_on */
1022 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1023 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1024 else
1025 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1026
1027 /* we_off */
1028 temp = gpmc_t->we_on + dev_t->t_wpl;
1029 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1030
1031 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1032 dev_t->t_wph);
1033
1034 /* wr_cycle */
1035 temp = max_t(u32, dev_t->t_wr_cycle,
1036 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1037 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1038
1039 return 0;
1040}
1041
1042static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1043 struct gpmc_device_timings *dev_t)
1044{
1045 u32 temp;
1046
1047 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1048 gpmc_get_fclk_period();
1049
1050 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1051 dev_t->t_bacc,
1052 gpmc_t->sync_clk);
1053
1054 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1055 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1056
1057 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1058 return 0;
1059
1060 if (dev_t->ce_xdelay)
1061 gpmc_t->bool_timings.cs_extra_delay = true;
1062 if (dev_t->avd_xdelay)
1063 gpmc_t->bool_timings.adv_extra_delay = true;
1064 if (dev_t->oe_xdelay)
1065 gpmc_t->bool_timings.oe_extra_delay = true;
1066 if (dev_t->we_xdelay)
1067 gpmc_t->bool_timings.we_extra_delay = true;
1068
1069 return 0;
1070}
1071
1072static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1073 struct gpmc_device_timings *dev_t,
1074 bool sync)
1075{
1076 u32 temp;
1077
1078 /* cs_on */
1079 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1080
1081 /* adv_on */
1082 temp = dev_t->t_avdasu;
1083 if (dev_t->t_ce_avd)
1084 temp = max_t(u32, temp,
1085 gpmc_t->cs_on + dev_t->t_ce_avd);
1086 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1087
1088 if (sync)
1089 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1090
1091 return 0;
1092}
1093
1094/* TODO: remove this function once all peripherals are confirmed to
1095 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1096 * has to be modified to handle timings in ps instead of ns
1097*/
1098static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1099{
1100 t->cs_on /= 1000;
1101 t->cs_rd_off /= 1000;
1102 t->cs_wr_off /= 1000;
1103 t->adv_on /= 1000;
1104 t->adv_rd_off /= 1000;
1105 t->adv_wr_off /= 1000;
1106 t->we_on /= 1000;
1107 t->we_off /= 1000;
1108 t->oe_on /= 1000;
1109 t->oe_off /= 1000;
1110 t->page_burst_access /= 1000;
1111 t->access /= 1000;
1112 t->rd_cycle /= 1000;
1113 t->wr_cycle /= 1000;
1114 t->bus_turnaround /= 1000;
1115 t->cycle2cycle_delay /= 1000;
1116 t->wait_monitoring /= 1000;
1117 t->clk_activation /= 1000;
1118 t->wr_access /= 1000;
1119 t->wr_data_mux_bus /= 1000;
1120}
1121
1122int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1123 struct gpmc_settings *gpmc_s,
1124 struct gpmc_device_timings *dev_t)
1125{
1126 bool mux = false, sync = false;
1127
1128 if (gpmc_s) {
1129 mux = gpmc_s->mux_add_data ? true : false;
1130 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1131 }
1132
1133 memset(gpmc_t, 0, sizeof(*gpmc_t));
1134
1135 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1136
1137 if (gpmc_s && gpmc_s->sync_read)
1138 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1139 else
1140 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1141
1142 if (gpmc_s && gpmc_s->sync_write)
1143 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1144 else
1145 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1146
1147 /* TODO: remove, see function definition */
1148 gpmc_convert_ps_to_ns(gpmc_t);
1149
1150 return 0;
1151}
1152
1153/**
1154 * gpmc_cs_program_settings - programs non-timing related settings
1155 * @cs: GPMC chip-select to program
1156 * @p: pointer to GPMC settings structure
1157 *
1158 * Programs non-timing related settings for a GPMC chip-select, such as
1159 * bus-width, burst configuration, etc. Function should be called once
1160 * for each chip-select that is being used and must be called before
1161 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1162 * register will be initialised to zero by this function. Returns 0 on
1163 * success and appropriate negative error code on failure.
1164 */
1165int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1166{
1167 u32 config1;
1168
1169 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1170 pr_err("%s: invalid width %d!", __func__, p->device_width);
1171 return -EINVAL;
1172 }
1173
1174 /* Address-data multiplexing not supported for NAND devices */
1175 if (p->device_nand && p->mux_add_data) {
1176 pr_err("%s: invalid configuration!\n", __func__);
1177 return -EINVAL;
1178 }
1179
1180 if ((p->mux_add_data > GPMC_MUX_AD) ||
1181 ((p->mux_add_data == GPMC_MUX_AAD) &&
1182 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1183 pr_err("%s: invalid multiplex configuration!\n", __func__);
1184 return -EINVAL;
1185 }
1186
1187 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1188 if (p->burst_read || p->burst_write) {
1189 switch (p->burst_len) {
1190 case GPMC_BURST_4:
1191 case GPMC_BURST_8:
1192 case GPMC_BURST_16:
1193 break;
1194 default:
1195 pr_err("%s: invalid page/burst-length (%d)\n",
1196 __func__, p->burst_len);
1197 return -EINVAL;
1198 }
1199 }
1200
1201 if ((p->wait_on_read || p->wait_on_write) &&
1202 (p->wait_pin > gpmc_nr_waitpins)) {
1203 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1204 return -EINVAL;
1205 }
1206
1207 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1208
1209 if (p->sync_read)
1210 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1211 if (p->sync_write)
1212 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1213 if (p->wait_on_read)
1214 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1215 if (p->wait_on_write)
1216 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1217 if (p->wait_on_read || p->wait_on_write)
1218 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1219 if (p->device_nand)
1220 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1221 if (p->mux_add_data)
1222 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1223 if (p->burst_read)
1224 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1225 if (p->burst_write)
1226 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1227 if (p->burst_read || p->burst_write) {
1228 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1229 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1230 }
1231
1232 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1233
1234 return 0;
1235}
1236
1237#ifdef CONFIG_OF
1238static struct of_device_id gpmc_dt_ids[] = {
1239 { .compatible = "ti,omap2420-gpmc" },
1240 { .compatible = "ti,omap2430-gpmc" },
1241 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1242 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1243 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1244 { }
1245};
1246MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1247
1248/**
1249 * gpmc_read_settings_dt - read gpmc settings from device-tree
1250 * @np: pointer to device-tree node for a gpmc child device
1251 * @p: pointer to gpmc settings structure
1252 *
1253 * Reads the GPMC settings for a GPMC child device from device-tree and
1254 * stores them in the GPMC settings structure passed. The GPMC settings
1255 * structure is initialised to zero by this function and so any
1256 * previously stored settings will be cleared.
1257 */
1258void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1259{
1260 memset(p, 0, sizeof(struct gpmc_settings));
1261
1262 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1263 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1264 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1265 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1266
1267 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1268 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1269 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1270 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1271 if (!p->burst_read && !p->burst_write)
1272 pr_warn("%s: page/burst-length set but not used!\n",
1273 __func__);
1274 }
1275
1276 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1277 p->wait_on_read = of_property_read_bool(np,
1278 "gpmc,wait-on-read");
1279 p->wait_on_write = of_property_read_bool(np,
1280 "gpmc,wait-on-write");
1281 if (!p->wait_on_read && !p->wait_on_write)
1282 pr_warn("%s: read/write wait monitoring not enabled!\n",
1283 __func__);
1284 }
1285}
1286
1287static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1288 struct gpmc_timings *gpmc_t)
1289{
1290 struct gpmc_bool_timings *p;
1291
1292 if (!np || !gpmc_t)
1293 return;
1294
1295 memset(gpmc_t, 0, sizeof(*gpmc_t));
1296
1297 /* minimum clock period for syncronous mode */
1298 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1299
1300 /* chip select timtings */
1301 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1302 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1303 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1304
1305 /* ADV signal timings */
1306 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1307 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1308 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1309
1310 /* WE signal timings */
1311 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1312 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1313
1314 /* OE signal timings */
1315 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1316 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1317
1318 /* access and cycle timings */
1319 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1320 &gpmc_t->page_burst_access);
1321 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1322 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1323 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1324 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1325 &gpmc_t->bus_turnaround);
1326 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1327 &gpmc_t->cycle2cycle_delay);
1328 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1329 &gpmc_t->wait_monitoring);
1330 of_property_read_u32(np, "gpmc,clk-activation-ns",
1331 &gpmc_t->clk_activation);
1332
1333 /* only applicable to OMAP3+ */
1334 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1335 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1336 &gpmc_t->wr_data_mux_bus);
1337
1338 /* bool timing parameters */
1339 p = &gpmc_t->bool_timings;
1340
1341 p->cycle2cyclediffcsen =
1342 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1343 p->cycle2cyclesamecsen =
1344 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1345 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1346 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1347 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1348 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1349 p->time_para_granularity =
1350 of_property_read_bool(np, "gpmc,time-para-granularity");
1351}
1352
1353#if IS_ENABLED(CONFIG_MTD_NAND)
1354
1355static const char * const nand_xfer_types[] = {
1356 [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled",
1357 [NAND_OMAP_POLLED] = "polled",
1358 [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma",
1359 [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq",
1360};
1361
1362static int gpmc_probe_nand_child(struct platform_device *pdev,
1363 struct device_node *child)
1364{
1365 u32 val;
1366 const char *s;
1367 struct gpmc_timings gpmc_t;
1368 struct omap_nand_platform_data *gpmc_nand_data;
1369
1370 if (of_property_read_u32(child, "reg", &val) < 0) {
1371 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1372 child->full_name);
1373 return -ENODEV;
1374 }
1375
1376 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1377 GFP_KERNEL);
1378 if (!gpmc_nand_data)
1379 return -ENOMEM;
1380
1381 gpmc_nand_data->cs = val;
1382 gpmc_nand_data->of_node = child;
1383
1384 /* Detect availability of ELM module */
1385 gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1386 if (gpmc_nand_data->elm_of_node == NULL)
1387 gpmc_nand_data->elm_of_node =
1388 of_parse_phandle(child, "elm_id", 0);
1389 if (gpmc_nand_data->elm_of_node == NULL)
1390 pr_warn("%s: ti,elm-id property not found\n", __func__);
1391
1392 /* select ecc-scheme for NAND */
1393 if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1394 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1395 return -ENODEV;
1396 }
1397 if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
1398 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1399 gpmc_nand_data->ecc_opt =
1400 OMAP_ECC_HAM1_CODE_HW;
1401 else if (!strcmp(s, "bch4"))
1402 if (gpmc_nand_data->elm_of_node)
1403 gpmc_nand_data->ecc_opt =
1404 OMAP_ECC_BCH4_CODE_HW;
1405 else
1406 gpmc_nand_data->ecc_opt =
1407 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1408 else if (!strcmp(s, "bch8"))
1409 if (gpmc_nand_data->elm_of_node)
1410 gpmc_nand_data->ecc_opt =
1411 OMAP_ECC_BCH8_CODE_HW;
1412 else
1413 gpmc_nand_data->ecc_opt =
1414 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1415 else
1416 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1417
1418 /* select data transfer mode for NAND controller */
1419 if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1420 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1421 if (!strcasecmp(s, nand_xfer_types[val])) {
1422 gpmc_nand_data->xfer_type = val;
1423 break;
1424 }
1425
1426 val = of_get_nand_bus_width(child);
1427 if (val == 16)
1428 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1429
1430 gpmc_read_timings_dt(child, &gpmc_t);
1431 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1432
1433 return 0;
1434}
1435#else
1436static int gpmc_probe_nand_child(struct platform_device *pdev,
1437 struct device_node *child)
1438{
1439 return 0;
1440}
1441#endif
1442
1443#if IS_ENABLED(CONFIG_MTD_ONENAND)
1444static int gpmc_probe_onenand_child(struct platform_device *pdev,
1445 struct device_node *child)
1446{
1447 u32 val;
1448 struct omap_onenand_platform_data *gpmc_onenand_data;
1449
1450 if (of_property_read_u32(child, "reg", &val) < 0) {
1451 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1452 child->full_name);
1453 return -ENODEV;
1454 }
1455
1456 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1457 GFP_KERNEL);
1458 if (!gpmc_onenand_data)
1459 return -ENOMEM;
1460
1461 gpmc_onenand_data->cs = val;
1462 gpmc_onenand_data->of_node = child;
1463 gpmc_onenand_data->dma_channel = -1;
1464
1465 if (!of_property_read_u32(child, "dma-channel", &val))
1466 gpmc_onenand_data->dma_channel = val;
1467
1468 gpmc_onenand_init(gpmc_onenand_data);
1469
1470 return 0;
1471}
1472#else
1473static int gpmc_probe_onenand_child(struct platform_device *pdev,
1474 struct device_node *child)
1475{
1476 return 0;
1477}
1478#endif
1479
1480/**
1481 * gpmc_probe_generic_child - configures the gpmc for a child device
1482 * @pdev: pointer to gpmc platform device
1483 * @child: pointer to device-tree node for child device
1484 *
1485 * Allocates and configures a GPMC chip-select for a child device.
1486 * Returns 0 on success and appropriate negative error code on failure.
1487 */
1488static int gpmc_probe_generic_child(struct platform_device *pdev,
1489 struct device_node *child)
1490{
1491 struct gpmc_settings gpmc_s;
1492 struct gpmc_timings gpmc_t;
1493 struct resource res;
1494 unsigned long base;
1495 int ret, cs;
1496
1497 if (of_property_read_u32(child, "reg", &cs) < 0) {
1498 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1499 child->full_name);
1500 return -ENODEV;
1501 }
1502
1503 if (of_address_to_resource(child, 0, &res) < 0) {
1504 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1505 child->full_name);
1506 return -ENODEV;
1507 }
1508
1509 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1510 if (ret < 0) {
1511 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1512 return ret;
1513 }
1514
1515 /*
1516 * For some GPMC devices we still need to rely on the bootloader
1517 * timings because the devices can be connected via FPGA. So far
1518 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1519 * REVISIT: Add timing support from slls644g.pdf and from the
1520 * lan91c96 manual.
1521 */
1522 if (of_device_is_compatible(child, "ns16550a") ||
1523 of_device_is_compatible(child, "smsc,lan91c94") ||
1524 of_device_is_compatible(child, "smsc,lan91c111")) {
1525 dev_warn(&pdev->dev,
1526 "%s using bootloader timings on CS%d\n",
1527 child->name, cs);
1528 goto no_timings;
1529 }
1530
1531 /*
1532 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1533 * location in the gpmc address space. When booting with
1534 * device-tree we want the NOR flash to be mapped to the
1535 * location specified in the device-tree blob. So remap the
1536 * CS to this location. Once DT migration is complete should
1537 * just make gpmc_cs_request() map a specific address.
1538 */
1539 ret = gpmc_cs_remap(cs, res.start);
1540 if (ret < 0) {
1541 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1542 cs, &res.start);
1543 goto err;
1544 }
1545
1546 gpmc_read_settings_dt(child, &gpmc_s);
1547
1548 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1549 if (ret < 0)
1550 goto err;
1551
1552 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1553 if (ret < 0)
1554 goto err;
1555
1556 gpmc_read_timings_dt(child, &gpmc_t);
1557 gpmc_cs_set_timings(cs, &gpmc_t);
1558
1559no_timings:
1560 if (of_platform_device_create(child, NULL, &pdev->dev))
1561 return 0;
1562
1563 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1564 ret = -ENODEV;
1565
1566err:
1567 gpmc_cs_free(cs);
1568
1569 return ret;
1570}
1571
1572static int gpmc_probe_dt(struct platform_device *pdev)
1573{
1574 int ret;
1575 struct device_node *child;
1576 const struct of_device_id *of_id =
1577 of_match_device(gpmc_dt_ids, &pdev->dev);
1578
1579 if (!of_id)
1580 return 0;
1581
1582 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
1583 &gpmc_cs_num);
1584 if (ret < 0) {
1585 pr_err("%s: number of chip-selects not defined\n", __func__);
1586 return ret;
1587 } else if (gpmc_cs_num < 1) {
1588 pr_err("%s: all chip-selects are disabled\n", __func__);
1589 return -EINVAL;
1590 } else if (gpmc_cs_num > GPMC_CS_NUM) {
1591 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1592 __func__, GPMC_CS_NUM);
1593 return -EINVAL;
1594 }
1595
1596 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
1597 &gpmc_nr_waitpins);
1598 if (ret < 0) {
1599 pr_err("%s: number of wait pins not found!\n", __func__);
1600 return ret;
1601 }
1602
1603 for_each_child_of_node(pdev->dev.of_node, child) {
1604
1605 if (!child->name)
1606 continue;
1607
1608 if (of_node_cmp(child->name, "nand") == 0)
1609 ret = gpmc_probe_nand_child(pdev, child);
1610 else if (of_node_cmp(child->name, "onenand") == 0)
1611 ret = gpmc_probe_onenand_child(pdev, child);
1612 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1613 of_node_cmp(child->name, "nor") == 0 ||
1614 of_node_cmp(child->name, "uart") == 0)
1615 ret = gpmc_probe_generic_child(pdev, child);
1616
1617 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1618 __func__, child->full_name))
1619 of_node_put(child);
1620 }
1621
1622 return 0;
1623}
1624#else
1625static int gpmc_probe_dt(struct platform_device *pdev)
1626{
1627 return 0;
1628}
1629#endif
1630
1631static int gpmc_probe(struct platform_device *pdev)
1632{
1633 int rc;
1634 u32 l;
1635 struct resource *res;
1636
1637 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1638 if (res == NULL)
1639 return -ENOENT;
1640
1641 phys_base = res->start;
1642 mem_size = resource_size(res);
1643
1644 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1645 if (IS_ERR(gpmc_base))
1646 return PTR_ERR(gpmc_base);
1647
1648 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1649 if (res == NULL)
1650 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1651 else
1652 gpmc_irq = res->start;
1653
1654 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1655 if (IS_ERR(gpmc_l3_clk)) {
1656 dev_err(&pdev->dev, "error: clk_get\n");
1657 gpmc_irq = 0;
1658 return PTR_ERR(gpmc_l3_clk);
1659 }
1660
1661 pm_runtime_enable(&pdev->dev);
1662 pm_runtime_get_sync(&pdev->dev);
1663
1664 gpmc_dev = &pdev->dev;
1665
1666 l = gpmc_read_reg(GPMC_REVISION);
1667
1668 /*
1669 * FIXME: Once device-tree migration is complete the below flags
1670 * should be populated based upon the device-tree compatible
1671 * string. For now just use the IP revision. OMAP3+ devices have
1672 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1673 * devices support the addr-addr-data multiplex protocol.
1674 *
1675 * GPMC IP revisions:
1676 * - OMAP24xx = 2.0
1677 * - OMAP3xxx = 5.0
1678 * - OMAP44xx/54xx/AM335x = 6.0
1679 */
1680 if (GPMC_REVISION_MAJOR(l) > 0x4)
1681 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1682 if (GPMC_REVISION_MAJOR(l) > 0x5)
1683 gpmc_capability |= GPMC_HAS_MUX_AAD;
1684 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1685 GPMC_REVISION_MINOR(l));
1686
1687 gpmc_mem_init();
1688
1689 if (gpmc_setup_irq() < 0)
1690 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1691
1692 /* Now the GPMC is initialised, unreserve the chip-selects */
1693 gpmc_cs_map = 0;
1694
1695 if (!pdev->dev.of_node) {
1696 gpmc_cs_num = GPMC_CS_NUM;
1697 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
1698 }
1699
1700 rc = gpmc_probe_dt(pdev);
1701 if (rc < 0) {
1702 pm_runtime_put_sync(&pdev->dev);
1703 clk_put(gpmc_l3_clk);
1704 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1705 return rc;
1706 }
1707
1708 return 0;
1709}
1710
1711static int gpmc_remove(struct platform_device *pdev)
1712{
1713 gpmc_free_irq();
1714 gpmc_mem_exit();
1715 pm_runtime_put_sync(&pdev->dev);
1716 pm_runtime_disable(&pdev->dev);
1717 gpmc_dev = NULL;
1718 return 0;
1719}
1720
1721#ifdef CONFIG_PM_SLEEP
1722static int gpmc_suspend(struct device *dev)
1723{
1724 omap3_gpmc_save_context();
1725 pm_runtime_put_sync(dev);
1726 return 0;
1727}
1728
1729static int gpmc_resume(struct device *dev)
1730{
1731 pm_runtime_get_sync(dev);
1732 omap3_gpmc_restore_context();
1733 return 0;
1734}
1735#endif
1736
1737static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
1738
1739static struct platform_driver gpmc_driver = {
1740 .probe = gpmc_probe,
1741 .remove = gpmc_remove,
1742 .driver = {
1743 .name = DEVICE_NAME,
1744 .owner = THIS_MODULE,
1745 .of_match_table = of_match_ptr(gpmc_dt_ids),
1746 .pm = &gpmc_pm_ops,
1747 },
1748};
1749
1750static __init int gpmc_init(void)
1751{
1752 return platform_driver_register(&gpmc_driver);
1753}
1754
1755static __exit void gpmc_exit(void)
1756{
1757 platform_driver_unregister(&gpmc_driver);
1758
1759}
1760
1761omap_postcore_initcall(gpmc_init);
1762module_exit(gpmc_exit);
1763
1764static int __init omap_gpmc_init(void)
1765{
1766 struct omap_hwmod *oh;
1767 struct platform_device *pdev;
1768 char *oh_name = "gpmc";
1769
1770 /*
1771 * if the board boots up with a populated DT, do not
1772 * manually add the device from this initcall
1773 */
1774 if (of_have_populated_dt())
1775 return -ENODEV;
1776
1777 oh = omap_hwmod_lookup(oh_name);
1778 if (!oh) {
1779 pr_err("Could not look up %s\n", oh_name);
1780 return -ENODEV;
1781 }
1782
1783 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1784 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1785
1786 return PTR_RET(pdev);
1787}
1788omap_postcore_initcall(omap_gpmc_init);
1789
1790static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1791{
1792 int i;
1793 u32 regval;
1794
1795 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1796
1797 if (!regval)
1798 return IRQ_NONE;
1799
1800 for (i = 0; i < GPMC_NR_IRQ; i++)
1801 if (regval & gpmc_client_irq[i].bitmask)
1802 generic_handle_irq(gpmc_client_irq[i].irq);
1803
1804 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1805
1806 return IRQ_HANDLED;
1807}
1808
1809static struct omap3_gpmc_regs gpmc_context;
1810
1811void omap3_gpmc_save_context(void)
1812{
1813 int i;
1814
1815 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1816 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1817 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1818 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1819 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1820 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1821 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1822 for (i = 0; i < gpmc_cs_num; i++) {
1823 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1824 if (gpmc_context.cs_context[i].is_valid) {
1825 gpmc_context.cs_context[i].config1 =
1826 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1827 gpmc_context.cs_context[i].config2 =
1828 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1829 gpmc_context.cs_context[i].config3 =
1830 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1831 gpmc_context.cs_context[i].config4 =
1832 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1833 gpmc_context.cs_context[i].config5 =
1834 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1835 gpmc_context.cs_context[i].config6 =
1836 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1837 gpmc_context.cs_context[i].config7 =
1838 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1839 }
1840 }
1841}
1842
1843void omap3_gpmc_restore_context(void)
1844{
1845 int i;
1846
1847 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1848 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1849 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1850 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1851 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1852 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1853 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1854 for (i = 0; i < gpmc_cs_num; i++) {
1855 if (gpmc_context.cs_context[i].is_valid) {
1856 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1857 gpmc_context.cs_context[i].config1);
1858 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1859 gpmc_context.cs_context[i].config2);
1860 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1861 gpmc_context.cs_context[i].config3);
1862 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1863 gpmc_context.cs_context[i].config4);
1864 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1865 gpmc_context.cs_context[i].config5);
1866 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1867 gpmc_context.cs_context[i].config6);
1868 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1869 gpmc_context.cs_context[i].config7);
1870 }
1871 }
1872}