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1/*
2 * gpmc-nand.c
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/mtd/nand.h>
16
17#include <asm/mach/flash.h>
18
19#include <plat/cpu.h>
20#include <plat/nand.h>
21#include <plat/board.h>
22#include <plat/gpmc.h>
23
24static struct resource gpmc_nand_resource = {
25 .flags = IORESOURCE_MEM,
26};
27
28static struct platform_device gpmc_nand_device = {
29 .name = "omap2-nand",
30 .id = 0,
31 .num_resources = 1,
32 .resource = &gpmc_nand_resource,
33};
34
35static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
36{
37 struct gpmc_timings t;
38 int err;
39
40 if (!gpmc_nand_data->gpmc_t)
41 return 0;
42
43 memset(&t, 0, sizeof(t));
44 t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
45 t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
46 t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
47
48 /* Read */
49 t.adv_rd_off = gpmc_round_ns_to_ticks(
50 gpmc_nand_data->gpmc_t->adv_rd_off);
51 t.oe_on = t.adv_on;
52 t.access = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->access);
53 t.oe_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->oe_off);
54 t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_rd_off);
55 t.rd_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->rd_cycle);
56
57 /* Write */
58 t.adv_wr_off = gpmc_round_ns_to_ticks(
59 gpmc_nand_data->gpmc_t->adv_wr_off);
60 t.we_on = t.oe_on;
61 if (cpu_is_omap34xx()) {
62 t.wr_data_mux_bus = gpmc_round_ns_to_ticks(
63 gpmc_nand_data->gpmc_t->wr_data_mux_bus);
64 t.wr_access = gpmc_round_ns_to_ticks(
65 gpmc_nand_data->gpmc_t->wr_access);
66 }
67 t.we_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->we_off);
68 t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_wr_off);
69 t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
70
71 /* Configure GPMC */
72 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
73 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
74 else
75 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
76 gpmc_cs_configure(gpmc_nand_data->cs,
77 GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
78 err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
79 if (err)
80 return err;
81
82 return 0;
83}
84
85int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
86{
87 int err = 0;
88 struct device *dev = &gpmc_nand_device.dev;
89
90 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
91
92 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
93 &gpmc_nand_data->phys_base);
94 if (err < 0) {
95 dev_err(dev, "Cannot request GPMC CS\n");
96 return err;
97 }
98
99 /* Set timings in GPMC */
100 err = omap2_nand_gpmc_retime(gpmc_nand_data);
101 if (err < 0) {
102 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
103 return err;
104 }
105
106 /* Enable RD PIN Monitoring Reg */
107 if (gpmc_nand_data->dev_ready) {
108 gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
109 }
110
111 err = platform_device_register(&gpmc_nand_device);
112 if (err < 0) {
113 dev_err(dev, "Unable to register NAND device\n");
114 goto out_free_cs;
115 }
116
117 return 0;
118
119out_free_cs:
120 gpmc_cs_free(gpmc_nand_data->cs);
121
122 return err;
123}
1/*
2 * gpmc-nand.c
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Vimal Singh <vimalsingh@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/mtd/nand.h>
16#include <linux/platform_data/mtd-nand-omap2.h>
17
18#include <asm/mach/flash.h>
19
20#include "gpmc.h"
21#include "soc.h"
22#include "gpmc-nand.h"
23
24/* minimum size for IO mapping */
25#define NAND_IO_SIZE 4
26
27static struct resource gpmc_nand_resource[] = {
28 {
29 .flags = IORESOURCE_MEM,
30 },
31 {
32 .flags = IORESOURCE_IRQ,
33 },
34 {
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39static struct platform_device gpmc_nand_device = {
40 .name = "omap2-nand",
41 .id = 0,
42 .num_resources = ARRAY_SIZE(gpmc_nand_resource),
43 .resource = gpmc_nand_resource,
44};
45
46static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
47{
48 /* platforms which support all ECC schemes */
49 if (soc_is_am33xx() || cpu_is_omap44xx() ||
50 soc_is_omap54xx() || soc_is_dra7xx())
51 return 1;
52
53 /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
54 * which require H/W based ECC error detection */
55 if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
56 ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
57 (ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
58 return 0;
59
60 /*
61 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
62 * and AM33xx derivates. Other chips may be added if confirmed to work.
63 */
64 if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) &&
65 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)))
66 return 0;
67
68 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
69 if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
70 return 1;
71 else
72 return 0;
73}
74
75/* This function will go away once the device-tree convertion is complete */
76static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
77 struct gpmc_settings *s)
78{
79 /* Enable RD PIN Monitoring Reg */
80 if (gpmc_nand_data->dev_ready) {
81 s->wait_on_read = true;
82 s->wait_on_write = true;
83 }
84
85 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
86 s->device_width = GPMC_DEVWIDTH_16BIT;
87 else
88 s->device_width = GPMC_DEVWIDTH_8BIT;
89}
90
91int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
92 struct gpmc_timings *gpmc_t)
93{
94 int err = 0;
95 struct gpmc_settings s;
96 struct device *dev = &gpmc_nand_device.dev;
97
98 memset(&s, 0, sizeof(struct gpmc_settings));
99
100 gpmc_nand_device.dev.platform_data = gpmc_nand_data;
101
102 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
103 (unsigned long *)&gpmc_nand_resource[0].start);
104 if (err < 0) {
105 dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
106 gpmc_nand_data->cs, err);
107 return err;
108 }
109
110 gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
111 NAND_IO_SIZE - 1;
112
113 gpmc_nand_resource[1].start =
114 gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
115 gpmc_nand_resource[2].start =
116 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
117
118 if (gpmc_t) {
119 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
120 if (err < 0) {
121 dev_err(dev, "Unable to set gpmc timings: %d\n", err);
122 return err;
123 }
124 }
125
126 if (gpmc_nand_data->of_node)
127 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
128 else
129 gpmc_set_legacy(gpmc_nand_data, &s);
130
131 s.device_nand = true;
132
133 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
134 if (err < 0)
135 goto out_free_cs;
136
137 err = gpmc_configure(GPMC_CONFIG_WP, 0);
138 if (err < 0)
139 goto out_free_cs;
140
141 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
142
143 if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
144 dev_err(dev, "Unsupported NAND ECC scheme selected\n");
145 return -EINVAL;
146 }
147
148 err = platform_device_register(&gpmc_nand_device);
149 if (err < 0) {
150 dev_err(dev, "Unable to register NAND device\n");
151 goto out_free_cs;
152 }
153
154 return 0;
155
156out_free_cs:
157 gpmc_cs_free(gpmc_nand_data->cs);
158
159 return err;
160}