Loading...
1/*
2 * OMAP4-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Rajendra Nayak
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/bitops.h>
17
18#include <plat/cpu.h>
19#include <plat/clock.h>
20
21#include "clock.h"
22#include "clock44xx.h"
23#include "cm-regbits-44xx.h"
24
25/* Supported only on OMAP4 */
26int omap4_dpllmx_gatectrl_read(struct clk *clk)
27{
28 u32 v;
29 u32 mask;
30
31 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
32 return -EINVAL;
33
34 mask = clk->flags & CLOCK_CLKOUTX2 ?
35 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
36 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
37
38 v = __raw_readl(clk->clksel_reg);
39 v &= mask;
40 v >>= __ffs(mask);
41
42 return v;
43}
44
45void omap4_dpllmx_allow_gatectrl(struct clk *clk)
46{
47 u32 v;
48 u32 mask;
49
50 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
51 return;
52
53 mask = clk->flags & CLOCK_CLKOUTX2 ?
54 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
55 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
56
57 v = __raw_readl(clk->clksel_reg);
58 /* Clear the bit to allow gatectrl */
59 v &= ~mask;
60 __raw_writel(v, clk->clksel_reg);
61}
62
63void omap4_dpllmx_deny_gatectrl(struct clk *clk)
64{
65 u32 v;
66 u32 mask;
67
68 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
69 return;
70
71 mask = clk->flags & CLOCK_CLKOUTX2 ?
72 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
73 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
74
75 v = __raw_readl(clk->clksel_reg);
76 /* Set the bit to deny gatectrl */
77 v |= mask;
78 __raw_writel(v, clk->clksel_reg);
79}
80
81const struct clkops clkops_omap4_dpllmx_ops = {
82 .allow_idle = omap4_dpllmx_allow_gatectrl,
83 .deny_idle = omap4_dpllmx_deny_gatectrl,
84};
85
86/**
87 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
88 * @clk: struct clk * of the DPLL to compute the rate for
89 *
90 * Compute the output rate for the OMAP4 DPLL represented by @clk.
91 * Takes the REGM4XEN bit into consideration, which is needed for the
92 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
93 * upon success, or 0 upon error.
94 */
95unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
96{
97 u32 v;
98 unsigned long rate;
99 struct dpll_data *dd;
100
101 if (!clk || !clk->dpll_data)
102 return 0;
103
104 dd = clk->dpll_data;
105
106 rate = omap2_get_dpll_rate(clk);
107
108 /* regm4xen adds a multiplier of 4 to DPLL calculations */
109 v = __raw_readl(dd->control_reg);
110 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
111 rate *= OMAP4430_REGM4XEN_MULT;
112
113 return rate;
114}
115
116/**
117 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
118 * @clk: struct clk * of the DPLL to round a rate for
119 * @target_rate: the desired rate of the DPLL
120 *
121 * Compute the rate that would be programmed into the DPLL hardware
122 * for @clk if set_rate() were to be provided with the rate
123 * @target_rate. Takes the REGM4XEN bit into consideration, which is
124 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
125 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
126 * ~0 if an error occurred in omap2_dpll_round_rate().
127 */
128long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
129{
130 u32 v;
131 struct dpll_data *dd;
132 long r;
133
134 if (!clk || !clk->dpll_data)
135 return -EINVAL;
136
137 dd = clk->dpll_data;
138
139 /* regm4xen adds a multiplier of 4 to DPLL calculations */
140 v = __raw_readl(dd->control_reg) & OMAP4430_DPLL_REGM4XEN_MASK;
141
142 if (v)
143 target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
144
145 r = omap2_dpll_round_rate(clk, target_rate);
146 if (r == ~0)
147 return r;
148
149 if (v)
150 clk->dpll_data->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
151
152 return clk->dpll_data->last_rounded_rate;
153}
1/*
2 * OMAP4-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Rajendra Nayak
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/bitops.h>
17
18#include "soc.h"
19#include "clock.h"
20#include "clock44xx.h"
21#include "cm-regbits-44xx.h"
22
23/*
24 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
25 * can supported when using the DPLL low-power mode. Frequencies are
26 * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
27 * Status, and Low-Power Operation Mode".
28 */
29#define OMAP4_DPLL_LP_FINT_MAX 1000000
30#define OMAP4_DPLL_LP_FOUT_MAX 100000000
31
32/* Supported only on OMAP4 */
33int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
34{
35 u32 v;
36 u32 mask;
37
38 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
39 return -EINVAL;
40
41 mask = clk->flags & CLOCK_CLKOUTX2 ?
42 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
43 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
44
45 v = omap2_clk_readl(clk, clk->clksel_reg);
46 v &= mask;
47 v >>= __ffs(mask);
48
49 return v;
50}
51
52void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
53{
54 u32 v;
55 u32 mask;
56
57 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
58 return;
59
60 mask = clk->flags & CLOCK_CLKOUTX2 ?
61 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
62 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
63
64 v = omap2_clk_readl(clk, clk->clksel_reg);
65 /* Clear the bit to allow gatectrl */
66 v &= ~mask;
67 omap2_clk_writel(v, clk, clk->clksel_reg);
68}
69
70void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
71{
72 u32 v;
73 u32 mask;
74
75 if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
76 return;
77
78 mask = clk->flags & CLOCK_CLKOUTX2 ?
79 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
80 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
81
82 v = omap2_clk_readl(clk, clk->clksel_reg);
83 /* Set the bit to deny gatectrl */
84 v |= mask;
85 omap2_clk_writel(v, clk, clk->clksel_reg);
86}
87
88const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
89 .allow_idle = omap4_dpllmx_allow_gatectrl,
90 .deny_idle = omap4_dpllmx_deny_gatectrl,
91};
92
93/**
94 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
95 * @dd: pointer to the dpll data structure
96 *
97 * Calculates if low-power mode can be enabled based upon the last
98 * multiplier and divider values calculated. If low-power mode can be
99 * enabled, then the bit to enable low-power mode is stored in the
100 * last_rounded_lpmode variable. This implementation is based upon the
101 * criteria for enabling low-power mode as described in the OMAP4430/60
102 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
103 * Operation Mode".
104 */
105static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
106{
107 long fint, fout;
108
109 fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
110 fout = fint * dd->last_rounded_m;
111
112 if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
113 dd->last_rounded_lpmode = 1;
114 else
115 dd->last_rounded_lpmode = 0;
116}
117
118/**
119 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
120 * @clk: struct clk * of the DPLL to compute the rate for
121 *
122 * Compute the output rate for the OMAP4 DPLL represented by @clk.
123 * Takes the REGM4XEN bit into consideration, which is needed for the
124 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
125 * upon success, or 0 upon error.
126 */
127unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
128 unsigned long parent_rate)
129{
130 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
131 u32 v;
132 unsigned long rate;
133 struct dpll_data *dd;
134
135 if (!clk || !clk->dpll_data)
136 return 0;
137
138 dd = clk->dpll_data;
139
140 rate = omap2_get_dpll_rate(clk);
141
142 /* regm4xen adds a multiplier of 4 to DPLL calculations */
143 v = omap2_clk_readl(clk, dd->control_reg);
144 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
145 rate *= OMAP4430_REGM4XEN_MULT;
146
147 return rate;
148}
149
150/**
151 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
152 * @clk: struct clk * of the DPLL to round a rate for
153 * @target_rate: the desired rate of the DPLL
154 *
155 * Compute the rate that would be programmed into the DPLL hardware
156 * for @clk if set_rate() were to be provided with the rate
157 * @target_rate. Takes the REGM4XEN bit into consideration, which is
158 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
159 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
160 * ~0 if an error occurred in omap2_dpll_round_rate().
161 */
162long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
163 unsigned long target_rate,
164 unsigned long *parent_rate)
165{
166 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
167 struct dpll_data *dd;
168 long r;
169
170 if (!clk || !clk->dpll_data)
171 return -EINVAL;
172
173 dd = clk->dpll_data;
174
175 dd->last_rounded_m4xen = 0;
176
177 /*
178 * First try to compute the DPLL configuration for
179 * target rate without using the 4X multiplier.
180 */
181 r = omap2_dpll_round_rate(hw, target_rate, NULL);
182 if (r != ~0)
183 goto out;
184
185 /*
186 * If we did not find a valid DPLL configuration, try again, but
187 * this time see if using the 4X multiplier can help. Enabling the
188 * 4X multiplier is equivalent to dividing the target rate by 4.
189 */
190 r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
191 NULL);
192 if (r == ~0)
193 return r;
194
195 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
196 dd->last_rounded_m4xen = 1;
197
198out:
199 omap4_dpll_lpmode_recalc(dd);
200
201 return dd->last_rounded_rate;
202}