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1/*
2 * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
32#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
33#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
34#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
35#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
36#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
37#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
38#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
39#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
40#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
41#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
42#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
43
44/* Registers shifts and masks */
45
46/* IP_REVISION */
47#define OMAP4_IP_REV_SCHEME_SHIFT 30
48#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
49#define OMAP4_IP_REV_FUNC_SHIFT 16
50#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
51#define OMAP4_IP_REV_RTL_SHIFT 11
52#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
53#define OMAP4_IP_REV_MAJOR_SHIFT 8
54#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
55#define OMAP4_IP_REV_CUSTOM_SHIFT 6
56#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
57#define OMAP4_IP_REV_MINOR_SHIFT 0
58#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
59
60/* IP_HWINFO */
61#define OMAP4_IP_HWINFO_SHIFT 0
62#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
63
64/* IP_SYSCONFIG */
65#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
66#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
67
68/* PADCONF_WAKEUPEVENT_0 */
69#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
70#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
71#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
72#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
73#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
74#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
75#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
76#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
77#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
78#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
79#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
80#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
81#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
82#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
83#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
84#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
85#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
86#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
87#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
88#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
89#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
90#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
91#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
92#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
93#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
94#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
95#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
96#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
97#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
98#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
99#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
100#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
101#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
102#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
103#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
104#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
105#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
106#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
107#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
108#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
109#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
110#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
111#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
112#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
113#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
114#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
115#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
116#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
117#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
118#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
119
120/* CONTROL_SMART1NOPMIO_PADCONF_0 */
121#define OMAP4_FREF_DR0_SC_SHIFT 30
122#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
123#define OMAP4_FREF_DR1_SC_SHIFT 28
124#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
125#define OMAP4_FREF_DR4_SC_SHIFT 26
126#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
127#define OMAP4_FREF_DR5_SC_SHIFT 24
128#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
129#define OMAP4_FREF_DR6_SC_SHIFT 22
130#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
131#define OMAP4_FREF_DR7_SC_SHIFT 20
132#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
133#define OMAP4_GPIO_DR7_SC_SHIFT 18
134#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
135#define OMAP4_DPM_DR0_SC_SHIFT 14
136#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
137#define OMAP4_SIM_DR0_SC_SHIFT 12
138#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
139
140/* CONTROL_SMART1NOPMIO_PADCONF_1 */
141#define OMAP4_FREF_DR0_LB_SHIFT 30
142#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
143#define OMAP4_FREF_DR1_LB_SHIFT 28
144#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
145#define OMAP4_FREF_DR4_LB_SHIFT 26
146#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
147#define OMAP4_FREF_DR5_LB_SHIFT 24
148#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
149#define OMAP4_FREF_DR6_LB_SHIFT 22
150#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
151#define OMAP4_FREF_DR7_LB_SHIFT 20
152#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
153#define OMAP4_GPIO_DR7_LB_SHIFT 18
154#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
155#define OMAP4_DPM_DR0_LB_SHIFT 14
156#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
157#define OMAP4_SIM_DR0_LB_SHIFT 12
158#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
159
160/* CONTROL_PADCONF_MODE */
161#define OMAP4_VDDS_DV_FREF_SHIFT 31
162#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
163#define OMAP4_VDDS_DV_BANK2_SHIFT 30
164#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
165
166/* CONTROL_XTAL_OSCILLATOR */
167#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
168#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
169#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
170#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
171
172/* CONTROL_USIMIO */
173#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
174#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
175#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
176#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
177#define OMAP4_USIM_PWRDNZ_SHIFT 28
178#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
179
180/* CONTROL_I2C_2 */
181#define OMAP4_SR_SDA_GLFENB_SHIFT 31
182#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
183#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
184#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
185#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
186#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
187#define OMAP4_SR_SCL_GLFENB_SHIFT 27
188#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
189#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
190#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
191#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
192#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
193
194/* CONTROL_JTAG */
195#define OMAP4_JTAG_NTRST_EN_SHIFT 31
196#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
197#define OMAP4_JTAG_TCK_EN_SHIFT 30
198#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
199#define OMAP4_JTAG_RTCK_EN_SHIFT 29
200#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
201#define OMAP4_JTAG_TDI_EN_SHIFT 28
202#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
203#define OMAP4_JTAG_TDO_EN_SHIFT 27
204#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
205
206/* CONTROL_SYS */
207#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
208#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
209
210/* WKUP_CONTROL_SPARE_RW */
211#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
212#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
213
214/* WKUP_CONTROL_SPARE_R */
215#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
216#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
217
218/* WKUP_CONTROL_SPARE_R_C0 */
219#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
220#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
221#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
222#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
223#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
224#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
225#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
226#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
227#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
228#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
229#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
230#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
231#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
232#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
233#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
234#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
235
236#endif