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1/*
2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Copyright (C) 2009 Texas Instruments
7 *
8 * Vimal Singh <vimalsingh@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/io.h>
19#include <plat/irqs.h>
20
21#include <plat/gpmc.h>
22#include <plat/nand.h>
23#include <plat/onenand.h>
24#include <plat/tc.h>
25
26#include "board-flash.h"
27
28#define REG_FPGA_REV 0x10
29#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
30#define MAX_SUPPORTED_GPMC_CONFIG 3
31
32#define DEBUG_BASE 0x08000000 /* debug board */
33
34/* various memory sizes */
35#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
36#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
37
38static struct physmap_flash_data board_nor_data = {
39 .width = 2,
40};
41
42static struct resource board_nor_resource = {
43 .flags = IORESOURCE_MEM,
44};
45
46static struct platform_device board_nor_device = {
47 .name = "physmap-flash",
48 .id = 0,
49 .dev = {
50 .platform_data = &board_nor_data,
51 },
52 .num_resources = 1,
53 .resource = &board_nor_resource,
54};
55
56static void
57__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
58{
59 int err;
60
61 board_nor_data.parts = nor_parts;
62 board_nor_data.nr_parts = nr_parts;
63
64 /* Configure start address and size of NOR device */
65 if (omap_rev() >= OMAP3430_REV_ES1_0) {
66 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
67 (unsigned long *)&board_nor_resource.start);
68 board_nor_resource.end = board_nor_resource.start
69 + FLASH_SIZE_SDPV2 - 1;
70 } else {
71 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
72 (unsigned long *)&board_nor_resource.start);
73 board_nor_resource.end = board_nor_resource.start
74 + FLASH_SIZE_SDPV1 - 1;
75 }
76 if (err < 0) {
77 pr_err("NOR: Can't request GPMC CS\n");
78 return;
79 }
80 if (platform_device_register(&board_nor_device) < 0)
81 pr_err("Unable to register NOR device\n");
82}
83
84#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
85 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
86static struct omap_onenand_platform_data board_onenand_data = {
87 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
88};
89
90void
91__init board_onenand_init(struct mtd_partition *onenand_parts,
92 u8 nr_parts, u8 cs)
93{
94 board_onenand_data.cs = cs;
95 board_onenand_data.parts = onenand_parts;
96 board_onenand_data.nr_parts = nr_parts;
97
98 gpmc_onenand_init(&board_onenand_data);
99}
100#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
101
102#if defined(CONFIG_MTD_NAND_OMAP2) || \
103 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
104
105/* Note that all values in this struct are in nanoseconds */
106static struct gpmc_timings nand_timings = {
107
108 .sync_clk = 0,
109
110 .cs_on = 0,
111 .cs_rd_off = 36,
112 .cs_wr_off = 36,
113
114 .adv_on = 6,
115 .adv_rd_off = 24,
116 .adv_wr_off = 36,
117
118 .we_off = 30,
119 .oe_off = 48,
120
121 .access = 54,
122 .rd_cycle = 72,
123 .wr_cycle = 72,
124
125 .wr_access = 30,
126 .wr_data_mux_bus = 0,
127};
128
129static struct omap_nand_platform_data board_nand_data = {
130 .gpmc_t = &nand_timings,
131};
132
133void
134__init board_nand_init(struct mtd_partition *nand_parts,
135 u8 nr_parts, u8 cs, int nand_type)
136{
137 board_nand_data.cs = cs;
138 board_nand_data.parts = nand_parts;
139 board_nand_data.nr_parts = nr_parts;
140 board_nand_data.devsize = nand_type;
141
142 board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
143 board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
144 gpmc_nand_init(&board_nand_data);
145}
146#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
147
148/**
149 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
150 * the various cs values.
151 */
152static u8 get_gpmc0_type(void)
153{
154 u8 cs = 0;
155 void __iomem *fpga_map_addr;
156
157 fpga_map_addr = ioremap(DEBUG_BASE, 4096);
158 if (!fpga_map_addr)
159 return -ENOMEM;
160
161 if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
162 /* we dont have an DEBUG FPGA??? */
163 /* Depend on #defines!! default to strata boot return param */
164 goto unmap;
165
166 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
167 cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
168
169 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
170 if (omap_rev() >= OMAP3430_REV_ES1_0)
171 /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
172 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
173 ((cs & 2) << 1) | ((cs & 1) << 3);
174 else
175 /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
176 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
177unmap:
178 iounmap(fpga_map_addr);
179 return cs;
180}
181
182/**
183 * board_flash_init - Identify devices connected to GPMC and register.
184 *
185 * @return - void.
186 */
187void __init board_flash_init(struct flash_partitions partition_info[],
188 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
189{
190 u8 cs = 0;
191 u8 norcs = GPMC_CS_NUM + 1;
192 u8 nandcs = GPMC_CS_NUM + 1;
193 u8 onenandcs = GPMC_CS_NUM + 1;
194 u8 idx;
195 unsigned char *config_sel = NULL;
196
197 /* REVISIT: Is this return correct idx for 2430 SDP?
198 * for which cs configuration matches for 2430 SDP?
199 */
200 idx = get_gpmc0_type();
201 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
202 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
203 return;
204 }
205 config_sel = (unsigned char *)(chip_sel_board[idx]);
206
207 while (cs < GPMC_CS_NUM) {
208 switch (config_sel[cs]) {
209 case PDC_NOR:
210 if (norcs > GPMC_CS_NUM)
211 norcs = cs;
212 break;
213 case PDC_NAND:
214 if (nandcs > GPMC_CS_NUM)
215 nandcs = cs;
216 break;
217 case PDC_ONENAND:
218 if (onenandcs > GPMC_CS_NUM)
219 onenandcs = cs;
220 break;
221 };
222 cs++;
223 }
224
225 if (norcs > GPMC_CS_NUM)
226 pr_err("NOR: Unable to find configuration in GPMC\n");
227 else
228 board_nor_init(partition_info[0].parts,
229 partition_info[0].nr_parts, norcs);
230
231 if (onenandcs > GPMC_CS_NUM)
232 pr_err("OneNAND: Unable to find configuration in GPMC\n");
233 else
234 board_onenand_init(partition_info[1].parts,
235 partition_info[1].nr_parts, onenandcs);
236
237 if (nandcs > GPMC_CS_NUM)
238 pr_err("NAND: Unable to find configuration in GPMC\n");
239 else
240 board_nand_init(partition_info[2].parts,
241 partition_info[2].nr_parts, nandcs, nand_type);
242}
1/*
2 * board-flash.c
3 * Modified from mach-omap2/board-3430sdp-flash.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Copyright (C) 2009 Texas Instruments
7 *
8 * Vimal Singh <vimalsingh@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/io.h>
19
20#include <linux/platform_data/mtd-nand-omap2.h>
21#include <linux/platform_data/mtd-onenand-omap2.h>
22
23#include "soc.h"
24#include "common.h"
25#include "board-flash.h"
26#include "gpmc-onenand.h"
27#include "gpmc-nand.h"
28
29#define REG_FPGA_REV 0x10
30#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
31#define MAX_SUPPORTED_GPMC_CONFIG 3
32
33#define DEBUG_BASE 0x08000000 /* debug board */
34
35/* various memory sizes */
36#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
37#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
38
39static struct physmap_flash_data board_nor_data = {
40 .width = 2,
41};
42
43static struct resource board_nor_resource = {
44 .flags = IORESOURCE_MEM,
45};
46
47static struct platform_device board_nor_device = {
48 .name = "physmap-flash",
49 .id = 0,
50 .dev = {
51 .platform_data = &board_nor_data,
52 },
53 .num_resources = 1,
54 .resource = &board_nor_resource,
55};
56
57static void
58__init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
59{
60 int err;
61
62 board_nor_data.parts = nor_parts;
63 board_nor_data.nr_parts = nr_parts;
64
65 /* Configure start address and size of NOR device */
66 if (omap_rev() >= OMAP3430_REV_ES1_0) {
67 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
68 (unsigned long *)&board_nor_resource.start);
69 board_nor_resource.end = board_nor_resource.start
70 + FLASH_SIZE_SDPV2 - 1;
71 } else {
72 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
73 (unsigned long *)&board_nor_resource.start);
74 board_nor_resource.end = board_nor_resource.start
75 + FLASH_SIZE_SDPV1 - 1;
76 }
77 if (err < 0) {
78 pr_err("NOR: Can't request GPMC CS\n");
79 return;
80 }
81 if (platform_device_register(&board_nor_device) < 0)
82 pr_err("Unable to register NOR device\n");
83}
84
85#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
86 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
87static struct omap_onenand_platform_data board_onenand_data = {
88 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
89};
90
91void
92__init board_onenand_init(struct mtd_partition *onenand_parts,
93 u8 nr_parts, u8 cs)
94{
95 board_onenand_data.cs = cs;
96 board_onenand_data.parts = onenand_parts;
97 board_onenand_data.nr_parts = nr_parts;
98
99 gpmc_onenand_init(&board_onenand_data);
100}
101#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
102
103#if defined(CONFIG_MTD_NAND_OMAP2) || \
104 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
105
106/* Note that all values in this struct are in nanoseconds */
107struct gpmc_timings nand_default_timings[1] = {
108 {
109 .sync_clk = 0,
110
111 .cs_on = 0,
112 .cs_rd_off = 36,
113 .cs_wr_off = 36,
114
115 .we_on = 6,
116 .oe_on = 6,
117
118 .adv_on = 6,
119 .adv_rd_off = 24,
120 .adv_wr_off = 36,
121
122 .we_off = 30,
123 .oe_off = 48,
124
125 .access = 54,
126 .rd_cycle = 72,
127 .wr_cycle = 72,
128
129 .wr_access = 30,
130 .wr_data_mux_bus = 0,
131 },
132};
133
134static struct omap_nand_platform_data board_nand_data;
135
136void
137__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
138 int nand_type, struct gpmc_timings *gpmc_t)
139{
140 board_nand_data.cs = cs;
141 board_nand_data.parts = nand_parts;
142 board_nand_data.nr_parts = nr_parts;
143 board_nand_data.devsize = nand_type;
144
145 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
146 gpmc_nand_init(&board_nand_data, gpmc_t);
147}
148#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
149
150/**
151 * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
152 * the various cs values.
153 */
154static u8 get_gpmc0_type(void)
155{
156 u8 cs = 0;
157 void __iomem *fpga_map_addr;
158
159 fpga_map_addr = ioremap(DEBUG_BASE, 4096);
160 if (!fpga_map_addr)
161 return -ENOMEM;
162
163 if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
164 /* we dont have an DEBUG FPGA??? */
165 /* Depend on #defines!! default to strata boot return param */
166 goto unmap;
167
168 /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
169 cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
170
171 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
172 if (omap_rev() >= OMAP3430_REV_ES1_0)
173 /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
174 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
175 ((cs & 2) << 1) | ((cs & 1) << 3);
176 else
177 /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
178 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
179unmap:
180 iounmap(fpga_map_addr);
181 return cs;
182}
183
184/**
185 * board_flash_init - Identify devices connected to GPMC and register.
186 *
187 * @return - void.
188 */
189void __init board_flash_init(struct flash_partitions partition_info[],
190 char chip_sel_board[][GPMC_CS_NUM], int nand_type)
191{
192 u8 cs = 0;
193 u8 norcs = GPMC_CS_NUM + 1;
194 u8 nandcs = GPMC_CS_NUM + 1;
195 u8 onenandcs = GPMC_CS_NUM + 1;
196 u8 idx;
197 unsigned char *config_sel = NULL;
198
199 /* REVISIT: Is this return correct idx for 2430 SDP?
200 * for which cs configuration matches for 2430 SDP?
201 */
202 idx = get_gpmc0_type();
203 if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
204 pr_err("%s: Invalid chip select: %d\n", __func__, cs);
205 return;
206 }
207 config_sel = (unsigned char *)(chip_sel_board[idx]);
208
209 while (cs < GPMC_CS_NUM) {
210 switch (config_sel[cs]) {
211 case PDC_NOR:
212 if (norcs > GPMC_CS_NUM)
213 norcs = cs;
214 break;
215 case PDC_NAND:
216 if (nandcs > GPMC_CS_NUM)
217 nandcs = cs;
218 break;
219 case PDC_ONENAND:
220 if (onenandcs > GPMC_CS_NUM)
221 onenandcs = cs;
222 break;
223 }
224 cs++;
225 }
226
227 if (norcs > GPMC_CS_NUM)
228 pr_err("NOR: Unable to find configuration in GPMC\n");
229 else
230 board_nor_init(partition_info[0].parts,
231 partition_info[0].nr_parts, norcs);
232
233 if (onenandcs > GPMC_CS_NUM)
234 pr_err("OneNAND: Unable to find configuration in GPMC\n");
235 else
236 board_onenand_init(partition_info[1].parts,
237 partition_info[1].nr_parts, onenandcs);
238
239 if (nandcs > GPMC_CS_NUM)
240 pr_err("NAND: Unable to find configuration in GPMC\n");
241 else
242 board_nand_init(partition_info[2].parts,
243 partition_info[2].nr_parts, nandcs,
244 nand_type, nand_default_timings);
245}