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1/*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/bitmap.h>
13#include <linux/clk.h>
14#include <linux/completion.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25
26#include <linux/spi/sh_msiof.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_bitbang.h>
29
30#include <asm/unaligned.h>
31
32struct sh_msiof_spi_priv {
33 struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
34 void __iomem *mapbase;
35 struct clk *clk;
36 struct platform_device *pdev;
37 struct sh_msiof_spi_info *info;
38 struct completion done;
39 unsigned long flags;
40 int tx_fifo_size;
41 int rx_fifo_size;
42};
43
44#define TMDR1 0x00
45#define TMDR2 0x04
46#define TMDR3 0x08
47#define RMDR1 0x10
48#define RMDR2 0x14
49#define RMDR3 0x18
50#define TSCR 0x20
51#define RSCR 0x22
52#define CTR 0x28
53#define FCTR 0x30
54#define STR 0x40
55#define IER 0x44
56#define TDR1 0x48
57#define TDR2 0x4c
58#define TFDR 0x50
59#define RDR1 0x58
60#define RDR2 0x5c
61#define RFDR 0x60
62
63#define CTR_TSCKE (1 << 15)
64#define CTR_TFSE (1 << 14)
65#define CTR_TXE (1 << 9)
66#define CTR_RXE (1 << 8)
67
68#define STR_TEOF (1 << 23)
69#define STR_REOF (1 << 7)
70
71static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
72{
73 switch (reg_offs) {
74 case TSCR:
75 case RSCR:
76 return ioread16(p->mapbase + reg_offs);
77 default:
78 return ioread32(p->mapbase + reg_offs);
79 }
80}
81
82static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
83 u32 value)
84{
85 switch (reg_offs) {
86 case TSCR:
87 case RSCR:
88 iowrite16(value, p->mapbase + reg_offs);
89 break;
90 default:
91 iowrite32(value, p->mapbase + reg_offs);
92 break;
93 }
94}
95
96static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
97 u32 clr, u32 set)
98{
99 u32 mask = clr | set;
100 u32 data;
101 int k;
102
103 data = sh_msiof_read(p, CTR);
104 data &= ~clr;
105 data |= set;
106 sh_msiof_write(p, CTR, data);
107
108 for (k = 100; k > 0; k--) {
109 if ((sh_msiof_read(p, CTR) & mask) == set)
110 break;
111
112 udelay(10);
113 }
114
115 return k > 0 ? 0 : -ETIMEDOUT;
116}
117
118static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
119{
120 struct sh_msiof_spi_priv *p = data;
121
122 /* just disable the interrupt and wake up */
123 sh_msiof_write(p, IER, 0);
124 complete(&p->done);
125
126 return IRQ_HANDLED;
127}
128
129static struct {
130 unsigned short div;
131 unsigned short scr;
132} const sh_msiof_spi_clk_table[] = {
133 { 1, 0x0007 },
134 { 2, 0x0000 },
135 { 4, 0x0001 },
136 { 8, 0x0002 },
137 { 16, 0x0003 },
138 { 32, 0x0004 },
139 { 64, 0x1f00 },
140 { 128, 0x1f01 },
141 { 256, 0x1f02 },
142 { 512, 0x1f03 },
143 { 1024, 0x1f04 },
144};
145
146static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
147 unsigned long parent_rate,
148 unsigned long spi_hz)
149{
150 unsigned long div = 1024;
151 size_t k;
152
153 if (!WARN_ON(!spi_hz || !parent_rate))
154 div = parent_rate / spi_hz;
155
156 /* TODO: make more fine grained */
157
158 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
159 if (sh_msiof_spi_clk_table[k].div >= div)
160 break;
161 }
162
163 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
164
165 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
166 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
167}
168
169static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
170 u32 cpol, u32 cpha,
171 u32 tx_hi_z, u32 lsb_first)
172{
173 u32 tmp;
174 int edge;
175
176 /*
177 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
178 * 0 0 10 10 1 1
179 * 0 1 10 10 0 0
180 * 1 0 11 11 0 0
181 * 1 1 11 11 1 1
182 */
183 sh_msiof_write(p, FCTR, 0);
184 sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
185 sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
186
187 tmp = 0xa0000000;
188 tmp |= cpol << 30; /* TSCKIZ */
189 tmp |= cpol << 28; /* RSCKIZ */
190
191 edge = cpol ^ !cpha;
192
193 tmp |= edge << 27; /* TEDG */
194 tmp |= edge << 26; /* REDG */
195 tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
196 sh_msiof_write(p, CTR, tmp);
197}
198
199static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
200 const void *tx_buf, void *rx_buf,
201 u32 bits, u32 words)
202{
203 u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
204
205 if (tx_buf)
206 sh_msiof_write(p, TMDR2, dr2);
207 else
208 sh_msiof_write(p, TMDR2, dr2 | 1);
209
210 if (rx_buf)
211 sh_msiof_write(p, RMDR2, dr2);
212
213 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
214}
215
216static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
217{
218 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
219}
220
221static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
222 const void *tx_buf, int words, int fs)
223{
224 const u8 *buf_8 = tx_buf;
225 int k;
226
227 for (k = 0; k < words; k++)
228 sh_msiof_write(p, TFDR, buf_8[k] << fs);
229}
230
231static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
232 const void *tx_buf, int words, int fs)
233{
234 const u16 *buf_16 = tx_buf;
235 int k;
236
237 for (k = 0; k < words; k++)
238 sh_msiof_write(p, TFDR, buf_16[k] << fs);
239}
240
241static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
242 const void *tx_buf, int words, int fs)
243{
244 const u16 *buf_16 = tx_buf;
245 int k;
246
247 for (k = 0; k < words; k++)
248 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
249}
250
251static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
252 const void *tx_buf, int words, int fs)
253{
254 const u32 *buf_32 = tx_buf;
255 int k;
256
257 for (k = 0; k < words; k++)
258 sh_msiof_write(p, TFDR, buf_32[k] << fs);
259}
260
261static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
262 const void *tx_buf, int words, int fs)
263{
264 const u32 *buf_32 = tx_buf;
265 int k;
266
267 for (k = 0; k < words; k++)
268 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
269}
270
271static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
272 const void *tx_buf, int words, int fs)
273{
274 const u32 *buf_32 = tx_buf;
275 int k;
276
277 for (k = 0; k < words; k++)
278 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
279}
280
281static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
282 const void *tx_buf, int words, int fs)
283{
284 const u32 *buf_32 = tx_buf;
285 int k;
286
287 for (k = 0; k < words; k++)
288 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
289}
290
291static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
292 void *rx_buf, int words, int fs)
293{
294 u8 *buf_8 = rx_buf;
295 int k;
296
297 for (k = 0; k < words; k++)
298 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
299}
300
301static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
302 void *rx_buf, int words, int fs)
303{
304 u16 *buf_16 = rx_buf;
305 int k;
306
307 for (k = 0; k < words; k++)
308 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
309}
310
311static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
312 void *rx_buf, int words, int fs)
313{
314 u16 *buf_16 = rx_buf;
315 int k;
316
317 for (k = 0; k < words; k++)
318 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
319}
320
321static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
322 void *rx_buf, int words, int fs)
323{
324 u32 *buf_32 = rx_buf;
325 int k;
326
327 for (k = 0; k < words; k++)
328 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
329}
330
331static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
332 void *rx_buf, int words, int fs)
333{
334 u32 *buf_32 = rx_buf;
335 int k;
336
337 for (k = 0; k < words; k++)
338 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
339}
340
341static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
342 void *rx_buf, int words, int fs)
343{
344 u32 *buf_32 = rx_buf;
345 int k;
346
347 for (k = 0; k < words; k++)
348 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
349}
350
351static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
352 void *rx_buf, int words, int fs)
353{
354 u32 *buf_32 = rx_buf;
355 int k;
356
357 for (k = 0; k < words; k++)
358 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
359}
360
361static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
362{
363 int bits;
364
365 bits = t ? t->bits_per_word : 0;
366 if (!bits)
367 bits = spi->bits_per_word;
368 return bits;
369}
370
371static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
372 struct spi_transfer *t)
373{
374 unsigned long hz;
375
376 hz = t ? t->speed_hz : 0;
377 if (!hz)
378 hz = spi->max_speed_hz;
379 return hz;
380}
381
382static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
383 struct spi_transfer *t)
384{
385 int bits;
386
387 /* noting to check hz values against since parent clock is disabled */
388
389 bits = sh_msiof_spi_bits(spi, t);
390 if (bits < 8)
391 return -EINVAL;
392 if (bits > 32)
393 return -EINVAL;
394
395 return spi_bitbang_setup_transfer(spi, t);
396}
397
398static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
399{
400 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
401 int value;
402
403 /* chip select is active low unless SPI_CS_HIGH is set */
404 if (spi->mode & SPI_CS_HIGH)
405 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
406 else
407 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
408
409 if (is_on == BITBANG_CS_ACTIVE) {
410 if (!test_and_set_bit(0, &p->flags)) {
411 pm_runtime_get_sync(&p->pdev->dev);
412 clk_enable(p->clk);
413 }
414
415 /* Configure pins before asserting CS */
416 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
417 !!(spi->mode & SPI_CPHA),
418 !!(spi->mode & SPI_3WIRE),
419 !!(spi->mode & SPI_LSB_FIRST));
420 }
421
422 /* use spi->controller data for CS (same strategy as spi_gpio) */
423 gpio_set_value((unsigned)spi->controller_data, value);
424
425 if (is_on == BITBANG_CS_INACTIVE) {
426 if (test_and_clear_bit(0, &p->flags)) {
427 clk_disable(p->clk);
428 pm_runtime_put(&p->pdev->dev);
429 }
430 }
431}
432
433static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
434 void (*tx_fifo)(struct sh_msiof_spi_priv *,
435 const void *, int, int),
436 void (*rx_fifo)(struct sh_msiof_spi_priv *,
437 void *, int, int),
438 const void *tx_buf, void *rx_buf,
439 int words, int bits)
440{
441 int fifo_shift;
442 int ret;
443
444 /* limit maximum word transfer to rx/tx fifo size */
445 if (tx_buf)
446 words = min_t(int, words, p->tx_fifo_size);
447 if (rx_buf)
448 words = min_t(int, words, p->rx_fifo_size);
449
450 /* the fifo contents need shifting */
451 fifo_shift = 32 - bits;
452
453 /* setup msiof transfer mode registers */
454 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
455
456 /* write tx fifo */
457 if (tx_buf)
458 tx_fifo(p, tx_buf, words, fifo_shift);
459
460 /* setup clock and rx/tx signals */
461 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
462 if (rx_buf)
463 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
464 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
465
466 /* start by setting frame bit */
467 INIT_COMPLETION(p->done);
468 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
469 if (ret) {
470 dev_err(&p->pdev->dev, "failed to start hardware\n");
471 goto err;
472 }
473
474 /* wait for tx fifo to be emptied / rx fifo to be filled */
475 wait_for_completion(&p->done);
476
477 /* read rx fifo */
478 if (rx_buf)
479 rx_fifo(p, rx_buf, words, fifo_shift);
480
481 /* clear status bits */
482 sh_msiof_reset_str(p);
483
484 /* shut down frame, tx/tx and clock signals */
485 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
486 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
487 if (rx_buf)
488 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
489 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
490 if (ret) {
491 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
492 goto err;
493 }
494
495 return words;
496
497 err:
498 sh_msiof_write(p, IER, 0);
499 return ret;
500}
501
502static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
503{
504 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
505 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
506 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
507 int bits;
508 int bytes_per_word;
509 int bytes_done;
510 int words;
511 int n;
512 bool swab;
513
514 bits = sh_msiof_spi_bits(spi, t);
515
516 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
517 bits = 32;
518 swab = true;
519 } else {
520 swab = false;
521 }
522
523 /* setup bytes per word and fifo read/write functions */
524 if (bits <= 8) {
525 bytes_per_word = 1;
526 tx_fifo = sh_msiof_spi_write_fifo_8;
527 rx_fifo = sh_msiof_spi_read_fifo_8;
528 } else if (bits <= 16) {
529 bytes_per_word = 2;
530 if ((unsigned long)t->tx_buf & 0x01)
531 tx_fifo = sh_msiof_spi_write_fifo_16u;
532 else
533 tx_fifo = sh_msiof_spi_write_fifo_16;
534
535 if ((unsigned long)t->rx_buf & 0x01)
536 rx_fifo = sh_msiof_spi_read_fifo_16u;
537 else
538 rx_fifo = sh_msiof_spi_read_fifo_16;
539 } else if (swab) {
540 bytes_per_word = 4;
541 if ((unsigned long)t->tx_buf & 0x03)
542 tx_fifo = sh_msiof_spi_write_fifo_s32u;
543 else
544 tx_fifo = sh_msiof_spi_write_fifo_s32;
545
546 if ((unsigned long)t->rx_buf & 0x03)
547 rx_fifo = sh_msiof_spi_read_fifo_s32u;
548 else
549 rx_fifo = sh_msiof_spi_read_fifo_s32;
550 } else {
551 bytes_per_word = 4;
552 if ((unsigned long)t->tx_buf & 0x03)
553 tx_fifo = sh_msiof_spi_write_fifo_32u;
554 else
555 tx_fifo = sh_msiof_spi_write_fifo_32;
556
557 if ((unsigned long)t->rx_buf & 0x03)
558 rx_fifo = sh_msiof_spi_read_fifo_32u;
559 else
560 rx_fifo = sh_msiof_spi_read_fifo_32;
561 }
562
563 /* setup clocks (clock already enabled in chipselect()) */
564 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
565 sh_msiof_spi_hz(spi, t));
566
567 /* transfer in fifo sized chunks */
568 words = t->len / bytes_per_word;
569 bytes_done = 0;
570
571 while (bytes_done < t->len) {
572 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
573 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
574 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
575 tx_buf,
576 rx_buf,
577 words, bits);
578 if (n < 0)
579 break;
580
581 bytes_done += n * bytes_per_word;
582 words -= n;
583 }
584
585 return bytes_done;
586}
587
588static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
589 u32 word, u8 bits)
590{
591 BUG(); /* unused but needed by bitbang code */
592 return 0;
593}
594
595static int sh_msiof_spi_probe(struct platform_device *pdev)
596{
597 struct resource *r;
598 struct spi_master *master;
599 struct sh_msiof_spi_priv *p;
600 char clk_name[16];
601 int i;
602 int ret;
603
604 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
605 if (master == NULL) {
606 dev_err(&pdev->dev, "failed to allocate spi master\n");
607 ret = -ENOMEM;
608 goto err0;
609 }
610
611 p = spi_master_get_devdata(master);
612
613 platform_set_drvdata(pdev, p);
614 p->info = pdev->dev.platform_data;
615 init_completion(&p->done);
616
617 snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id);
618 p->clk = clk_get(&pdev->dev, clk_name);
619 if (IS_ERR(p->clk)) {
620 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
621 ret = PTR_ERR(p->clk);
622 goto err1;
623 }
624
625 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 i = platform_get_irq(pdev, 0);
627 if (!r || i < 0) {
628 dev_err(&pdev->dev, "cannot get platform resources\n");
629 ret = -ENOENT;
630 goto err2;
631 }
632 p->mapbase = ioremap_nocache(r->start, resource_size(r));
633 if (!p->mapbase) {
634 dev_err(&pdev->dev, "unable to ioremap\n");
635 ret = -ENXIO;
636 goto err2;
637 }
638
639 ret = request_irq(i, sh_msiof_spi_irq, 0,
640 dev_name(&pdev->dev), p);
641 if (ret) {
642 dev_err(&pdev->dev, "unable to request irq\n");
643 goto err3;
644 }
645
646 p->pdev = pdev;
647 pm_runtime_enable(&pdev->dev);
648
649 /* The standard version of MSIOF use 64 word FIFOs */
650 p->tx_fifo_size = 64;
651 p->rx_fifo_size = 64;
652
653 /* Platform data may override FIFO sizes */
654 if (p->info->tx_fifo_override)
655 p->tx_fifo_size = p->info->tx_fifo_override;
656 if (p->info->rx_fifo_override)
657 p->rx_fifo_size = p->info->rx_fifo_override;
658
659 /* init master and bitbang code */
660 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
661 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
662 master->flags = 0;
663 master->bus_num = pdev->id;
664 master->num_chipselect = p->info->num_chipselect;
665 master->setup = spi_bitbang_setup;
666 master->cleanup = spi_bitbang_cleanup;
667
668 p->bitbang.master = master;
669 p->bitbang.chipselect = sh_msiof_spi_chipselect;
670 p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
671 p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
672 p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
673 p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
674 p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
675 p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
676
677 ret = spi_bitbang_start(&p->bitbang);
678 if (ret == 0)
679 return 0;
680
681 pm_runtime_disable(&pdev->dev);
682 err3:
683 iounmap(p->mapbase);
684 err2:
685 clk_put(p->clk);
686 err1:
687 spi_master_put(master);
688 err0:
689 return ret;
690}
691
692static int sh_msiof_spi_remove(struct platform_device *pdev)
693{
694 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
695 int ret;
696
697 ret = spi_bitbang_stop(&p->bitbang);
698 if (!ret) {
699 pm_runtime_disable(&pdev->dev);
700 free_irq(platform_get_irq(pdev, 0), p);
701 iounmap(p->mapbase);
702 clk_put(p->clk);
703 spi_master_put(p->bitbang.master);
704 }
705 return ret;
706}
707
708static int sh_msiof_spi_runtime_nop(struct device *dev)
709{
710 /* Runtime PM callback shared between ->runtime_suspend()
711 * and ->runtime_resume(). Simply returns success.
712 *
713 * This driver re-initializes all registers after
714 * pm_runtime_get_sync() anyway so there is no need
715 * to save and restore registers here.
716 */
717 return 0;
718}
719
720static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = {
721 .runtime_suspend = sh_msiof_spi_runtime_nop,
722 .runtime_resume = sh_msiof_spi_runtime_nop,
723};
724
725static struct platform_driver sh_msiof_spi_drv = {
726 .probe = sh_msiof_spi_probe,
727 .remove = sh_msiof_spi_remove,
728 .driver = {
729 .name = "spi_sh_msiof",
730 .owner = THIS_MODULE,
731 .pm = &sh_msiof_spi_dev_pm_ops,
732 },
733};
734module_platform_driver(sh_msiof_spi_drv);
735
736MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
737MODULE_AUTHOR("Magnus Damm");
738MODULE_LICENSE("GPL v2");
739MODULE_ALIAS("platform:spi_sh_msiof");
1/*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/bitmap.h>
13#include <linux/clk.h>
14#include <linux/completion.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26
27#include <linux/spi/sh_msiof.h>
28#include <linux/spi/spi.h>
29
30#include <asm/unaligned.h>
31
32
33struct sh_msiof_chipdata {
34 u16 tx_fifo_size;
35 u16 rx_fifo_size;
36 u16 master_flags;
37};
38
39struct sh_msiof_spi_priv {
40 void __iomem *mapbase;
41 struct clk *clk;
42 struct platform_device *pdev;
43 const struct sh_msiof_chipdata *chipdata;
44 struct sh_msiof_spi_info *info;
45 struct completion done;
46 int tx_fifo_size;
47 int rx_fifo_size;
48};
49
50#define TMDR1 0x00 /* Transmit Mode Register 1 */
51#define TMDR2 0x04 /* Transmit Mode Register 2 */
52#define TMDR3 0x08 /* Transmit Mode Register 3 */
53#define RMDR1 0x10 /* Receive Mode Register 1 */
54#define RMDR2 0x14 /* Receive Mode Register 2 */
55#define RMDR3 0x18 /* Receive Mode Register 3 */
56#define TSCR 0x20 /* Transmit Clock Select Register */
57#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
58#define CTR 0x28 /* Control Register */
59#define FCTR 0x30 /* FIFO Control Register */
60#define STR 0x40 /* Status Register */
61#define IER 0x44 /* Interrupt Enable Register */
62#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
63#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
64#define TFDR 0x50 /* Transmit FIFO Data Register */
65#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
66#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
67#define RFDR 0x60 /* Receive FIFO Data Register */
68
69/* TMDR1 and RMDR1 */
70#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
71#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
72#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
73#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
74#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
75#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
76#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
77#define MDR1_FLD_SHIFT 2
78#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
79/* TMDR1 */
80#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
81
82/* TMDR2 and RMDR2 */
83#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
84#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
85#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
86
87/* TSCR and RSCR */
88#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
89#define SCR_BRPS(i) (((i) - 1) << 8)
90#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
91#define SCR_BRDV_DIV_2 0x0000
92#define SCR_BRDV_DIV_4 0x0001
93#define SCR_BRDV_DIV_8 0x0002
94#define SCR_BRDV_DIV_16 0x0003
95#define SCR_BRDV_DIV_32 0x0004
96#define SCR_BRDV_DIV_1 0x0007
97
98/* CTR */
99#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
100#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
101#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
102#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
103#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
104#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
105#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
106#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
107#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
108#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
109#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
110#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
111#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
112#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
113#define CTR_TXE 0x00000200 /* Transmit Enable */
114#define CTR_RXE 0x00000100 /* Receive Enable */
115
116/* STR and IER */
117#define STR_TEOF 0x00800000 /* Frame Transmission End */
118#define STR_REOF 0x00000080 /* Frame Reception End */
119
120
121static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
122{
123 switch (reg_offs) {
124 case TSCR:
125 case RSCR:
126 return ioread16(p->mapbase + reg_offs);
127 default:
128 return ioread32(p->mapbase + reg_offs);
129 }
130}
131
132static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
133 u32 value)
134{
135 switch (reg_offs) {
136 case TSCR:
137 case RSCR:
138 iowrite16(value, p->mapbase + reg_offs);
139 break;
140 default:
141 iowrite32(value, p->mapbase + reg_offs);
142 break;
143 }
144}
145
146static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
147 u32 clr, u32 set)
148{
149 u32 mask = clr | set;
150 u32 data;
151 int k;
152
153 data = sh_msiof_read(p, CTR);
154 data &= ~clr;
155 data |= set;
156 sh_msiof_write(p, CTR, data);
157
158 for (k = 100; k > 0; k--) {
159 if ((sh_msiof_read(p, CTR) & mask) == set)
160 break;
161
162 udelay(10);
163 }
164
165 return k > 0 ? 0 : -ETIMEDOUT;
166}
167
168static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
169{
170 struct sh_msiof_spi_priv *p = data;
171
172 /* just disable the interrupt and wake up */
173 sh_msiof_write(p, IER, 0);
174 complete(&p->done);
175
176 return IRQ_HANDLED;
177}
178
179static struct {
180 unsigned short div;
181 unsigned short scr;
182} const sh_msiof_spi_clk_table[] = {
183 { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
184 { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
185 { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
186 { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
187 { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
188 { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
189 { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
190 { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
191 { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
192 { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
193 { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
194};
195
196static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
197 unsigned long parent_rate, u32 spi_hz)
198{
199 unsigned long div = 1024;
200 size_t k;
201
202 if (!WARN_ON(!spi_hz || !parent_rate))
203 div = DIV_ROUND_UP(parent_rate, spi_hz);
204
205 /* TODO: make more fine grained */
206
207 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
208 if (sh_msiof_spi_clk_table[k].div >= div)
209 break;
210 }
211
212 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
213
214 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
215 if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
216 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
217}
218
219static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
220 u32 cpol, u32 cpha,
221 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
222{
223 u32 tmp;
224 int edge;
225
226 /*
227 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
228 * 0 0 10 10 1 1
229 * 0 1 10 10 0 0
230 * 1 0 11 11 0 0
231 * 1 1 11 11 1 1
232 */
233 sh_msiof_write(p, FCTR, 0);
234
235 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
236 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
237 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
238 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
239 if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
240 /* These bits are reserved if RX needs TX */
241 tmp &= ~0x0000ffff;
242 }
243 sh_msiof_write(p, RMDR1, tmp);
244
245 tmp = 0;
246 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
247 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
248
249 edge = cpol ^ !cpha;
250
251 tmp |= edge << CTR_TEDG_SHIFT;
252 tmp |= edge << CTR_REDG_SHIFT;
253 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
254 sh_msiof_write(p, CTR, tmp);
255}
256
257static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
258 const void *tx_buf, void *rx_buf,
259 u32 bits, u32 words)
260{
261 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
262
263 if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
264 sh_msiof_write(p, TMDR2, dr2);
265 else
266 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
267
268 if (rx_buf)
269 sh_msiof_write(p, RMDR2, dr2);
270
271 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
272}
273
274static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
275{
276 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
277}
278
279static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
280 const void *tx_buf, int words, int fs)
281{
282 const u8 *buf_8 = tx_buf;
283 int k;
284
285 for (k = 0; k < words; k++)
286 sh_msiof_write(p, TFDR, buf_8[k] << fs);
287}
288
289static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
290 const void *tx_buf, int words, int fs)
291{
292 const u16 *buf_16 = tx_buf;
293 int k;
294
295 for (k = 0; k < words; k++)
296 sh_msiof_write(p, TFDR, buf_16[k] << fs);
297}
298
299static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
300 const void *tx_buf, int words, int fs)
301{
302 const u16 *buf_16 = tx_buf;
303 int k;
304
305 for (k = 0; k < words; k++)
306 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
307}
308
309static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
310 const void *tx_buf, int words, int fs)
311{
312 const u32 *buf_32 = tx_buf;
313 int k;
314
315 for (k = 0; k < words; k++)
316 sh_msiof_write(p, TFDR, buf_32[k] << fs);
317}
318
319static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
320 const void *tx_buf, int words, int fs)
321{
322 const u32 *buf_32 = tx_buf;
323 int k;
324
325 for (k = 0; k < words; k++)
326 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
327}
328
329static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
330 const void *tx_buf, int words, int fs)
331{
332 const u32 *buf_32 = tx_buf;
333 int k;
334
335 for (k = 0; k < words; k++)
336 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
337}
338
339static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
340 const void *tx_buf, int words, int fs)
341{
342 const u32 *buf_32 = tx_buf;
343 int k;
344
345 for (k = 0; k < words; k++)
346 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
347}
348
349static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
350 void *rx_buf, int words, int fs)
351{
352 u8 *buf_8 = rx_buf;
353 int k;
354
355 for (k = 0; k < words; k++)
356 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
357}
358
359static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
360 void *rx_buf, int words, int fs)
361{
362 u16 *buf_16 = rx_buf;
363 int k;
364
365 for (k = 0; k < words; k++)
366 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
367}
368
369static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
370 void *rx_buf, int words, int fs)
371{
372 u16 *buf_16 = rx_buf;
373 int k;
374
375 for (k = 0; k < words; k++)
376 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
377}
378
379static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
380 void *rx_buf, int words, int fs)
381{
382 u32 *buf_32 = rx_buf;
383 int k;
384
385 for (k = 0; k < words; k++)
386 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
387}
388
389static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
390 void *rx_buf, int words, int fs)
391{
392 u32 *buf_32 = rx_buf;
393 int k;
394
395 for (k = 0; k < words; k++)
396 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
397}
398
399static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
400 void *rx_buf, int words, int fs)
401{
402 u32 *buf_32 = rx_buf;
403 int k;
404
405 for (k = 0; k < words; k++)
406 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
407}
408
409static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
410 void *rx_buf, int words, int fs)
411{
412 u32 *buf_32 = rx_buf;
413 int k;
414
415 for (k = 0; k < words; k++)
416 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
417}
418
419static int sh_msiof_spi_setup(struct spi_device *spi)
420{
421 struct device_node *np = spi->master->dev.of_node;
422 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
423
424 if (!np) {
425 /*
426 * Use spi->controller_data for CS (same strategy as spi_gpio),
427 * if any. otherwise let HW control CS
428 */
429 spi->cs_gpio = (uintptr_t)spi->controller_data;
430 }
431
432 /* Configure pins before deasserting CS */
433 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
434 !!(spi->mode & SPI_CPHA),
435 !!(spi->mode & SPI_3WIRE),
436 !!(spi->mode & SPI_LSB_FIRST),
437 !!(spi->mode & SPI_CS_HIGH));
438
439 if (spi->cs_gpio >= 0)
440 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
441
442 return 0;
443}
444
445static int sh_msiof_prepare_message(struct spi_master *master,
446 struct spi_message *msg)
447{
448 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
449 const struct spi_device *spi = msg->spi;
450
451 /* Configure pins before asserting CS */
452 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
453 !!(spi->mode & SPI_CPHA),
454 !!(spi->mode & SPI_3WIRE),
455 !!(spi->mode & SPI_LSB_FIRST),
456 !!(spi->mode & SPI_CS_HIGH));
457 return 0;
458}
459
460static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
461 void (*tx_fifo)(struct sh_msiof_spi_priv *,
462 const void *, int, int),
463 void (*rx_fifo)(struct sh_msiof_spi_priv *,
464 void *, int, int),
465 const void *tx_buf, void *rx_buf,
466 int words, int bits)
467{
468 int fifo_shift;
469 int ret;
470
471 /* limit maximum word transfer to rx/tx fifo size */
472 if (tx_buf)
473 words = min_t(int, words, p->tx_fifo_size);
474 if (rx_buf)
475 words = min_t(int, words, p->rx_fifo_size);
476
477 /* the fifo contents need shifting */
478 fifo_shift = 32 - bits;
479
480 /* setup msiof transfer mode registers */
481 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
482
483 /* write tx fifo */
484 if (tx_buf)
485 tx_fifo(p, tx_buf, words, fifo_shift);
486
487 /* setup clock and rx/tx signals */
488 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
489 if (rx_buf)
490 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
491 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
492
493 /* start by setting frame bit */
494 reinit_completion(&p->done);
495 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
496 if (ret) {
497 dev_err(&p->pdev->dev, "failed to start hardware\n");
498 goto err;
499 }
500
501 /* wait for tx fifo to be emptied / rx fifo to be filled */
502 wait_for_completion(&p->done);
503
504 /* read rx fifo */
505 if (rx_buf)
506 rx_fifo(p, rx_buf, words, fifo_shift);
507
508 /* clear status bits */
509 sh_msiof_reset_str(p);
510
511 /* shut down frame, rx/tx and clock signals */
512 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
513 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
514 if (rx_buf)
515 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
516 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
517 if (ret) {
518 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
519 goto err;
520 }
521
522 return words;
523
524 err:
525 sh_msiof_write(p, IER, 0);
526 return ret;
527}
528
529static int sh_msiof_transfer_one(struct spi_master *master,
530 struct spi_device *spi,
531 struct spi_transfer *t)
532{
533 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
534 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
535 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
536 int bits;
537 int bytes_per_word;
538 int bytes_done;
539 int words;
540 int n;
541 bool swab;
542
543 bits = t->bits_per_word;
544
545 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
546 bits = 32;
547 swab = true;
548 } else {
549 swab = false;
550 }
551
552 /* setup bytes per word and fifo read/write functions */
553 if (bits <= 8) {
554 bytes_per_word = 1;
555 tx_fifo = sh_msiof_spi_write_fifo_8;
556 rx_fifo = sh_msiof_spi_read_fifo_8;
557 } else if (bits <= 16) {
558 bytes_per_word = 2;
559 if ((unsigned long)t->tx_buf & 0x01)
560 tx_fifo = sh_msiof_spi_write_fifo_16u;
561 else
562 tx_fifo = sh_msiof_spi_write_fifo_16;
563
564 if ((unsigned long)t->rx_buf & 0x01)
565 rx_fifo = sh_msiof_spi_read_fifo_16u;
566 else
567 rx_fifo = sh_msiof_spi_read_fifo_16;
568 } else if (swab) {
569 bytes_per_word = 4;
570 if ((unsigned long)t->tx_buf & 0x03)
571 tx_fifo = sh_msiof_spi_write_fifo_s32u;
572 else
573 tx_fifo = sh_msiof_spi_write_fifo_s32;
574
575 if ((unsigned long)t->rx_buf & 0x03)
576 rx_fifo = sh_msiof_spi_read_fifo_s32u;
577 else
578 rx_fifo = sh_msiof_spi_read_fifo_s32;
579 } else {
580 bytes_per_word = 4;
581 if ((unsigned long)t->tx_buf & 0x03)
582 tx_fifo = sh_msiof_spi_write_fifo_32u;
583 else
584 tx_fifo = sh_msiof_spi_write_fifo_32;
585
586 if ((unsigned long)t->rx_buf & 0x03)
587 rx_fifo = sh_msiof_spi_read_fifo_32u;
588 else
589 rx_fifo = sh_msiof_spi_read_fifo_32;
590 }
591
592 /* setup clocks (clock already enabled in chipselect()) */
593 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
594
595 /* transfer in fifo sized chunks */
596 words = t->len / bytes_per_word;
597 bytes_done = 0;
598
599 while (bytes_done < t->len) {
600 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
601 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
602 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
603 tx_buf,
604 rx_buf,
605 words, bits);
606 if (n < 0)
607 break;
608
609 bytes_done += n * bytes_per_word;
610 words -= n;
611 }
612
613 return 0;
614}
615
616static const struct sh_msiof_chipdata sh_data = {
617 .tx_fifo_size = 64,
618 .rx_fifo_size = 64,
619 .master_flags = 0,
620};
621
622static const struct sh_msiof_chipdata r8a779x_data = {
623 .tx_fifo_size = 64,
624 .rx_fifo_size = 256,
625 .master_flags = SPI_MASTER_MUST_TX,
626};
627
628static const struct of_device_id sh_msiof_match[] = {
629 { .compatible = "renesas,sh-msiof", .data = &sh_data },
630 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
631 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
632 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
633 {},
634};
635MODULE_DEVICE_TABLE(of, sh_msiof_match);
636
637#ifdef CONFIG_OF
638static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
639{
640 struct sh_msiof_spi_info *info;
641 struct device_node *np = dev->of_node;
642 u32 num_cs = 1;
643
644 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
645 if (!info) {
646 dev_err(dev, "failed to allocate setup data\n");
647 return NULL;
648 }
649
650 /* Parse the MSIOF properties */
651 of_property_read_u32(np, "num-cs", &num_cs);
652 of_property_read_u32(np, "renesas,tx-fifo-size",
653 &info->tx_fifo_override);
654 of_property_read_u32(np, "renesas,rx-fifo-size",
655 &info->rx_fifo_override);
656
657 info->num_chipselect = num_cs;
658
659 return info;
660}
661#else
662static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
663{
664 return NULL;
665}
666#endif
667
668static int sh_msiof_spi_probe(struct platform_device *pdev)
669{
670 struct resource *r;
671 struct spi_master *master;
672 const struct of_device_id *of_id;
673 struct sh_msiof_spi_priv *p;
674 int i;
675 int ret;
676
677 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
678 if (master == NULL) {
679 dev_err(&pdev->dev, "failed to allocate spi master\n");
680 return -ENOMEM;
681 }
682
683 p = spi_master_get_devdata(master);
684
685 platform_set_drvdata(pdev, p);
686
687 of_id = of_match_device(sh_msiof_match, &pdev->dev);
688 if (of_id) {
689 p->chipdata = of_id->data;
690 p->info = sh_msiof_spi_parse_dt(&pdev->dev);
691 } else {
692 p->chipdata = (const void *)pdev->id_entry->driver_data;
693 p->info = dev_get_platdata(&pdev->dev);
694 }
695
696 if (!p->info) {
697 dev_err(&pdev->dev, "failed to obtain device info\n");
698 ret = -ENXIO;
699 goto err1;
700 }
701
702 init_completion(&p->done);
703
704 p->clk = devm_clk_get(&pdev->dev, NULL);
705 if (IS_ERR(p->clk)) {
706 dev_err(&pdev->dev, "cannot get clock\n");
707 ret = PTR_ERR(p->clk);
708 goto err1;
709 }
710
711 i = platform_get_irq(pdev, 0);
712 if (i < 0) {
713 dev_err(&pdev->dev, "cannot get platform IRQ\n");
714 ret = -ENOENT;
715 goto err1;
716 }
717
718 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
720 if (IS_ERR(p->mapbase)) {
721 ret = PTR_ERR(p->mapbase);
722 goto err1;
723 }
724
725 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
726 dev_name(&pdev->dev), p);
727 if (ret) {
728 dev_err(&pdev->dev, "unable to request irq\n");
729 goto err1;
730 }
731
732 p->pdev = pdev;
733 pm_runtime_enable(&pdev->dev);
734
735 /* Platform data may override FIFO sizes */
736 p->tx_fifo_size = p->chipdata->tx_fifo_size;
737 p->rx_fifo_size = p->chipdata->rx_fifo_size;
738 if (p->info->tx_fifo_override)
739 p->tx_fifo_size = p->info->tx_fifo_override;
740 if (p->info->rx_fifo_override)
741 p->rx_fifo_size = p->info->rx_fifo_override;
742
743 /* init master code */
744 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
745 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
746 master->flags = p->chipdata->master_flags;
747 master->bus_num = pdev->id;
748 master->dev.of_node = pdev->dev.of_node;
749 master->num_chipselect = p->info->num_chipselect;
750 master->setup = sh_msiof_spi_setup;
751 master->prepare_message = sh_msiof_prepare_message;
752 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
753 master->auto_runtime_pm = true;
754 master->transfer_one = sh_msiof_transfer_one;
755
756 ret = devm_spi_register_master(&pdev->dev, master);
757 if (ret < 0) {
758 dev_err(&pdev->dev, "spi_register_master error.\n");
759 goto err2;
760 }
761
762 return 0;
763
764 err2:
765 pm_runtime_disable(&pdev->dev);
766 err1:
767 spi_master_put(master);
768 return ret;
769}
770
771static int sh_msiof_spi_remove(struct platform_device *pdev)
772{
773 pm_runtime_disable(&pdev->dev);
774 return 0;
775}
776
777static struct platform_device_id spi_driver_ids[] = {
778 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
779 { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
780 { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
781 {},
782};
783MODULE_DEVICE_TABLE(platform, spi_driver_ids);
784
785static struct platform_driver sh_msiof_spi_drv = {
786 .probe = sh_msiof_spi_probe,
787 .remove = sh_msiof_spi_remove,
788 .id_table = spi_driver_ids,
789 .driver = {
790 .name = "spi_sh_msiof",
791 .owner = THIS_MODULE,
792 .of_match_table = of_match_ptr(sh_msiof_match),
793 },
794};
795module_platform_driver(sh_msiof_spi_drv);
796
797MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
798MODULE_AUTHOR("Magnus Damm");
799MODULE_LICENSE("GPL v2");
800MODULE_ALIAS("platform:spi_sh_msiof");