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1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/slab.h>
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_gpio.h>
40#include <linux/pinctrl/consumer.h>
41
42#include <mach/spi.h>
43
44#define DRIVER_NAME "spi_imx"
45
46#define MXC_CSPIRXDATA 0x00
47#define MXC_CSPITXDATA 0x04
48#define MXC_CSPICTRL 0x08
49#define MXC_CSPIINT 0x0c
50#define MXC_RESET 0x1c
51
52/* generic defines to abstract from the different register layouts */
53#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
54#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
55
56struct spi_imx_config {
57 unsigned int speed_hz;
58 unsigned int bpw;
59 unsigned int mode;
60 u8 cs;
61};
62
63enum spi_imx_devtype {
64 IMX1_CSPI,
65 IMX21_CSPI,
66 IMX27_CSPI,
67 IMX31_CSPI,
68 IMX35_CSPI, /* CSPI on all i.mx except above */
69 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
70};
71
72struct spi_imx_data;
73
74struct spi_imx_devtype_data {
75 void (*intctrl)(struct spi_imx_data *, int);
76 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
77 void (*trigger)(struct spi_imx_data *);
78 int (*rx_available)(struct spi_imx_data *);
79 void (*reset)(struct spi_imx_data *);
80 enum spi_imx_devtype devtype;
81};
82
83struct spi_imx_data {
84 struct spi_bitbang bitbang;
85
86 struct completion xfer_done;
87 void __iomem *base;
88 int irq;
89 struct clk *clk_per;
90 struct clk *clk_ipg;
91 unsigned long spi_clk;
92
93 unsigned int count;
94 void (*tx)(struct spi_imx_data *);
95 void (*rx)(struct spi_imx_data *);
96 void *rx_buf;
97 const void *tx_buf;
98 unsigned int txfifo; /* number of words pushed in tx FIFO */
99
100 struct spi_imx_devtype_data *devtype_data;
101 int chipselect[0];
102};
103
104static inline int is_imx27_cspi(struct spi_imx_data *d)
105{
106 return d->devtype_data->devtype == IMX27_CSPI;
107}
108
109static inline int is_imx35_cspi(struct spi_imx_data *d)
110{
111 return d->devtype_data->devtype == IMX35_CSPI;
112}
113
114static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
115{
116 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
117}
118
119#define MXC_SPI_BUF_RX(type) \
120static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
121{ \
122 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
123 \
124 if (spi_imx->rx_buf) { \
125 *(type *)spi_imx->rx_buf = val; \
126 spi_imx->rx_buf += sizeof(type); \
127 } \
128}
129
130#define MXC_SPI_BUF_TX(type) \
131static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
132{ \
133 type val = 0; \
134 \
135 if (spi_imx->tx_buf) { \
136 val = *(type *)spi_imx->tx_buf; \
137 spi_imx->tx_buf += sizeof(type); \
138 } \
139 \
140 spi_imx->count -= sizeof(type); \
141 \
142 writel(val, spi_imx->base + MXC_CSPITXDATA); \
143}
144
145MXC_SPI_BUF_RX(u8)
146MXC_SPI_BUF_TX(u8)
147MXC_SPI_BUF_RX(u16)
148MXC_SPI_BUF_TX(u16)
149MXC_SPI_BUF_RX(u32)
150MXC_SPI_BUF_TX(u32)
151
152/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
153 * (which is currently not the case in this driver)
154 */
155static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
156 256, 384, 512, 768, 1024};
157
158/* MX21, MX27 */
159static unsigned int spi_imx_clkdiv_1(unsigned int fin,
160 unsigned int fspi, unsigned int max)
161{
162 int i;
163
164 for (i = 2; i < max; i++)
165 if (fspi * mxc_clkdivs[i] >= fin)
166 return i;
167
168 return max;
169}
170
171/* MX1, MX31, MX35, MX51 CSPI */
172static unsigned int spi_imx_clkdiv_2(unsigned int fin,
173 unsigned int fspi)
174{
175 int i, div = 4;
176
177 for (i = 0; i < 7; i++) {
178 if (fspi * div >= fin)
179 return i;
180 div <<= 1;
181 }
182
183 return 7;
184}
185
186#define MX51_ECSPI_CTRL 0x08
187#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
188#define MX51_ECSPI_CTRL_XCH (1 << 2)
189#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
190#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
191#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
192#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
193#define MX51_ECSPI_CTRL_BL_OFFSET 20
194
195#define MX51_ECSPI_CONFIG 0x0c
196#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
197#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
198#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
199#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
200
201#define MX51_ECSPI_INT 0x10
202#define MX51_ECSPI_INT_TEEN (1 << 0)
203#define MX51_ECSPI_INT_RREN (1 << 3)
204
205#define MX51_ECSPI_STAT 0x18
206#define MX51_ECSPI_STAT_RR (1 << 3)
207
208/* MX51 eCSPI */
209static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
210{
211 /*
212 * there are two 4-bit dividers, the pre-divider divides by
213 * $pre, the post-divider by 2^$post
214 */
215 unsigned int pre, post;
216
217 if (unlikely(fspi > fin))
218 return 0;
219
220 post = fls(fin) - fls(fspi);
221 if (fin > fspi << post)
222 post++;
223
224 /* now we have: (fin <= fspi << post) with post being minimal */
225
226 post = max(4U, post) - 4;
227 if (unlikely(post > 0xf)) {
228 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
229 __func__, fspi, fin);
230 return 0xff;
231 }
232
233 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
234
235 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236 __func__, fin, fspi, post, pre);
237 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
238 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
239}
240
241static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
242{
243 unsigned val = 0;
244
245 if (enable & MXC_INT_TE)
246 val |= MX51_ECSPI_INT_TEEN;
247
248 if (enable & MXC_INT_RR)
249 val |= MX51_ECSPI_INT_RREN;
250
251 writel(val, spi_imx->base + MX51_ECSPI_INT);
252}
253
254static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
255{
256 u32 reg;
257
258 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
259 reg |= MX51_ECSPI_CTRL_XCH;
260 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
261}
262
263static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
264 struct spi_imx_config *config)
265{
266 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
267
268 /*
269 * The hardware seems to have a race condition when changing modes. The
270 * current assumption is that the selection of the channel arrives
271 * earlier in the hardware than the mode bits when they are written at
272 * the same time.
273 * So set master mode for all channels as we do not support slave mode.
274 */
275 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
276
277 /* set clock speed */
278 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
279
280 /* set chip select to use */
281 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
282
283 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
284
285 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
286
287 if (config->mode & SPI_CPHA)
288 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
289
290 if (config->mode & SPI_CPOL)
291 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
292
293 if (config->mode & SPI_CS_HIGH)
294 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
295
296 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
297 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
298
299 return 0;
300}
301
302static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
303{
304 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
305}
306
307static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
308{
309 /* drain receive buffer */
310 while (mx51_ecspi_rx_available(spi_imx))
311 readl(spi_imx->base + MXC_CSPIRXDATA);
312}
313
314#define MX31_INTREG_TEEN (1 << 0)
315#define MX31_INTREG_RREN (1 << 3)
316
317#define MX31_CSPICTRL_ENABLE (1 << 0)
318#define MX31_CSPICTRL_MASTER (1 << 1)
319#define MX31_CSPICTRL_XCH (1 << 2)
320#define MX31_CSPICTRL_POL (1 << 4)
321#define MX31_CSPICTRL_PHA (1 << 5)
322#define MX31_CSPICTRL_SSCTL (1 << 6)
323#define MX31_CSPICTRL_SSPOL (1 << 7)
324#define MX31_CSPICTRL_BC_SHIFT 8
325#define MX35_CSPICTRL_BL_SHIFT 20
326#define MX31_CSPICTRL_CS_SHIFT 24
327#define MX35_CSPICTRL_CS_SHIFT 12
328#define MX31_CSPICTRL_DR_SHIFT 16
329
330#define MX31_CSPISTATUS 0x14
331#define MX31_STATUS_RR (1 << 3)
332
333/* These functions also work for the i.MX35, but be aware that
334 * the i.MX35 has a slightly different register layout for bits
335 * we do not use here.
336 */
337static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
338{
339 unsigned int val = 0;
340
341 if (enable & MXC_INT_TE)
342 val |= MX31_INTREG_TEEN;
343 if (enable & MXC_INT_RR)
344 val |= MX31_INTREG_RREN;
345
346 writel(val, spi_imx->base + MXC_CSPIINT);
347}
348
349static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
350{
351 unsigned int reg;
352
353 reg = readl(spi_imx->base + MXC_CSPICTRL);
354 reg |= MX31_CSPICTRL_XCH;
355 writel(reg, spi_imx->base + MXC_CSPICTRL);
356}
357
358static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
359 struct spi_imx_config *config)
360{
361 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
362 int cs = spi_imx->chipselect[config->cs];
363
364 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
365 MX31_CSPICTRL_DR_SHIFT;
366
367 if (is_imx35_cspi(spi_imx)) {
368 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
369 reg |= MX31_CSPICTRL_SSCTL;
370 } else {
371 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
372 }
373
374 if (config->mode & SPI_CPHA)
375 reg |= MX31_CSPICTRL_PHA;
376 if (config->mode & SPI_CPOL)
377 reg |= MX31_CSPICTRL_POL;
378 if (config->mode & SPI_CS_HIGH)
379 reg |= MX31_CSPICTRL_SSPOL;
380 if (cs < 0)
381 reg |= (cs + 32) <<
382 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
383 MX31_CSPICTRL_CS_SHIFT);
384
385 writel(reg, spi_imx->base + MXC_CSPICTRL);
386
387 return 0;
388}
389
390static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
391{
392 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
393}
394
395static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
396{
397 /* drain receive buffer */
398 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
399 readl(spi_imx->base + MXC_CSPIRXDATA);
400}
401
402#define MX21_INTREG_RR (1 << 4)
403#define MX21_INTREG_TEEN (1 << 9)
404#define MX21_INTREG_RREN (1 << 13)
405
406#define MX21_CSPICTRL_POL (1 << 5)
407#define MX21_CSPICTRL_PHA (1 << 6)
408#define MX21_CSPICTRL_SSPOL (1 << 8)
409#define MX21_CSPICTRL_XCH (1 << 9)
410#define MX21_CSPICTRL_ENABLE (1 << 10)
411#define MX21_CSPICTRL_MASTER (1 << 11)
412#define MX21_CSPICTRL_DR_SHIFT 14
413#define MX21_CSPICTRL_CS_SHIFT 19
414
415static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
416{
417 unsigned int val = 0;
418
419 if (enable & MXC_INT_TE)
420 val |= MX21_INTREG_TEEN;
421 if (enable & MXC_INT_RR)
422 val |= MX21_INTREG_RREN;
423
424 writel(val, spi_imx->base + MXC_CSPIINT);
425}
426
427static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
428{
429 unsigned int reg;
430
431 reg = readl(spi_imx->base + MXC_CSPICTRL);
432 reg |= MX21_CSPICTRL_XCH;
433 writel(reg, spi_imx->base + MXC_CSPICTRL);
434}
435
436static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
437 struct spi_imx_config *config)
438{
439 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
440 int cs = spi_imx->chipselect[config->cs];
441 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
442
443 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
444 MX21_CSPICTRL_DR_SHIFT;
445 reg |= config->bpw - 1;
446
447 if (config->mode & SPI_CPHA)
448 reg |= MX21_CSPICTRL_PHA;
449 if (config->mode & SPI_CPOL)
450 reg |= MX21_CSPICTRL_POL;
451 if (config->mode & SPI_CS_HIGH)
452 reg |= MX21_CSPICTRL_SSPOL;
453 if (cs < 0)
454 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
455
456 writel(reg, spi_imx->base + MXC_CSPICTRL);
457
458 return 0;
459}
460
461static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
462{
463 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
464}
465
466static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
467{
468 writel(1, spi_imx->base + MXC_RESET);
469}
470
471#define MX1_INTREG_RR (1 << 3)
472#define MX1_INTREG_TEEN (1 << 8)
473#define MX1_INTREG_RREN (1 << 11)
474
475#define MX1_CSPICTRL_POL (1 << 4)
476#define MX1_CSPICTRL_PHA (1 << 5)
477#define MX1_CSPICTRL_XCH (1 << 8)
478#define MX1_CSPICTRL_ENABLE (1 << 9)
479#define MX1_CSPICTRL_MASTER (1 << 10)
480#define MX1_CSPICTRL_DR_SHIFT 13
481
482static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
483{
484 unsigned int val = 0;
485
486 if (enable & MXC_INT_TE)
487 val |= MX1_INTREG_TEEN;
488 if (enable & MXC_INT_RR)
489 val |= MX1_INTREG_RREN;
490
491 writel(val, spi_imx->base + MXC_CSPIINT);
492}
493
494static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
495{
496 unsigned int reg;
497
498 reg = readl(spi_imx->base + MXC_CSPICTRL);
499 reg |= MX1_CSPICTRL_XCH;
500 writel(reg, spi_imx->base + MXC_CSPICTRL);
501}
502
503static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
504 struct spi_imx_config *config)
505{
506 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
507
508 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
509 MX1_CSPICTRL_DR_SHIFT;
510 reg |= config->bpw - 1;
511
512 if (config->mode & SPI_CPHA)
513 reg |= MX1_CSPICTRL_PHA;
514 if (config->mode & SPI_CPOL)
515 reg |= MX1_CSPICTRL_POL;
516
517 writel(reg, spi_imx->base + MXC_CSPICTRL);
518
519 return 0;
520}
521
522static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
523{
524 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
525}
526
527static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
528{
529 writel(1, spi_imx->base + MXC_RESET);
530}
531
532static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
533 .intctrl = mx1_intctrl,
534 .config = mx1_config,
535 .trigger = mx1_trigger,
536 .rx_available = mx1_rx_available,
537 .reset = mx1_reset,
538 .devtype = IMX1_CSPI,
539};
540
541static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
542 .intctrl = mx21_intctrl,
543 .config = mx21_config,
544 .trigger = mx21_trigger,
545 .rx_available = mx21_rx_available,
546 .reset = mx21_reset,
547 .devtype = IMX21_CSPI,
548};
549
550static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
551 /* i.mx27 cspi shares the functions with i.mx21 one */
552 .intctrl = mx21_intctrl,
553 .config = mx21_config,
554 .trigger = mx21_trigger,
555 .rx_available = mx21_rx_available,
556 .reset = mx21_reset,
557 .devtype = IMX27_CSPI,
558};
559
560static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
561 .intctrl = mx31_intctrl,
562 .config = mx31_config,
563 .trigger = mx31_trigger,
564 .rx_available = mx31_rx_available,
565 .reset = mx31_reset,
566 .devtype = IMX31_CSPI,
567};
568
569static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
570 /* i.mx35 and later cspi shares the functions with i.mx31 one */
571 .intctrl = mx31_intctrl,
572 .config = mx31_config,
573 .trigger = mx31_trigger,
574 .rx_available = mx31_rx_available,
575 .reset = mx31_reset,
576 .devtype = IMX35_CSPI,
577};
578
579static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
580 .intctrl = mx51_ecspi_intctrl,
581 .config = mx51_ecspi_config,
582 .trigger = mx51_ecspi_trigger,
583 .rx_available = mx51_ecspi_rx_available,
584 .reset = mx51_ecspi_reset,
585 .devtype = IMX51_ECSPI,
586};
587
588static struct platform_device_id spi_imx_devtype[] = {
589 {
590 .name = "imx1-cspi",
591 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
592 }, {
593 .name = "imx21-cspi",
594 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
595 }, {
596 .name = "imx27-cspi",
597 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
598 }, {
599 .name = "imx31-cspi",
600 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
601 }, {
602 .name = "imx35-cspi",
603 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
604 }, {
605 .name = "imx51-ecspi",
606 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
607 }, {
608 /* sentinel */
609 }
610};
611
612static const struct of_device_id spi_imx_dt_ids[] = {
613 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
614 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
615 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
616 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
617 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
618 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
619 { /* sentinel */ }
620};
621
622static void spi_imx_chipselect(struct spi_device *spi, int is_active)
623{
624 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
625 int gpio = spi_imx->chipselect[spi->chip_select];
626 int active = is_active != BITBANG_CS_INACTIVE;
627 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
628
629 if (gpio < 0)
630 return;
631
632 gpio_set_value(gpio, dev_is_lowactive ^ active);
633}
634
635static void spi_imx_push(struct spi_imx_data *spi_imx)
636{
637 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
638 if (!spi_imx->count)
639 break;
640 spi_imx->tx(spi_imx);
641 spi_imx->txfifo++;
642 }
643
644 spi_imx->devtype_data->trigger(spi_imx);
645}
646
647static irqreturn_t spi_imx_isr(int irq, void *dev_id)
648{
649 struct spi_imx_data *spi_imx = dev_id;
650
651 while (spi_imx->devtype_data->rx_available(spi_imx)) {
652 spi_imx->rx(spi_imx);
653 spi_imx->txfifo--;
654 }
655
656 if (spi_imx->count) {
657 spi_imx_push(spi_imx);
658 return IRQ_HANDLED;
659 }
660
661 if (spi_imx->txfifo) {
662 /* No data left to push, but still waiting for rx data,
663 * enable receive data available interrupt.
664 */
665 spi_imx->devtype_data->intctrl(
666 spi_imx, MXC_INT_RR);
667 return IRQ_HANDLED;
668 }
669
670 spi_imx->devtype_data->intctrl(spi_imx, 0);
671 complete(&spi_imx->xfer_done);
672
673 return IRQ_HANDLED;
674}
675
676static int spi_imx_setupxfer(struct spi_device *spi,
677 struct spi_transfer *t)
678{
679 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
680 struct spi_imx_config config;
681
682 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
683 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
684 config.mode = spi->mode;
685 config.cs = spi->chip_select;
686
687 if (!config.speed_hz)
688 config.speed_hz = spi->max_speed_hz;
689 if (!config.bpw)
690 config.bpw = spi->bits_per_word;
691 if (!config.speed_hz)
692 config.speed_hz = spi->max_speed_hz;
693
694 /* Initialize the functions for transfer */
695 if (config.bpw <= 8) {
696 spi_imx->rx = spi_imx_buf_rx_u8;
697 spi_imx->tx = spi_imx_buf_tx_u8;
698 } else if (config.bpw <= 16) {
699 spi_imx->rx = spi_imx_buf_rx_u16;
700 spi_imx->tx = spi_imx_buf_tx_u16;
701 } else if (config.bpw <= 32) {
702 spi_imx->rx = spi_imx_buf_rx_u32;
703 spi_imx->tx = spi_imx_buf_tx_u32;
704 } else
705 BUG();
706
707 spi_imx->devtype_data->config(spi_imx, &config);
708
709 return 0;
710}
711
712static int spi_imx_transfer(struct spi_device *spi,
713 struct spi_transfer *transfer)
714{
715 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
716
717 spi_imx->tx_buf = transfer->tx_buf;
718 spi_imx->rx_buf = transfer->rx_buf;
719 spi_imx->count = transfer->len;
720 spi_imx->txfifo = 0;
721
722 init_completion(&spi_imx->xfer_done);
723
724 spi_imx_push(spi_imx);
725
726 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
727
728 wait_for_completion(&spi_imx->xfer_done);
729
730 return transfer->len;
731}
732
733static int spi_imx_setup(struct spi_device *spi)
734{
735 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
736 int gpio = spi_imx->chipselect[spi->chip_select];
737
738 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
739 spi->mode, spi->bits_per_word, spi->max_speed_hz);
740
741 if (gpio >= 0)
742 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
743
744 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
745
746 return 0;
747}
748
749static void spi_imx_cleanup(struct spi_device *spi)
750{
751}
752
753static int __devinit spi_imx_probe(struct platform_device *pdev)
754{
755 struct device_node *np = pdev->dev.of_node;
756 const struct of_device_id *of_id =
757 of_match_device(spi_imx_dt_ids, &pdev->dev);
758 struct spi_imx_master *mxc_platform_info =
759 dev_get_platdata(&pdev->dev);
760 struct spi_master *master;
761 struct spi_imx_data *spi_imx;
762 struct resource *res;
763 struct pinctrl *pinctrl;
764 int i, ret, num_cs;
765
766 if (!np && !mxc_platform_info) {
767 dev_err(&pdev->dev, "can't get the platform data\n");
768 return -EINVAL;
769 }
770
771 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
772 if (ret < 0) {
773 if (mxc_platform_info)
774 num_cs = mxc_platform_info->num_chipselect;
775 else
776 return ret;
777 }
778
779 master = spi_alloc_master(&pdev->dev,
780 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
781 if (!master)
782 return -ENOMEM;
783
784 platform_set_drvdata(pdev, master);
785
786 master->bus_num = pdev->id;
787 master->num_chipselect = num_cs;
788
789 spi_imx = spi_master_get_devdata(master);
790 spi_imx->bitbang.master = spi_master_get(master);
791
792 for (i = 0; i < master->num_chipselect; i++) {
793 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
794 if (cs_gpio < 0 && mxc_platform_info)
795 cs_gpio = mxc_platform_info->chipselect[i];
796
797 spi_imx->chipselect[i] = cs_gpio;
798 if (cs_gpio < 0)
799 continue;
800
801 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
802 if (ret) {
803 dev_err(&pdev->dev, "can't get cs gpios\n");
804 goto out_gpio_free;
805 }
806 }
807
808 spi_imx->bitbang.chipselect = spi_imx_chipselect;
809 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
810 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
811 spi_imx->bitbang.master->setup = spi_imx_setup;
812 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
813 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
814
815 init_completion(&spi_imx->xfer_done);
816
817 spi_imx->devtype_data = of_id ? of_id->data :
818 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
819
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 if (!res) {
822 dev_err(&pdev->dev, "can't get platform resource\n");
823 ret = -ENOMEM;
824 goto out_gpio_free;
825 }
826
827 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
828 dev_err(&pdev->dev, "request_mem_region failed\n");
829 ret = -EBUSY;
830 goto out_gpio_free;
831 }
832
833 spi_imx->base = ioremap(res->start, resource_size(res));
834 if (!spi_imx->base) {
835 ret = -EINVAL;
836 goto out_release_mem;
837 }
838
839 spi_imx->irq = platform_get_irq(pdev, 0);
840 if (spi_imx->irq < 0) {
841 ret = -EINVAL;
842 goto out_iounmap;
843 }
844
845 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
846 if (ret) {
847 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
848 goto out_iounmap;
849 }
850
851 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
852 if (IS_ERR(pinctrl)) {
853 ret = PTR_ERR(pinctrl);
854 goto out_free_irq;
855 }
856
857 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
858 if (IS_ERR(spi_imx->clk_ipg)) {
859 ret = PTR_ERR(spi_imx->clk_ipg);
860 goto out_free_irq;
861 }
862
863 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
864 if (IS_ERR(spi_imx->clk_per)) {
865 ret = PTR_ERR(spi_imx->clk_per);
866 goto out_free_irq;
867 }
868
869 clk_prepare_enable(spi_imx->clk_per);
870 clk_prepare_enable(spi_imx->clk_ipg);
871
872 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
873
874 spi_imx->devtype_data->reset(spi_imx);
875
876 spi_imx->devtype_data->intctrl(spi_imx, 0);
877
878 master->dev.of_node = pdev->dev.of_node;
879 ret = spi_bitbang_start(&spi_imx->bitbang);
880 if (ret) {
881 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
882 goto out_clk_put;
883 }
884
885 dev_info(&pdev->dev, "probed\n");
886
887 return ret;
888
889out_clk_put:
890 clk_disable_unprepare(spi_imx->clk_per);
891 clk_disable_unprepare(spi_imx->clk_ipg);
892out_free_irq:
893 free_irq(spi_imx->irq, spi_imx);
894out_iounmap:
895 iounmap(spi_imx->base);
896out_release_mem:
897 release_mem_region(res->start, resource_size(res));
898out_gpio_free:
899 while (--i >= 0) {
900 if (spi_imx->chipselect[i] >= 0)
901 gpio_free(spi_imx->chipselect[i]);
902 }
903 spi_master_put(master);
904 kfree(master);
905 platform_set_drvdata(pdev, NULL);
906 return ret;
907}
908
909static int __devexit spi_imx_remove(struct platform_device *pdev)
910{
911 struct spi_master *master = platform_get_drvdata(pdev);
912 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
913 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
914 int i;
915
916 spi_bitbang_stop(&spi_imx->bitbang);
917
918 writel(0, spi_imx->base + MXC_CSPICTRL);
919 clk_disable_unprepare(spi_imx->clk_per);
920 clk_disable_unprepare(spi_imx->clk_ipg);
921 free_irq(spi_imx->irq, spi_imx);
922 iounmap(spi_imx->base);
923
924 for (i = 0; i < master->num_chipselect; i++)
925 if (spi_imx->chipselect[i] >= 0)
926 gpio_free(spi_imx->chipselect[i]);
927
928 spi_master_put(master);
929
930 release_mem_region(res->start, resource_size(res));
931
932 platform_set_drvdata(pdev, NULL);
933
934 return 0;
935}
936
937static struct platform_driver spi_imx_driver = {
938 .driver = {
939 .name = DRIVER_NAME,
940 .owner = THIS_MODULE,
941 .of_match_table = spi_imx_dt_ids,
942 },
943 .id_table = spi_imx_devtype,
944 .probe = spi_imx_probe,
945 .remove = __devexit_p(spi_imx_remove),
946};
947module_platform_driver(spi_imx_driver);
948
949MODULE_DESCRIPTION("SPI Master Controller driver");
950MODULE_AUTHOR("Sascha Hauer, Pengutronix");
951MODULE_LICENSE("GPL");
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35#include <linux/types.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/of_gpio.h>
39
40#include <linux/platform_data/spi-imx.h>
41
42#define DRIVER_NAME "spi_imx"
43
44#define MXC_CSPIRXDATA 0x00
45#define MXC_CSPITXDATA 0x04
46#define MXC_CSPICTRL 0x08
47#define MXC_CSPIINT 0x0c
48#define MXC_RESET 0x1c
49
50/* generic defines to abstract from the different register layouts */
51#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
52#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
53
54struct spi_imx_config {
55 unsigned int speed_hz;
56 unsigned int bpw;
57 unsigned int mode;
58 u8 cs;
59};
60
61enum spi_imx_devtype {
62 IMX1_CSPI,
63 IMX21_CSPI,
64 IMX27_CSPI,
65 IMX31_CSPI,
66 IMX35_CSPI, /* CSPI on all i.mx except above */
67 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
68};
69
70struct spi_imx_data;
71
72struct spi_imx_devtype_data {
73 void (*intctrl)(struct spi_imx_data *, int);
74 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
75 void (*trigger)(struct spi_imx_data *);
76 int (*rx_available)(struct spi_imx_data *);
77 void (*reset)(struct spi_imx_data *);
78 enum spi_imx_devtype devtype;
79};
80
81struct spi_imx_data {
82 struct spi_bitbang bitbang;
83
84 struct completion xfer_done;
85 void __iomem *base;
86 int irq;
87 struct clk *clk_per;
88 struct clk *clk_ipg;
89 unsigned long spi_clk;
90
91 unsigned int count;
92 void (*tx)(struct spi_imx_data *);
93 void (*rx)(struct spi_imx_data *);
94 void *rx_buf;
95 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */
97
98 const struct spi_imx_devtype_data *devtype_data;
99 int chipselect[0];
100};
101
102static inline int is_imx27_cspi(struct spi_imx_data *d)
103{
104 return d->devtype_data->devtype == IMX27_CSPI;
105}
106
107static inline int is_imx35_cspi(struct spi_imx_data *d)
108{
109 return d->devtype_data->devtype == IMX35_CSPI;
110}
111
112static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
113{
114 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
115}
116
117#define MXC_SPI_BUF_RX(type) \
118static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
119{ \
120 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
121 \
122 if (spi_imx->rx_buf) { \
123 *(type *)spi_imx->rx_buf = val; \
124 spi_imx->rx_buf += sizeof(type); \
125 } \
126}
127
128#define MXC_SPI_BUF_TX(type) \
129static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
130{ \
131 type val = 0; \
132 \
133 if (spi_imx->tx_buf) { \
134 val = *(type *)spi_imx->tx_buf; \
135 spi_imx->tx_buf += sizeof(type); \
136 } \
137 \
138 spi_imx->count -= sizeof(type); \
139 \
140 writel(val, spi_imx->base + MXC_CSPITXDATA); \
141}
142
143MXC_SPI_BUF_RX(u8)
144MXC_SPI_BUF_TX(u8)
145MXC_SPI_BUF_RX(u16)
146MXC_SPI_BUF_TX(u16)
147MXC_SPI_BUF_RX(u32)
148MXC_SPI_BUF_TX(u32)
149
150/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
151 * (which is currently not the case in this driver)
152 */
153static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
154 256, 384, 512, 768, 1024};
155
156/* MX21, MX27 */
157static unsigned int spi_imx_clkdiv_1(unsigned int fin,
158 unsigned int fspi, unsigned int max)
159{
160 int i;
161
162 for (i = 2; i < max; i++)
163 if (fspi * mxc_clkdivs[i] >= fin)
164 return i;
165
166 return max;
167}
168
169/* MX1, MX31, MX35, MX51 CSPI */
170static unsigned int spi_imx_clkdiv_2(unsigned int fin,
171 unsigned int fspi)
172{
173 int i, div = 4;
174
175 for (i = 0; i < 7; i++) {
176 if (fspi * div >= fin)
177 return i;
178 div <<= 1;
179 }
180
181 return 7;
182}
183
184#define MX51_ECSPI_CTRL 0x08
185#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
186#define MX51_ECSPI_CTRL_XCH (1 << 2)
187#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
188#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
189#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
190#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
191#define MX51_ECSPI_CTRL_BL_OFFSET 20
192
193#define MX51_ECSPI_CONFIG 0x0c
194#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
195#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
196#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
197#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
198#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
199
200#define MX51_ECSPI_INT 0x10
201#define MX51_ECSPI_INT_TEEN (1 << 0)
202#define MX51_ECSPI_INT_RREN (1 << 3)
203
204#define MX51_ECSPI_STAT 0x18
205#define MX51_ECSPI_STAT_RR (1 << 3)
206
207/* MX51 eCSPI */
208static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
209 unsigned int *fres)
210{
211 /*
212 * there are two 4-bit dividers, the pre-divider divides by
213 * $pre, the post-divider by 2^$post
214 */
215 unsigned int pre, post;
216
217 if (unlikely(fspi > fin))
218 return 0;
219
220 post = fls(fin) - fls(fspi);
221 if (fin > fspi << post)
222 post++;
223
224 /* now we have: (fin <= fspi << post) with post being minimal */
225
226 post = max(4U, post) - 4;
227 if (unlikely(post > 0xf)) {
228 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
229 __func__, fspi, fin);
230 return 0xff;
231 }
232
233 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
234
235 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
236 __func__, fin, fspi, post, pre);
237
238 /* Resulting frequency for the SCLK line. */
239 *fres = (fin / (pre + 1)) >> post;
240
241 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
242 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
243}
244
245static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
246{
247 unsigned val = 0;
248
249 if (enable & MXC_INT_TE)
250 val |= MX51_ECSPI_INT_TEEN;
251
252 if (enable & MXC_INT_RR)
253 val |= MX51_ECSPI_INT_RREN;
254
255 writel(val, spi_imx->base + MX51_ECSPI_INT);
256}
257
258static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
259{
260 u32 reg;
261
262 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
263 reg |= MX51_ECSPI_CTRL_XCH;
264 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
265}
266
267static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
268 struct spi_imx_config *config)
269{
270 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
271 u32 clk = config->speed_hz, delay;
272
273 /*
274 * The hardware seems to have a race condition when changing modes. The
275 * current assumption is that the selection of the channel arrives
276 * earlier in the hardware than the mode bits when they are written at
277 * the same time.
278 * So set master mode for all channels as we do not support slave mode.
279 */
280 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
281
282 /* set clock speed */
283 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
284
285 /* set chip select to use */
286 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
287
288 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
289
290 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
291
292 if (config->mode & SPI_CPHA)
293 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
294
295 if (config->mode & SPI_CPOL) {
296 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
297 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
298 }
299 if (config->mode & SPI_CS_HIGH)
300 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
301
302 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
303 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
304
305 /*
306 * Wait until the changes in the configuration register CONFIGREG
307 * propagate into the hardware. It takes exactly one tick of the
308 * SCLK clock, but we will wait two SCLK clock just to be sure. The
309 * effect of the delay it takes for the hardware to apply changes
310 * is noticable if the SCLK clock run very slow. In such a case, if
311 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
312 * be asserted before the SCLK polarity changes, which would disrupt
313 * the SPI communication as the device on the other end would consider
314 * the change of SCLK polarity as a clock tick already.
315 */
316 delay = (2 * 1000000) / clk;
317 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
318 udelay(delay);
319 else /* SCLK is _very_ slow */
320 usleep_range(delay, delay + 10);
321
322 return 0;
323}
324
325static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
326{
327 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
328}
329
330static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
331{
332 /* drain receive buffer */
333 while (mx51_ecspi_rx_available(spi_imx))
334 readl(spi_imx->base + MXC_CSPIRXDATA);
335}
336
337#define MX31_INTREG_TEEN (1 << 0)
338#define MX31_INTREG_RREN (1 << 3)
339
340#define MX31_CSPICTRL_ENABLE (1 << 0)
341#define MX31_CSPICTRL_MASTER (1 << 1)
342#define MX31_CSPICTRL_XCH (1 << 2)
343#define MX31_CSPICTRL_POL (1 << 4)
344#define MX31_CSPICTRL_PHA (1 << 5)
345#define MX31_CSPICTRL_SSCTL (1 << 6)
346#define MX31_CSPICTRL_SSPOL (1 << 7)
347#define MX31_CSPICTRL_BC_SHIFT 8
348#define MX35_CSPICTRL_BL_SHIFT 20
349#define MX31_CSPICTRL_CS_SHIFT 24
350#define MX35_CSPICTRL_CS_SHIFT 12
351#define MX31_CSPICTRL_DR_SHIFT 16
352
353#define MX31_CSPISTATUS 0x14
354#define MX31_STATUS_RR (1 << 3)
355
356/* These functions also work for the i.MX35, but be aware that
357 * the i.MX35 has a slightly different register layout for bits
358 * we do not use here.
359 */
360static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
361{
362 unsigned int val = 0;
363
364 if (enable & MXC_INT_TE)
365 val |= MX31_INTREG_TEEN;
366 if (enable & MXC_INT_RR)
367 val |= MX31_INTREG_RREN;
368
369 writel(val, spi_imx->base + MXC_CSPIINT);
370}
371
372static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
373{
374 unsigned int reg;
375
376 reg = readl(spi_imx->base + MXC_CSPICTRL);
377 reg |= MX31_CSPICTRL_XCH;
378 writel(reg, spi_imx->base + MXC_CSPICTRL);
379}
380
381static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
382 struct spi_imx_config *config)
383{
384 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
385 int cs = spi_imx->chipselect[config->cs];
386
387 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
388 MX31_CSPICTRL_DR_SHIFT;
389
390 if (is_imx35_cspi(spi_imx)) {
391 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
392 reg |= MX31_CSPICTRL_SSCTL;
393 } else {
394 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
395 }
396
397 if (config->mode & SPI_CPHA)
398 reg |= MX31_CSPICTRL_PHA;
399 if (config->mode & SPI_CPOL)
400 reg |= MX31_CSPICTRL_POL;
401 if (config->mode & SPI_CS_HIGH)
402 reg |= MX31_CSPICTRL_SSPOL;
403 if (cs < 0)
404 reg |= (cs + 32) <<
405 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
406 MX31_CSPICTRL_CS_SHIFT);
407
408 writel(reg, spi_imx->base + MXC_CSPICTRL);
409
410 return 0;
411}
412
413static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
414{
415 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
416}
417
418static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
419{
420 /* drain receive buffer */
421 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
422 readl(spi_imx->base + MXC_CSPIRXDATA);
423}
424
425#define MX21_INTREG_RR (1 << 4)
426#define MX21_INTREG_TEEN (1 << 9)
427#define MX21_INTREG_RREN (1 << 13)
428
429#define MX21_CSPICTRL_POL (1 << 5)
430#define MX21_CSPICTRL_PHA (1 << 6)
431#define MX21_CSPICTRL_SSPOL (1 << 8)
432#define MX21_CSPICTRL_XCH (1 << 9)
433#define MX21_CSPICTRL_ENABLE (1 << 10)
434#define MX21_CSPICTRL_MASTER (1 << 11)
435#define MX21_CSPICTRL_DR_SHIFT 14
436#define MX21_CSPICTRL_CS_SHIFT 19
437
438static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
439{
440 unsigned int val = 0;
441
442 if (enable & MXC_INT_TE)
443 val |= MX21_INTREG_TEEN;
444 if (enable & MXC_INT_RR)
445 val |= MX21_INTREG_RREN;
446
447 writel(val, spi_imx->base + MXC_CSPIINT);
448}
449
450static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
451{
452 unsigned int reg;
453
454 reg = readl(spi_imx->base + MXC_CSPICTRL);
455 reg |= MX21_CSPICTRL_XCH;
456 writel(reg, spi_imx->base + MXC_CSPICTRL);
457}
458
459static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
460 struct spi_imx_config *config)
461{
462 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
463 int cs = spi_imx->chipselect[config->cs];
464 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
465
466 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
467 MX21_CSPICTRL_DR_SHIFT;
468 reg |= config->bpw - 1;
469
470 if (config->mode & SPI_CPHA)
471 reg |= MX21_CSPICTRL_PHA;
472 if (config->mode & SPI_CPOL)
473 reg |= MX21_CSPICTRL_POL;
474 if (config->mode & SPI_CS_HIGH)
475 reg |= MX21_CSPICTRL_SSPOL;
476 if (cs < 0)
477 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
478
479 writel(reg, spi_imx->base + MXC_CSPICTRL);
480
481 return 0;
482}
483
484static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
485{
486 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
487}
488
489static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
490{
491 writel(1, spi_imx->base + MXC_RESET);
492}
493
494#define MX1_INTREG_RR (1 << 3)
495#define MX1_INTREG_TEEN (1 << 8)
496#define MX1_INTREG_RREN (1 << 11)
497
498#define MX1_CSPICTRL_POL (1 << 4)
499#define MX1_CSPICTRL_PHA (1 << 5)
500#define MX1_CSPICTRL_XCH (1 << 8)
501#define MX1_CSPICTRL_ENABLE (1 << 9)
502#define MX1_CSPICTRL_MASTER (1 << 10)
503#define MX1_CSPICTRL_DR_SHIFT 13
504
505static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
506{
507 unsigned int val = 0;
508
509 if (enable & MXC_INT_TE)
510 val |= MX1_INTREG_TEEN;
511 if (enable & MXC_INT_RR)
512 val |= MX1_INTREG_RREN;
513
514 writel(val, spi_imx->base + MXC_CSPIINT);
515}
516
517static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
518{
519 unsigned int reg;
520
521 reg = readl(spi_imx->base + MXC_CSPICTRL);
522 reg |= MX1_CSPICTRL_XCH;
523 writel(reg, spi_imx->base + MXC_CSPICTRL);
524}
525
526static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
527 struct spi_imx_config *config)
528{
529 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
530
531 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
532 MX1_CSPICTRL_DR_SHIFT;
533 reg |= config->bpw - 1;
534
535 if (config->mode & SPI_CPHA)
536 reg |= MX1_CSPICTRL_PHA;
537 if (config->mode & SPI_CPOL)
538 reg |= MX1_CSPICTRL_POL;
539
540 writel(reg, spi_imx->base + MXC_CSPICTRL);
541
542 return 0;
543}
544
545static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
546{
547 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
548}
549
550static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
551{
552 writel(1, spi_imx->base + MXC_RESET);
553}
554
555static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
556 .intctrl = mx1_intctrl,
557 .config = mx1_config,
558 .trigger = mx1_trigger,
559 .rx_available = mx1_rx_available,
560 .reset = mx1_reset,
561 .devtype = IMX1_CSPI,
562};
563
564static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
565 .intctrl = mx21_intctrl,
566 .config = mx21_config,
567 .trigger = mx21_trigger,
568 .rx_available = mx21_rx_available,
569 .reset = mx21_reset,
570 .devtype = IMX21_CSPI,
571};
572
573static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
574 /* i.mx27 cspi shares the functions with i.mx21 one */
575 .intctrl = mx21_intctrl,
576 .config = mx21_config,
577 .trigger = mx21_trigger,
578 .rx_available = mx21_rx_available,
579 .reset = mx21_reset,
580 .devtype = IMX27_CSPI,
581};
582
583static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
584 .intctrl = mx31_intctrl,
585 .config = mx31_config,
586 .trigger = mx31_trigger,
587 .rx_available = mx31_rx_available,
588 .reset = mx31_reset,
589 .devtype = IMX31_CSPI,
590};
591
592static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
593 /* i.mx35 and later cspi shares the functions with i.mx31 one */
594 .intctrl = mx31_intctrl,
595 .config = mx31_config,
596 .trigger = mx31_trigger,
597 .rx_available = mx31_rx_available,
598 .reset = mx31_reset,
599 .devtype = IMX35_CSPI,
600};
601
602static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
603 .intctrl = mx51_ecspi_intctrl,
604 .config = mx51_ecspi_config,
605 .trigger = mx51_ecspi_trigger,
606 .rx_available = mx51_ecspi_rx_available,
607 .reset = mx51_ecspi_reset,
608 .devtype = IMX51_ECSPI,
609};
610
611static struct platform_device_id spi_imx_devtype[] = {
612 {
613 .name = "imx1-cspi",
614 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
615 }, {
616 .name = "imx21-cspi",
617 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
618 }, {
619 .name = "imx27-cspi",
620 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
621 }, {
622 .name = "imx31-cspi",
623 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
624 }, {
625 .name = "imx35-cspi",
626 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
627 }, {
628 .name = "imx51-ecspi",
629 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
630 }, {
631 /* sentinel */
632 }
633};
634
635static const struct of_device_id spi_imx_dt_ids[] = {
636 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
637 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
638 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
639 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
640 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
641 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
642 { /* sentinel */ }
643};
644MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
645
646static void spi_imx_chipselect(struct spi_device *spi, int is_active)
647{
648 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
649 int gpio = spi_imx->chipselect[spi->chip_select];
650 int active = is_active != BITBANG_CS_INACTIVE;
651 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
652
653 if (!gpio_is_valid(gpio))
654 return;
655
656 gpio_set_value(gpio, dev_is_lowactive ^ active);
657}
658
659static void spi_imx_push(struct spi_imx_data *spi_imx)
660{
661 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
662 if (!spi_imx->count)
663 break;
664 spi_imx->tx(spi_imx);
665 spi_imx->txfifo++;
666 }
667
668 spi_imx->devtype_data->trigger(spi_imx);
669}
670
671static irqreturn_t spi_imx_isr(int irq, void *dev_id)
672{
673 struct spi_imx_data *spi_imx = dev_id;
674
675 while (spi_imx->devtype_data->rx_available(spi_imx)) {
676 spi_imx->rx(spi_imx);
677 spi_imx->txfifo--;
678 }
679
680 if (spi_imx->count) {
681 spi_imx_push(spi_imx);
682 return IRQ_HANDLED;
683 }
684
685 if (spi_imx->txfifo) {
686 /* No data left to push, but still waiting for rx data,
687 * enable receive data available interrupt.
688 */
689 spi_imx->devtype_data->intctrl(
690 spi_imx, MXC_INT_RR);
691 return IRQ_HANDLED;
692 }
693
694 spi_imx->devtype_data->intctrl(spi_imx, 0);
695 complete(&spi_imx->xfer_done);
696
697 return IRQ_HANDLED;
698}
699
700static int spi_imx_setupxfer(struct spi_device *spi,
701 struct spi_transfer *t)
702{
703 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
704 struct spi_imx_config config;
705
706 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
707 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
708 config.mode = spi->mode;
709 config.cs = spi->chip_select;
710
711 if (!config.speed_hz)
712 config.speed_hz = spi->max_speed_hz;
713 if (!config.bpw)
714 config.bpw = spi->bits_per_word;
715
716 /* Initialize the functions for transfer */
717 if (config.bpw <= 8) {
718 spi_imx->rx = spi_imx_buf_rx_u8;
719 spi_imx->tx = spi_imx_buf_tx_u8;
720 } else if (config.bpw <= 16) {
721 spi_imx->rx = spi_imx_buf_rx_u16;
722 spi_imx->tx = spi_imx_buf_tx_u16;
723 } else {
724 spi_imx->rx = spi_imx_buf_rx_u32;
725 spi_imx->tx = spi_imx_buf_tx_u32;
726 }
727
728 spi_imx->devtype_data->config(spi_imx, &config);
729
730 return 0;
731}
732
733static int spi_imx_transfer(struct spi_device *spi,
734 struct spi_transfer *transfer)
735{
736 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
737
738 spi_imx->tx_buf = transfer->tx_buf;
739 spi_imx->rx_buf = transfer->rx_buf;
740 spi_imx->count = transfer->len;
741 spi_imx->txfifo = 0;
742
743 reinit_completion(&spi_imx->xfer_done);
744
745 spi_imx_push(spi_imx);
746
747 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
748
749 wait_for_completion(&spi_imx->xfer_done);
750
751 return transfer->len;
752}
753
754static int spi_imx_setup(struct spi_device *spi)
755{
756 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
757 int gpio = spi_imx->chipselect[spi->chip_select];
758
759 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
760 spi->mode, spi->bits_per_word, spi->max_speed_hz);
761
762 if (gpio_is_valid(gpio))
763 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
764
765 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
766
767 return 0;
768}
769
770static void spi_imx_cleanup(struct spi_device *spi)
771{
772}
773
774static int
775spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
776{
777 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
778 int ret;
779
780 ret = clk_enable(spi_imx->clk_per);
781 if (ret)
782 return ret;
783
784 ret = clk_enable(spi_imx->clk_ipg);
785 if (ret) {
786 clk_disable(spi_imx->clk_per);
787 return ret;
788 }
789
790 return 0;
791}
792
793static int
794spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
795{
796 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
797
798 clk_disable(spi_imx->clk_ipg);
799 clk_disable(spi_imx->clk_per);
800 return 0;
801}
802
803static int spi_imx_probe(struct platform_device *pdev)
804{
805 struct device_node *np = pdev->dev.of_node;
806 const struct of_device_id *of_id =
807 of_match_device(spi_imx_dt_ids, &pdev->dev);
808 struct spi_imx_master *mxc_platform_info =
809 dev_get_platdata(&pdev->dev);
810 struct spi_master *master;
811 struct spi_imx_data *spi_imx;
812 struct resource *res;
813 int i, ret, num_cs;
814
815 if (!np && !mxc_platform_info) {
816 dev_err(&pdev->dev, "can't get the platform data\n");
817 return -EINVAL;
818 }
819
820 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
821 if (ret < 0) {
822 if (mxc_platform_info)
823 num_cs = mxc_platform_info->num_chipselect;
824 else
825 return ret;
826 }
827
828 master = spi_alloc_master(&pdev->dev,
829 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
830 if (!master)
831 return -ENOMEM;
832
833 platform_set_drvdata(pdev, master);
834
835 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
836 master->bus_num = pdev->id;
837 master->num_chipselect = num_cs;
838
839 spi_imx = spi_master_get_devdata(master);
840 spi_imx->bitbang.master = master;
841
842 for (i = 0; i < master->num_chipselect; i++) {
843 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
844 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
845 cs_gpio = mxc_platform_info->chipselect[i];
846
847 spi_imx->chipselect[i] = cs_gpio;
848 if (!gpio_is_valid(cs_gpio))
849 continue;
850
851 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
852 DRIVER_NAME);
853 if (ret) {
854 dev_err(&pdev->dev, "can't get cs gpios\n");
855 goto out_master_put;
856 }
857 }
858
859 spi_imx->bitbang.chipselect = spi_imx_chipselect;
860 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
861 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
862 spi_imx->bitbang.master->setup = spi_imx_setup;
863 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
864 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
865 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
866 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
867
868 init_completion(&spi_imx->xfer_done);
869
870 spi_imx->devtype_data = of_id ? of_id->data :
871 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
872
873 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
874 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
875 if (IS_ERR(spi_imx->base)) {
876 ret = PTR_ERR(spi_imx->base);
877 goto out_master_put;
878 }
879
880 spi_imx->irq = platform_get_irq(pdev, 0);
881 if (spi_imx->irq < 0) {
882 ret = spi_imx->irq;
883 goto out_master_put;
884 }
885
886 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
887 dev_name(&pdev->dev), spi_imx);
888 if (ret) {
889 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
890 goto out_master_put;
891 }
892
893 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
894 if (IS_ERR(spi_imx->clk_ipg)) {
895 ret = PTR_ERR(spi_imx->clk_ipg);
896 goto out_master_put;
897 }
898
899 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
900 if (IS_ERR(spi_imx->clk_per)) {
901 ret = PTR_ERR(spi_imx->clk_per);
902 goto out_master_put;
903 }
904
905 ret = clk_prepare_enable(spi_imx->clk_per);
906 if (ret)
907 goto out_master_put;
908
909 ret = clk_prepare_enable(spi_imx->clk_ipg);
910 if (ret)
911 goto out_put_per;
912
913 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
914
915 spi_imx->devtype_data->reset(spi_imx);
916
917 spi_imx->devtype_data->intctrl(spi_imx, 0);
918
919 master->dev.of_node = pdev->dev.of_node;
920 ret = spi_bitbang_start(&spi_imx->bitbang);
921 if (ret) {
922 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
923 goto out_clk_put;
924 }
925
926 dev_info(&pdev->dev, "probed\n");
927
928 clk_disable(spi_imx->clk_ipg);
929 clk_disable(spi_imx->clk_per);
930 return ret;
931
932out_clk_put:
933 clk_disable_unprepare(spi_imx->clk_ipg);
934out_put_per:
935 clk_disable_unprepare(spi_imx->clk_per);
936out_master_put:
937 spi_master_put(master);
938
939 return ret;
940}
941
942static int spi_imx_remove(struct platform_device *pdev)
943{
944 struct spi_master *master = platform_get_drvdata(pdev);
945 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
946
947 spi_bitbang_stop(&spi_imx->bitbang);
948
949 writel(0, spi_imx->base + MXC_CSPICTRL);
950 clk_unprepare(spi_imx->clk_ipg);
951 clk_unprepare(spi_imx->clk_per);
952 spi_master_put(master);
953
954 return 0;
955}
956
957static struct platform_driver spi_imx_driver = {
958 .driver = {
959 .name = DRIVER_NAME,
960 .owner = THIS_MODULE,
961 .of_match_table = spi_imx_dt_ids,
962 },
963 .id_table = spi_imx_devtype,
964 .probe = spi_imx_probe,
965 .remove = spi_imx_remove,
966};
967module_platform_driver(spi_imx_driver);
968
969MODULE_DESCRIPTION("SPI Master Controller driver");
970MODULE_AUTHOR("Sascha Hauer, Pengutronix");
971MODULE_LICENSE("GPL");
972MODULE_ALIAS("platform:" DRIVER_NAME);