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1/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/module.h>
34#include <linux/pm_domain.h>
35
36struct sh_mtu2_priv {
37 void __iomem *mapbase;
38 struct clk *clk;
39 struct irqaction irqaction;
40 struct platform_device *pdev;
41 unsigned long rate;
42 unsigned long periodic;
43 struct clock_event_device ced;
44};
45
46static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
47
48#define TSTR -1 /* shared register */
49#define TCR 0 /* channel register */
50#define TMDR 1 /* channel register */
51#define TIOR 2 /* channel register */
52#define TIER 3 /* channel register */
53#define TSR 4 /* channel register */
54#define TCNT 5 /* channel register */
55#define TGR 6 /* channel register */
56
57static unsigned long mtu2_reg_offs[] = {
58 [TCR] = 0,
59 [TMDR] = 1,
60 [TIOR] = 2,
61 [TIER] = 4,
62 [TSR] = 5,
63 [TCNT] = 6,
64 [TGR] = 8,
65};
66
67static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
68{
69 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
70 void __iomem *base = p->mapbase;
71 unsigned long offs;
72
73 if (reg_nr == TSTR)
74 return ioread8(base + cfg->channel_offset);
75
76 offs = mtu2_reg_offs[reg_nr];
77
78 if ((reg_nr == TCNT) || (reg_nr == TGR))
79 return ioread16(base + offs);
80 else
81 return ioread8(base + offs);
82}
83
84static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
85 unsigned long value)
86{
87 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
88 void __iomem *base = p->mapbase;
89 unsigned long offs;
90
91 if (reg_nr == TSTR) {
92 iowrite8(value, base + cfg->channel_offset);
93 return;
94 }
95
96 offs = mtu2_reg_offs[reg_nr];
97
98 if ((reg_nr == TCNT) || (reg_nr == TGR))
99 iowrite16(value, base + offs);
100 else
101 iowrite8(value, base + offs);
102}
103
104static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
105{
106 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
107 unsigned long flags, value;
108
109 /* start stop register shared by multiple timer channels */
110 raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
111 value = sh_mtu2_read(p, TSTR);
112
113 if (start)
114 value |= 1 << cfg->timer_bit;
115 else
116 value &= ~(1 << cfg->timer_bit);
117
118 sh_mtu2_write(p, TSTR, value);
119 raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
120}
121
122static int sh_mtu2_enable(struct sh_mtu2_priv *p)
123{
124 int ret;
125
126 /* enable clock */
127 ret = clk_enable(p->clk);
128 if (ret) {
129 dev_err(&p->pdev->dev, "cannot enable clock\n");
130 return ret;
131 }
132
133 /* make sure channel is disabled */
134 sh_mtu2_start_stop_ch(p, 0);
135
136 p->rate = clk_get_rate(p->clk) / 64;
137 p->periodic = (p->rate + HZ/2) / HZ;
138
139 /* "Periodic Counter Operation" */
140 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
141 sh_mtu2_write(p, TIOR, 0);
142 sh_mtu2_write(p, TGR, p->periodic);
143 sh_mtu2_write(p, TCNT, 0);
144 sh_mtu2_write(p, TMDR, 0);
145 sh_mtu2_write(p, TIER, 0x01);
146
147 /* enable channel */
148 sh_mtu2_start_stop_ch(p, 1);
149
150 return 0;
151}
152
153static void sh_mtu2_disable(struct sh_mtu2_priv *p)
154{
155 /* disable channel */
156 sh_mtu2_start_stop_ch(p, 0);
157
158 /* stop clock */
159 clk_disable(p->clk);
160}
161
162static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
163{
164 struct sh_mtu2_priv *p = dev_id;
165
166 /* acknowledge interrupt */
167 sh_mtu2_read(p, TSR);
168 sh_mtu2_write(p, TSR, 0xfe);
169
170 /* notify clockevent layer */
171 p->ced.event_handler(&p->ced);
172 return IRQ_HANDLED;
173}
174
175static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
176{
177 return container_of(ced, struct sh_mtu2_priv, ced);
178}
179
180static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
181 struct clock_event_device *ced)
182{
183 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
184 int disabled = 0;
185
186 /* deal with old setting first */
187 switch (ced->mode) {
188 case CLOCK_EVT_MODE_PERIODIC:
189 sh_mtu2_disable(p);
190 disabled = 1;
191 break;
192 default:
193 break;
194 }
195
196 switch (mode) {
197 case CLOCK_EVT_MODE_PERIODIC:
198 dev_info(&p->pdev->dev, "used for periodic clock events\n");
199 sh_mtu2_enable(p);
200 break;
201 case CLOCK_EVT_MODE_UNUSED:
202 if (!disabled)
203 sh_mtu2_disable(p);
204 break;
205 case CLOCK_EVT_MODE_SHUTDOWN:
206 default:
207 break;
208 }
209}
210
211static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
212 char *name, unsigned long rating)
213{
214 struct clock_event_device *ced = &p->ced;
215 int ret;
216
217 memset(ced, 0, sizeof(*ced));
218
219 ced->name = name;
220 ced->features = CLOCK_EVT_FEAT_PERIODIC;
221 ced->rating = rating;
222 ced->cpumask = cpumask_of(0);
223 ced->set_mode = sh_mtu2_clock_event_mode;
224
225 dev_info(&p->pdev->dev, "used for clock events\n");
226 clockevents_register_device(ced);
227
228 ret = setup_irq(p->irqaction.irq, &p->irqaction);
229 if (ret) {
230 dev_err(&p->pdev->dev, "failed to request irq %d\n",
231 p->irqaction.irq);
232 return;
233 }
234}
235
236static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
237 unsigned long clockevent_rating)
238{
239 if (clockevent_rating)
240 sh_mtu2_register_clockevent(p, name, clockevent_rating);
241
242 return 0;
243}
244
245static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
246{
247 struct sh_timer_config *cfg = pdev->dev.platform_data;
248 struct resource *res;
249 int irq, ret;
250 ret = -ENXIO;
251
252 memset(p, 0, sizeof(*p));
253 p->pdev = pdev;
254
255 if (!cfg) {
256 dev_err(&p->pdev->dev, "missing platform data\n");
257 goto err0;
258 }
259
260 platform_set_drvdata(pdev, p);
261
262 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
263 if (!res) {
264 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
265 goto err0;
266 }
267
268 irq = platform_get_irq(p->pdev, 0);
269 if (irq < 0) {
270 dev_err(&p->pdev->dev, "failed to get irq\n");
271 goto err0;
272 }
273
274 /* map memory, let mapbase point to our channel */
275 p->mapbase = ioremap_nocache(res->start, resource_size(res));
276 if (p->mapbase == NULL) {
277 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
278 goto err0;
279 }
280
281 /* setup data for setup_irq() (too early for request_irq()) */
282 p->irqaction.name = dev_name(&p->pdev->dev);
283 p->irqaction.handler = sh_mtu2_interrupt;
284 p->irqaction.dev_id = p;
285 p->irqaction.irq = irq;
286 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
287 IRQF_IRQPOLL | IRQF_NOBALANCING;
288
289 /* get hold of clock */
290 p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
291 if (IS_ERR(p->clk)) {
292 dev_err(&p->pdev->dev, "cannot get clock\n");
293 ret = PTR_ERR(p->clk);
294 goto err1;
295 }
296
297 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
298 cfg->clockevent_rating);
299 err1:
300 iounmap(p->mapbase);
301 err0:
302 return ret;
303}
304
305static int __devinit sh_mtu2_probe(struct platform_device *pdev)
306{
307 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
308 int ret;
309
310 if (!is_early_platform_device(pdev))
311 pm_genpd_dev_always_on(&pdev->dev, true);
312
313 if (p) {
314 dev_info(&pdev->dev, "kept as earlytimer\n");
315 return 0;
316 }
317
318 p = kmalloc(sizeof(*p), GFP_KERNEL);
319 if (p == NULL) {
320 dev_err(&pdev->dev, "failed to allocate driver data\n");
321 return -ENOMEM;
322 }
323
324 ret = sh_mtu2_setup(p, pdev);
325 if (ret) {
326 kfree(p);
327 platform_set_drvdata(pdev, NULL);
328 }
329 return ret;
330}
331
332static int __devexit sh_mtu2_remove(struct platform_device *pdev)
333{
334 return -EBUSY; /* cannot unregister clockevent */
335}
336
337static struct platform_driver sh_mtu2_device_driver = {
338 .probe = sh_mtu2_probe,
339 .remove = __devexit_p(sh_mtu2_remove),
340 .driver = {
341 .name = "sh_mtu2",
342 }
343};
344
345static int __init sh_mtu2_init(void)
346{
347 return platform_driver_register(&sh_mtu2_device_driver);
348}
349
350static void __exit sh_mtu2_exit(void)
351{
352 platform_driver_unregister(&sh_mtu2_device_driver);
353}
354
355early_platform_init("earlytimer", &sh_mtu2_device_driver);
356module_init(sh_mtu2_init);
357module_exit(sh_mtu2_exit);
358
359MODULE_AUTHOR("Magnus Damm");
360MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
361MODULE_LICENSE("GPL v2");
1/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/module.h>
34#include <linux/pm_domain.h>
35#include <linux/pm_runtime.h>
36
37struct sh_mtu2_priv {
38 void __iomem *mapbase;
39 struct clk *clk;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
42 unsigned long rate;
43 unsigned long periodic;
44 struct clock_event_device ced;
45};
46
47static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
48
49#define TSTR -1 /* shared register */
50#define TCR 0 /* channel register */
51#define TMDR 1 /* channel register */
52#define TIOR 2 /* channel register */
53#define TIER 3 /* channel register */
54#define TSR 4 /* channel register */
55#define TCNT 5 /* channel register */
56#define TGR 6 /* channel register */
57
58static unsigned long mtu2_reg_offs[] = {
59 [TCR] = 0,
60 [TMDR] = 1,
61 [TIOR] = 2,
62 [TIER] = 4,
63 [TSR] = 5,
64 [TCNT] = 6,
65 [TGR] = 8,
66};
67
68static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
69{
70 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
71 void __iomem *base = p->mapbase;
72 unsigned long offs;
73
74 if (reg_nr == TSTR)
75 return ioread8(base + cfg->channel_offset);
76
77 offs = mtu2_reg_offs[reg_nr];
78
79 if ((reg_nr == TCNT) || (reg_nr == TGR))
80 return ioread16(base + offs);
81 else
82 return ioread8(base + offs);
83}
84
85static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
86 unsigned long value)
87{
88 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
89 void __iomem *base = p->mapbase;
90 unsigned long offs;
91
92 if (reg_nr == TSTR) {
93 iowrite8(value, base + cfg->channel_offset);
94 return;
95 }
96
97 offs = mtu2_reg_offs[reg_nr];
98
99 if ((reg_nr == TCNT) || (reg_nr == TGR))
100 iowrite16(value, base + offs);
101 else
102 iowrite8(value, base + offs);
103}
104
105static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
106{
107 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
108 unsigned long flags, value;
109
110 /* start stop register shared by multiple timer channels */
111 raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
112 value = sh_mtu2_read(p, TSTR);
113
114 if (start)
115 value |= 1 << cfg->timer_bit;
116 else
117 value &= ~(1 << cfg->timer_bit);
118
119 sh_mtu2_write(p, TSTR, value);
120 raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
121}
122
123static int sh_mtu2_enable(struct sh_mtu2_priv *p)
124{
125 int ret;
126
127 pm_runtime_get_sync(&p->pdev->dev);
128 dev_pm_syscore_device(&p->pdev->dev, true);
129
130 /* enable clock */
131 ret = clk_enable(p->clk);
132 if (ret) {
133 dev_err(&p->pdev->dev, "cannot enable clock\n");
134 return ret;
135 }
136
137 /* make sure channel is disabled */
138 sh_mtu2_start_stop_ch(p, 0);
139
140 p->rate = clk_get_rate(p->clk) / 64;
141 p->periodic = (p->rate + HZ/2) / HZ;
142
143 /* "Periodic Counter Operation" */
144 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
145 sh_mtu2_write(p, TIOR, 0);
146 sh_mtu2_write(p, TGR, p->periodic);
147 sh_mtu2_write(p, TCNT, 0);
148 sh_mtu2_write(p, TMDR, 0);
149 sh_mtu2_write(p, TIER, 0x01);
150
151 /* enable channel */
152 sh_mtu2_start_stop_ch(p, 1);
153
154 return 0;
155}
156
157static void sh_mtu2_disable(struct sh_mtu2_priv *p)
158{
159 /* disable channel */
160 sh_mtu2_start_stop_ch(p, 0);
161
162 /* stop clock */
163 clk_disable(p->clk);
164
165 dev_pm_syscore_device(&p->pdev->dev, false);
166 pm_runtime_put(&p->pdev->dev);
167}
168
169static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
170{
171 struct sh_mtu2_priv *p = dev_id;
172
173 /* acknowledge interrupt */
174 sh_mtu2_read(p, TSR);
175 sh_mtu2_write(p, TSR, 0xfe);
176
177 /* notify clockevent layer */
178 p->ced.event_handler(&p->ced);
179 return IRQ_HANDLED;
180}
181
182static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
183{
184 return container_of(ced, struct sh_mtu2_priv, ced);
185}
186
187static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
188 struct clock_event_device *ced)
189{
190 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
191 int disabled = 0;
192
193 /* deal with old setting first */
194 switch (ced->mode) {
195 case CLOCK_EVT_MODE_PERIODIC:
196 sh_mtu2_disable(p);
197 disabled = 1;
198 break;
199 default:
200 break;
201 }
202
203 switch (mode) {
204 case CLOCK_EVT_MODE_PERIODIC:
205 dev_info(&p->pdev->dev, "used for periodic clock events\n");
206 sh_mtu2_enable(p);
207 break;
208 case CLOCK_EVT_MODE_UNUSED:
209 if (!disabled)
210 sh_mtu2_disable(p);
211 break;
212 case CLOCK_EVT_MODE_SHUTDOWN:
213 default:
214 break;
215 }
216}
217
218static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
219{
220 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->pdev->dev);
221}
222
223static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
224{
225 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->pdev->dev);
226}
227
228static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
229 char *name, unsigned long rating)
230{
231 struct clock_event_device *ced = &p->ced;
232 int ret;
233
234 memset(ced, 0, sizeof(*ced));
235
236 ced->name = name;
237 ced->features = CLOCK_EVT_FEAT_PERIODIC;
238 ced->rating = rating;
239 ced->cpumask = cpumask_of(0);
240 ced->set_mode = sh_mtu2_clock_event_mode;
241 ced->suspend = sh_mtu2_clock_event_suspend;
242 ced->resume = sh_mtu2_clock_event_resume;
243
244 dev_info(&p->pdev->dev, "used for clock events\n");
245 clockevents_register_device(ced);
246
247 ret = setup_irq(p->irqaction.irq, &p->irqaction);
248 if (ret) {
249 dev_err(&p->pdev->dev, "failed to request irq %d\n",
250 p->irqaction.irq);
251 return;
252 }
253}
254
255static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
256 unsigned long clockevent_rating)
257{
258 if (clockevent_rating)
259 sh_mtu2_register_clockevent(p, name, clockevent_rating);
260
261 return 0;
262}
263
264static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
265{
266 struct sh_timer_config *cfg = pdev->dev.platform_data;
267 struct resource *res;
268 int irq, ret;
269 ret = -ENXIO;
270
271 memset(p, 0, sizeof(*p));
272 p->pdev = pdev;
273
274 if (!cfg) {
275 dev_err(&p->pdev->dev, "missing platform data\n");
276 goto err0;
277 }
278
279 platform_set_drvdata(pdev, p);
280
281 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
282 if (!res) {
283 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
284 goto err0;
285 }
286
287 irq = platform_get_irq(p->pdev, 0);
288 if (irq < 0) {
289 dev_err(&p->pdev->dev, "failed to get irq\n");
290 goto err0;
291 }
292
293 /* map memory, let mapbase point to our channel */
294 p->mapbase = ioremap_nocache(res->start, resource_size(res));
295 if (p->mapbase == NULL) {
296 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
297 goto err0;
298 }
299
300 /* setup data for setup_irq() (too early for request_irq()) */
301 p->irqaction.name = dev_name(&p->pdev->dev);
302 p->irqaction.handler = sh_mtu2_interrupt;
303 p->irqaction.dev_id = p;
304 p->irqaction.irq = irq;
305 p->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING;
306
307 /* get hold of clock */
308 p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
309 if (IS_ERR(p->clk)) {
310 dev_err(&p->pdev->dev, "cannot get clock\n");
311 ret = PTR_ERR(p->clk);
312 goto err1;
313 }
314
315 ret = clk_prepare(p->clk);
316 if (ret < 0)
317 goto err2;
318
319 ret = sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
320 cfg->clockevent_rating);
321 if (ret < 0)
322 goto err3;
323
324 return 0;
325 err3:
326 clk_unprepare(p->clk);
327 err2:
328 clk_put(p->clk);
329 err1:
330 iounmap(p->mapbase);
331 err0:
332 return ret;
333}
334
335static int sh_mtu2_probe(struct platform_device *pdev)
336{
337 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
338 struct sh_timer_config *cfg = pdev->dev.platform_data;
339 int ret;
340
341 if (!is_early_platform_device(pdev)) {
342 pm_runtime_set_active(&pdev->dev);
343 pm_runtime_enable(&pdev->dev);
344 }
345
346 if (p) {
347 dev_info(&pdev->dev, "kept as earlytimer\n");
348 goto out;
349 }
350
351 p = kmalloc(sizeof(*p), GFP_KERNEL);
352 if (p == NULL) {
353 dev_err(&pdev->dev, "failed to allocate driver data\n");
354 return -ENOMEM;
355 }
356
357 ret = sh_mtu2_setup(p, pdev);
358 if (ret) {
359 kfree(p);
360 pm_runtime_idle(&pdev->dev);
361 return ret;
362 }
363 if (is_early_platform_device(pdev))
364 return 0;
365
366 out:
367 if (cfg->clockevent_rating)
368 pm_runtime_irq_safe(&pdev->dev);
369 else
370 pm_runtime_idle(&pdev->dev);
371
372 return 0;
373}
374
375static int sh_mtu2_remove(struct platform_device *pdev)
376{
377 return -EBUSY; /* cannot unregister clockevent */
378}
379
380static struct platform_driver sh_mtu2_device_driver = {
381 .probe = sh_mtu2_probe,
382 .remove = sh_mtu2_remove,
383 .driver = {
384 .name = "sh_mtu2",
385 }
386};
387
388static int __init sh_mtu2_init(void)
389{
390 return platform_driver_register(&sh_mtu2_device_driver);
391}
392
393static void __exit sh_mtu2_exit(void)
394{
395 platform_driver_unregister(&sh_mtu2_device_driver);
396}
397
398early_platform_init("earlytimer", &sh_mtu2_device_driver);
399subsys_initcall(sh_mtu2_init);
400module_exit(sh_mtu2_exit);
401
402MODULE_AUTHOR("Magnus Damm");
403MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
404MODULE_LICENSE("GPL v2");