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1/*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/reset-controller.h>
22
23#include "clk-factors.h"
24
25static DEFINE_SPINLOCK(clk_lock);
26
27/* Maximum number of parents our clocks have */
28#define SUNXI_MAX_PARENTS 5
29
30/**
31 * sun4i_osc_clk_setup() - Setup function for gatable oscillator
32 */
33
34#define SUNXI_OSC24M_GATE 0
35
36static void __init sun4i_osc_clk_setup(struct device_node *node)
37{
38 struct clk *clk;
39 struct clk_fixed_rate *fixed;
40 struct clk_gate *gate;
41 const char *clk_name = node->name;
42 u32 rate;
43
44 if (of_property_read_u32(node, "clock-frequency", &rate))
45 return;
46
47 /* allocate fixed-rate and gate clock structs */
48 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
49 if (!fixed)
50 return;
51 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
52 if (!gate)
53 goto err_free_fixed;
54
55 of_property_read_string(node, "clock-output-names", &clk_name);
56
57 /* set up gate and fixed rate properties */
58 gate->reg = of_iomap(node, 0);
59 gate->bit_idx = SUNXI_OSC24M_GATE;
60 gate->lock = &clk_lock;
61 fixed->fixed_rate = rate;
62
63 clk = clk_register_composite(NULL, clk_name,
64 NULL, 0,
65 NULL, NULL,
66 &fixed->hw, &clk_fixed_rate_ops,
67 &gate->hw, &clk_gate_ops,
68 CLK_IS_ROOT);
69
70 if (IS_ERR(clk))
71 goto err_free_gate;
72
73 of_clk_add_provider(node, of_clk_src_simple_get, clk);
74 clk_register_clkdev(clk, clk_name, NULL);
75
76 return;
77
78err_free_gate:
79 kfree(gate);
80err_free_fixed:
81 kfree(fixed);
82}
83CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
84
85
86
87/**
88 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
89 * PLL1 rate is calculated as follows
90 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
91 * parent_rate is always 24Mhz
92 */
93
94static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
95 u8 *n, u8 *k, u8 *m, u8 *p)
96{
97 u8 div;
98
99 /* Normalize value to a 6M multiple */
100 div = *freq / 6000000;
101 *freq = 6000000 * div;
102
103 /* we were called to round the frequency, we can now return */
104 if (n == NULL)
105 return;
106
107 /* m is always zero for pll1 */
108 *m = 0;
109
110 /* k is 1 only on these cases */
111 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
112 *k = 1;
113 else
114 *k = 0;
115
116 /* p will be 3 for divs under 10 */
117 if (div < 10)
118 *p = 3;
119
120 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
121 else if (div < 20 || (div < 32 && (div & 1)))
122 *p = 2;
123
124 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
125 * of divs between 40-62 */
126 else if (div < 40 || (div < 64 && (div & 2)))
127 *p = 1;
128
129 /* any other entries have p = 0 */
130 else
131 *p = 0;
132
133 /* calculate a suitable n based on k and p */
134 div <<= *p;
135 div /= (*k + 1);
136 *n = div / 4;
137}
138
139/**
140 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
141 * PLL1 rate is calculated as follows
142 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
143 * parent_rate should always be 24MHz
144 */
145static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
146 u8 *n, u8 *k, u8 *m, u8 *p)
147{
148 /*
149 * We can operate only on MHz, this will make our life easier
150 * later.
151 */
152 u32 freq_mhz = *freq / 1000000;
153 u32 parent_freq_mhz = parent_rate / 1000000;
154
155 /*
156 * Round down the frequency to the closest multiple of either
157 * 6 or 16
158 */
159 u32 round_freq_6 = round_down(freq_mhz, 6);
160 u32 round_freq_16 = round_down(freq_mhz, 16);
161
162 if (round_freq_6 > round_freq_16)
163 freq_mhz = round_freq_6;
164 else
165 freq_mhz = round_freq_16;
166
167 *freq = freq_mhz * 1000000;
168
169 /*
170 * If the factors pointer are null, we were just called to
171 * round down the frequency.
172 * Exit.
173 */
174 if (n == NULL)
175 return;
176
177 /* If the frequency is a multiple of 32 MHz, k is always 3 */
178 if (!(freq_mhz % 32))
179 *k = 3;
180 /* If the frequency is a multiple of 9 MHz, k is always 2 */
181 else if (!(freq_mhz % 9))
182 *k = 2;
183 /* If the frequency is a multiple of 8 MHz, k is always 1 */
184 else if (!(freq_mhz % 8))
185 *k = 1;
186 /* Otherwise, we don't use the k factor */
187 else
188 *k = 0;
189
190 /*
191 * If the frequency is a multiple of 2 but not a multiple of
192 * 3, m is 3. This is the first time we use 6 here, yet we
193 * will use it on several other places.
194 * We use this number because it's the lowest frequency we can
195 * generate (with n = 0, k = 0, m = 3), so every other frequency
196 * somehow relates to this frequency.
197 */
198 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
199 *m = 2;
200 /*
201 * If the frequency is a multiple of 6MHz, but the factor is
202 * odd, m will be 3
203 */
204 else if ((freq_mhz / 6) & 1)
205 *m = 3;
206 /* Otherwise, we end up with m = 1 */
207 else
208 *m = 1;
209
210 /* Calculate n thanks to the above factors we already got */
211 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
212
213 /*
214 * If n end up being outbound, and that we can still decrease
215 * m, do it.
216 */
217 if ((*n + 1) > 31 && (*m + 1) > 1) {
218 *n = (*n + 1) / 2 - 1;
219 *m = (*m + 1) / 2 - 1;
220 }
221}
222
223/**
224 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
225 * PLL5 rate is calculated as follows
226 * rate = parent_rate * n * (k + 1)
227 * parent_rate is always 24Mhz
228 */
229
230static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
231 u8 *n, u8 *k, u8 *m, u8 *p)
232{
233 u8 div;
234
235 /* Normalize value to a parent_rate multiple (24M) */
236 div = *freq / parent_rate;
237 *freq = parent_rate * div;
238
239 /* we were called to round the frequency, we can now return */
240 if (n == NULL)
241 return;
242
243 if (div < 31)
244 *k = 0;
245 else if (div / 2 < 31)
246 *k = 1;
247 else if (div / 3 < 31)
248 *k = 2;
249 else
250 *k = 3;
251
252 *n = DIV_ROUND_UP(div, (*k+1));
253}
254
255/**
256 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
257 * PLL6 rate is calculated as follows
258 * rate = parent_rate * n * (k + 1) / 2
259 * parent_rate is always 24Mhz
260 */
261
262static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
263 u8 *n, u8 *k, u8 *m, u8 *p)
264{
265 u8 div;
266
267 /*
268 * We always have 24MHz / 2, so we can just say that our
269 * parent clock is 12MHz.
270 */
271 parent_rate = parent_rate / 2;
272
273 /* Normalize value to a parent_rate multiple (24M / 2) */
274 div = *freq / parent_rate;
275 *freq = parent_rate * div;
276
277 /* we were called to round the frequency, we can now return */
278 if (n == NULL)
279 return;
280
281 *k = div / 32;
282 if (*k > 3)
283 *k = 3;
284
285 *n = DIV_ROUND_UP(div, (*k+1));
286}
287
288/**
289 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
290 * APB1 rate is calculated as follows
291 * rate = (parent_rate >> p) / (m + 1);
292 */
293
294static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
295 u8 *n, u8 *k, u8 *m, u8 *p)
296{
297 u8 calcm, calcp;
298
299 if (parent_rate < *freq)
300 *freq = parent_rate;
301
302 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
303
304 /* Invalid rate! */
305 if (parent_rate > 32)
306 return;
307
308 if (parent_rate <= 4)
309 calcp = 0;
310 else if (parent_rate <= 8)
311 calcp = 1;
312 else if (parent_rate <= 16)
313 calcp = 2;
314 else
315 calcp = 3;
316
317 calcm = (parent_rate >> calcp) - 1;
318
319 *freq = (parent_rate >> calcp) / (calcm + 1);
320
321 /* we were called to round the frequency, we can now return */
322 if (n == NULL)
323 return;
324
325 *m = calcm;
326 *p = calcp;
327}
328
329
330
331/**
332 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
333 * MOD0 rate is calculated as follows
334 * rate = (parent_rate >> p) / (m + 1);
335 */
336
337static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
338 u8 *n, u8 *k, u8 *m, u8 *p)
339{
340 u8 div, calcm, calcp;
341
342 /* These clocks can only divide, so we will never be able to achieve
343 * frequencies higher than the parent frequency */
344 if (*freq > parent_rate)
345 *freq = parent_rate;
346
347 div = DIV_ROUND_UP(parent_rate, *freq);
348
349 if (div < 16)
350 calcp = 0;
351 else if (div / 2 < 16)
352 calcp = 1;
353 else if (div / 4 < 16)
354 calcp = 2;
355 else
356 calcp = 3;
357
358 calcm = DIV_ROUND_UP(div, 1 << calcp);
359
360 *freq = (parent_rate >> calcp) / calcm;
361
362 /* we were called to round the frequency, we can now return */
363 if (n == NULL)
364 return;
365
366 *m = calcm - 1;
367 *p = calcp;
368}
369
370
371
372/**
373 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
374 * CLK_OUT rate is calculated as follows
375 * rate = (parent_rate >> p) / (m + 1);
376 */
377
378static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
379 u8 *n, u8 *k, u8 *m, u8 *p)
380{
381 u8 div, calcm, calcp;
382
383 /* These clocks can only divide, so we will never be able to achieve
384 * frequencies higher than the parent frequency */
385 if (*freq > parent_rate)
386 *freq = parent_rate;
387
388 div = DIV_ROUND_UP(parent_rate, *freq);
389
390 if (div < 32)
391 calcp = 0;
392 else if (div / 2 < 32)
393 calcp = 1;
394 else if (div / 4 < 32)
395 calcp = 2;
396 else
397 calcp = 3;
398
399 calcm = DIV_ROUND_UP(div, 1 << calcp);
400
401 *freq = (parent_rate >> calcp) / calcm;
402
403 /* we were called to round the frequency, we can now return */
404 if (n == NULL)
405 return;
406
407 *m = calcm - 1;
408 *p = calcp;
409}
410
411
412
413/**
414 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
415 *
416 * This clock looks something like this
417 * ________________________
418 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
419 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
420 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
421 * |________________________|
422 *
423 * The external 125 MHz reference is optional, i.e. GMAC can use its
424 * internal TX clock just fine. The A31 GMAC clock module does not have
425 * the divider controls for the external reference.
426 *
427 * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
428 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
429 * select the appropriate source and gate/ungate the output to the PHY.
430 *
431 * Only the GMAC should use this clock. Altering the clock so that it doesn't
432 * match the GMAC's operation parameters will result in the GMAC not being
433 * able to send traffic out. The GMAC driver should set the clock rate and
434 * enable/disable this clock to configure the required state. The clock
435 * driver then responds by auto-reparenting the clock.
436 */
437
438#define SUN7I_A20_GMAC_GPIT 2
439#define SUN7I_A20_GMAC_MASK 0x3
440#define SUN7I_A20_GMAC_PARENTS 2
441
442static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
443{
444 struct clk *clk;
445 struct clk_mux *mux;
446 struct clk_gate *gate;
447 const char *clk_name = node->name;
448 const char *parents[SUN7I_A20_GMAC_PARENTS];
449 void *reg;
450
451 if (of_property_read_string(node, "clock-output-names", &clk_name))
452 return;
453
454 /* allocate mux and gate clock structs */
455 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
456 if (!mux)
457 return;
458
459 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
460 if (!gate)
461 goto free_mux;
462
463 /* gmac clock requires exactly 2 parents */
464 parents[0] = of_clk_get_parent_name(node, 0);
465 parents[1] = of_clk_get_parent_name(node, 1);
466 if (!parents[0] || !parents[1])
467 goto free_gate;
468
469 reg = of_iomap(node, 0);
470 if (!reg)
471 goto free_gate;
472
473 /* set up gate and fixed rate properties */
474 gate->reg = reg;
475 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
476 gate->lock = &clk_lock;
477 mux->reg = reg;
478 mux->mask = SUN7I_A20_GMAC_MASK;
479 mux->flags = CLK_MUX_INDEX_BIT;
480 mux->lock = &clk_lock;
481
482 clk = clk_register_composite(NULL, clk_name,
483 parents, SUN7I_A20_GMAC_PARENTS,
484 &mux->hw, &clk_mux_ops,
485 NULL, NULL,
486 &gate->hw, &clk_gate_ops,
487 0);
488
489 if (IS_ERR(clk))
490 goto iounmap_reg;
491
492 of_clk_add_provider(node, of_clk_src_simple_get, clk);
493 clk_register_clkdev(clk, clk_name, NULL);
494
495 return;
496
497iounmap_reg:
498 iounmap(reg);
499free_gate:
500 kfree(gate);
501free_mux:
502 kfree(mux);
503}
504CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
505 sun7i_a20_gmac_clk_setup);
506
507
508
509/**
510 * sunxi_factors_clk_setup() - Setup function for factor clocks
511 */
512
513#define SUNXI_FACTORS_MUX_MASK 0x3
514
515struct factors_data {
516 int enable;
517 int mux;
518 struct clk_factors_config *table;
519 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
520 const char *name;
521};
522
523static struct clk_factors_config sun4i_pll1_config = {
524 .nshift = 8,
525 .nwidth = 5,
526 .kshift = 4,
527 .kwidth = 2,
528 .mshift = 0,
529 .mwidth = 2,
530 .pshift = 16,
531 .pwidth = 2,
532};
533
534static struct clk_factors_config sun6i_a31_pll1_config = {
535 .nshift = 8,
536 .nwidth = 5,
537 .kshift = 4,
538 .kwidth = 2,
539 .mshift = 0,
540 .mwidth = 2,
541};
542
543static struct clk_factors_config sun4i_pll5_config = {
544 .nshift = 8,
545 .nwidth = 5,
546 .kshift = 4,
547 .kwidth = 2,
548};
549
550static struct clk_factors_config sun6i_a31_pll6_config = {
551 .nshift = 8,
552 .nwidth = 5,
553 .kshift = 4,
554 .kwidth = 2,
555};
556
557static struct clk_factors_config sun4i_apb1_config = {
558 .mshift = 0,
559 .mwidth = 5,
560 .pshift = 16,
561 .pwidth = 2,
562};
563
564/* user manual says "n" but it's really "p" */
565static struct clk_factors_config sun4i_mod0_config = {
566 .mshift = 0,
567 .mwidth = 4,
568 .pshift = 16,
569 .pwidth = 2,
570};
571
572/* user manual says "n" but it's really "p" */
573static struct clk_factors_config sun7i_a20_out_config = {
574 .mshift = 8,
575 .mwidth = 5,
576 .pshift = 20,
577 .pwidth = 2,
578};
579
580static const struct factors_data sun4i_pll1_data __initconst = {
581 .enable = 31,
582 .table = &sun4i_pll1_config,
583 .getter = sun4i_get_pll1_factors,
584};
585
586static const struct factors_data sun6i_a31_pll1_data __initconst = {
587 .enable = 31,
588 .table = &sun6i_a31_pll1_config,
589 .getter = sun6i_a31_get_pll1_factors,
590};
591
592static const struct factors_data sun7i_a20_pll4_data __initconst = {
593 .enable = 31,
594 .table = &sun4i_pll5_config,
595 .getter = sun4i_get_pll5_factors,
596};
597
598static const struct factors_data sun4i_pll5_data __initconst = {
599 .enable = 31,
600 .table = &sun4i_pll5_config,
601 .getter = sun4i_get_pll5_factors,
602 .name = "pll5",
603};
604
605static const struct factors_data sun4i_pll6_data __initconst = {
606 .enable = 31,
607 .table = &sun4i_pll5_config,
608 .getter = sun4i_get_pll5_factors,
609 .name = "pll6",
610};
611
612static const struct factors_data sun6i_a31_pll6_data __initconst = {
613 .enable = 31,
614 .table = &sun6i_a31_pll6_config,
615 .getter = sun6i_a31_get_pll6_factors,
616};
617
618static const struct factors_data sun4i_apb1_data __initconst = {
619 .table = &sun4i_apb1_config,
620 .getter = sun4i_get_apb1_factors,
621};
622
623static const struct factors_data sun4i_mod0_data __initconst = {
624 .enable = 31,
625 .mux = 24,
626 .table = &sun4i_mod0_config,
627 .getter = sun4i_get_mod0_factors,
628};
629
630static const struct factors_data sun7i_a20_out_data __initconst = {
631 .enable = 31,
632 .mux = 24,
633 .table = &sun7i_a20_out_config,
634 .getter = sun7i_a20_get_out_factors,
635};
636
637static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
638 const struct factors_data *data)
639{
640 struct clk *clk;
641 struct clk_factors *factors;
642 struct clk_gate *gate = NULL;
643 struct clk_mux *mux = NULL;
644 struct clk_hw *gate_hw = NULL;
645 struct clk_hw *mux_hw = NULL;
646 const char *clk_name = node->name;
647 const char *parents[SUNXI_MAX_PARENTS];
648 void *reg;
649 int i = 0;
650
651 reg = of_iomap(node, 0);
652
653 /* if we have a mux, we will have >1 parents */
654 while (i < SUNXI_MAX_PARENTS &&
655 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
656 i++;
657
658 /*
659 * some factor clocks, such as pll5 and pll6, may have multiple
660 * outputs, and have their name designated in factors_data
661 */
662 if (data->name)
663 clk_name = data->name;
664 else
665 of_property_read_string(node, "clock-output-names", &clk_name);
666
667 factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
668 if (!factors)
669 return NULL;
670
671 /* Add a gate if this factor clock can be gated */
672 if (data->enable) {
673 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
674 if (!gate) {
675 kfree(factors);
676 return NULL;
677 }
678
679 /* set up gate properties */
680 gate->reg = reg;
681 gate->bit_idx = data->enable;
682 gate->lock = &clk_lock;
683 gate_hw = &gate->hw;
684 }
685
686 /* Add a mux if this factor clock can be muxed */
687 if (data->mux) {
688 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
689 if (!mux) {
690 kfree(factors);
691 kfree(gate);
692 return NULL;
693 }
694
695 /* set up gate properties */
696 mux->reg = reg;
697 mux->shift = data->mux;
698 mux->mask = SUNXI_FACTORS_MUX_MASK;
699 mux->lock = &clk_lock;
700 mux_hw = &mux->hw;
701 }
702
703 /* set up factors properties */
704 factors->reg = reg;
705 factors->config = data->table;
706 factors->get_factors = data->getter;
707 factors->lock = &clk_lock;
708
709 clk = clk_register_composite(NULL, clk_name,
710 parents, i,
711 mux_hw, &clk_mux_ops,
712 &factors->hw, &clk_factors_ops,
713 gate_hw, &clk_gate_ops, 0);
714
715 if (!IS_ERR(clk)) {
716 of_clk_add_provider(node, of_clk_src_simple_get, clk);
717 clk_register_clkdev(clk, clk_name, NULL);
718 }
719
720 return clk;
721}
722
723
724
725/**
726 * sunxi_mux_clk_setup() - Setup function for muxes
727 */
728
729#define SUNXI_MUX_GATE_WIDTH 2
730
731struct mux_data {
732 u8 shift;
733};
734
735static const struct mux_data sun4i_cpu_mux_data __initconst = {
736 .shift = 16,
737};
738
739static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
740 .shift = 12,
741};
742
743static const struct mux_data sun4i_apb1_mux_data __initconst = {
744 .shift = 24,
745};
746
747static void __init sunxi_mux_clk_setup(struct device_node *node,
748 struct mux_data *data)
749{
750 struct clk *clk;
751 const char *clk_name = node->name;
752 const char *parents[SUNXI_MAX_PARENTS];
753 void *reg;
754 int i = 0;
755
756 reg = of_iomap(node, 0);
757
758 while (i < SUNXI_MAX_PARENTS &&
759 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
760 i++;
761
762 of_property_read_string(node, "clock-output-names", &clk_name);
763
764 clk = clk_register_mux(NULL, clk_name, parents, i,
765 CLK_SET_RATE_NO_REPARENT, reg,
766 data->shift, SUNXI_MUX_GATE_WIDTH,
767 0, &clk_lock);
768
769 if (clk) {
770 of_clk_add_provider(node, of_clk_src_simple_get, clk);
771 clk_register_clkdev(clk, clk_name, NULL);
772 }
773}
774
775
776
777/**
778 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
779 */
780
781struct div_data {
782 u8 shift;
783 u8 pow;
784 u8 width;
785};
786
787static const struct div_data sun4i_axi_data __initconst = {
788 .shift = 0,
789 .pow = 0,
790 .width = 2,
791};
792
793static const struct div_data sun4i_ahb_data __initconst = {
794 .shift = 4,
795 .pow = 1,
796 .width = 2,
797};
798
799static const struct div_data sun4i_apb0_data __initconst = {
800 .shift = 8,
801 .pow = 1,
802 .width = 2,
803};
804
805static const struct div_data sun6i_a31_apb2_div_data __initconst = {
806 .shift = 0,
807 .pow = 0,
808 .width = 4,
809};
810
811static void __init sunxi_divider_clk_setup(struct device_node *node,
812 struct div_data *data)
813{
814 struct clk *clk;
815 const char *clk_name = node->name;
816 const char *clk_parent;
817 void *reg;
818
819 reg = of_iomap(node, 0);
820
821 clk_parent = of_clk_get_parent_name(node, 0);
822
823 of_property_read_string(node, "clock-output-names", &clk_name);
824
825 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
826 reg, data->shift, data->width,
827 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
828 &clk_lock);
829 if (clk) {
830 of_clk_add_provider(node, of_clk_src_simple_get, clk);
831 clk_register_clkdev(clk, clk_name, NULL);
832 }
833}
834
835
836
837/**
838 * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
839 */
840
841struct gates_reset_data {
842 void __iomem *reg;
843 spinlock_t *lock;
844 struct reset_controller_dev rcdev;
845};
846
847static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
848 unsigned long id)
849{
850 struct gates_reset_data *data = container_of(rcdev,
851 struct gates_reset_data,
852 rcdev);
853 unsigned long flags;
854 u32 reg;
855
856 spin_lock_irqsave(data->lock, flags);
857
858 reg = readl(data->reg);
859 writel(reg & ~BIT(id), data->reg);
860
861 spin_unlock_irqrestore(data->lock, flags);
862
863 return 0;
864}
865
866static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
867 unsigned long id)
868{
869 struct gates_reset_data *data = container_of(rcdev,
870 struct gates_reset_data,
871 rcdev);
872 unsigned long flags;
873 u32 reg;
874
875 spin_lock_irqsave(data->lock, flags);
876
877 reg = readl(data->reg);
878 writel(reg | BIT(id), data->reg);
879
880 spin_unlock_irqrestore(data->lock, flags);
881
882 return 0;
883}
884
885static struct reset_control_ops sunxi_gates_reset_ops = {
886 .assert = sunxi_gates_reset_assert,
887 .deassert = sunxi_gates_reset_deassert,
888};
889
890/**
891 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
892 */
893
894#define SUNXI_GATES_MAX_SIZE 64
895
896struct gates_data {
897 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
898 u32 reset_mask;
899};
900
901static const struct gates_data sun4i_axi_gates_data __initconst = {
902 .mask = {1},
903};
904
905static const struct gates_data sun4i_ahb_gates_data __initconst = {
906 .mask = {0x7F77FFF, 0x14FB3F},
907};
908
909static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
910 .mask = {0x147667e7, 0x185915},
911};
912
913static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
914 .mask = {0x107067e7, 0x185111},
915};
916
917static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
918 .mask = {0xEDFE7F62, 0x794F931},
919};
920
921static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
922 .mask = { 0x12f77fff, 0x16ff3f },
923};
924
925static const struct gates_data sun4i_apb0_gates_data __initconst = {
926 .mask = {0x4EF},
927};
928
929static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
930 .mask = {0x469},
931};
932
933static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
934 .mask = {0x61},
935};
936
937static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
938 .mask = { 0x4ff },
939};
940
941static const struct gates_data sun4i_apb1_gates_data __initconst = {
942 .mask = {0xFF00F7},
943};
944
945static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
946 .mask = {0xf0007},
947};
948
949static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
950 .mask = {0xa0007},
951};
952
953static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
954 .mask = {0x3031},
955};
956
957static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
958 .mask = {0x3F000F},
959};
960
961static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
962 .mask = { 0xff80ff },
963};
964
965static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
966 .mask = {0x1C0},
967 .reset_mask = 0x07,
968};
969
970static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
971 .mask = {0x140},
972 .reset_mask = 0x03,
973};
974
975static void __init sunxi_gates_clk_setup(struct device_node *node,
976 struct gates_data *data)
977{
978 struct clk_onecell_data *clk_data;
979 struct gates_reset_data *reset_data;
980 const char *clk_parent;
981 const char *clk_name;
982 void *reg;
983 int qty;
984 int i = 0;
985 int j = 0;
986 int ignore;
987
988 reg = of_iomap(node, 0);
989
990 clk_parent = of_clk_get_parent_name(node, 0);
991
992 /* Worst-case size approximation and memory allocation */
993 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
994 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
995 if (!clk_data)
996 return;
997 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
998 if (!clk_data->clks) {
999 kfree(clk_data);
1000 return;
1001 }
1002
1003 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1004 of_property_read_string_index(node, "clock-output-names",
1005 j, &clk_name);
1006
1007 /* No driver claims this clock, but it should remain gated */
1008 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
1009
1010 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
1011 clk_parent, ignore,
1012 reg + 4 * (i/32), i % 32,
1013 0, &clk_lock);
1014 WARN_ON(IS_ERR(clk_data->clks[i]));
1015
1016 j++;
1017 }
1018
1019 /* Adjust to the real max */
1020 clk_data->clk_num = i;
1021
1022 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1023
1024 /* Register a reset controler for gates with reset bits */
1025 if (data->reset_mask == 0)
1026 return;
1027
1028 reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
1029 if (!reset_data)
1030 return;
1031
1032 reset_data->reg = reg;
1033 reset_data->lock = &clk_lock;
1034 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
1035 reset_data->rcdev.ops = &sunxi_gates_reset_ops;
1036 reset_data->rcdev.of_node = node;
1037 reset_controller_register(&reset_data->rcdev);
1038}
1039
1040
1041
1042/**
1043 * sunxi_divs_clk_setup() helper data
1044 */
1045
1046#define SUNXI_DIVS_MAX_QTY 2
1047#define SUNXI_DIVISOR_WIDTH 2
1048
1049struct divs_data {
1050 const struct factors_data *factors; /* data for the factor clock */
1051 struct {
1052 u8 fixed; /* is it a fixed divisor? if not... */
1053 struct clk_div_table *table; /* is it a table based divisor? */
1054 u8 shift; /* otherwise it's a normal divisor with this shift */
1055 u8 pow; /* is it power-of-two based? */
1056 u8 gate; /* is it independently gateable? */
1057 } div[SUNXI_DIVS_MAX_QTY];
1058};
1059
1060static struct clk_div_table pll6_sata_tbl[] = {
1061 { .val = 0, .div = 6, },
1062 { .val = 1, .div = 12, },
1063 { .val = 2, .div = 18, },
1064 { .val = 3, .div = 24, },
1065 { } /* sentinel */
1066};
1067
1068static const struct divs_data pll5_divs_data __initconst = {
1069 .factors = &sun4i_pll5_data,
1070 .div = {
1071 { .shift = 0, .pow = 0, }, /* M, DDR */
1072 { .shift = 16, .pow = 1, }, /* P, other */
1073 }
1074};
1075
1076static const struct divs_data pll6_divs_data __initconst = {
1077 .factors = &sun4i_pll6_data,
1078 .div = {
1079 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1080 { .fixed = 2 }, /* P, other */
1081 }
1082};
1083
1084/**
1085 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1086 *
1087 * These clocks look something like this
1088 * ________________________
1089 * | ___divisor 1---|----> to consumer
1090 * parent >--| pll___/___divisor 2---|----> to consumer
1091 * | \_______________|____> to consumer
1092 * |________________________|
1093 */
1094
1095static void __init sunxi_divs_clk_setup(struct device_node *node,
1096 struct divs_data *data)
1097{
1098 struct clk_onecell_data *clk_data;
1099 const char *parent;
1100 const char *clk_name;
1101 struct clk **clks, *pclk;
1102 struct clk_hw *gate_hw, *rate_hw;
1103 const struct clk_ops *rate_ops;
1104 struct clk_gate *gate = NULL;
1105 struct clk_fixed_factor *fix_factor;
1106 struct clk_divider *divider;
1107 void *reg;
1108 int i = 0;
1109 int flags, clkflags;
1110
1111 /* Set up factor clock that we will be dividing */
1112 pclk = sunxi_factors_clk_setup(node, data->factors);
1113 parent = __clk_get_name(pclk);
1114
1115 reg = of_iomap(node, 0);
1116
1117 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1118 if (!clk_data)
1119 return;
1120
1121 clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL);
1122 if (!clks)
1123 goto free_clkdata;
1124
1125 clk_data->clks = clks;
1126
1127 /* It's not a good idea to have automatic reparenting changing
1128 * our RAM clock! */
1129 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1130
1131 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
1132 if (of_property_read_string_index(node, "clock-output-names",
1133 i, &clk_name) != 0)
1134 break;
1135
1136 gate_hw = NULL;
1137 rate_hw = NULL;
1138 rate_ops = NULL;
1139
1140 /* If this leaf clock can be gated, create a gate */
1141 if (data->div[i].gate) {
1142 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1143 if (!gate)
1144 goto free_clks;
1145
1146 gate->reg = reg;
1147 gate->bit_idx = data->div[i].gate;
1148 gate->lock = &clk_lock;
1149
1150 gate_hw = &gate->hw;
1151 }
1152
1153 /* Leaves can be fixed or configurable divisors */
1154 if (data->div[i].fixed) {
1155 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1156 if (!fix_factor)
1157 goto free_gate;
1158
1159 fix_factor->mult = 1;
1160 fix_factor->div = data->div[i].fixed;
1161
1162 rate_hw = &fix_factor->hw;
1163 rate_ops = &clk_fixed_factor_ops;
1164 } else {
1165 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1166 if (!divider)
1167 goto free_gate;
1168
1169 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1170
1171 divider->reg = reg;
1172 divider->shift = data->div[i].shift;
1173 divider->width = SUNXI_DIVISOR_WIDTH;
1174 divider->flags = flags;
1175 divider->lock = &clk_lock;
1176 divider->table = data->div[i].table;
1177
1178 rate_hw = ÷r->hw;
1179 rate_ops = &clk_divider_ops;
1180 }
1181
1182 /* Wrap the (potential) gate and the divisor on a composite
1183 * clock to unify them */
1184 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1185 NULL, NULL,
1186 rate_hw, rate_ops,
1187 gate_hw, &clk_gate_ops,
1188 clkflags);
1189
1190 WARN_ON(IS_ERR(clk_data->clks[i]));
1191 clk_register_clkdev(clks[i], clk_name, NULL);
1192 }
1193
1194 /* The last clock available on the getter is the parent */
1195 clks[i++] = pclk;
1196
1197 /* Adjust to the real max */
1198 clk_data->clk_num = i;
1199
1200 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1201
1202 return;
1203
1204free_gate:
1205 kfree(gate);
1206free_clks:
1207 kfree(clks);
1208free_clkdata:
1209 kfree(clk_data);
1210}
1211
1212
1213
1214/* Matches for factors clocks */
1215static const struct of_device_id clk_factors_match[] __initconst = {
1216 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1217 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1218 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1219 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1220 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
1221 {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
1222 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
1223 {}
1224};
1225
1226/* Matches for divider clocks */
1227static const struct of_device_id clk_div_match[] __initconst = {
1228 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1229 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1230 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1231 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
1232 {}
1233};
1234
1235/* Matches for divided outputs */
1236static const struct of_device_id clk_divs_match[] __initconst = {
1237 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1238 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
1239 {}
1240};
1241
1242/* Matches for mux clocks */
1243static const struct of_device_id clk_mux_match[] __initconst = {
1244 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
1245 {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
1246 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1247 {}
1248};
1249
1250/* Matches for gate clocks */
1251static const struct of_device_id clk_gates_match[] __initconst = {
1252 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1253 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
1254 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
1255 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1256 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1257 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1258 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1259 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1260 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
1261 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
1262 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
1263 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
1264 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1265 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1266 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1267 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1268 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1269 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1270 {}
1271};
1272
1273static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1274 void *function)
1275{
1276 struct device_node *np;
1277 const struct div_data *data;
1278 const struct of_device_id *match;
1279 void (*setup_function)(struct device_node *, const void *) = function;
1280
1281 for_each_matching_node(np, clk_match) {
1282 match = of_match_node(clk_match, np);
1283 data = match->data;
1284 setup_function(np, data);
1285 }
1286}
1287
1288/**
1289 * System clock protection
1290 *
1291 * By enabling these critical clocks, we prevent their accidental gating
1292 * by the framework
1293 */
1294static void __init sunxi_clock_protect(void)
1295{
1296 struct clk *clk;
1297
1298 /* memory bus clock - sun5i+ */
1299 clk = clk_get(NULL, "mbus");
1300 if (!IS_ERR(clk)) {
1301 clk_prepare_enable(clk);
1302 clk_put(clk);
1303 }
1304
1305 /* DDR clock - sun4i+ */
1306 clk = clk_get(NULL, "pll5_ddr");
1307 if (!IS_ERR(clk)) {
1308 clk_prepare_enable(clk);
1309 clk_put(clk);
1310 }
1311}
1312
1313static void __init sunxi_init_clocks(void)
1314{
1315 /* Register factor clocks */
1316 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1317
1318 /* Register divider clocks */
1319 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1320
1321 /* Register divided output clocks */
1322 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1323
1324 /* Register mux clocks */
1325 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
1326
1327 /* Register gate clocks */
1328 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
1329
1330 /* Enable core system clocks */
1331 sunxi_clock_protect();
1332}
1333CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
1334CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
1335CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
1336CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
1337CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);