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1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adjustable divider clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/string.h>
19
20/*
21 * DOC: basic adjustable divider clock that cannot gate
22 *
23 * Traits of this clock:
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is adjustable. clk->rate = parent->rate / divisor
27 * parent - fixed parent. No clk_set_parent support
28 */
29
30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31
32#define div_mask(d) ((1 << (d->width)) - 1)
33
34static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct clk_divider *divider = to_clk_divider(hw);
38 unsigned int div;
39
40 div = readl(divider->reg) >> divider->shift;
41 div &= div_mask(divider);
42
43 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
44 div++;
45
46 return parent_rate / div;
47}
48
49/*
50 * The reverse of DIV_ROUND_UP: The maximum number which
51 * divided by m is r
52 */
53#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
54
55static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
56 unsigned long *best_parent_rate)
57{
58 struct clk_divider *divider = to_clk_divider(hw);
59 int i, bestdiv = 0;
60 unsigned long parent_rate, best = 0, now, maxdiv;
61
62 if (!rate)
63 rate = 1;
64
65 maxdiv = (1 << divider->width);
66
67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
68 maxdiv--;
69
70 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
71 parent_rate = *best_parent_rate;
72 bestdiv = DIV_ROUND_UP(parent_rate, rate);
73 bestdiv = bestdiv == 0 ? 1 : bestdiv;
74 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
75 return bestdiv;
76 }
77
78 /*
79 * The maximum divider we can use without overflowing
80 * unsigned long in rate * i below
81 */
82 maxdiv = min(ULONG_MAX / rate, maxdiv);
83
84 for (i = 1; i <= maxdiv; i++) {
85 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
86 MULT_ROUND_UP(rate, i));
87 now = parent_rate / i;
88 if (now <= rate && now > best) {
89 bestdiv = i;
90 best = now;
91 *best_parent_rate = parent_rate;
92 }
93 }
94
95 if (!bestdiv) {
96 bestdiv = (1 << divider->width);
97 if (divider->flags & CLK_DIVIDER_ONE_BASED)
98 bestdiv--;
99 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
100 }
101
102 return bestdiv;
103}
104
105static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *prate)
107{
108 int div;
109 div = clk_divider_bestdiv(hw, rate, prate);
110
111 return *prate / div;
112}
113
114static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
115 unsigned long parent_rate)
116{
117 struct clk_divider *divider = to_clk_divider(hw);
118 unsigned int div;
119 unsigned long flags = 0;
120 u32 val;
121
122 div = parent_rate / rate;
123
124 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
125 div--;
126
127 if (div > div_mask(divider))
128 div = div_mask(divider);
129
130 if (divider->lock)
131 spin_lock_irqsave(divider->lock, flags);
132
133 val = readl(divider->reg);
134 val &= ~(div_mask(divider) << divider->shift);
135 val |= div << divider->shift;
136 writel(val, divider->reg);
137
138 if (divider->lock)
139 spin_unlock_irqrestore(divider->lock, flags);
140
141 return 0;
142}
143
144const struct clk_ops clk_divider_ops = {
145 .recalc_rate = clk_divider_recalc_rate,
146 .round_rate = clk_divider_round_rate,
147 .set_rate = clk_divider_set_rate,
148};
149EXPORT_SYMBOL_GPL(clk_divider_ops);
150
151/**
152 * clk_register_divider - register a divider clock with the clock framework
153 * @dev: device registering this clock
154 * @name: name of this clock
155 * @parent_name: name of clock's parent
156 * @flags: framework-specific flags
157 * @reg: register address to adjust divider
158 * @shift: number of bits to shift the bitfield
159 * @width: width of the bitfield
160 * @clk_divider_flags: divider-specific flags for this clock
161 * @lock: shared register lock for this clock
162 */
163struct clk *clk_register_divider(struct device *dev, const char *name,
164 const char *parent_name, unsigned long flags,
165 void __iomem *reg, u8 shift, u8 width,
166 u8 clk_divider_flags, spinlock_t *lock)
167{
168 struct clk_divider *div;
169 struct clk *clk;
170 struct clk_init_data init;
171
172 /* allocate the divider */
173 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
174 if (!div) {
175 pr_err("%s: could not allocate divider clk\n", __func__);
176 return ERR_PTR(-ENOMEM);
177 }
178
179 init.name = name;
180 init.ops = &clk_divider_ops;
181 init.flags = flags;
182 init.parent_names = (parent_name ? &parent_name: NULL);
183 init.num_parents = (parent_name ? 1 : 0);
184
185 /* struct clk_divider assignments */
186 div->reg = reg;
187 div->shift = shift;
188 div->width = width;
189 div->flags = clk_divider_flags;
190 div->lock = lock;
191 div->hw.init = &init;
192
193 /* register the clock */
194 clk = clk_register(dev, &div->hw);
195
196 if (IS_ERR(clk))
197 kfree(div);
198
199 return clk;
200}
1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adjustable divider clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/log2.h>
20
21/*
22 * DOC: basic adjustable divider clock that cannot gate
23 *
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
28 * parent - fixed parent. No clk_set_parent support
29 */
30
31#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
32
33#define div_mask(d) ((1 << ((d)->width)) - 1)
34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
36{
37 unsigned int maxdiv = 0;
38 const struct clk_div_table *clkt;
39
40 for (clkt = table; clkt->div; clkt++)
41 if (clkt->div > maxdiv)
42 maxdiv = clkt->div;
43 return maxdiv;
44}
45
46static unsigned int _get_maxdiv(struct clk_divider *divider)
47{
48 if (divider->flags & CLK_DIVIDER_ONE_BASED)
49 return div_mask(divider);
50 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
51 return 1 << div_mask(divider);
52 if (divider->table)
53 return _get_table_maxdiv(divider->table);
54 return div_mask(divider) + 1;
55}
56
57static unsigned int _get_table_div(const struct clk_div_table *table,
58 unsigned int val)
59{
60 const struct clk_div_table *clkt;
61
62 for (clkt = table; clkt->div; clkt++)
63 if (clkt->val == val)
64 return clkt->div;
65 return 0;
66}
67
68static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
69{
70 if (divider->flags & CLK_DIVIDER_ONE_BASED)
71 return val;
72 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
73 return 1 << val;
74 if (divider->table)
75 return _get_table_div(divider->table, val);
76 return val + 1;
77}
78
79static unsigned int _get_table_val(const struct clk_div_table *table,
80 unsigned int div)
81{
82 const struct clk_div_table *clkt;
83
84 for (clkt = table; clkt->div; clkt++)
85 if (clkt->div == div)
86 return clkt->val;
87 return 0;
88}
89
90static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
91{
92 if (divider->flags & CLK_DIVIDER_ONE_BASED)
93 return div;
94 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
95 return __ffs(div);
96 if (divider->table)
97 return _get_table_val(divider->table, div);
98 return div - 1;
99}
100
101static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
102 unsigned long parent_rate)
103{
104 struct clk_divider *divider = to_clk_divider(hw);
105 unsigned int div, val;
106
107 val = clk_readl(divider->reg) >> divider->shift;
108 val &= div_mask(divider);
109
110 div = _get_div(divider, val);
111 if (!div) {
112 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
113 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
114 __clk_get_name(hw->clk));
115 return parent_rate;
116 }
117
118 return DIV_ROUND_UP(parent_rate, div);
119}
120
121/*
122 * The reverse of DIV_ROUND_UP: The maximum number which
123 * divided by m is r
124 */
125#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
126
127static bool _is_valid_table_div(const struct clk_div_table *table,
128 unsigned int div)
129{
130 const struct clk_div_table *clkt;
131
132 for (clkt = table; clkt->div; clkt++)
133 if (clkt->div == div)
134 return true;
135 return false;
136}
137
138static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
139{
140 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
141 return is_power_of_2(div);
142 if (divider->table)
143 return _is_valid_table_div(divider->table, div);
144 return true;
145}
146
147static int _round_up_table(const struct clk_div_table *table, int div)
148{
149 const struct clk_div_table *clkt;
150 int up = INT_MAX;
151
152 for (clkt = table; clkt->div; clkt++) {
153 if (clkt->div == div)
154 return clkt->div;
155 else if (clkt->div < div)
156 continue;
157
158 if ((clkt->div - div) < (up - div))
159 up = clkt->div;
160 }
161
162 return up;
163}
164
165static int _div_round_up(struct clk_divider *divider,
166 unsigned long parent_rate, unsigned long rate)
167{
168 int div = DIV_ROUND_UP(parent_rate, rate);
169
170 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
171 div = __roundup_pow_of_two(div);
172 if (divider->table)
173 div = _round_up_table(divider->table, div);
174
175 return div;
176}
177
178static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
179 unsigned long *best_parent_rate)
180{
181 struct clk_divider *divider = to_clk_divider(hw);
182 int i, bestdiv = 0;
183 unsigned long parent_rate, best = 0, now, maxdiv;
184 unsigned long parent_rate_saved = *best_parent_rate;
185
186 if (!rate)
187 rate = 1;
188
189 maxdiv = _get_maxdiv(divider);
190
191 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
192 parent_rate = *best_parent_rate;
193 bestdiv = _div_round_up(divider, parent_rate, rate);
194 bestdiv = bestdiv == 0 ? 1 : bestdiv;
195 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
196 return bestdiv;
197 }
198
199 /*
200 * The maximum divider we can use without overflowing
201 * unsigned long in rate * i below
202 */
203 maxdiv = min(ULONG_MAX / rate, maxdiv);
204
205 for (i = 1; i <= maxdiv; i++) {
206 if (!_is_valid_div(divider, i))
207 continue;
208 if (rate * i == parent_rate_saved) {
209 /*
210 * It's the most ideal case if the requested rate can be
211 * divided from parent clock without needing to change
212 * parent rate, so return the divider immediately.
213 */
214 *best_parent_rate = parent_rate_saved;
215 return i;
216 }
217 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
218 MULT_ROUND_UP(rate, i));
219 now = DIV_ROUND_UP(parent_rate, i);
220 if (now <= rate && now > best) {
221 bestdiv = i;
222 best = now;
223 *best_parent_rate = parent_rate;
224 }
225 }
226
227 if (!bestdiv) {
228 bestdiv = _get_maxdiv(divider);
229 *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
230 }
231
232 return bestdiv;
233}
234
235static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
236 unsigned long *prate)
237{
238 int div;
239 div = clk_divider_bestdiv(hw, rate, prate);
240
241 return DIV_ROUND_UP(*prate, div);
242}
243
244static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
245 unsigned long parent_rate)
246{
247 struct clk_divider *divider = to_clk_divider(hw);
248 unsigned int div, value;
249 unsigned long flags = 0;
250 u32 val;
251
252 div = DIV_ROUND_UP(parent_rate, rate);
253
254 if (!_is_valid_div(divider, div))
255 return -EINVAL;
256
257 value = _get_val(divider, div);
258
259 if (value > div_mask(divider))
260 value = div_mask(divider);
261
262 if (divider->lock)
263 spin_lock_irqsave(divider->lock, flags);
264
265 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
266 val = div_mask(divider) << (divider->shift + 16);
267 } else {
268 val = clk_readl(divider->reg);
269 val &= ~(div_mask(divider) << divider->shift);
270 }
271 val |= value << divider->shift;
272 clk_writel(val, divider->reg);
273
274 if (divider->lock)
275 spin_unlock_irqrestore(divider->lock, flags);
276
277 return 0;
278}
279
280const struct clk_ops clk_divider_ops = {
281 .recalc_rate = clk_divider_recalc_rate,
282 .round_rate = clk_divider_round_rate,
283 .set_rate = clk_divider_set_rate,
284};
285EXPORT_SYMBOL_GPL(clk_divider_ops);
286
287static struct clk *_register_divider(struct device *dev, const char *name,
288 const char *parent_name, unsigned long flags,
289 void __iomem *reg, u8 shift, u8 width,
290 u8 clk_divider_flags, const struct clk_div_table *table,
291 spinlock_t *lock)
292{
293 struct clk_divider *div;
294 struct clk *clk;
295 struct clk_init_data init;
296
297 if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
298 if (width + shift > 16) {
299 pr_warn("divider value exceeds LOWORD field\n");
300 return ERR_PTR(-EINVAL);
301 }
302 }
303
304 /* allocate the divider */
305 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
306 if (!div) {
307 pr_err("%s: could not allocate divider clk\n", __func__);
308 return ERR_PTR(-ENOMEM);
309 }
310
311 init.name = name;
312 init.ops = &clk_divider_ops;
313 init.flags = flags | CLK_IS_BASIC;
314 init.parent_names = (parent_name ? &parent_name: NULL);
315 init.num_parents = (parent_name ? 1 : 0);
316
317 /* struct clk_divider assignments */
318 div->reg = reg;
319 div->shift = shift;
320 div->width = width;
321 div->flags = clk_divider_flags;
322 div->lock = lock;
323 div->hw.init = &init;
324 div->table = table;
325
326 /* register the clock */
327 clk = clk_register(dev, &div->hw);
328
329 if (IS_ERR(clk))
330 kfree(div);
331
332 return clk;
333}
334
335/**
336 * clk_register_divider - register a divider clock with the clock framework
337 * @dev: device registering this clock
338 * @name: name of this clock
339 * @parent_name: name of clock's parent
340 * @flags: framework-specific flags
341 * @reg: register address to adjust divider
342 * @shift: number of bits to shift the bitfield
343 * @width: width of the bitfield
344 * @clk_divider_flags: divider-specific flags for this clock
345 * @lock: shared register lock for this clock
346 */
347struct clk *clk_register_divider(struct device *dev, const char *name,
348 const char *parent_name, unsigned long flags,
349 void __iomem *reg, u8 shift, u8 width,
350 u8 clk_divider_flags, spinlock_t *lock)
351{
352 return _register_divider(dev, name, parent_name, flags, reg, shift,
353 width, clk_divider_flags, NULL, lock);
354}
355EXPORT_SYMBOL_GPL(clk_register_divider);
356
357/**
358 * clk_register_divider_table - register a table based divider clock with
359 * the clock framework
360 * @dev: device registering this clock
361 * @name: name of this clock
362 * @parent_name: name of clock's parent
363 * @flags: framework-specific flags
364 * @reg: register address to adjust divider
365 * @shift: number of bits to shift the bitfield
366 * @width: width of the bitfield
367 * @clk_divider_flags: divider-specific flags for this clock
368 * @table: array of divider/value pairs ending with a div set to 0
369 * @lock: shared register lock for this clock
370 */
371struct clk *clk_register_divider_table(struct device *dev, const char *name,
372 const char *parent_name, unsigned long flags,
373 void __iomem *reg, u8 shift, u8 width,
374 u8 clk_divider_flags, const struct clk_div_table *table,
375 spinlock_t *lock)
376{
377 return _register_divider(dev, name, parent_name, flags, reg, shift,
378 width, clk_divider_flags, table, lock);
379}
380EXPORT_SYMBOL_GPL(clk_register_divider_table);