1#ifndef __ASM_SH_HW_IRQ_H
 2#define __ASM_SH_HW_IRQ_H
 3
 4#include <linux/init.h>
 5#include <linux/sh_intc.h>
 6#include <linux/atomic.h>
 7
 8extern atomic_t irq_err_count;
 9
10struct ipr_data {
11	unsigned char irq;
12	unsigned char ipr_idx;		/* Index for the IPR registered */
13	unsigned char shift;		/* Number of bits to shift the data */
14	unsigned char priority;		/* The priority */
15};
16
17struct ipr_desc {
18	unsigned long *ipr_offsets;
19	unsigned int nr_offsets;
20	struct ipr_data *ipr_data;
21	unsigned int nr_irqs;
22	struct irq_chip chip;
23};
24
25void register_ipr_controller(struct ipr_desc *);
26
27void __init plat_irq_setup(void);
28void __init plat_irq_setup_sh3(void);
29void __init plat_irq_setup_pins(int mode);
30
31enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
32       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
33       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
34
35#endif /* __ASM_SH_HW_IRQ_H */

 1#ifndef __ASM_SH_HW_IRQ_H
 2#define __ASM_SH_HW_IRQ_H
 3
 4#include <linux/init.h>
 5#include <linux/sh_intc.h>
 6#include <linux/atomic.h>
 7
 8extern atomic_t irq_err_count;
 9
10struct ipr_data {
11	unsigned char irq;
12	unsigned char ipr_idx;		/* Index for the IPR registered */
13	unsigned char shift;		/* Number of bits to shift the data */
14	unsigned char priority;		/* The priority */
15};
16
17struct ipr_desc {
18	unsigned long *ipr_offsets;
19	unsigned int nr_offsets;
20	struct ipr_data *ipr_data;
21	unsigned int nr_irqs;
22	struct irq_chip chip;
23};
24
25void register_ipr_controller(struct ipr_desc *);
26
27void __init plat_irq_setup(void);
28void __init plat_irq_setup_sh3(void);
29void __init plat_irq_setup_pins(int mode);
30
31enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
32       IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
33       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
34
35#endif /* __ASM_SH_HW_IRQ_H */