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1/*
2 * Cache operations for the cache instruction.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
9 * (C) Copyright 1999 Silicon Graphics, Inc.
10 */
11#ifndef __ASM_CACHEOPS_H
12#define __ASM_CACHEOPS_H
13
14/*
15 * Cache Operations available on all MIPS processors with R4000-style caches
16 */
17#define Index_Invalidate_I 0x00
18#define Index_Writeback_Inv_D 0x01
19#define Index_Load_Tag_I 0x04
20#define Index_Load_Tag_D 0x05
21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09
23#if defined(CONFIG_CPU_LOONGSON2)
24#define Hit_Invalidate_I 0x00
25#else
26#define Hit_Invalidate_I 0x10
27#endif
28#define Hit_Invalidate_D 0x11
29#define Hit_Writeback_Inv_D 0x15
30
31/*
32 * R4000-specific cacheops
33 */
34#define Create_Dirty_Excl_D 0x0d
35#define Fill 0x14
36#define Hit_Writeback_I 0x18
37#define Hit_Writeback_D 0x19
38
39/*
40 * R4000SC and R4400SC-specific cacheops
41 */
42#define Index_Invalidate_SI 0x02
43#define Index_Writeback_Inv_SD 0x03
44#define Index_Load_Tag_SI 0x06
45#define Index_Load_Tag_SD 0x07
46#define Index_Store_Tag_SI 0x0A
47#define Index_Store_Tag_SD 0x0B
48#define Create_Dirty_Excl_SD 0x0f
49#define Hit_Invalidate_SI 0x12
50#define Hit_Invalidate_SD 0x13
51#define Hit_Writeback_Inv_SD 0x17
52#define Hit_Writeback_SD 0x1b
53#define Hit_Set_Virtual_SI 0x1e
54#define Hit_Set_Virtual_SD 0x1f
55
56/*
57 * R5000-specific cacheops
58 */
59#define R5K_Page_Invalidate_S 0x17
60
61/*
62 * RM7000-specific cacheops
63 */
64#define Page_Invalidate_T 0x16
65#define Index_Store_Tag_T 0x0a
66#define Index_Load_Tag_T 0x06
67
68/*
69 * R10000-specific cacheops
70 *
71 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
72 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
73 */
74#define Index_Writeback_Inv_S 0x03
75#define Index_Load_Tag_S 0x07
76#define Index_Store_Tag_S 0x0B
77#define Hit_Invalidate_S 0x13
78#define Cache_Barrier 0x14
79#define Hit_Writeback_Inv_S 0x17
80#define Index_Load_Data_I 0x18
81#define Index_Load_Data_D 0x19
82#define Index_Load_Data_S 0x1b
83#define Index_Store_Data_I 0x1c
84#define Index_Store_Data_D 0x1d
85#define Index_Store_Data_S 0x1f
86
87#endif /* __ASM_CACHEOPS_H */
1/*
2 * Cache operations for the cache instruction.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
9 * (C) Copyright 1999 Silicon Graphics, Inc.
10 */
11#ifndef __ASM_CACHEOPS_H
12#define __ASM_CACHEOPS_H
13
14/*
15 * Cache Operations available on all MIPS processors with R4000-style caches
16 */
17#define Index_Invalidate_I 0x00
18#define Index_Writeback_Inv_D 0x01
19#define Index_Load_Tag_I 0x04
20#define Index_Load_Tag_D 0x05
21#define Index_Store_Tag_I 0x08
22#define Index_Store_Tag_D 0x09
23#define Hit_Invalidate_I 0x10
24#define Hit_Invalidate_D 0x11
25#define Hit_Writeback_Inv_D 0x15
26
27/*
28 * R4000-specific cacheops
29 */
30#define Create_Dirty_Excl_D 0x0d
31#define Fill 0x14
32#define Hit_Writeback_I 0x18
33#define Hit_Writeback_D 0x19
34
35/*
36 * R4000SC and R4400SC-specific cacheops
37 */
38#define Index_Invalidate_SI 0x02
39#define Index_Writeback_Inv_SD 0x03
40#define Index_Load_Tag_SI 0x06
41#define Index_Load_Tag_SD 0x07
42#define Index_Store_Tag_SI 0x0A
43#define Index_Store_Tag_SD 0x0B
44#define Create_Dirty_Excl_SD 0x0f
45#define Hit_Invalidate_SI 0x12
46#define Hit_Invalidate_SD 0x13
47#define Hit_Writeback_Inv_SD 0x17
48#define Hit_Writeback_SD 0x1b
49#define Hit_Set_Virtual_SI 0x1e
50#define Hit_Set_Virtual_SD 0x1f
51
52/*
53 * R5000-specific cacheops
54 */
55#define R5K_Page_Invalidate_S 0x17
56
57/*
58 * RM7000-specific cacheops
59 */
60#define Page_Invalidate_T 0x16
61#define Index_Store_Tag_T 0x0a
62#define Index_Load_Tag_T 0x06
63
64/*
65 * R10000-specific cacheops
66 *
67 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
68 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
69 */
70#define Index_Writeback_Inv_S 0x03
71#define Index_Load_Tag_S 0x07
72#define Index_Store_Tag_S 0x0B
73#define Hit_Invalidate_S 0x13
74#define Cache_Barrier 0x14
75#define Hit_Writeback_Inv_S 0x17
76#define Index_Load_Data_I 0x18
77#define Index_Load_Data_D 0x19
78#define Index_Load_Data_S 0x1b
79#define Index_Store_Data_I 0x1c
80#define Index_Store_Data_D 0x1d
81#define Index_Store_Data_S 0x1f
82
83/*
84 * Loongson2-specific cacheops
85 */
86#define Hit_Invalidate_I_Loongson2 0x00
87
88#endif /* __ASM_CACHEOPS_H */