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1/*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/proc-fns.h>
16#include <asm/irq.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <asm/system_misc.h>
20#include <mach/at91sam9263.h>
21#include <mach/at91_pmc.h>
22#include <mach/at91_rstc.h>
23
24#include "soc.h"
25#include "generic.h"
26#include "clock.h"
27#include "sam9_smc.h"
28
29/* --------------------------------------------------------------------
30 * Clocks
31 * -------------------------------------------------------------------- */
32
33/*
34 * The peripheral clocks.
35 */
36static struct clk pioA_clk = {
37 .name = "pioA_clk",
38 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
40};
41static struct clk pioB_clk = {
42 .name = "pioB_clk",
43 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioCDE_clk = {
47 .name = "pioCDE_clk",
48 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk usart0_clk = {
52 .name = "usart0_clk",
53 .pmc_mask = 1 << AT91SAM9263_ID_US0,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk usart1_clk = {
57 .name = "usart1_clk",
58 .pmc_mask = 1 << AT91SAM9263_ID_US1,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart2_clk = {
62 .name = "usart2_clk",
63 .pmc_mask = 1 << AT91SAM9263_ID_US2,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk mmc0_clk = {
67 .name = "mci0_clk",
68 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk mmc1_clk = {
72 .name = "mci1_clk",
73 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk can_clk = {
77 .name = "can_clk",
78 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk twi_clk = {
82 .name = "twi_clk",
83 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk spi0_clk = {
87 .name = "spi0_clk",
88 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk spi1_clk = {
92 .name = "spi1_clk",
93 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk ssc0_clk = {
97 .name = "ssc0_clk",
98 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc1_clk = {
102 .name = "ssc1_clk",
103 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk ac97_clk = {
107 .name = "ac97_clk",
108 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tcb_clk = {
112 .name = "tcb_clk",
113 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk pwm_clk = {
117 .name = "pwm_clk",
118 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk macb_clk = {
122 .name = "pclk",
123 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk dma_clk = {
127 .name = "dma_clk",
128 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk twodge_clk = {
132 .name = "2dge_clk",
133 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk udc_clk = {
137 .name = "udc_clk",
138 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk isi_clk = {
142 .name = "isi_clk",
143 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ohci_clk = {
152 .name = "ohci_clk",
153 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156
157static struct clk *periph_clocks[] __initdata = {
158 &pioA_clk,
159 &pioB_clk,
160 &pioCDE_clk,
161 &usart0_clk,
162 &usart1_clk,
163 &usart2_clk,
164 &mmc0_clk,
165 &mmc1_clk,
166 &can_clk,
167 &twi_clk,
168 &spi0_clk,
169 &spi1_clk,
170 &ssc0_clk,
171 &ssc1_clk,
172 &ac97_clk,
173 &tcb_clk,
174 &pwm_clk,
175 &macb_clk,
176 &twodge_clk,
177 &udc_clk,
178 &isi_clk,
179 &lcdc_clk,
180 &dma_clk,
181 &ohci_clk,
182 // irq0 .. irq1
183};
184
185static struct clk_lookup periph_clocks_lookups[] = {
186 /* One additional fake clock for macb_hclk */
187 CLKDEV_CON_ID("hclk", &macb_clk),
188 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
189 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
190 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
191 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
192 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
193 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
194 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
195 /* fake hclk clock */
196 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
197 CLKDEV_CON_ID("pioA", &pioA_clk),
198 CLKDEV_CON_ID("pioB", &pioB_clk),
199 CLKDEV_CON_ID("pioC", &pioCDE_clk),
200 CLKDEV_CON_ID("pioD", &pioCDE_clk),
201 CLKDEV_CON_ID("pioE", &pioCDE_clk),
202 /* more usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
204 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
207 /* more tc lookup table for DT entries */
208 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
209 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
210 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
211 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
212};
213
214static struct clk_lookup usart_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
219};
220
221/*
222 * The four programmable clocks.
223 * You must configure pin multiplexing to bring these signals out.
224 */
225static struct clk pck0 = {
226 .name = "pck0",
227 .pmc_mask = AT91_PMC_PCK0,
228 .type = CLK_TYPE_PROGRAMMABLE,
229 .id = 0,
230};
231static struct clk pck1 = {
232 .name = "pck1",
233 .pmc_mask = AT91_PMC_PCK1,
234 .type = CLK_TYPE_PROGRAMMABLE,
235 .id = 1,
236};
237static struct clk pck2 = {
238 .name = "pck2",
239 .pmc_mask = AT91_PMC_PCK2,
240 .type = CLK_TYPE_PROGRAMMABLE,
241 .id = 2,
242};
243static struct clk pck3 = {
244 .name = "pck3",
245 .pmc_mask = AT91_PMC_PCK3,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 3,
248};
249
250static void __init at91sam9263_register_clocks(void)
251{
252 int i;
253
254 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
255 clk_register(periph_clocks[i]);
256
257 clkdev_add_table(periph_clocks_lookups,
258 ARRAY_SIZE(periph_clocks_lookups));
259 clkdev_add_table(usart_clocks_lookups,
260 ARRAY_SIZE(usart_clocks_lookups));
261
262 clk_register(&pck0);
263 clk_register(&pck1);
264 clk_register(&pck2);
265 clk_register(&pck3);
266}
267
268/* --------------------------------------------------------------------
269 * GPIO
270 * -------------------------------------------------------------------- */
271
272static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
273 {
274 .id = AT91SAM9263_ID_PIOA,
275 .regbase = AT91SAM9263_BASE_PIOA,
276 }, {
277 .id = AT91SAM9263_ID_PIOB,
278 .regbase = AT91SAM9263_BASE_PIOB,
279 }, {
280 .id = AT91SAM9263_ID_PIOCDE,
281 .regbase = AT91SAM9263_BASE_PIOC,
282 }, {
283 .id = AT91SAM9263_ID_PIOCDE,
284 .regbase = AT91SAM9263_BASE_PIOD,
285 }, {
286 .id = AT91SAM9263_ID_PIOCDE,
287 .regbase = AT91SAM9263_BASE_PIOE,
288 }
289};
290
291/* --------------------------------------------------------------------
292 * AT91SAM9263 processor initialization
293 * -------------------------------------------------------------------- */
294
295static void __init at91sam9263_map_io(void)
296{
297 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
298 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
299}
300
301static void __init at91sam9263_ioremap_registers(void)
302{
303 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
304 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
305 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
306 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
307 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
308 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
309 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
310 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
311}
312
313static void __init at91sam9263_initialize(void)
314{
315 arm_pm_idle = at91sam9_idle;
316 arm_pm_restart = at91sam9_alt_restart;
317 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
318
319 /* Register GPIO subsystem */
320 at91_gpio_init(at91sam9263_gpio, 5);
321}
322
323/* --------------------------------------------------------------------
324 * Interrupt initialization
325 * -------------------------------------------------------------------- */
326
327/*
328 * The default interrupt priority levels (0 = lowest, 7 = highest).
329 */
330static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
331 7, /* Advanced Interrupt Controller (FIQ) */
332 7, /* System Peripherals */
333 1, /* Parallel IO Controller A */
334 1, /* Parallel IO Controller B */
335 1, /* Parallel IO Controller C, D and E */
336 0,
337 0,
338 5, /* USART 0 */
339 5, /* USART 1 */
340 5, /* USART 2 */
341 0, /* Multimedia Card Interface 0 */
342 0, /* Multimedia Card Interface 1 */
343 3, /* CAN */
344 6, /* Two-Wire Interface */
345 5, /* Serial Peripheral Interface 0 */
346 5, /* Serial Peripheral Interface 1 */
347 4, /* Serial Synchronous Controller 0 */
348 4, /* Serial Synchronous Controller 1 */
349 5, /* AC97 Controller */
350 0, /* Timer Counter 0, 1 and 2 */
351 0, /* Pulse Width Modulation Controller */
352 3, /* Ethernet */
353 0,
354 0, /* 2D Graphic Engine */
355 2, /* USB Device Port */
356 0, /* Image Sensor Interface */
357 3, /* LDC Controller */
358 0, /* DMA Controller */
359 0,
360 2, /* USB Host port */
361 0, /* Advanced Interrupt Controller (IRQ0) */
362 0, /* Advanced Interrupt Controller (IRQ1) */
363};
364
365struct at91_init_soc __initdata at91sam9263_soc = {
366 .map_io = at91sam9263_map_io,
367 .default_irq_priority = at91sam9263_default_irq_priority,
368 .ioremap_registers = at91sam9263_ioremap_registers,
369 .register_clocks = at91sam9263_register_clocks,
370 .init = at91sam9263_initialize,
371};
1/*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h>
21#include <mach/at91sam9263.h>
22#include <mach/hardware.h>
23
24#include "at91_aic.h"
25#include "at91_rstc.h"
26#include "soc.h"
27#include "generic.h"
28#include "clock.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35
36/*
37 * The peripheral clocks.
38 */
39static struct clk pioA_clk = {
40 .name = "pioA_clk",
41 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
42 .type = CLK_TYPE_PERIPHERAL,
43};
44static struct clk pioB_clk = {
45 .name = "pioB_clk",
46 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk pioCDE_clk = {
50 .name = "pioCDE_clk",
51 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk usart0_clk = {
55 .name = "usart0_clk",
56 .pmc_mask = 1 << AT91SAM9263_ID_US0,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk usart1_clk = {
60 .name = "usart1_clk",
61 .pmc_mask = 1 << AT91SAM9263_ID_US1,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk usart2_clk = {
65 .name = "usart2_clk",
66 .pmc_mask = 1 << AT91SAM9263_ID_US2,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk mmc0_clk = {
70 .name = "mci0_clk",
71 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk mmc1_clk = {
75 .name = "mci1_clk",
76 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk can_clk = {
80 .name = "can_clk",
81 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk twi_clk = {
85 .name = "twi_clk",
86 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk ssc0_clk = {
100 .name = "ssc0_clk",
101 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk ssc1_clk = {
105 .name = "ssc1_clk",
106 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk ac97_clk = {
110 .name = "ac97_clk",
111 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk tcb_clk = {
115 .name = "tcb_clk",
116 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk pwm_clk = {
120 .name = "pwm_clk",
121 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk macb_clk = {
125 .name = "pclk",
126 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk dma_clk = {
130 .name = "dma_clk",
131 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk twodge_clk = {
135 .name = "2dge_clk",
136 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk udc_clk = {
140 .name = "udc_clk",
141 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk isi_clk = {
145 .name = "isi_clk",
146 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149static struct clk lcdc_clk = {
150 .name = "lcdc_clk",
151 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
152 .type = CLK_TYPE_PERIPHERAL,
153};
154static struct clk ohci_clk = {
155 .name = "ohci_clk",
156 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
157 .type = CLK_TYPE_PERIPHERAL,
158};
159
160static struct clk *periph_clocks[] __initdata = {
161 &pioA_clk,
162 &pioB_clk,
163 &pioCDE_clk,
164 &usart0_clk,
165 &usart1_clk,
166 &usart2_clk,
167 &mmc0_clk,
168 &mmc1_clk,
169 &can_clk,
170 &twi_clk,
171 &spi0_clk,
172 &spi1_clk,
173 &ssc0_clk,
174 &ssc1_clk,
175 &ac97_clk,
176 &tcb_clk,
177 &pwm_clk,
178 &macb_clk,
179 &twodge_clk,
180 &udc_clk,
181 &isi_clk,
182 &lcdc_clk,
183 &dma_clk,
184 &ohci_clk,
185 // irq0 .. irq1
186};
187
188static struct clk_lookup periph_clocks_lookups[] = {
189 /* One additional fake clock for macb_hclk */
190 CLKDEV_CON_ID("hclk", &macb_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
195 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
196 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
198 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
202 /* fake hclk clock */
203 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioCDE_clk),
207 CLKDEV_CON_ID("pioD", &pioCDE_clk),
208 CLKDEV_CON_ID("pioE", &pioCDE_clk),
209 /* more usart lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
211 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
212 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
213 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
214 /* more tc lookup table for DT entries */
215 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
216 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
219 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
220 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
228};
229
230static struct clk_lookup usart_clocks_lookups[] = {
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
235};
236
237/*
238 * The four programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
240 */
241static struct clk pck0 = {
242 .name = "pck0",
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 0,
246};
247static struct clk pck1 = {
248 .name = "pck1",
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 1,
252};
253static struct clk pck2 = {
254 .name = "pck2",
255 .pmc_mask = AT91_PMC_PCK2,
256 .type = CLK_TYPE_PROGRAMMABLE,
257 .id = 2,
258};
259static struct clk pck3 = {
260 .name = "pck3",
261 .pmc_mask = AT91_PMC_PCK3,
262 .type = CLK_TYPE_PROGRAMMABLE,
263 .id = 3,
264};
265
266static void __init at91sam9263_register_clocks(void)
267{
268 int i;
269
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
272
273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
277
278 clk_register(&pck0);
279 clk_register(&pck1);
280 clk_register(&pck2);
281 clk_register(&pck3);
282}
283
284/* --------------------------------------------------------------------
285 * GPIO
286 * -------------------------------------------------------------------- */
287
288static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
289 {
290 .id = AT91SAM9263_ID_PIOA,
291 .regbase = AT91SAM9263_BASE_PIOA,
292 }, {
293 .id = AT91SAM9263_ID_PIOB,
294 .regbase = AT91SAM9263_BASE_PIOB,
295 }, {
296 .id = AT91SAM9263_ID_PIOCDE,
297 .regbase = AT91SAM9263_BASE_PIOC,
298 }, {
299 .id = AT91SAM9263_ID_PIOCDE,
300 .regbase = AT91SAM9263_BASE_PIOD,
301 }, {
302 .id = AT91SAM9263_ID_PIOCDE,
303 .regbase = AT91SAM9263_BASE_PIOE,
304 }
305};
306
307/* --------------------------------------------------------------------
308 * AT91SAM9263 processor initialization
309 * -------------------------------------------------------------------- */
310
311static void __init at91sam9263_map_io(void)
312{
313 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
314 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
315}
316
317static void __init at91sam9263_ioremap_registers(void)
318{
319 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
320 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
321 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
322 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
323 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
324 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
325 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
326 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
327 at91_pm_set_standby(at91sam9_sdram_standby);
328}
329
330static void __init at91sam9263_initialize(void)
331{
332 arm_pm_idle = at91sam9_idle;
333 arm_pm_restart = at91sam9_alt_restart;
334
335 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
336 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
337
338 /* Register GPIO subsystem */
339 at91_gpio_init(at91sam9263_gpio, 5);
340}
341
342/* --------------------------------------------------------------------
343 * Interrupt initialization
344 * -------------------------------------------------------------------- */
345
346/*
347 * The default interrupt priority levels (0 = lowest, 7 = highest).
348 */
349static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
350 7, /* Advanced Interrupt Controller (FIQ) */
351 7, /* System Peripherals */
352 1, /* Parallel IO Controller A */
353 1, /* Parallel IO Controller B */
354 1, /* Parallel IO Controller C, D and E */
355 0,
356 0,
357 5, /* USART 0 */
358 5, /* USART 1 */
359 5, /* USART 2 */
360 0, /* Multimedia Card Interface 0 */
361 0, /* Multimedia Card Interface 1 */
362 3, /* CAN */
363 6, /* Two-Wire Interface */
364 5, /* Serial Peripheral Interface 0 */
365 5, /* Serial Peripheral Interface 1 */
366 4, /* Serial Synchronous Controller 0 */
367 4, /* Serial Synchronous Controller 1 */
368 5, /* AC97 Controller */
369 0, /* Timer Counter 0, 1 and 2 */
370 0, /* Pulse Width Modulation Controller */
371 3, /* Ethernet */
372 0,
373 0, /* 2D Graphic Engine */
374 2, /* USB Device Port */
375 0, /* Image Sensor Interface */
376 3, /* LDC Controller */
377 0, /* DMA Controller */
378 0,
379 2, /* USB Host port */
380 0, /* Advanced Interrupt Controller (IRQ0) */
381 0, /* Advanced Interrupt Controller (IRQ1) */
382};
383
384AT91_SOC_START(at91sam9263)
385 .map_io = at91sam9263_map_io,
386 .default_irq_priority = at91sam9263_default_irq_priority,
387 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
388 .ioremap_registers = at91sam9263_ioremap_registers,
389 .register_clocks = at91sam9263_register_clocks,
390 .init = at91sam9263_initialize,
391AT91_SOC_END