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1/*
2 * Davicom DM9000 Fast Ethernet driver for Linux.
3 * Copyright (C) 1997 Sten Wang
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
16 *
17 * Additional updates, Copyright:
18 * Ben Dooks <ben@simtec.co.uk>
19 * Sascha Hauer <s.hauer@pengutronix.de>
20 */
21
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/skbuff.h>
29#include <linux/spinlock.h>
30#include <linux/crc32.h>
31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/dm9000.h>
34#include <linux/delay.h>
35#include <linux/platform_device.h>
36#include <linux/irq.h>
37#include <linux/slab.h>
38
39#include <asm/delay.h>
40#include <asm/irq.h>
41#include <asm/io.h>
42
43#include "dm9000.h"
44
45/* Board/System/Debug information/definition ---------------- */
46
47#define DM9000_PHY 0x40 /* PHY address 0x01 */
48
49#define CARDNAME "dm9000"
50#define DRV_VERSION "1.31"
51
52/*
53 * Transmit timeout, default 5 seconds.
54 */
55static int watchdog = 5000;
56module_param(watchdog, int, 0400);
57MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
58
59/*
60 * Debug messages level
61 */
62static int debug;
63module_param(debug, int, 0644);
64MODULE_PARM_DESC(debug, "dm9000 debug level (0-4)");
65
66/* DM9000 register address locking.
67 *
68 * The DM9000 uses an address register to control where data written
69 * to the data register goes. This means that the address register
70 * must be preserved over interrupts or similar calls.
71 *
72 * During interrupt and other critical calls, a spinlock is used to
73 * protect the system, but the calls themselves save the address
74 * in the address register in case they are interrupting another
75 * access to the device.
76 *
77 * For general accesses a lock is provided so that calls which are
78 * allowed to sleep are serialised so that the address register does
79 * not need to be saved. This lock also serves to serialise access
80 * to the EEPROM and PHY access registers which are shared between
81 * these two devices.
82 */
83
84/* The driver supports the original DM9000E, and now the two newer
85 * devices, DM9000A and DM9000B.
86 */
87
88enum dm9000_type {
89 TYPE_DM9000E, /* original DM9000 */
90 TYPE_DM9000A,
91 TYPE_DM9000B
92};
93
94/* Structure/enum declaration ------------------------------- */
95typedef struct board_info {
96
97 void __iomem *io_addr; /* Register I/O base address */
98 void __iomem *io_data; /* Data I/O address */
99 u16 irq; /* IRQ */
100
101 u16 tx_pkt_cnt;
102 u16 queue_pkt_len;
103 u16 queue_start_addr;
104 u16 queue_ip_summed;
105 u16 dbug_cnt;
106 u8 io_mode; /* 0:word, 2:byte */
107 u8 phy_addr;
108 u8 imr_all;
109
110 unsigned int flags;
111 unsigned int in_suspend :1;
112 unsigned int wake_supported :1;
113
114 enum dm9000_type type;
115
116 void (*inblk)(void __iomem *port, void *data, int length);
117 void (*outblk)(void __iomem *port, void *data, int length);
118 void (*dumpblk)(void __iomem *port, int length);
119
120 struct device *dev; /* parent device */
121
122 struct resource *addr_res; /* resources found */
123 struct resource *data_res;
124 struct resource *addr_req; /* resources requested */
125 struct resource *data_req;
126 struct resource *irq_res;
127
128 int irq_wake;
129
130 struct mutex addr_lock; /* phy and eeprom access lock */
131
132 struct delayed_work phy_poll;
133 struct net_device *ndev;
134
135 spinlock_t lock;
136
137 struct mii_if_info mii;
138 u32 msg_enable;
139 u32 wake_state;
140
141 int ip_summed;
142} board_info_t;
143
144/* debug code */
145
146#define dm9000_dbg(db, lev, msg...) do { \
147 if ((lev) < debug) { \
148 dev_dbg(db->dev, msg); \
149 } \
150} while (0)
151
152static inline board_info_t *to_dm9000_board(struct net_device *dev)
153{
154 return netdev_priv(dev);
155}
156
157/* DM9000 network board routine ---------------------------- */
158
159static void
160dm9000_reset(board_info_t * db)
161{
162 dev_dbg(db->dev, "resetting device\n");
163
164 /* RESET device */
165 writeb(DM9000_NCR, db->io_addr);
166 udelay(200);
167 writeb(NCR_RST, db->io_data);
168 udelay(200);
169}
170
171/*
172 * Read a byte from I/O port
173 */
174static u8
175ior(board_info_t * db, int reg)
176{
177 writeb(reg, db->io_addr);
178 return readb(db->io_data);
179}
180
181/*
182 * Write a byte to I/O port
183 */
184
185static void
186iow(board_info_t * db, int reg, int value)
187{
188 writeb(reg, db->io_addr);
189 writeb(value, db->io_data);
190}
191
192/* routines for sending block to chip */
193
194static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
195{
196 writesb(reg, data, count);
197}
198
199static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
200{
201 writesw(reg, data, (count+1) >> 1);
202}
203
204static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
205{
206 writesl(reg, data, (count+3) >> 2);
207}
208
209/* input block from chip to memory */
210
211static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
212{
213 readsb(reg, data, count);
214}
215
216
217static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
218{
219 readsw(reg, data, (count+1) >> 1);
220}
221
222static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
223{
224 readsl(reg, data, (count+3) >> 2);
225}
226
227/* dump block from chip to null */
228
229static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
230{
231 int i;
232 int tmp;
233
234 for (i = 0; i < count; i++)
235 tmp = readb(reg);
236}
237
238static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
239{
240 int i;
241 int tmp;
242
243 count = (count + 1) >> 1;
244
245 for (i = 0; i < count; i++)
246 tmp = readw(reg);
247}
248
249static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
250{
251 int i;
252 int tmp;
253
254 count = (count + 3) >> 2;
255
256 for (i = 0; i < count; i++)
257 tmp = readl(reg);
258}
259
260/* dm9000_set_io
261 *
262 * select the specified set of io routines to use with the
263 * device
264 */
265
266static void dm9000_set_io(struct board_info *db, int byte_width)
267{
268 /* use the size of the data resource to work out what IO
269 * routines we want to use
270 */
271
272 switch (byte_width) {
273 case 1:
274 db->dumpblk = dm9000_dumpblk_8bit;
275 db->outblk = dm9000_outblk_8bit;
276 db->inblk = dm9000_inblk_8bit;
277 break;
278
279
280 case 3:
281 dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
282 case 2:
283 db->dumpblk = dm9000_dumpblk_16bit;
284 db->outblk = dm9000_outblk_16bit;
285 db->inblk = dm9000_inblk_16bit;
286 break;
287
288 case 4:
289 default:
290 db->dumpblk = dm9000_dumpblk_32bit;
291 db->outblk = dm9000_outblk_32bit;
292 db->inblk = dm9000_inblk_32bit;
293 break;
294 }
295}
296
297static void dm9000_schedule_poll(board_info_t *db)
298{
299 if (db->type == TYPE_DM9000E)
300 schedule_delayed_work(&db->phy_poll, HZ * 2);
301}
302
303static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
304{
305 board_info_t *dm = to_dm9000_board(dev);
306
307 if (!netif_running(dev))
308 return -EINVAL;
309
310 return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL);
311}
312
313static unsigned int
314dm9000_read_locked(board_info_t *db, int reg)
315{
316 unsigned long flags;
317 unsigned int ret;
318
319 spin_lock_irqsave(&db->lock, flags);
320 ret = ior(db, reg);
321 spin_unlock_irqrestore(&db->lock, flags);
322
323 return ret;
324}
325
326static int dm9000_wait_eeprom(board_info_t *db)
327{
328 unsigned int status;
329 int timeout = 8; /* wait max 8msec */
330
331 /* The DM9000 data sheets say we should be able to
332 * poll the ERRE bit in EPCR to wait for the EEPROM
333 * operation. From testing several chips, this bit
334 * does not seem to work.
335 *
336 * We attempt to use the bit, but fall back to the
337 * timeout (which is why we do not return an error
338 * on expiry) to say that the EEPROM operation has
339 * completed.
340 */
341
342 while (1) {
343 status = dm9000_read_locked(db, DM9000_EPCR);
344
345 if ((status & EPCR_ERRE) == 0)
346 break;
347
348 msleep(1);
349
350 if (timeout-- < 0) {
351 dev_dbg(db->dev, "timeout waiting EEPROM\n");
352 break;
353 }
354 }
355
356 return 0;
357}
358
359/*
360 * Read a word data from EEPROM
361 */
362static void
363dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
364{
365 unsigned long flags;
366
367 if (db->flags & DM9000_PLATF_NO_EEPROM) {
368 to[0] = 0xff;
369 to[1] = 0xff;
370 return;
371 }
372
373 mutex_lock(&db->addr_lock);
374
375 spin_lock_irqsave(&db->lock, flags);
376
377 iow(db, DM9000_EPAR, offset);
378 iow(db, DM9000_EPCR, EPCR_ERPRR);
379
380 spin_unlock_irqrestore(&db->lock, flags);
381
382 dm9000_wait_eeprom(db);
383
384 /* delay for at-least 150uS */
385 msleep(1);
386
387 spin_lock_irqsave(&db->lock, flags);
388
389 iow(db, DM9000_EPCR, 0x0);
390
391 to[0] = ior(db, DM9000_EPDRL);
392 to[1] = ior(db, DM9000_EPDRH);
393
394 spin_unlock_irqrestore(&db->lock, flags);
395
396 mutex_unlock(&db->addr_lock);
397}
398
399/*
400 * Write a word data to SROM
401 */
402static void
403dm9000_write_eeprom(board_info_t *db, int offset, u8 *data)
404{
405 unsigned long flags;
406
407 if (db->flags & DM9000_PLATF_NO_EEPROM)
408 return;
409
410 mutex_lock(&db->addr_lock);
411
412 spin_lock_irqsave(&db->lock, flags);
413 iow(db, DM9000_EPAR, offset);
414 iow(db, DM9000_EPDRH, data[1]);
415 iow(db, DM9000_EPDRL, data[0]);
416 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
417 spin_unlock_irqrestore(&db->lock, flags);
418
419 dm9000_wait_eeprom(db);
420
421 mdelay(1); /* wait at least 150uS to clear */
422
423 spin_lock_irqsave(&db->lock, flags);
424 iow(db, DM9000_EPCR, 0);
425 spin_unlock_irqrestore(&db->lock, flags);
426
427 mutex_unlock(&db->addr_lock);
428}
429
430/* ethtool ops */
431
432static void dm9000_get_drvinfo(struct net_device *dev,
433 struct ethtool_drvinfo *info)
434{
435 board_info_t *dm = to_dm9000_board(dev);
436
437 strcpy(info->driver, CARDNAME);
438 strcpy(info->version, DRV_VERSION);
439 strcpy(info->bus_info, to_platform_device(dm->dev)->name);
440}
441
442static u32 dm9000_get_msglevel(struct net_device *dev)
443{
444 board_info_t *dm = to_dm9000_board(dev);
445
446 return dm->msg_enable;
447}
448
449static void dm9000_set_msglevel(struct net_device *dev, u32 value)
450{
451 board_info_t *dm = to_dm9000_board(dev);
452
453 dm->msg_enable = value;
454}
455
456static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
457{
458 board_info_t *dm = to_dm9000_board(dev);
459
460 mii_ethtool_gset(&dm->mii, cmd);
461 return 0;
462}
463
464static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
465{
466 board_info_t *dm = to_dm9000_board(dev);
467
468 return mii_ethtool_sset(&dm->mii, cmd);
469}
470
471static int dm9000_nway_reset(struct net_device *dev)
472{
473 board_info_t *dm = to_dm9000_board(dev);
474 return mii_nway_restart(&dm->mii);
475}
476
477static int dm9000_set_features(struct net_device *dev,
478 netdev_features_t features)
479{
480 board_info_t *dm = to_dm9000_board(dev);
481 netdev_features_t changed = dev->features ^ features;
482 unsigned long flags;
483
484 if (!(changed & NETIF_F_RXCSUM))
485 return 0;
486
487 spin_lock_irqsave(&dm->lock, flags);
488 iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
489 spin_unlock_irqrestore(&dm->lock, flags);
490
491 return 0;
492}
493
494static u32 dm9000_get_link(struct net_device *dev)
495{
496 board_info_t *dm = to_dm9000_board(dev);
497 u32 ret;
498
499 if (dm->flags & DM9000_PLATF_EXT_PHY)
500 ret = mii_link_ok(&dm->mii);
501 else
502 ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0;
503
504 return ret;
505}
506
507#define DM_EEPROM_MAGIC (0x444D394B)
508
509static int dm9000_get_eeprom_len(struct net_device *dev)
510{
511 return 128;
512}
513
514static int dm9000_get_eeprom(struct net_device *dev,
515 struct ethtool_eeprom *ee, u8 *data)
516{
517 board_info_t *dm = to_dm9000_board(dev);
518 int offset = ee->offset;
519 int len = ee->len;
520 int i;
521
522 /* EEPROM access is aligned to two bytes */
523
524 if ((len & 1) != 0 || (offset & 1) != 0)
525 return -EINVAL;
526
527 if (dm->flags & DM9000_PLATF_NO_EEPROM)
528 return -ENOENT;
529
530 ee->magic = DM_EEPROM_MAGIC;
531
532 for (i = 0; i < len; i += 2)
533 dm9000_read_eeprom(dm, (offset + i) / 2, data + i);
534
535 return 0;
536}
537
538static int dm9000_set_eeprom(struct net_device *dev,
539 struct ethtool_eeprom *ee, u8 *data)
540{
541 board_info_t *dm = to_dm9000_board(dev);
542 int offset = ee->offset;
543 int len = ee->len;
544 int done;
545
546 /* EEPROM access is aligned to two bytes */
547
548 if (dm->flags & DM9000_PLATF_NO_EEPROM)
549 return -ENOENT;
550
551 if (ee->magic != DM_EEPROM_MAGIC)
552 return -EINVAL;
553
554 while (len > 0) {
555 if (len & 1 || offset & 1) {
556 int which = offset & 1;
557 u8 tmp[2];
558
559 dm9000_read_eeprom(dm, offset / 2, tmp);
560 tmp[which] = *data;
561 dm9000_write_eeprom(dm, offset / 2, tmp);
562
563 done = 1;
564 } else {
565 dm9000_write_eeprom(dm, offset / 2, data);
566 done = 2;
567 }
568
569 data += done;
570 offset += done;
571 len -= done;
572 }
573
574 return 0;
575}
576
577static void dm9000_get_wol(struct net_device *dev, struct ethtool_wolinfo *w)
578{
579 board_info_t *dm = to_dm9000_board(dev);
580
581 memset(w, 0, sizeof(struct ethtool_wolinfo));
582
583 /* note, we could probably support wake-phy too */
584 w->supported = dm->wake_supported ? WAKE_MAGIC : 0;
585 w->wolopts = dm->wake_state;
586}
587
588static int dm9000_set_wol(struct net_device *dev, struct ethtool_wolinfo *w)
589{
590 board_info_t *dm = to_dm9000_board(dev);
591 unsigned long flags;
592 u32 opts = w->wolopts;
593 u32 wcr = 0;
594
595 if (!dm->wake_supported)
596 return -EOPNOTSUPP;
597
598 if (opts & ~WAKE_MAGIC)
599 return -EINVAL;
600
601 if (opts & WAKE_MAGIC)
602 wcr |= WCR_MAGICEN;
603
604 mutex_lock(&dm->addr_lock);
605
606 spin_lock_irqsave(&dm->lock, flags);
607 iow(dm, DM9000_WCR, wcr);
608 spin_unlock_irqrestore(&dm->lock, flags);
609
610 mutex_unlock(&dm->addr_lock);
611
612 if (dm->wake_state != opts) {
613 /* change in wol state, update IRQ state */
614
615 if (!dm->wake_state)
616 irq_set_irq_wake(dm->irq_wake, 1);
617 else if (dm->wake_state && !opts)
618 irq_set_irq_wake(dm->irq_wake, 0);
619 }
620
621 dm->wake_state = opts;
622 return 0;
623}
624
625static const struct ethtool_ops dm9000_ethtool_ops = {
626 .get_drvinfo = dm9000_get_drvinfo,
627 .get_settings = dm9000_get_settings,
628 .set_settings = dm9000_set_settings,
629 .get_msglevel = dm9000_get_msglevel,
630 .set_msglevel = dm9000_set_msglevel,
631 .nway_reset = dm9000_nway_reset,
632 .get_link = dm9000_get_link,
633 .get_wol = dm9000_get_wol,
634 .set_wol = dm9000_set_wol,
635 .get_eeprom_len = dm9000_get_eeprom_len,
636 .get_eeprom = dm9000_get_eeprom,
637 .set_eeprom = dm9000_set_eeprom,
638};
639
640static void dm9000_show_carrier(board_info_t *db,
641 unsigned carrier, unsigned nsr)
642{
643 struct net_device *ndev = db->ndev;
644 unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
645
646 if (carrier)
647 dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n",
648 ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
649 (ncr & NCR_FDX) ? "full" : "half");
650 else
651 dev_info(db->dev, "%s: link down\n", ndev->name);
652}
653
654static void
655dm9000_poll_work(struct work_struct *w)
656{
657 struct delayed_work *dw = to_delayed_work(w);
658 board_info_t *db = container_of(dw, board_info_t, phy_poll);
659 struct net_device *ndev = db->ndev;
660
661 if (db->flags & DM9000_PLATF_SIMPLE_PHY &&
662 !(db->flags & DM9000_PLATF_EXT_PHY)) {
663 unsigned nsr = dm9000_read_locked(db, DM9000_NSR);
664 unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0;
665 unsigned new_carrier;
666
667 new_carrier = (nsr & NSR_LINKST) ? 1 : 0;
668
669 if (old_carrier != new_carrier) {
670 if (netif_msg_link(db))
671 dm9000_show_carrier(db, new_carrier, nsr);
672
673 if (!new_carrier)
674 netif_carrier_off(ndev);
675 else
676 netif_carrier_on(ndev);
677 }
678 } else
679 mii_check_media(&db->mii, netif_msg_link(db), 0);
680
681 if (netif_running(ndev))
682 dm9000_schedule_poll(db);
683}
684
685/* dm9000_release_board
686 *
687 * release a board, and any mapped resources
688 */
689
690static void
691dm9000_release_board(struct platform_device *pdev, struct board_info *db)
692{
693 /* unmap our resources */
694
695 iounmap(db->io_addr);
696 iounmap(db->io_data);
697
698 /* release the resources */
699
700 release_resource(db->data_req);
701 kfree(db->data_req);
702
703 release_resource(db->addr_req);
704 kfree(db->addr_req);
705}
706
707static unsigned char dm9000_type_to_char(enum dm9000_type type)
708{
709 switch (type) {
710 case TYPE_DM9000E: return 'e';
711 case TYPE_DM9000A: return 'a';
712 case TYPE_DM9000B: return 'b';
713 }
714
715 return '?';
716}
717
718/*
719 * Set DM9000 multicast address
720 */
721static void
722dm9000_hash_table_unlocked(struct net_device *dev)
723{
724 board_info_t *db = netdev_priv(dev);
725 struct netdev_hw_addr *ha;
726 int i, oft;
727 u32 hash_val;
728 u16 hash_table[4];
729 u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
730
731 dm9000_dbg(db, 1, "entering %s\n", __func__);
732
733 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
734 iow(db, oft, dev->dev_addr[i]);
735
736 /* Clear Hash Table */
737 for (i = 0; i < 4; i++)
738 hash_table[i] = 0x0;
739
740 /* broadcast address */
741 hash_table[3] = 0x8000;
742
743 if (dev->flags & IFF_PROMISC)
744 rcr |= RCR_PRMSC;
745
746 if (dev->flags & IFF_ALLMULTI)
747 rcr |= RCR_ALL;
748
749 /* the multicast address in Hash Table : 64 bits */
750 netdev_for_each_mc_addr(ha, dev) {
751 hash_val = ether_crc_le(6, ha->addr) & 0x3f;
752 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
753 }
754
755 /* Write the hash table to MAC MD table */
756 for (i = 0, oft = DM9000_MAR; i < 4; i++) {
757 iow(db, oft++, hash_table[i]);
758 iow(db, oft++, hash_table[i] >> 8);
759 }
760
761 iow(db, DM9000_RCR, rcr);
762}
763
764static void
765dm9000_hash_table(struct net_device *dev)
766{
767 board_info_t *db = netdev_priv(dev);
768 unsigned long flags;
769
770 spin_lock_irqsave(&db->lock, flags);
771 dm9000_hash_table_unlocked(dev);
772 spin_unlock_irqrestore(&db->lock, flags);
773}
774
775/*
776 * Initialize dm9000 board
777 */
778static void
779dm9000_init_dm9000(struct net_device *dev)
780{
781 board_info_t *db = netdev_priv(dev);
782 unsigned int imr;
783 unsigned int ncr;
784
785 dm9000_dbg(db, 1, "entering %s\n", __func__);
786
787 /* I/O mode */
788 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
789
790 /* Checksum mode */
791 if (dev->hw_features & NETIF_F_RXCSUM)
792 iow(db, DM9000_RCSR,
793 (dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
794
795 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
796
797 ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
798
799 /* if wol is needed, then always set NCR_WAKEEN otherwise we end
800 * up dumping the wake events if we disable this. There is already
801 * a wake-mask in DM9000_WCR */
802 if (db->wake_supported)
803 ncr |= NCR_WAKEEN;
804
805 iow(db, DM9000_NCR, ncr);
806
807 /* Program operating register */
808 iow(db, DM9000_TCR, 0); /* TX Polling clear */
809 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
810 iow(db, DM9000_FCR, 0xff); /* Flow Control */
811 iow(db, DM9000_SMCR, 0); /* Special Mode */
812 /* clear TX status */
813 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
814 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
815
816 /* Set address filter table */
817 dm9000_hash_table_unlocked(dev);
818
819 imr = IMR_PAR | IMR_PTM | IMR_PRM;
820 if (db->type != TYPE_DM9000E)
821 imr |= IMR_LNKCHNG;
822
823 db->imr_all = imr;
824
825 /* Enable TX/RX interrupt mask */
826 iow(db, DM9000_IMR, imr);
827
828 /* Init Driver variable */
829 db->tx_pkt_cnt = 0;
830 db->queue_pkt_len = 0;
831 dev->trans_start = jiffies;
832}
833
834/* Our watchdog timed out. Called by the networking layer */
835static void dm9000_timeout(struct net_device *dev)
836{
837 board_info_t *db = netdev_priv(dev);
838 u8 reg_save;
839 unsigned long flags;
840
841 /* Save previous register address */
842 spin_lock_irqsave(&db->lock, flags);
843 reg_save = readb(db->io_addr);
844
845 netif_stop_queue(dev);
846 dm9000_reset(db);
847 dm9000_init_dm9000(dev);
848 /* We can accept TX packets again */
849 dev->trans_start = jiffies; /* prevent tx timeout */
850 netif_wake_queue(dev);
851
852 /* Restore previous register address */
853 writeb(reg_save, db->io_addr);
854 spin_unlock_irqrestore(&db->lock, flags);
855}
856
857static void dm9000_send_packet(struct net_device *dev,
858 int ip_summed,
859 u16 pkt_len)
860{
861 board_info_t *dm = to_dm9000_board(dev);
862
863 /* The DM9000 is not smart enough to leave fragmented packets alone. */
864 if (dm->ip_summed != ip_summed) {
865 if (ip_summed == CHECKSUM_NONE)
866 iow(dm, DM9000_TCCR, 0);
867 else
868 iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);
869 dm->ip_summed = ip_summed;
870 }
871
872 /* Set TX length to DM9000 */
873 iow(dm, DM9000_TXPLL, pkt_len);
874 iow(dm, DM9000_TXPLH, pkt_len >> 8);
875
876 /* Issue TX polling command */
877 iow(dm, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
878}
879
880/*
881 * Hardware start transmission.
882 * Send a packet to media from the upper layer.
883 */
884static int
885dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
886{
887 unsigned long flags;
888 board_info_t *db = netdev_priv(dev);
889
890 dm9000_dbg(db, 3, "%s:\n", __func__);
891
892 if (db->tx_pkt_cnt > 1)
893 return NETDEV_TX_BUSY;
894
895 spin_lock_irqsave(&db->lock, flags);
896
897 /* Move data to DM9000 TX RAM */
898 writeb(DM9000_MWCMD, db->io_addr);
899
900 (db->outblk)(db->io_data, skb->data, skb->len);
901 dev->stats.tx_bytes += skb->len;
902
903 db->tx_pkt_cnt++;
904 /* TX control: First packet immediately send, second packet queue */
905 if (db->tx_pkt_cnt == 1) {
906 dm9000_send_packet(dev, skb->ip_summed, skb->len);
907 } else {
908 /* Second packet */
909 db->queue_pkt_len = skb->len;
910 db->queue_ip_summed = skb->ip_summed;
911 netif_stop_queue(dev);
912 }
913
914 spin_unlock_irqrestore(&db->lock, flags);
915
916 /* free this SKB */
917 dev_kfree_skb(skb);
918
919 return NETDEV_TX_OK;
920}
921
922/*
923 * DM9000 interrupt handler
924 * receive the packet to upper layer, free the transmitted packet
925 */
926
927static void dm9000_tx_done(struct net_device *dev, board_info_t *db)
928{
929 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
930
931 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
932 /* One packet sent complete */
933 db->tx_pkt_cnt--;
934 dev->stats.tx_packets++;
935
936 if (netif_msg_tx_done(db))
937 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
938
939 /* Queue packet check & send */
940 if (db->tx_pkt_cnt > 0)
941 dm9000_send_packet(dev, db->queue_ip_summed,
942 db->queue_pkt_len);
943 netif_wake_queue(dev);
944 }
945}
946
947struct dm9000_rxhdr {
948 u8 RxPktReady;
949 u8 RxStatus;
950 __le16 RxLen;
951} __packed;
952
953/*
954 * Received a packet and pass to upper layer
955 */
956static void
957dm9000_rx(struct net_device *dev)
958{
959 board_info_t *db = netdev_priv(dev);
960 struct dm9000_rxhdr rxhdr;
961 struct sk_buff *skb;
962 u8 rxbyte, *rdptr;
963 bool GoodPacket;
964 int RxLen;
965
966 /* Check packet ready or not */
967 do {
968 ior(db, DM9000_MRCMDX); /* Dummy read */
969
970 /* Get most updated data */
971 rxbyte = readb(db->io_data);
972
973 /* Status check: this byte must be 0 or 1 */
974 if (rxbyte & DM9000_PKT_ERR) {
975 dev_warn(db->dev, "status check fail: %d\n", rxbyte);
976 iow(db, DM9000_RCR, 0x00); /* Stop Device */
977 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
978 return;
979 }
980
981 if (!(rxbyte & DM9000_PKT_RDY))
982 return;
983
984 /* A packet ready now & Get status/length */
985 GoodPacket = true;
986 writeb(DM9000_MRCMD, db->io_addr);
987
988 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
989
990 RxLen = le16_to_cpu(rxhdr.RxLen);
991
992 if (netif_msg_rx_status(db))
993 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
994 rxhdr.RxStatus, RxLen);
995
996 /* Packet Status check */
997 if (RxLen < 0x40) {
998 GoodPacket = false;
999 if (netif_msg_rx_err(db))
1000 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
1001 }
1002
1003 if (RxLen > DM9000_PKT_MAX) {
1004 dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
1005 }
1006
1007 /* rxhdr.RxStatus is identical to RSR register. */
1008 if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE |
1009 RSR_PLE | RSR_RWTO |
1010 RSR_LCS | RSR_RF)) {
1011 GoodPacket = false;
1012 if (rxhdr.RxStatus & RSR_FOE) {
1013 if (netif_msg_rx_err(db))
1014 dev_dbg(db->dev, "fifo error\n");
1015 dev->stats.rx_fifo_errors++;
1016 }
1017 if (rxhdr.RxStatus & RSR_CE) {
1018 if (netif_msg_rx_err(db))
1019 dev_dbg(db->dev, "crc error\n");
1020 dev->stats.rx_crc_errors++;
1021 }
1022 if (rxhdr.RxStatus & RSR_RF) {
1023 if (netif_msg_rx_err(db))
1024 dev_dbg(db->dev, "length error\n");
1025 dev->stats.rx_length_errors++;
1026 }
1027 }
1028
1029 /* Move data from DM9000 */
1030 if (GoodPacket &&
1031 ((skb = netdev_alloc_skb(dev, RxLen + 4)) != NULL)) {
1032 skb_reserve(skb, 2);
1033 rdptr = (u8 *) skb_put(skb, RxLen - 4);
1034
1035 /* Read received packet from RX SRAM */
1036
1037 (db->inblk)(db->io_data, rdptr, RxLen);
1038 dev->stats.rx_bytes += RxLen;
1039
1040 /* Pass to upper layer */
1041 skb->protocol = eth_type_trans(skb, dev);
1042 if (dev->features & NETIF_F_RXCSUM) {
1043 if ((((rxbyte & 0x1c) << 3) & rxbyte) == 0)
1044 skb->ip_summed = CHECKSUM_UNNECESSARY;
1045 else
1046 skb_checksum_none_assert(skb);
1047 }
1048 netif_rx(skb);
1049 dev->stats.rx_packets++;
1050
1051 } else {
1052 /* need to dump the packet's data */
1053
1054 (db->dumpblk)(db->io_data, RxLen);
1055 }
1056 } while (rxbyte & DM9000_PKT_RDY);
1057}
1058
1059static irqreturn_t dm9000_interrupt(int irq, void *dev_id)
1060{
1061 struct net_device *dev = dev_id;
1062 board_info_t *db = netdev_priv(dev);
1063 int int_status;
1064 unsigned long flags;
1065 u8 reg_save;
1066
1067 dm9000_dbg(db, 3, "entering %s\n", __func__);
1068
1069 /* A real interrupt coming */
1070
1071 /* holders of db->lock must always block IRQs */
1072 spin_lock_irqsave(&db->lock, flags);
1073
1074 /* Save previous register address */
1075 reg_save = readb(db->io_addr);
1076
1077 /* Disable all interrupts */
1078 iow(db, DM9000_IMR, IMR_PAR);
1079
1080 /* Got DM9000 interrupt status */
1081 int_status = ior(db, DM9000_ISR); /* Got ISR */
1082 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
1083
1084 if (netif_msg_intr(db))
1085 dev_dbg(db->dev, "interrupt status %02x\n", int_status);
1086
1087 /* Received the coming packet */
1088 if (int_status & ISR_PRS)
1089 dm9000_rx(dev);
1090
1091 /* Trnasmit Interrupt check */
1092 if (int_status & ISR_PTS)
1093 dm9000_tx_done(dev, db);
1094
1095 if (db->type != TYPE_DM9000E) {
1096 if (int_status & ISR_LNKCHNG) {
1097 /* fire a link-change request */
1098 schedule_delayed_work(&db->phy_poll, 1);
1099 }
1100 }
1101
1102 /* Re-enable interrupt mask */
1103 iow(db, DM9000_IMR, db->imr_all);
1104
1105 /* Restore previous register address */
1106 writeb(reg_save, db->io_addr);
1107
1108 spin_unlock_irqrestore(&db->lock, flags);
1109
1110 return IRQ_HANDLED;
1111}
1112
1113static irqreturn_t dm9000_wol_interrupt(int irq, void *dev_id)
1114{
1115 struct net_device *dev = dev_id;
1116 board_info_t *db = netdev_priv(dev);
1117 unsigned long flags;
1118 unsigned nsr, wcr;
1119
1120 spin_lock_irqsave(&db->lock, flags);
1121
1122 nsr = ior(db, DM9000_NSR);
1123 wcr = ior(db, DM9000_WCR);
1124
1125 dev_dbg(db->dev, "%s: NSR=0x%02x, WCR=0x%02x\n", __func__, nsr, wcr);
1126
1127 if (nsr & NSR_WAKEST) {
1128 /* clear, so we can avoid */
1129 iow(db, DM9000_NSR, NSR_WAKEST);
1130
1131 if (wcr & WCR_LINKST)
1132 dev_info(db->dev, "wake by link status change\n");
1133 if (wcr & WCR_SAMPLEST)
1134 dev_info(db->dev, "wake by sample packet\n");
1135 if (wcr & WCR_MAGICST )
1136 dev_info(db->dev, "wake by magic packet\n");
1137 if (!(wcr & (WCR_LINKST | WCR_SAMPLEST | WCR_MAGICST)))
1138 dev_err(db->dev, "wake signalled with no reason? "
1139 "NSR=0x%02x, WSR=0x%02x\n", nsr, wcr);
1140
1141 }
1142
1143 spin_unlock_irqrestore(&db->lock, flags);
1144
1145 return (nsr & NSR_WAKEST) ? IRQ_HANDLED : IRQ_NONE;
1146}
1147
1148#ifdef CONFIG_NET_POLL_CONTROLLER
1149/*
1150 *Used by netconsole
1151 */
1152static void dm9000_poll_controller(struct net_device *dev)
1153{
1154 disable_irq(dev->irq);
1155 dm9000_interrupt(dev->irq, dev);
1156 enable_irq(dev->irq);
1157}
1158#endif
1159
1160/*
1161 * Open the interface.
1162 * The interface is opened whenever "ifconfig" actives it.
1163 */
1164static int
1165dm9000_open(struct net_device *dev)
1166{
1167 board_info_t *db = netdev_priv(dev);
1168 unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
1169
1170 if (netif_msg_ifup(db))
1171 dev_dbg(db->dev, "enabling %s\n", dev->name);
1172
1173 /* If there is no IRQ type specified, default to something that
1174 * may work, and tell the user that this is a problem */
1175
1176 if (irqflags == IRQF_TRIGGER_NONE)
1177 dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
1178
1179 irqflags |= IRQF_SHARED;
1180
1181 /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
1182 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
1183 mdelay(1); /* delay needs by DM9000B */
1184
1185 /* Initialize DM9000 board */
1186 dm9000_reset(db);
1187 dm9000_init_dm9000(dev);
1188
1189 if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
1190 return -EAGAIN;
1191
1192 /* Init driver variable */
1193 db->dbug_cnt = 0;
1194
1195 mii_check_media(&db->mii, netif_msg_link(db), 1);
1196 netif_start_queue(dev);
1197
1198 dm9000_schedule_poll(db);
1199
1200 return 0;
1201}
1202
1203/*
1204 * Sleep, either by using msleep() or if we are suspending, then
1205 * use mdelay() to sleep.
1206 */
1207static void dm9000_msleep(board_info_t *db, unsigned int ms)
1208{
1209 if (db->in_suspend)
1210 mdelay(ms);
1211 else
1212 msleep(ms);
1213}
1214
1215/*
1216 * Read a word from phyxcer
1217 */
1218static int
1219dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1220{
1221 board_info_t *db = netdev_priv(dev);
1222 unsigned long flags;
1223 unsigned int reg_save;
1224 int ret;
1225
1226 mutex_lock(&db->addr_lock);
1227
1228 spin_lock_irqsave(&db->lock,flags);
1229
1230 /* Save previous register address */
1231 reg_save = readb(db->io_addr);
1232
1233 /* Fill the phyxcer register into REG_0C */
1234 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1235
1236 iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */
1237
1238 writeb(reg_save, db->io_addr);
1239 spin_unlock_irqrestore(&db->lock,flags);
1240
1241 dm9000_msleep(db, 1); /* Wait read complete */
1242
1243 spin_lock_irqsave(&db->lock,flags);
1244 reg_save = readb(db->io_addr);
1245
1246 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
1247
1248 /* The read data keeps on REG_0D & REG_0E */
1249 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
1250
1251 /* restore the previous address */
1252 writeb(reg_save, db->io_addr);
1253 spin_unlock_irqrestore(&db->lock,flags);
1254
1255 mutex_unlock(&db->addr_lock);
1256
1257 dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
1258 return ret;
1259}
1260
1261/*
1262 * Write a word to phyxcer
1263 */
1264static void
1265dm9000_phy_write(struct net_device *dev,
1266 int phyaddr_unused, int reg, int value)
1267{
1268 board_info_t *db = netdev_priv(dev);
1269 unsigned long flags;
1270 unsigned long reg_save;
1271
1272 dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
1273 mutex_lock(&db->addr_lock);
1274
1275 spin_lock_irqsave(&db->lock,flags);
1276
1277 /* Save previous register address */
1278 reg_save = readb(db->io_addr);
1279
1280 /* Fill the phyxcer register into REG_0C */
1281 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1282
1283 /* Fill the written data into REG_0D & REG_0E */
1284 iow(db, DM9000_EPDRL, value);
1285 iow(db, DM9000_EPDRH, value >> 8);
1286
1287 iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */
1288
1289 writeb(reg_save, db->io_addr);
1290 spin_unlock_irqrestore(&db->lock, flags);
1291
1292 dm9000_msleep(db, 1); /* Wait write complete */
1293
1294 spin_lock_irqsave(&db->lock,flags);
1295 reg_save = readb(db->io_addr);
1296
1297 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
1298
1299 /* restore the previous address */
1300 writeb(reg_save, db->io_addr);
1301
1302 spin_unlock_irqrestore(&db->lock, flags);
1303 mutex_unlock(&db->addr_lock);
1304}
1305
1306static void
1307dm9000_shutdown(struct net_device *dev)
1308{
1309 board_info_t *db = netdev_priv(dev);
1310
1311 /* RESET device */
1312 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
1313 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
1314 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
1315 iow(db, DM9000_RCR, 0x00); /* Disable RX */
1316}
1317
1318/*
1319 * Stop the interface.
1320 * The interface is stopped when it is brought.
1321 */
1322static int
1323dm9000_stop(struct net_device *ndev)
1324{
1325 board_info_t *db = netdev_priv(ndev);
1326
1327 if (netif_msg_ifdown(db))
1328 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
1329
1330 cancel_delayed_work_sync(&db->phy_poll);
1331
1332 netif_stop_queue(ndev);
1333 netif_carrier_off(ndev);
1334
1335 /* free interrupt */
1336 free_irq(ndev->irq, ndev);
1337
1338 dm9000_shutdown(ndev);
1339
1340 return 0;
1341}
1342
1343static const struct net_device_ops dm9000_netdev_ops = {
1344 .ndo_open = dm9000_open,
1345 .ndo_stop = dm9000_stop,
1346 .ndo_start_xmit = dm9000_start_xmit,
1347 .ndo_tx_timeout = dm9000_timeout,
1348 .ndo_set_rx_mode = dm9000_hash_table,
1349 .ndo_do_ioctl = dm9000_ioctl,
1350 .ndo_change_mtu = eth_change_mtu,
1351 .ndo_set_features = dm9000_set_features,
1352 .ndo_validate_addr = eth_validate_addr,
1353 .ndo_set_mac_address = eth_mac_addr,
1354#ifdef CONFIG_NET_POLL_CONTROLLER
1355 .ndo_poll_controller = dm9000_poll_controller,
1356#endif
1357};
1358
1359/*
1360 * Search DM9000 board, allocate space and register it
1361 */
1362static int __devinit
1363dm9000_probe(struct platform_device *pdev)
1364{
1365 struct dm9000_plat_data *pdata = pdev->dev.platform_data;
1366 struct board_info *db; /* Point a board information structure */
1367 struct net_device *ndev;
1368 const unsigned char *mac_src;
1369 int ret = 0;
1370 int iosize;
1371 int i;
1372 u32 id_val;
1373
1374 /* Init network device */
1375 ndev = alloc_etherdev(sizeof(struct board_info));
1376 if (!ndev)
1377 return -ENOMEM;
1378
1379 SET_NETDEV_DEV(ndev, &pdev->dev);
1380
1381 dev_dbg(&pdev->dev, "dm9000_probe()\n");
1382
1383 /* setup board info structure */
1384 db = netdev_priv(ndev);
1385
1386 db->dev = &pdev->dev;
1387 db->ndev = ndev;
1388
1389 spin_lock_init(&db->lock);
1390 mutex_init(&db->addr_lock);
1391
1392 INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work);
1393
1394 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1395 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1396 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1397
1398 if (db->addr_res == NULL || db->data_res == NULL ||
1399 db->irq_res == NULL) {
1400 dev_err(db->dev, "insufficient resources\n");
1401 ret = -ENOENT;
1402 goto out;
1403 }
1404
1405 db->irq_wake = platform_get_irq(pdev, 1);
1406 if (db->irq_wake >= 0) {
1407 dev_dbg(db->dev, "wakeup irq %d\n", db->irq_wake);
1408
1409 ret = request_irq(db->irq_wake, dm9000_wol_interrupt,
1410 IRQF_SHARED, dev_name(db->dev), ndev);
1411 if (ret) {
1412 dev_err(db->dev, "cannot get wakeup irq (%d)\n", ret);
1413 } else {
1414
1415 /* test to see if irq is really wakeup capable */
1416 ret = irq_set_irq_wake(db->irq_wake, 1);
1417 if (ret) {
1418 dev_err(db->dev, "irq %d cannot set wakeup (%d)\n",
1419 db->irq_wake, ret);
1420 ret = 0;
1421 } else {
1422 irq_set_irq_wake(db->irq_wake, 0);
1423 db->wake_supported = 1;
1424 }
1425 }
1426 }
1427
1428 iosize = resource_size(db->addr_res);
1429 db->addr_req = request_mem_region(db->addr_res->start, iosize,
1430 pdev->name);
1431
1432 if (db->addr_req == NULL) {
1433 dev_err(db->dev, "cannot claim address reg area\n");
1434 ret = -EIO;
1435 goto out;
1436 }
1437
1438 db->io_addr = ioremap(db->addr_res->start, iosize);
1439
1440 if (db->io_addr == NULL) {
1441 dev_err(db->dev, "failed to ioremap address reg\n");
1442 ret = -EINVAL;
1443 goto out;
1444 }
1445
1446 iosize = resource_size(db->data_res);
1447 db->data_req = request_mem_region(db->data_res->start, iosize,
1448 pdev->name);
1449
1450 if (db->data_req == NULL) {
1451 dev_err(db->dev, "cannot claim data reg area\n");
1452 ret = -EIO;
1453 goto out;
1454 }
1455
1456 db->io_data = ioremap(db->data_res->start, iosize);
1457
1458 if (db->io_data == NULL) {
1459 dev_err(db->dev, "failed to ioremap data reg\n");
1460 ret = -EINVAL;
1461 goto out;
1462 }
1463
1464 /* fill in parameters for net-dev structure */
1465 ndev->base_addr = (unsigned long)db->io_addr;
1466 ndev->irq = db->irq_res->start;
1467
1468 /* ensure at least we have a default set of IO routines */
1469 dm9000_set_io(db, iosize);
1470
1471 /* check to see if anything is being over-ridden */
1472 if (pdata != NULL) {
1473 /* check to see if the driver wants to over-ride the
1474 * default IO width */
1475
1476 if (pdata->flags & DM9000_PLATF_8BITONLY)
1477 dm9000_set_io(db, 1);
1478
1479 if (pdata->flags & DM9000_PLATF_16BITONLY)
1480 dm9000_set_io(db, 2);
1481
1482 if (pdata->flags & DM9000_PLATF_32BITONLY)
1483 dm9000_set_io(db, 4);
1484
1485 /* check to see if there are any IO routine
1486 * over-rides */
1487
1488 if (pdata->inblk != NULL)
1489 db->inblk = pdata->inblk;
1490
1491 if (pdata->outblk != NULL)
1492 db->outblk = pdata->outblk;
1493
1494 if (pdata->dumpblk != NULL)
1495 db->dumpblk = pdata->dumpblk;
1496
1497 db->flags = pdata->flags;
1498 }
1499
1500#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
1501 db->flags |= DM9000_PLATF_SIMPLE_PHY;
1502#endif
1503
1504 dm9000_reset(db);
1505
1506 /* try multiple times, DM9000 sometimes gets the read wrong */
1507 for (i = 0; i < 8; i++) {
1508 id_val = ior(db, DM9000_VIDL);
1509 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
1510 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
1511 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
1512
1513 if (id_val == DM9000_ID)
1514 break;
1515 dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
1516 }
1517
1518 if (id_val != DM9000_ID) {
1519 dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
1520 ret = -ENODEV;
1521 goto out;
1522 }
1523
1524 /* Identify what type of DM9000 we are working on */
1525
1526 id_val = ior(db, DM9000_CHIPR);
1527 dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
1528
1529 switch (id_val) {
1530 case CHIPR_DM9000A:
1531 db->type = TYPE_DM9000A;
1532 break;
1533 case CHIPR_DM9000B:
1534 db->type = TYPE_DM9000B;
1535 break;
1536 default:
1537 dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
1538 db->type = TYPE_DM9000E;
1539 }
1540
1541 /* dm9000a/b are capable of hardware checksum offload */
1542 if (db->type == TYPE_DM9000A || db->type == TYPE_DM9000B) {
1543 ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM;
1544 ndev->features |= ndev->hw_features;
1545 }
1546
1547 /* from this point we assume that we have found a DM9000 */
1548
1549 /* driver system function */
1550 ether_setup(ndev);
1551
1552 ndev->netdev_ops = &dm9000_netdev_ops;
1553 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1554 ndev->ethtool_ops = &dm9000_ethtool_ops;
1555
1556 db->msg_enable = NETIF_MSG_LINK;
1557 db->mii.phy_id_mask = 0x1f;
1558 db->mii.reg_num_mask = 0x1f;
1559 db->mii.force_media = 0;
1560 db->mii.full_duplex = 0;
1561 db->mii.dev = ndev;
1562 db->mii.mdio_read = dm9000_phy_read;
1563 db->mii.mdio_write = dm9000_phy_write;
1564
1565 mac_src = "eeprom";
1566
1567 /* try reading the node address from the attached EEPROM */
1568 for (i = 0; i < 6; i += 2)
1569 dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
1570
1571 if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) {
1572 mac_src = "platform data";
1573 memcpy(ndev->dev_addr, pdata->dev_addr, 6);
1574 }
1575
1576 if (!is_valid_ether_addr(ndev->dev_addr)) {
1577 /* try reading from mac */
1578
1579 mac_src = "chip";
1580 for (i = 0; i < 6; i++)
1581 ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
1582 }
1583
1584 if (!is_valid_ether_addr(ndev->dev_addr)) {
1585 dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
1586 "set using ifconfig\n", ndev->name);
1587
1588 eth_hw_addr_random(ndev);
1589 mac_src = "random";
1590 }
1591
1592
1593 platform_set_drvdata(pdev, ndev);
1594 ret = register_netdev(ndev);
1595
1596 if (ret == 0)
1597 printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
1598 ndev->name, dm9000_type_to_char(db->type),
1599 db->io_addr, db->io_data, ndev->irq,
1600 ndev->dev_addr, mac_src);
1601 return 0;
1602
1603out:
1604 dev_err(db->dev, "not found (%d).\n", ret);
1605
1606 dm9000_release_board(pdev, db);
1607 free_netdev(ndev);
1608
1609 return ret;
1610}
1611
1612static int
1613dm9000_drv_suspend(struct device *dev)
1614{
1615 struct platform_device *pdev = to_platform_device(dev);
1616 struct net_device *ndev = platform_get_drvdata(pdev);
1617 board_info_t *db;
1618
1619 if (ndev) {
1620 db = netdev_priv(ndev);
1621 db->in_suspend = 1;
1622
1623 if (!netif_running(ndev))
1624 return 0;
1625
1626 netif_device_detach(ndev);
1627
1628 /* only shutdown if not using WoL */
1629 if (!db->wake_state)
1630 dm9000_shutdown(ndev);
1631 }
1632 return 0;
1633}
1634
1635static int
1636dm9000_drv_resume(struct device *dev)
1637{
1638 struct platform_device *pdev = to_platform_device(dev);
1639 struct net_device *ndev = platform_get_drvdata(pdev);
1640 board_info_t *db = netdev_priv(ndev);
1641
1642 if (ndev) {
1643 if (netif_running(ndev)) {
1644 /* reset if we were not in wake mode to ensure if
1645 * the device was powered off it is in a known state */
1646 if (!db->wake_state) {
1647 dm9000_reset(db);
1648 dm9000_init_dm9000(ndev);
1649 }
1650
1651 netif_device_attach(ndev);
1652 }
1653
1654 db->in_suspend = 0;
1655 }
1656 return 0;
1657}
1658
1659static const struct dev_pm_ops dm9000_drv_pm_ops = {
1660 .suspend = dm9000_drv_suspend,
1661 .resume = dm9000_drv_resume,
1662};
1663
1664static int __devexit
1665dm9000_drv_remove(struct platform_device *pdev)
1666{
1667 struct net_device *ndev = platform_get_drvdata(pdev);
1668
1669 platform_set_drvdata(pdev, NULL);
1670
1671 unregister_netdev(ndev);
1672 dm9000_release_board(pdev, netdev_priv(ndev));
1673 free_netdev(ndev); /* free device structure */
1674
1675 dev_dbg(&pdev->dev, "released and freed device\n");
1676 return 0;
1677}
1678
1679static struct platform_driver dm9000_driver = {
1680 .driver = {
1681 .name = "dm9000",
1682 .owner = THIS_MODULE,
1683 .pm = &dm9000_drv_pm_ops,
1684 },
1685 .probe = dm9000_probe,
1686 .remove = __devexit_p(dm9000_drv_remove),
1687};
1688
1689static int __init
1690dm9000_init(void)
1691{
1692 printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
1693
1694 return platform_driver_register(&dm9000_driver);
1695}
1696
1697static void __exit
1698dm9000_cleanup(void)
1699{
1700 platform_driver_unregister(&dm9000_driver);
1701}
1702
1703module_init(dm9000_init);
1704module_exit(dm9000_cleanup);
1705
1706MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1707MODULE_DESCRIPTION("Davicom DM9000 network driver");
1708MODULE_LICENSE("GPL");
1709MODULE_ALIAS("platform:dm9000");