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1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/dma-mapping.h>
21#include <linux/slab.h>
22#include <linux/scatterlist.h>
23#include <linux/regulator/consumer.h>
24#include <linux/pm_runtime.h>
25
26#include <linux/leds.h>
27
28#include <linux/mmc/mmc.h>
29#include <linux/mmc/host.h>
30#include <linux/mmc/card.h>
31
32#include "sdhci.h"
33
34#define DRIVER_NAME "sdhci"
35
36#define DBG(f, x...) \
37 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
38
39#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
40 defined(CONFIG_MMC_SDHCI_MODULE))
41#define SDHCI_USE_LEDS_CLASS
42#endif
43
44#define MAX_TUNING_LOOP 40
45
46static unsigned int debug_quirks = 0;
47static unsigned int debug_quirks2;
48
49static void sdhci_finish_data(struct sdhci_host *);
50
51static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
52static void sdhci_finish_command(struct sdhci_host *);
53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54static void sdhci_tuning_timer(unsigned long data);
55
56#ifdef CONFIG_PM_RUNTIME
57static int sdhci_runtime_pm_get(struct sdhci_host *host);
58static int sdhci_runtime_pm_put(struct sdhci_host *host);
59#else
60static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
61{
62 return 0;
63}
64static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
65{
66 return 0;
67}
68#endif
69
70static void sdhci_dumpregs(struct sdhci_host *host)
71{
72 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
73 mmc_hostname(host->mmc));
74
75 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
76 sdhci_readl(host, SDHCI_DMA_ADDRESS),
77 sdhci_readw(host, SDHCI_HOST_VERSION));
78 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
79 sdhci_readw(host, SDHCI_BLOCK_SIZE),
80 sdhci_readw(host, SDHCI_BLOCK_COUNT));
81 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
82 sdhci_readl(host, SDHCI_ARGUMENT),
83 sdhci_readw(host, SDHCI_TRANSFER_MODE));
84 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
85 sdhci_readl(host, SDHCI_PRESENT_STATE),
86 sdhci_readb(host, SDHCI_HOST_CONTROL));
87 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
88 sdhci_readb(host, SDHCI_POWER_CONTROL),
89 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
90 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
91 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
92 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
93 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
94 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
95 sdhci_readl(host, SDHCI_INT_STATUS));
96 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
97 sdhci_readl(host, SDHCI_INT_ENABLE),
98 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
99 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
100 sdhci_readw(host, SDHCI_ACMD12_ERR),
101 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
102 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
103 sdhci_readl(host, SDHCI_CAPABILITIES),
104 sdhci_readl(host, SDHCI_CAPABILITIES_1));
105 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
106 sdhci_readw(host, SDHCI_COMMAND),
107 sdhci_readl(host, SDHCI_MAX_CURRENT));
108 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
109 sdhci_readw(host, SDHCI_HOST_CONTROL2));
110
111 if (host->flags & SDHCI_USE_ADMA)
112 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
113 readl(host->ioaddr + SDHCI_ADMA_ERROR),
114 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
115
116 pr_debug(DRIVER_NAME ": ===========================================\n");
117}
118
119/*****************************************************************************\
120 * *
121 * Low level functions *
122 * *
123\*****************************************************************************/
124
125static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
126{
127 u32 ier;
128
129 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
130 ier &= ~clear;
131 ier |= set;
132 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
133 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
134}
135
136static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
137{
138 sdhci_clear_set_irqs(host, 0, irqs);
139}
140
141static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
142{
143 sdhci_clear_set_irqs(host, irqs, 0);
144}
145
146static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
147{
148 u32 present, irqs;
149
150 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
151 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
152 return;
153
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
157
158 if (enable)
159 sdhci_unmask_irqs(host, irqs);
160 else
161 sdhci_mask_irqs(host, irqs);
162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
174static void sdhci_reset(struct sdhci_host *host, u8 mask)
175{
176 unsigned long timeout;
177 u32 uninitialized_var(ier);
178
179 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
180 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
181 SDHCI_CARD_PRESENT))
182 return;
183 }
184
185 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
186 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
187
188 if (host->ops->platform_reset_enter)
189 host->ops->platform_reset_enter(host, mask);
190
191 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
192
193 if (mask & SDHCI_RESET_ALL)
194 host->clock = 0;
195
196 /* Wait max 100 ms */
197 timeout = 100;
198
199 /* hw clears the bit when it's done */
200 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
201 if (timeout == 0) {
202 pr_err("%s: Reset 0x%x never completed.\n",
203 mmc_hostname(host->mmc), (int)mask);
204 sdhci_dumpregs(host);
205 return;
206 }
207 timeout--;
208 mdelay(1);
209 }
210
211 if (host->ops->platform_reset_exit)
212 host->ops->platform_reset_exit(host, mask);
213
214 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
215 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
216
217 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
218 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
219 host->ops->enable_dma(host);
220 }
221}
222
223static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
224
225static void sdhci_init(struct sdhci_host *host, int soft)
226{
227 if (soft)
228 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
229 else
230 sdhci_reset(host, SDHCI_RESET_ALL);
231
232 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
233 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
235 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
236 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
237
238 if (soft) {
239 /* force clock reconfiguration */
240 host->clock = 0;
241 sdhci_set_ios(host->mmc, &host->mmc->ios);
242 }
243}
244
245static void sdhci_reinit(struct sdhci_host *host)
246{
247 sdhci_init(host, 0);
248 sdhci_enable_card_detection(host);
249}
250
251static void sdhci_activate_led(struct sdhci_host *host)
252{
253 u8 ctrl;
254
255 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
256 ctrl |= SDHCI_CTRL_LED;
257 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
258}
259
260static void sdhci_deactivate_led(struct sdhci_host *host)
261{
262 u8 ctrl;
263
264 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
265 ctrl &= ~SDHCI_CTRL_LED;
266 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
267}
268
269#ifdef SDHCI_USE_LEDS_CLASS
270static void sdhci_led_control(struct led_classdev *led,
271 enum led_brightness brightness)
272{
273 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
274 unsigned long flags;
275
276 spin_lock_irqsave(&host->lock, flags);
277
278 if (host->runtime_suspended)
279 goto out;
280
281 if (brightness == LED_OFF)
282 sdhci_deactivate_led(host);
283 else
284 sdhci_activate_led(host);
285out:
286 spin_unlock_irqrestore(&host->lock, flags);
287}
288#endif
289
290/*****************************************************************************\
291 * *
292 * Core functions *
293 * *
294\*****************************************************************************/
295
296static void sdhci_read_block_pio(struct sdhci_host *host)
297{
298 unsigned long flags;
299 size_t blksize, len, chunk;
300 u32 uninitialized_var(scratch);
301 u8 *buf;
302
303 DBG("PIO reading\n");
304
305 blksize = host->data->blksz;
306 chunk = 0;
307
308 local_irq_save(flags);
309
310 while (blksize) {
311 if (!sg_miter_next(&host->sg_miter))
312 BUG();
313
314 len = min(host->sg_miter.length, blksize);
315
316 blksize -= len;
317 host->sg_miter.consumed = len;
318
319 buf = host->sg_miter.addr;
320
321 while (len) {
322 if (chunk == 0) {
323 scratch = sdhci_readl(host, SDHCI_BUFFER);
324 chunk = 4;
325 }
326
327 *buf = scratch & 0xFF;
328
329 buf++;
330 scratch >>= 8;
331 chunk--;
332 len--;
333 }
334 }
335
336 sg_miter_stop(&host->sg_miter);
337
338 local_irq_restore(flags);
339}
340
341static void sdhci_write_block_pio(struct sdhci_host *host)
342{
343 unsigned long flags;
344 size_t blksize, len, chunk;
345 u32 scratch;
346 u8 *buf;
347
348 DBG("PIO writing\n");
349
350 blksize = host->data->blksz;
351 chunk = 0;
352 scratch = 0;
353
354 local_irq_save(flags);
355
356 while (blksize) {
357 if (!sg_miter_next(&host->sg_miter))
358 BUG();
359
360 len = min(host->sg_miter.length, blksize);
361
362 blksize -= len;
363 host->sg_miter.consumed = len;
364
365 buf = host->sg_miter.addr;
366
367 while (len) {
368 scratch |= (u32)*buf << (chunk * 8);
369
370 buf++;
371 chunk++;
372 len--;
373
374 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
375 sdhci_writel(host, scratch, SDHCI_BUFFER);
376 chunk = 0;
377 scratch = 0;
378 }
379 }
380 }
381
382 sg_miter_stop(&host->sg_miter);
383
384 local_irq_restore(flags);
385}
386
387static void sdhci_transfer_pio(struct sdhci_host *host)
388{
389 u32 mask;
390
391 BUG_ON(!host->data);
392
393 if (host->blocks == 0)
394 return;
395
396 if (host->data->flags & MMC_DATA_READ)
397 mask = SDHCI_DATA_AVAILABLE;
398 else
399 mask = SDHCI_SPACE_AVAILABLE;
400
401 /*
402 * Some controllers (JMicron JMB38x) mess up the buffer bits
403 * for transfers < 4 bytes. As long as it is just one block,
404 * we can ignore the bits.
405 */
406 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
407 (host->data->blocks == 1))
408 mask = ~0;
409
410 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
411 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
412 udelay(100);
413
414 if (host->data->flags & MMC_DATA_READ)
415 sdhci_read_block_pio(host);
416 else
417 sdhci_write_block_pio(host);
418
419 host->blocks--;
420 if (host->blocks == 0)
421 break;
422 }
423
424 DBG("PIO transfer complete.\n");
425}
426
427static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
428{
429 local_irq_save(*flags);
430 return kmap_atomic(sg_page(sg)) + sg->offset;
431}
432
433static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
434{
435 kunmap_atomic(buffer);
436 local_irq_restore(*flags);
437}
438
439static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
440{
441 __le32 *dataddr = (__le32 __force *)(desc + 4);
442 __le16 *cmdlen = (__le16 __force *)desc;
443
444 /* SDHCI specification says ADMA descriptors should be 4 byte
445 * aligned, so using 16 or 32bit operations should be safe. */
446
447 cmdlen[0] = cpu_to_le16(cmd);
448 cmdlen[1] = cpu_to_le16(len);
449
450 dataddr[0] = cpu_to_le32(addr);
451}
452
453static int sdhci_adma_table_pre(struct sdhci_host *host,
454 struct mmc_data *data)
455{
456 int direction;
457
458 u8 *desc;
459 u8 *align;
460 dma_addr_t addr;
461 dma_addr_t align_addr;
462 int len, offset;
463
464 struct scatterlist *sg;
465 int i;
466 char *buffer;
467 unsigned long flags;
468
469 /*
470 * The spec does not specify endianness of descriptor table.
471 * We currently guess that it is LE.
472 */
473
474 if (data->flags & MMC_DATA_READ)
475 direction = DMA_FROM_DEVICE;
476 else
477 direction = DMA_TO_DEVICE;
478
479 /*
480 * The ADMA descriptor table is mapped further down as we
481 * need to fill it with data first.
482 */
483
484 host->align_addr = dma_map_single(mmc_dev(host->mmc),
485 host->align_buffer, 128 * 4, direction);
486 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
487 goto fail;
488 BUG_ON(host->align_addr & 0x3);
489
490 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
491 data->sg, data->sg_len, direction);
492 if (host->sg_count == 0)
493 goto unmap_align;
494
495 desc = host->adma_desc;
496 align = host->align_buffer;
497
498 align_addr = host->align_addr;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 addr = sg_dma_address(sg);
502 len = sg_dma_len(sg);
503
504 /*
505 * The SDHCI specification states that ADMA
506 * addresses must be 32-bit aligned. If they
507 * aren't, then we use a bounce buffer for
508 * the (up to three) bytes that screw up the
509 * alignment.
510 */
511 offset = (4 - (addr & 0x3)) & 0x3;
512 if (offset) {
513 if (data->flags & MMC_DATA_WRITE) {
514 buffer = sdhci_kmap_atomic(sg, &flags);
515 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
516 memcpy(align, buffer, offset);
517 sdhci_kunmap_atomic(buffer, &flags);
518 }
519
520 /* tran, valid */
521 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
522
523 BUG_ON(offset > 65536);
524
525 align += 4;
526 align_addr += 4;
527
528 desc += 8;
529
530 addr += offset;
531 len -= offset;
532 }
533
534 BUG_ON(len > 65536);
535
536 /* tran, valid */
537 sdhci_set_adma_desc(desc, addr, len, 0x21);
538 desc += 8;
539
540 /*
541 * If this triggers then we have a calculation bug
542 * somewhere. :/
543 */
544 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
545 }
546
547 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
548 /*
549 * Mark the last descriptor as the terminating descriptor
550 */
551 if (desc != host->adma_desc) {
552 desc -= 8;
553 desc[0] |= 0x2; /* end */
554 }
555 } else {
556 /*
557 * Add a terminating entry.
558 */
559
560 /* nop, end, valid */
561 sdhci_set_adma_desc(desc, 0, 0, 0x3);
562 }
563
564 /*
565 * Resync align buffer as we might have changed it.
566 */
567 if (data->flags & MMC_DATA_WRITE) {
568 dma_sync_single_for_device(mmc_dev(host->mmc),
569 host->align_addr, 128 * 4, direction);
570 }
571
572 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
573 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
574 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
575 goto unmap_entries;
576 BUG_ON(host->adma_addr & 0x3);
577
578 return 0;
579
580unmap_entries:
581 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
582 data->sg_len, direction);
583unmap_align:
584 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585 128 * 4, direction);
586fail:
587 return -EINVAL;
588}
589
590static void sdhci_adma_table_post(struct sdhci_host *host,
591 struct mmc_data *data)
592{
593 int direction;
594
595 struct scatterlist *sg;
596 int i, size;
597 u8 *align;
598 char *buffer;
599 unsigned long flags;
600
601 if (data->flags & MMC_DATA_READ)
602 direction = DMA_FROM_DEVICE;
603 else
604 direction = DMA_TO_DEVICE;
605
606 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
607 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
608
609 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
610 128 * 4, direction);
611
612 if (data->flags & MMC_DATA_READ) {
613 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
614 data->sg_len, direction);
615
616 align = host->align_buffer;
617
618 for_each_sg(data->sg, sg, host->sg_count, i) {
619 if (sg_dma_address(sg) & 0x3) {
620 size = 4 - (sg_dma_address(sg) & 0x3);
621
622 buffer = sdhci_kmap_atomic(sg, &flags);
623 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
624 memcpy(buffer, align, size);
625 sdhci_kunmap_atomic(buffer, &flags);
626
627 align += 4;
628 }
629 }
630 }
631
632 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
633 data->sg_len, direction);
634}
635
636static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
637{
638 u8 count;
639 struct mmc_data *data = cmd->data;
640 unsigned target_timeout, current_timeout;
641
642 /*
643 * If the host controller provides us with an incorrect timeout
644 * value, just skip the check and use 0xE. The hardware may take
645 * longer to time out, but that's much better than having a too-short
646 * timeout value.
647 */
648 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
649 return 0xE;
650
651 /* Unspecified timeout, assume max */
652 if (!data && !cmd->cmd_timeout_ms)
653 return 0xE;
654
655 /* timeout in us */
656 if (!data)
657 target_timeout = cmd->cmd_timeout_ms * 1000;
658 else {
659 target_timeout = data->timeout_ns / 1000;
660 if (host->clock)
661 target_timeout += data->timeout_clks / host->clock;
662 }
663
664 /*
665 * Figure out needed cycles.
666 * We do this in steps in order to fit inside a 32 bit int.
667 * The first step is the minimum timeout, which will have a
668 * minimum resolution of 6 bits:
669 * (1) 2^13*1000 > 2^22,
670 * (2) host->timeout_clk < 2^16
671 * =>
672 * (1) / (2) > 2^6
673 */
674 count = 0;
675 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
676 while (current_timeout < target_timeout) {
677 count++;
678 current_timeout <<= 1;
679 if (count >= 0xF)
680 break;
681 }
682
683 if (count >= 0xF) {
684 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
685 mmc_hostname(host->mmc), count, cmd->opcode);
686 count = 0xE;
687 }
688
689 return count;
690}
691
692static void sdhci_set_transfer_irqs(struct sdhci_host *host)
693{
694 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
695 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
696
697 if (host->flags & SDHCI_REQ_USE_DMA)
698 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
699 else
700 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
701}
702
703static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
704{
705 u8 count;
706 u8 ctrl;
707 struct mmc_data *data = cmd->data;
708 int ret;
709
710 WARN_ON(host->data);
711
712 if (data || (cmd->flags & MMC_RSP_BUSY)) {
713 count = sdhci_calc_timeout(host, cmd);
714 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
715 }
716
717 if (!data)
718 return;
719
720 /* Sanity checks */
721 BUG_ON(data->blksz * data->blocks > 524288);
722 BUG_ON(data->blksz > host->mmc->max_blk_size);
723 BUG_ON(data->blocks > 65535);
724
725 host->data = data;
726 host->data_early = 0;
727 host->data->bytes_xfered = 0;
728
729 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
730 host->flags |= SDHCI_REQ_USE_DMA;
731
732 /*
733 * FIXME: This doesn't account for merging when mapping the
734 * scatterlist.
735 */
736 if (host->flags & SDHCI_REQ_USE_DMA) {
737 int broken, i;
738 struct scatterlist *sg;
739
740 broken = 0;
741 if (host->flags & SDHCI_USE_ADMA) {
742 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
743 broken = 1;
744 } else {
745 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
746 broken = 1;
747 }
748
749 if (unlikely(broken)) {
750 for_each_sg(data->sg, sg, data->sg_len, i) {
751 if (sg->length & 0x3) {
752 DBG("Reverting to PIO because of "
753 "transfer size (%d)\n",
754 sg->length);
755 host->flags &= ~SDHCI_REQ_USE_DMA;
756 break;
757 }
758 }
759 }
760 }
761
762 /*
763 * The assumption here being that alignment is the same after
764 * translation to device address space.
765 */
766 if (host->flags & SDHCI_REQ_USE_DMA) {
767 int broken, i;
768 struct scatterlist *sg;
769
770 broken = 0;
771 if (host->flags & SDHCI_USE_ADMA) {
772 /*
773 * As we use 3 byte chunks to work around
774 * alignment problems, we need to check this
775 * quirk.
776 */
777 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 broken = 1;
779 } else {
780 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
781 broken = 1;
782 }
783
784 if (unlikely(broken)) {
785 for_each_sg(data->sg, sg, data->sg_len, i) {
786 if (sg->offset & 0x3) {
787 DBG("Reverting to PIO because of "
788 "bad alignment\n");
789 host->flags &= ~SDHCI_REQ_USE_DMA;
790 break;
791 }
792 }
793 }
794 }
795
796 if (host->flags & SDHCI_REQ_USE_DMA) {
797 if (host->flags & SDHCI_USE_ADMA) {
798 ret = sdhci_adma_table_pre(host, data);
799 if (ret) {
800 /*
801 * This only happens when someone fed
802 * us an invalid request.
803 */
804 WARN_ON(1);
805 host->flags &= ~SDHCI_REQ_USE_DMA;
806 } else {
807 sdhci_writel(host, host->adma_addr,
808 SDHCI_ADMA_ADDRESS);
809 }
810 } else {
811 int sg_cnt;
812
813 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
814 data->sg, data->sg_len,
815 (data->flags & MMC_DATA_READ) ?
816 DMA_FROM_DEVICE :
817 DMA_TO_DEVICE);
818 if (sg_cnt == 0) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 WARN_ON(sg_cnt != 1);
827 sdhci_writel(host, sg_dma_address(data->sg),
828 SDHCI_DMA_ADDRESS);
829 }
830 }
831 }
832
833 /*
834 * Always adjust the DMA selection as some controllers
835 * (e.g. JMicron) can't do PIO properly when the selection
836 * is ADMA.
837 */
838 if (host->version >= SDHCI_SPEC_200) {
839 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
840 ctrl &= ~SDHCI_CTRL_DMA_MASK;
841 if ((host->flags & SDHCI_REQ_USE_DMA) &&
842 (host->flags & SDHCI_USE_ADMA))
843 ctrl |= SDHCI_CTRL_ADMA32;
844 else
845 ctrl |= SDHCI_CTRL_SDMA;
846 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
847 }
848
849 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
850 int flags;
851
852 flags = SG_MITER_ATOMIC;
853 if (host->data->flags & MMC_DATA_READ)
854 flags |= SG_MITER_TO_SG;
855 else
856 flags |= SG_MITER_FROM_SG;
857 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
858 host->blocks = data->blocks;
859 }
860
861 sdhci_set_transfer_irqs(host);
862
863 /* Set the DMA boundary value and block size */
864 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
865 data->blksz), SDHCI_BLOCK_SIZE);
866 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
867}
868
869static void sdhci_set_transfer_mode(struct sdhci_host *host,
870 struct mmc_command *cmd)
871{
872 u16 mode;
873 struct mmc_data *data = cmd->data;
874
875 if (data == NULL)
876 return;
877
878 WARN_ON(!host->data);
879
880 mode = SDHCI_TRNS_BLK_CNT_EN;
881 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
882 mode |= SDHCI_TRNS_MULTI;
883 /*
884 * If we are sending CMD23, CMD12 never gets sent
885 * on successful completion (so no Auto-CMD12).
886 */
887 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
888 mode |= SDHCI_TRNS_AUTO_CMD12;
889 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
890 mode |= SDHCI_TRNS_AUTO_CMD23;
891 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
892 }
893 }
894
895 if (data->flags & MMC_DATA_READ)
896 mode |= SDHCI_TRNS_READ;
897 if (host->flags & SDHCI_REQ_USE_DMA)
898 mode |= SDHCI_TRNS_DMA;
899
900 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
901}
902
903static void sdhci_finish_data(struct sdhci_host *host)
904{
905 struct mmc_data *data;
906
907 BUG_ON(!host->data);
908
909 data = host->data;
910 host->data = NULL;
911
912 if (host->flags & SDHCI_REQ_USE_DMA) {
913 if (host->flags & SDHCI_USE_ADMA)
914 sdhci_adma_table_post(host, data);
915 else {
916 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
917 data->sg_len, (data->flags & MMC_DATA_READ) ?
918 DMA_FROM_DEVICE : DMA_TO_DEVICE);
919 }
920 }
921
922 /*
923 * The specification states that the block count register must
924 * be updated, but it does not specify at what point in the
925 * data flow. That makes the register entirely useless to read
926 * back so we have to assume that nothing made it to the card
927 * in the event of an error.
928 */
929 if (data->error)
930 data->bytes_xfered = 0;
931 else
932 data->bytes_xfered = data->blksz * data->blocks;
933
934 /*
935 * Need to send CMD12 if -
936 * a) open-ended multiblock transfer (no CMD23)
937 * b) error in multiblock transfer
938 */
939 if (data->stop &&
940 (data->error ||
941 !host->mrq->sbc)) {
942
943 /*
944 * The controller needs a reset of internal state machines
945 * upon error conditions.
946 */
947 if (data->error) {
948 sdhci_reset(host, SDHCI_RESET_CMD);
949 sdhci_reset(host, SDHCI_RESET_DATA);
950 }
951
952 sdhci_send_command(host, data->stop);
953 } else
954 tasklet_schedule(&host->finish_tasklet);
955}
956
957static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
958{
959 int flags;
960 u32 mask;
961 unsigned long timeout;
962
963 WARN_ON(host->cmd);
964
965 /* Wait max 10 ms */
966 timeout = 10;
967
968 mask = SDHCI_CMD_INHIBIT;
969 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
970 mask |= SDHCI_DATA_INHIBIT;
971
972 /* We shouldn't wait for data inihibit for stop commands, even
973 though they might use busy signaling */
974 if (host->mrq->data && (cmd == host->mrq->data->stop))
975 mask &= ~SDHCI_DATA_INHIBIT;
976
977 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
978 if (timeout == 0) {
979 pr_err("%s: Controller never released "
980 "inhibit bit(s).\n", mmc_hostname(host->mmc));
981 sdhci_dumpregs(host);
982 cmd->error = -EIO;
983 tasklet_schedule(&host->finish_tasklet);
984 return;
985 }
986 timeout--;
987 mdelay(1);
988 }
989
990 mod_timer(&host->timer, jiffies + 10 * HZ);
991
992 host->cmd = cmd;
993
994 sdhci_prepare_data(host, cmd);
995
996 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
997
998 sdhci_set_transfer_mode(host, cmd);
999
1000 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1001 pr_err("%s: Unsupported response type!\n",
1002 mmc_hostname(host->mmc));
1003 cmd->error = -EINVAL;
1004 tasklet_schedule(&host->finish_tasklet);
1005 return;
1006 }
1007
1008 if (!(cmd->flags & MMC_RSP_PRESENT))
1009 flags = SDHCI_CMD_RESP_NONE;
1010 else if (cmd->flags & MMC_RSP_136)
1011 flags = SDHCI_CMD_RESP_LONG;
1012 else if (cmd->flags & MMC_RSP_BUSY)
1013 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1014 else
1015 flags = SDHCI_CMD_RESP_SHORT;
1016
1017 if (cmd->flags & MMC_RSP_CRC)
1018 flags |= SDHCI_CMD_CRC;
1019 if (cmd->flags & MMC_RSP_OPCODE)
1020 flags |= SDHCI_CMD_INDEX;
1021
1022 /* CMD19 is special in that the Data Present Select should be set */
1023 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1024 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1025 flags |= SDHCI_CMD_DATA;
1026
1027 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1028}
1029
1030static void sdhci_finish_command(struct sdhci_host *host)
1031{
1032 int i;
1033
1034 BUG_ON(host->cmd == NULL);
1035
1036 if (host->cmd->flags & MMC_RSP_PRESENT) {
1037 if (host->cmd->flags & MMC_RSP_136) {
1038 /* CRC is stripped so we need to do some shifting. */
1039 for (i = 0;i < 4;i++) {
1040 host->cmd->resp[i] = sdhci_readl(host,
1041 SDHCI_RESPONSE + (3-i)*4) << 8;
1042 if (i != 3)
1043 host->cmd->resp[i] |=
1044 sdhci_readb(host,
1045 SDHCI_RESPONSE + (3-i)*4-1);
1046 }
1047 } else {
1048 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1049 }
1050 }
1051
1052 host->cmd->error = 0;
1053
1054 /* Finished CMD23, now send actual command. */
1055 if (host->cmd == host->mrq->sbc) {
1056 host->cmd = NULL;
1057 sdhci_send_command(host, host->mrq->cmd);
1058 } else {
1059
1060 /* Processed actual command. */
1061 if (host->data && host->data_early)
1062 sdhci_finish_data(host);
1063
1064 if (!host->cmd->data)
1065 tasklet_schedule(&host->finish_tasklet);
1066
1067 host->cmd = NULL;
1068 }
1069}
1070
1071static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1072{
1073 int div = 0; /* Initialized for compiler warning */
1074 int real_div = div, clk_mul = 1;
1075 u16 clk = 0;
1076 unsigned long timeout;
1077
1078 if (clock && clock == host->clock)
1079 return;
1080
1081 host->mmc->actual_clock = 0;
1082
1083 if (host->ops->set_clock) {
1084 host->ops->set_clock(host, clock);
1085 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1086 return;
1087 }
1088
1089 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1090
1091 if (clock == 0)
1092 goto out;
1093
1094 if (host->version >= SDHCI_SPEC_300) {
1095 /*
1096 * Check if the Host Controller supports Programmable Clock
1097 * Mode.
1098 */
1099 if (host->clk_mul) {
1100 u16 ctrl;
1101
1102 /*
1103 * We need to figure out whether the Host Driver needs
1104 * to select Programmable Clock Mode, or the value can
1105 * be set automatically by the Host Controller based on
1106 * the Preset Value registers.
1107 */
1108 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1109 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1110 for (div = 1; div <= 1024; div++) {
1111 if (((host->max_clk * host->clk_mul) /
1112 div) <= clock)
1113 break;
1114 }
1115 /*
1116 * Set Programmable Clock Mode in the Clock
1117 * Control register.
1118 */
1119 clk = SDHCI_PROG_CLOCK_MODE;
1120 real_div = div;
1121 clk_mul = host->clk_mul;
1122 div--;
1123 }
1124 } else {
1125 /* Version 3.00 divisors must be a multiple of 2. */
1126 if (host->max_clk <= clock)
1127 div = 1;
1128 else {
1129 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1130 div += 2) {
1131 if ((host->max_clk / div) <= clock)
1132 break;
1133 }
1134 }
1135 real_div = div;
1136 div >>= 1;
1137 }
1138 } else {
1139 /* Version 2.00 divisors must be a power of 2. */
1140 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1141 if ((host->max_clk / div) <= clock)
1142 break;
1143 }
1144 real_div = div;
1145 div >>= 1;
1146 }
1147
1148 if (real_div)
1149 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1150
1151 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1152 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1153 << SDHCI_DIVIDER_HI_SHIFT;
1154 clk |= SDHCI_CLOCK_INT_EN;
1155 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1156
1157 /* Wait max 20 ms */
1158 timeout = 20;
1159 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1160 & SDHCI_CLOCK_INT_STABLE)) {
1161 if (timeout == 0) {
1162 pr_err("%s: Internal clock never "
1163 "stabilised.\n", mmc_hostname(host->mmc));
1164 sdhci_dumpregs(host);
1165 return;
1166 }
1167 timeout--;
1168 mdelay(1);
1169 }
1170
1171 clk |= SDHCI_CLOCK_CARD_EN;
1172 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1173
1174out:
1175 host->clock = clock;
1176}
1177
1178static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1179{
1180 u8 pwr = 0;
1181
1182 if (power != (unsigned short)-1) {
1183 switch (1 << power) {
1184 case MMC_VDD_165_195:
1185 pwr = SDHCI_POWER_180;
1186 break;
1187 case MMC_VDD_29_30:
1188 case MMC_VDD_30_31:
1189 pwr = SDHCI_POWER_300;
1190 break;
1191 case MMC_VDD_32_33:
1192 case MMC_VDD_33_34:
1193 pwr = SDHCI_POWER_330;
1194 break;
1195 default:
1196 BUG();
1197 }
1198 }
1199
1200 if (host->pwr == pwr)
1201 return -1;
1202
1203 host->pwr = pwr;
1204
1205 if (pwr == 0) {
1206 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1207 return 0;
1208 }
1209
1210 /*
1211 * Spec says that we should clear the power reg before setting
1212 * a new value. Some controllers don't seem to like this though.
1213 */
1214 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1215 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1216
1217 /*
1218 * At least the Marvell CaFe chip gets confused if we set the voltage
1219 * and set turn on power at the same time, so set the voltage first.
1220 */
1221 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1222 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1223
1224 pwr |= SDHCI_POWER_ON;
1225
1226 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1227
1228 /*
1229 * Some controllers need an extra 10ms delay of 10ms before they
1230 * can apply clock after applying power
1231 */
1232 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1233 mdelay(10);
1234
1235 return power;
1236}
1237
1238/*****************************************************************************\
1239 * *
1240 * MMC callbacks *
1241 * *
1242\*****************************************************************************/
1243
1244static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245{
1246 struct sdhci_host *host;
1247 bool present;
1248 unsigned long flags;
1249 u32 tuning_opcode;
1250
1251 host = mmc_priv(mmc);
1252
1253 sdhci_runtime_pm_get(host);
1254
1255 spin_lock_irqsave(&host->lock, flags);
1256
1257 WARN_ON(host->mrq != NULL);
1258
1259#ifndef SDHCI_USE_LEDS_CLASS
1260 sdhci_activate_led(host);
1261#endif
1262
1263 /*
1264 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1265 * requests if Auto-CMD12 is enabled.
1266 */
1267 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1268 if (mrq->stop) {
1269 mrq->data->stop = NULL;
1270 mrq->stop = NULL;
1271 }
1272 }
1273
1274 host->mrq = mrq;
1275
1276 /* If polling, assume that the card is always present. */
1277 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1278 present = true;
1279 else
1280 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1281 SDHCI_CARD_PRESENT;
1282
1283 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1284 host->mrq->cmd->error = -ENOMEDIUM;
1285 tasklet_schedule(&host->finish_tasklet);
1286 } else {
1287 u32 present_state;
1288
1289 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1290 /*
1291 * Check if the re-tuning timer has already expired and there
1292 * is no on-going data transfer. If so, we need to execute
1293 * tuning procedure before sending command.
1294 */
1295 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1296 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1297 /* eMMC uses cmd21 while sd and sdio use cmd19 */
1298 tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1299 MMC_SEND_TUNING_BLOCK_HS200 :
1300 MMC_SEND_TUNING_BLOCK;
1301 spin_unlock_irqrestore(&host->lock, flags);
1302 sdhci_execute_tuning(mmc, tuning_opcode);
1303 spin_lock_irqsave(&host->lock, flags);
1304
1305 /* Restore original mmc_request structure */
1306 host->mrq = mrq;
1307 }
1308
1309 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1310 sdhci_send_command(host, mrq->sbc);
1311 else
1312 sdhci_send_command(host, mrq->cmd);
1313 }
1314
1315 mmiowb();
1316 spin_unlock_irqrestore(&host->lock, flags);
1317}
1318
1319static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1320{
1321 unsigned long flags;
1322 int vdd_bit = -1;
1323 u8 ctrl;
1324
1325 spin_lock_irqsave(&host->lock, flags);
1326
1327 if (host->flags & SDHCI_DEVICE_DEAD) {
1328 spin_unlock_irqrestore(&host->lock, flags);
1329 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1330 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1331 return;
1332 }
1333
1334 /*
1335 * Reset the chip on each power off.
1336 * Should clear out any weird states.
1337 */
1338 if (ios->power_mode == MMC_POWER_OFF) {
1339 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1340 sdhci_reinit(host);
1341 }
1342
1343 sdhci_set_clock(host, ios->clock);
1344
1345 if (ios->power_mode == MMC_POWER_OFF)
1346 vdd_bit = sdhci_set_power(host, -1);
1347 else
1348 vdd_bit = sdhci_set_power(host, ios->vdd);
1349
1350 if (host->vmmc && vdd_bit != -1) {
1351 spin_unlock_irqrestore(&host->lock, flags);
1352 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1353 spin_lock_irqsave(&host->lock, flags);
1354 }
1355
1356 if (host->ops->platform_send_init_74_clocks)
1357 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1358
1359 /*
1360 * If your platform has 8-bit width support but is not a v3 controller,
1361 * or if it requires special setup code, you should implement that in
1362 * platform_8bit_width().
1363 */
1364 if (host->ops->platform_8bit_width)
1365 host->ops->platform_8bit_width(host, ios->bus_width);
1366 else {
1367 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1368 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1369 ctrl &= ~SDHCI_CTRL_4BITBUS;
1370 if (host->version >= SDHCI_SPEC_300)
1371 ctrl |= SDHCI_CTRL_8BITBUS;
1372 } else {
1373 if (host->version >= SDHCI_SPEC_300)
1374 ctrl &= ~SDHCI_CTRL_8BITBUS;
1375 if (ios->bus_width == MMC_BUS_WIDTH_4)
1376 ctrl |= SDHCI_CTRL_4BITBUS;
1377 else
1378 ctrl &= ~SDHCI_CTRL_4BITBUS;
1379 }
1380 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1381 }
1382
1383 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1384
1385 if ((ios->timing == MMC_TIMING_SD_HS ||
1386 ios->timing == MMC_TIMING_MMC_HS)
1387 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1388 ctrl |= SDHCI_CTRL_HISPD;
1389 else
1390 ctrl &= ~SDHCI_CTRL_HISPD;
1391
1392 if (host->version >= SDHCI_SPEC_300) {
1393 u16 clk, ctrl_2;
1394 unsigned int clock;
1395
1396 /* In case of UHS-I modes, set High Speed Enable */
1397 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1398 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1399 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1400 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1401 (ios->timing == MMC_TIMING_UHS_SDR25))
1402 ctrl |= SDHCI_CTRL_HISPD;
1403
1404 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1405 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1406 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1407 /*
1408 * We only need to set Driver Strength if the
1409 * preset value enable is not set.
1410 */
1411 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1412 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1413 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1414 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1415 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1416
1417 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1418 } else {
1419 /*
1420 * According to SDHC Spec v3.00, if the Preset Value
1421 * Enable in the Host Control 2 register is set, we
1422 * need to reset SD Clock Enable before changing High
1423 * Speed Enable to avoid generating clock gliches.
1424 */
1425
1426 /* Reset SD Clock Enable */
1427 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1428 clk &= ~SDHCI_CLOCK_CARD_EN;
1429 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1430
1431 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1432
1433 /* Re-enable SD Clock */
1434 clock = host->clock;
1435 host->clock = 0;
1436 sdhci_set_clock(host, clock);
1437 }
1438
1439
1440 /* Reset SD Clock Enable */
1441 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1442 clk &= ~SDHCI_CLOCK_CARD_EN;
1443 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1444
1445 if (host->ops->set_uhs_signaling)
1446 host->ops->set_uhs_signaling(host, ios->timing);
1447 else {
1448 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1449 /* Select Bus Speed Mode for host */
1450 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1451 if (ios->timing == MMC_TIMING_MMC_HS200)
1452 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1453 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1454 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1455 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1456 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1457 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1458 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1459 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1460 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1461 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1462 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1463 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1464 }
1465
1466 /* Re-enable SD Clock */
1467 clock = host->clock;
1468 host->clock = 0;
1469 sdhci_set_clock(host, clock);
1470 } else
1471 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1472
1473 /*
1474 * Some (ENE) controllers go apeshit on some ios operation,
1475 * signalling timeout and CRC errors even on CMD0. Resetting
1476 * it on each ios seems to solve the problem.
1477 */
1478 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1479 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1480
1481 mmiowb();
1482 spin_unlock_irqrestore(&host->lock, flags);
1483}
1484
1485static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1486{
1487 struct sdhci_host *host = mmc_priv(mmc);
1488
1489 sdhci_runtime_pm_get(host);
1490 sdhci_do_set_ios(host, ios);
1491 sdhci_runtime_pm_put(host);
1492}
1493
1494static int sdhci_check_ro(struct sdhci_host *host)
1495{
1496 unsigned long flags;
1497 int is_readonly;
1498
1499 spin_lock_irqsave(&host->lock, flags);
1500
1501 if (host->flags & SDHCI_DEVICE_DEAD)
1502 is_readonly = 0;
1503 else if (host->ops->get_ro)
1504 is_readonly = host->ops->get_ro(host);
1505 else
1506 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1507 & SDHCI_WRITE_PROTECT);
1508
1509 spin_unlock_irqrestore(&host->lock, flags);
1510
1511 /* This quirk needs to be replaced by a callback-function later */
1512 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1513 !is_readonly : is_readonly;
1514}
1515
1516#define SAMPLE_COUNT 5
1517
1518static int sdhci_do_get_ro(struct sdhci_host *host)
1519{
1520 int i, ro_count;
1521
1522 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1523 return sdhci_check_ro(host);
1524
1525 ro_count = 0;
1526 for (i = 0; i < SAMPLE_COUNT; i++) {
1527 if (sdhci_check_ro(host)) {
1528 if (++ro_count > SAMPLE_COUNT / 2)
1529 return 1;
1530 }
1531 msleep(30);
1532 }
1533 return 0;
1534}
1535
1536static void sdhci_hw_reset(struct mmc_host *mmc)
1537{
1538 struct sdhci_host *host = mmc_priv(mmc);
1539
1540 if (host->ops && host->ops->hw_reset)
1541 host->ops->hw_reset(host);
1542}
1543
1544static int sdhci_get_ro(struct mmc_host *mmc)
1545{
1546 struct sdhci_host *host = mmc_priv(mmc);
1547 int ret;
1548
1549 sdhci_runtime_pm_get(host);
1550 ret = sdhci_do_get_ro(host);
1551 sdhci_runtime_pm_put(host);
1552 return ret;
1553}
1554
1555static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1556{
1557 if (host->flags & SDHCI_DEVICE_DEAD)
1558 goto out;
1559
1560 if (enable)
1561 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1562 else
1563 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1564
1565 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1566 if (host->runtime_suspended)
1567 goto out;
1568
1569 if (enable)
1570 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1571 else
1572 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1573out:
1574 mmiowb();
1575}
1576
1577static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1578{
1579 struct sdhci_host *host = mmc_priv(mmc);
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(&host->lock, flags);
1583 sdhci_enable_sdio_irq_nolock(host, enable);
1584 spin_unlock_irqrestore(&host->lock, flags);
1585}
1586
1587static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1588 struct mmc_ios *ios)
1589{
1590 u8 pwr;
1591 u16 clk, ctrl;
1592 u32 present_state;
1593
1594 /*
1595 * Signal Voltage Switching is only applicable for Host Controllers
1596 * v3.00 and above.
1597 */
1598 if (host->version < SDHCI_SPEC_300)
1599 return 0;
1600
1601 /*
1602 * We first check whether the request is to set signalling voltage
1603 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1604 */
1605 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1606 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1607 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1608 ctrl &= ~SDHCI_CTRL_VDD_180;
1609 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1610
1611 /* Wait for 5ms */
1612 usleep_range(5000, 5500);
1613
1614 /* 3.3V regulator output should be stable within 5 ms */
1615 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1616 if (!(ctrl & SDHCI_CTRL_VDD_180))
1617 return 0;
1618 else {
1619 pr_info(DRIVER_NAME ": Switching to 3.3V "
1620 "signalling voltage failed\n");
1621 return -EIO;
1622 }
1623 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1624 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1625 /* Stop SDCLK */
1626 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1627 clk &= ~SDHCI_CLOCK_CARD_EN;
1628 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1629
1630 /* Check whether DAT[3:0] is 0000 */
1631 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1632 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1633 SDHCI_DATA_LVL_SHIFT)) {
1634 /*
1635 * Enable 1.8V Signal Enable in the Host Control2
1636 * register
1637 */
1638 ctrl |= SDHCI_CTRL_VDD_180;
1639 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1640
1641 /* Wait for 5ms */
1642 usleep_range(5000, 5500);
1643
1644 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1645 if (ctrl & SDHCI_CTRL_VDD_180) {
1646 /* Provide SDCLK again and wait for 1ms*/
1647 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1648 clk |= SDHCI_CLOCK_CARD_EN;
1649 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1650 usleep_range(1000, 1500);
1651
1652 /*
1653 * If DAT[3:0] level is 1111b, then the card
1654 * was successfully switched to 1.8V signaling.
1655 */
1656 present_state = sdhci_readl(host,
1657 SDHCI_PRESENT_STATE);
1658 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1659 SDHCI_DATA_LVL_MASK)
1660 return 0;
1661 }
1662 }
1663
1664 /*
1665 * If we are here, that means the switch to 1.8V signaling
1666 * failed. We power cycle the card, and retry initialization
1667 * sequence by setting S18R to 0.
1668 */
1669 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1670 pwr &= ~SDHCI_POWER_ON;
1671 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1672
1673 /* Wait for 1ms as per the spec */
1674 usleep_range(1000, 1500);
1675 pwr |= SDHCI_POWER_ON;
1676 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1677
1678 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1679 "voltage failed, retrying with S18R set to 0\n");
1680 return -EAGAIN;
1681 } else
1682 /* No signal voltage switch required */
1683 return 0;
1684}
1685
1686static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1687 struct mmc_ios *ios)
1688{
1689 struct sdhci_host *host = mmc_priv(mmc);
1690 int err;
1691
1692 if (host->version < SDHCI_SPEC_300)
1693 return 0;
1694 sdhci_runtime_pm_get(host);
1695 err = sdhci_do_start_signal_voltage_switch(host, ios);
1696 sdhci_runtime_pm_put(host);
1697 return err;
1698}
1699
1700static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1701{
1702 struct sdhci_host *host;
1703 u16 ctrl;
1704 u32 ier;
1705 int tuning_loop_counter = MAX_TUNING_LOOP;
1706 unsigned long timeout;
1707 int err = 0;
1708 bool requires_tuning_nonuhs = false;
1709
1710 host = mmc_priv(mmc);
1711
1712 sdhci_runtime_pm_get(host);
1713 disable_irq(host->irq);
1714 spin_lock(&host->lock);
1715
1716 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1717
1718 /*
1719 * The Host Controller needs tuning only in case of SDR104 mode
1720 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1721 * Capabilities register.
1722 * If the Host Controller supports the HS200 mode then the
1723 * tuning function has to be executed.
1724 */
1725 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1726 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1727 host->flags & SDHCI_HS200_NEEDS_TUNING))
1728 requires_tuning_nonuhs = true;
1729
1730 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1731 requires_tuning_nonuhs)
1732 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1733 else {
1734 spin_unlock(&host->lock);
1735 enable_irq(host->irq);
1736 sdhci_runtime_pm_put(host);
1737 return 0;
1738 }
1739
1740 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1741
1742 /*
1743 * As per the Host Controller spec v3.00, tuning command
1744 * generates Buffer Read Ready interrupt, so enable that.
1745 *
1746 * Note: The spec clearly says that when tuning sequence
1747 * is being performed, the controller does not generate
1748 * interrupts other than Buffer Read Ready interrupt. But
1749 * to make sure we don't hit a controller bug, we _only_
1750 * enable Buffer Read Ready interrupt here.
1751 */
1752 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1753 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1754
1755 /*
1756 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1757 * of loops reaches 40 times or a timeout of 150ms occurs.
1758 */
1759 timeout = 150;
1760 do {
1761 struct mmc_command cmd = {0};
1762 struct mmc_request mrq = {NULL};
1763
1764 if (!tuning_loop_counter && !timeout)
1765 break;
1766
1767 cmd.opcode = opcode;
1768 cmd.arg = 0;
1769 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1770 cmd.retries = 0;
1771 cmd.data = NULL;
1772 cmd.error = 0;
1773
1774 mrq.cmd = &cmd;
1775 host->mrq = &mrq;
1776
1777 /*
1778 * In response to CMD19, the card sends 64 bytes of tuning
1779 * block to the Host Controller. So we set the block size
1780 * to 64 here.
1781 */
1782 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1783 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1784 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1785 SDHCI_BLOCK_SIZE);
1786 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1787 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1788 SDHCI_BLOCK_SIZE);
1789 } else {
1790 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1791 SDHCI_BLOCK_SIZE);
1792 }
1793
1794 /*
1795 * The tuning block is sent by the card to the host controller.
1796 * So we set the TRNS_READ bit in the Transfer Mode register.
1797 * This also takes care of setting DMA Enable and Multi Block
1798 * Select in the same register to 0.
1799 */
1800 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1801
1802 sdhci_send_command(host, &cmd);
1803
1804 host->cmd = NULL;
1805 host->mrq = NULL;
1806
1807 spin_unlock(&host->lock);
1808 enable_irq(host->irq);
1809
1810 /* Wait for Buffer Read Ready interrupt */
1811 wait_event_interruptible_timeout(host->buf_ready_int,
1812 (host->tuning_done == 1),
1813 msecs_to_jiffies(50));
1814 disable_irq(host->irq);
1815 spin_lock(&host->lock);
1816
1817 if (!host->tuning_done) {
1818 pr_info(DRIVER_NAME ": Timeout waiting for "
1819 "Buffer Read Ready interrupt during tuning "
1820 "procedure, falling back to fixed sampling "
1821 "clock\n");
1822 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1823 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1824 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1825 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1826
1827 err = -EIO;
1828 goto out;
1829 }
1830
1831 host->tuning_done = 0;
1832
1833 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1834 tuning_loop_counter--;
1835 timeout--;
1836 mdelay(1);
1837 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1838
1839 /*
1840 * The Host Driver has exhausted the maximum number of loops allowed,
1841 * so use fixed sampling frequency.
1842 */
1843 if (!tuning_loop_counter || !timeout) {
1844 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1845 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1846 } else {
1847 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1848 pr_info(DRIVER_NAME ": Tuning procedure"
1849 " failed, falling back to fixed sampling"
1850 " clock\n");
1851 err = -EIO;
1852 }
1853 }
1854
1855out:
1856 /*
1857 * If this is the very first time we are here, we start the retuning
1858 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1859 * flag won't be set, we check this condition before actually starting
1860 * the timer.
1861 */
1862 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1863 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1864 mod_timer(&host->tuning_timer, jiffies +
1865 host->tuning_count * HZ);
1866 /* Tuning mode 1 limits the maximum data length to 4MB */
1867 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1868 } else {
1869 host->flags &= ~SDHCI_NEEDS_RETUNING;
1870 /* Reload the new initial value for timer */
1871 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1872 mod_timer(&host->tuning_timer, jiffies +
1873 host->tuning_count * HZ);
1874 }
1875
1876 /*
1877 * In case tuning fails, host controllers which support re-tuning can
1878 * try tuning again at a later time, when the re-tuning timer expires.
1879 * So for these controllers, we return 0. Since there might be other
1880 * controllers who do not have this capability, we return error for
1881 * them.
1882 */
1883 if (err && host->tuning_count &&
1884 host->tuning_mode == SDHCI_TUNING_MODE_1)
1885 err = 0;
1886
1887 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1888 spin_unlock(&host->lock);
1889 enable_irq(host->irq);
1890 sdhci_runtime_pm_put(host);
1891
1892 return err;
1893}
1894
1895static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1896{
1897 u16 ctrl;
1898 unsigned long flags;
1899
1900 /* Host Controller v3.00 defines preset value registers */
1901 if (host->version < SDHCI_SPEC_300)
1902 return;
1903
1904 spin_lock_irqsave(&host->lock, flags);
1905
1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907
1908 /*
1909 * We only enable or disable Preset Value if they are not already
1910 * enabled or disabled respectively. Otherwise, we bail out.
1911 */
1912 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1913 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1914 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1915 host->flags |= SDHCI_PV_ENABLED;
1916 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1917 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1918 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1919 host->flags &= ~SDHCI_PV_ENABLED;
1920 }
1921
1922 spin_unlock_irqrestore(&host->lock, flags);
1923}
1924
1925static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1926{
1927 struct sdhci_host *host = mmc_priv(mmc);
1928
1929 sdhci_runtime_pm_get(host);
1930 sdhci_do_enable_preset_value(host, enable);
1931 sdhci_runtime_pm_put(host);
1932}
1933
1934static const struct mmc_host_ops sdhci_ops = {
1935 .request = sdhci_request,
1936 .set_ios = sdhci_set_ios,
1937 .get_ro = sdhci_get_ro,
1938 .hw_reset = sdhci_hw_reset,
1939 .enable_sdio_irq = sdhci_enable_sdio_irq,
1940 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1941 .execute_tuning = sdhci_execute_tuning,
1942 .enable_preset_value = sdhci_enable_preset_value,
1943};
1944
1945/*****************************************************************************\
1946 * *
1947 * Tasklets *
1948 * *
1949\*****************************************************************************/
1950
1951static void sdhci_tasklet_card(unsigned long param)
1952{
1953 struct sdhci_host *host;
1954 unsigned long flags;
1955
1956 host = (struct sdhci_host*)param;
1957
1958 spin_lock_irqsave(&host->lock, flags);
1959
1960 /* Check host->mrq first in case we are runtime suspended */
1961 if (host->mrq &&
1962 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1963 pr_err("%s: Card removed during transfer!\n",
1964 mmc_hostname(host->mmc));
1965 pr_err("%s: Resetting controller.\n",
1966 mmc_hostname(host->mmc));
1967
1968 sdhci_reset(host, SDHCI_RESET_CMD);
1969 sdhci_reset(host, SDHCI_RESET_DATA);
1970
1971 host->mrq->cmd->error = -ENOMEDIUM;
1972 tasklet_schedule(&host->finish_tasklet);
1973 }
1974
1975 spin_unlock_irqrestore(&host->lock, flags);
1976
1977 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1978}
1979
1980static void sdhci_tasklet_finish(unsigned long param)
1981{
1982 struct sdhci_host *host;
1983 unsigned long flags;
1984 struct mmc_request *mrq;
1985
1986 host = (struct sdhci_host*)param;
1987
1988 spin_lock_irqsave(&host->lock, flags);
1989
1990 /*
1991 * If this tasklet gets rescheduled while running, it will
1992 * be run again afterwards but without any active request.
1993 */
1994 if (!host->mrq) {
1995 spin_unlock_irqrestore(&host->lock, flags);
1996 return;
1997 }
1998
1999 del_timer(&host->timer);
2000
2001 mrq = host->mrq;
2002
2003 /*
2004 * The controller needs a reset of internal state machines
2005 * upon error conditions.
2006 */
2007 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2008 ((mrq->cmd && mrq->cmd->error) ||
2009 (mrq->data && (mrq->data->error ||
2010 (mrq->data->stop && mrq->data->stop->error))) ||
2011 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2012
2013 /* Some controllers need this kick or reset won't work here */
2014 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2015 unsigned int clock;
2016
2017 /* This is to force an update */
2018 clock = host->clock;
2019 host->clock = 0;
2020 sdhci_set_clock(host, clock);
2021 }
2022
2023 /* Spec says we should do both at the same time, but Ricoh
2024 controllers do not like that. */
2025 sdhci_reset(host, SDHCI_RESET_CMD);
2026 sdhci_reset(host, SDHCI_RESET_DATA);
2027 }
2028
2029 host->mrq = NULL;
2030 host->cmd = NULL;
2031 host->data = NULL;
2032
2033#ifndef SDHCI_USE_LEDS_CLASS
2034 sdhci_deactivate_led(host);
2035#endif
2036
2037 mmiowb();
2038 spin_unlock_irqrestore(&host->lock, flags);
2039
2040 mmc_request_done(host->mmc, mrq);
2041 sdhci_runtime_pm_put(host);
2042}
2043
2044static void sdhci_timeout_timer(unsigned long data)
2045{
2046 struct sdhci_host *host;
2047 unsigned long flags;
2048
2049 host = (struct sdhci_host*)data;
2050
2051 spin_lock_irqsave(&host->lock, flags);
2052
2053 if (host->mrq) {
2054 pr_err("%s: Timeout waiting for hardware "
2055 "interrupt.\n", mmc_hostname(host->mmc));
2056 sdhci_dumpregs(host);
2057
2058 if (host->data) {
2059 host->data->error = -ETIMEDOUT;
2060 sdhci_finish_data(host);
2061 } else {
2062 if (host->cmd)
2063 host->cmd->error = -ETIMEDOUT;
2064 else
2065 host->mrq->cmd->error = -ETIMEDOUT;
2066
2067 tasklet_schedule(&host->finish_tasklet);
2068 }
2069 }
2070
2071 mmiowb();
2072 spin_unlock_irqrestore(&host->lock, flags);
2073}
2074
2075static void sdhci_tuning_timer(unsigned long data)
2076{
2077 struct sdhci_host *host;
2078 unsigned long flags;
2079
2080 host = (struct sdhci_host *)data;
2081
2082 spin_lock_irqsave(&host->lock, flags);
2083
2084 host->flags |= SDHCI_NEEDS_RETUNING;
2085
2086 spin_unlock_irqrestore(&host->lock, flags);
2087}
2088
2089/*****************************************************************************\
2090 * *
2091 * Interrupt handling *
2092 * *
2093\*****************************************************************************/
2094
2095static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2096{
2097 BUG_ON(intmask == 0);
2098
2099 if (!host->cmd) {
2100 pr_err("%s: Got command interrupt 0x%08x even "
2101 "though no command operation was in progress.\n",
2102 mmc_hostname(host->mmc), (unsigned)intmask);
2103 sdhci_dumpregs(host);
2104 return;
2105 }
2106
2107 if (intmask & SDHCI_INT_TIMEOUT)
2108 host->cmd->error = -ETIMEDOUT;
2109 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2110 SDHCI_INT_INDEX))
2111 host->cmd->error = -EILSEQ;
2112
2113 if (host->cmd->error) {
2114 tasklet_schedule(&host->finish_tasklet);
2115 return;
2116 }
2117
2118 /*
2119 * The host can send and interrupt when the busy state has
2120 * ended, allowing us to wait without wasting CPU cycles.
2121 * Unfortunately this is overloaded on the "data complete"
2122 * interrupt, so we need to take some care when handling
2123 * it.
2124 *
2125 * Note: The 1.0 specification is a bit ambiguous about this
2126 * feature so there might be some problems with older
2127 * controllers.
2128 */
2129 if (host->cmd->flags & MMC_RSP_BUSY) {
2130 if (host->cmd->data)
2131 DBG("Cannot wait for busy signal when also "
2132 "doing a data transfer");
2133 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2134 return;
2135
2136 /* The controller does not support the end-of-busy IRQ,
2137 * fall through and take the SDHCI_INT_RESPONSE */
2138 }
2139
2140 if (intmask & SDHCI_INT_RESPONSE)
2141 sdhci_finish_command(host);
2142}
2143
2144#ifdef CONFIG_MMC_DEBUG
2145static void sdhci_show_adma_error(struct sdhci_host *host)
2146{
2147 const char *name = mmc_hostname(host->mmc);
2148 u8 *desc = host->adma_desc;
2149 __le32 *dma;
2150 __le16 *len;
2151 u8 attr;
2152
2153 sdhci_dumpregs(host);
2154
2155 while (true) {
2156 dma = (__le32 *)(desc + 4);
2157 len = (__le16 *)(desc + 2);
2158 attr = *desc;
2159
2160 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2161 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2162
2163 desc += 8;
2164
2165 if (attr & 2)
2166 break;
2167 }
2168}
2169#else
2170static void sdhci_show_adma_error(struct sdhci_host *host) { }
2171#endif
2172
2173static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2174{
2175 u32 command;
2176 BUG_ON(intmask == 0);
2177
2178 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2179 if (intmask & SDHCI_INT_DATA_AVAIL) {
2180 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2181 if (command == MMC_SEND_TUNING_BLOCK ||
2182 command == MMC_SEND_TUNING_BLOCK_HS200) {
2183 host->tuning_done = 1;
2184 wake_up(&host->buf_ready_int);
2185 return;
2186 }
2187 }
2188
2189 if (!host->data) {
2190 /*
2191 * The "data complete" interrupt is also used to
2192 * indicate that a busy state has ended. See comment
2193 * above in sdhci_cmd_irq().
2194 */
2195 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2196 if (intmask & SDHCI_INT_DATA_END) {
2197 sdhci_finish_command(host);
2198 return;
2199 }
2200 }
2201
2202 pr_err("%s: Got data interrupt 0x%08x even "
2203 "though no data operation was in progress.\n",
2204 mmc_hostname(host->mmc), (unsigned)intmask);
2205 sdhci_dumpregs(host);
2206
2207 return;
2208 }
2209
2210 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2211 host->data->error = -ETIMEDOUT;
2212 else if (intmask & SDHCI_INT_DATA_END_BIT)
2213 host->data->error = -EILSEQ;
2214 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2215 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2216 != MMC_BUS_TEST_R)
2217 host->data->error = -EILSEQ;
2218 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2219 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2220 sdhci_show_adma_error(host);
2221 host->data->error = -EIO;
2222 }
2223
2224 if (host->data->error)
2225 sdhci_finish_data(host);
2226 else {
2227 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2228 sdhci_transfer_pio(host);
2229
2230 /*
2231 * We currently don't do anything fancy with DMA
2232 * boundaries, but as we can't disable the feature
2233 * we need to at least restart the transfer.
2234 *
2235 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2236 * should return a valid address to continue from, but as
2237 * some controllers are faulty, don't trust them.
2238 */
2239 if (intmask & SDHCI_INT_DMA_END) {
2240 u32 dmastart, dmanow;
2241 dmastart = sg_dma_address(host->data->sg);
2242 dmanow = dmastart + host->data->bytes_xfered;
2243 /*
2244 * Force update to the next DMA block boundary.
2245 */
2246 dmanow = (dmanow &
2247 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2248 SDHCI_DEFAULT_BOUNDARY_SIZE;
2249 host->data->bytes_xfered = dmanow - dmastart;
2250 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2251 " next 0x%08x\n",
2252 mmc_hostname(host->mmc), dmastart,
2253 host->data->bytes_xfered, dmanow);
2254 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2255 }
2256
2257 if (intmask & SDHCI_INT_DATA_END) {
2258 if (host->cmd) {
2259 /*
2260 * Data managed to finish before the
2261 * command completed. Make sure we do
2262 * things in the proper order.
2263 */
2264 host->data_early = 1;
2265 } else {
2266 sdhci_finish_data(host);
2267 }
2268 }
2269 }
2270}
2271
2272static irqreturn_t sdhci_irq(int irq, void *dev_id)
2273{
2274 irqreturn_t result;
2275 struct sdhci_host *host = dev_id;
2276 u32 intmask, unexpected = 0;
2277 int cardint = 0, max_loops = 16;
2278
2279 spin_lock(&host->lock);
2280
2281 if (host->runtime_suspended) {
2282 spin_unlock(&host->lock);
2283 pr_warning("%s: got irq while runtime suspended\n",
2284 mmc_hostname(host->mmc));
2285 return IRQ_HANDLED;
2286 }
2287
2288 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2289
2290 if (!intmask || intmask == 0xffffffff) {
2291 result = IRQ_NONE;
2292 goto out;
2293 }
2294
2295again:
2296 DBG("*** %s got interrupt: 0x%08x\n",
2297 mmc_hostname(host->mmc), intmask);
2298
2299 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2300 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2301 SDHCI_CARD_PRESENT;
2302
2303 /*
2304 * There is a observation on i.mx esdhc. INSERT bit will be
2305 * immediately set again when it gets cleared, if a card is
2306 * inserted. We have to mask the irq to prevent interrupt
2307 * storm which will freeze the system. And the REMOVE gets
2308 * the same situation.
2309 *
2310 * More testing are needed here to ensure it works for other
2311 * platforms though.
2312 */
2313 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2314 SDHCI_INT_CARD_REMOVE);
2315 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2316 SDHCI_INT_CARD_INSERT);
2317
2318 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2319 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2320 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2321 tasklet_schedule(&host->card_tasklet);
2322 }
2323
2324 if (intmask & SDHCI_INT_CMD_MASK) {
2325 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2326 SDHCI_INT_STATUS);
2327 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2328 }
2329
2330 if (intmask & SDHCI_INT_DATA_MASK) {
2331 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2332 SDHCI_INT_STATUS);
2333 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2334 }
2335
2336 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2337
2338 intmask &= ~SDHCI_INT_ERROR;
2339
2340 if (intmask & SDHCI_INT_BUS_POWER) {
2341 pr_err("%s: Card is consuming too much power!\n",
2342 mmc_hostname(host->mmc));
2343 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2344 }
2345
2346 intmask &= ~SDHCI_INT_BUS_POWER;
2347
2348 if (intmask & SDHCI_INT_CARD_INT)
2349 cardint = 1;
2350
2351 intmask &= ~SDHCI_INT_CARD_INT;
2352
2353 if (intmask) {
2354 unexpected |= intmask;
2355 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2356 }
2357
2358 result = IRQ_HANDLED;
2359
2360 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2361 if (intmask && --max_loops)
2362 goto again;
2363out:
2364 spin_unlock(&host->lock);
2365
2366 if (unexpected) {
2367 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2368 mmc_hostname(host->mmc), unexpected);
2369 sdhci_dumpregs(host);
2370 }
2371 /*
2372 * We have to delay this as it calls back into the driver.
2373 */
2374 if (cardint)
2375 mmc_signal_sdio_irq(host->mmc);
2376
2377 return result;
2378}
2379
2380/*****************************************************************************\
2381 * *
2382 * Suspend/resume *
2383 * *
2384\*****************************************************************************/
2385
2386#ifdef CONFIG_PM
2387
2388int sdhci_suspend_host(struct sdhci_host *host)
2389{
2390 int ret;
2391 bool has_tuning_timer;
2392
2393 if (host->ops->platform_suspend)
2394 host->ops->platform_suspend(host);
2395
2396 sdhci_disable_card_detection(host);
2397
2398 /* Disable tuning since we are suspending */
2399 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2400 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2401 if (has_tuning_timer) {
2402 del_timer_sync(&host->tuning_timer);
2403 host->flags &= ~SDHCI_NEEDS_RETUNING;
2404 }
2405
2406 ret = mmc_suspend_host(host->mmc);
2407 if (ret) {
2408 if (has_tuning_timer) {
2409 host->flags |= SDHCI_NEEDS_RETUNING;
2410 mod_timer(&host->tuning_timer, jiffies +
2411 host->tuning_count * HZ);
2412 }
2413
2414 sdhci_enable_card_detection(host);
2415
2416 return ret;
2417 }
2418
2419 free_irq(host->irq, host);
2420
2421 return ret;
2422}
2423
2424EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2425
2426int sdhci_resume_host(struct sdhci_host *host)
2427{
2428 int ret;
2429
2430 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2431 if (host->ops->enable_dma)
2432 host->ops->enable_dma(host);
2433 }
2434
2435 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2436 mmc_hostname(host->mmc), host);
2437 if (ret)
2438 return ret;
2439
2440 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2441 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2442 /* Card keeps power but host controller does not */
2443 sdhci_init(host, 0);
2444 host->pwr = 0;
2445 host->clock = 0;
2446 sdhci_do_set_ios(host, &host->mmc->ios);
2447 } else {
2448 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2449 mmiowb();
2450 }
2451
2452 ret = mmc_resume_host(host->mmc);
2453 sdhci_enable_card_detection(host);
2454
2455 if (host->ops->platform_resume)
2456 host->ops->platform_resume(host);
2457
2458 /* Set the re-tuning expiration flag */
2459 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2460 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2461 host->flags |= SDHCI_NEEDS_RETUNING;
2462
2463 return ret;
2464}
2465
2466EXPORT_SYMBOL_GPL(sdhci_resume_host);
2467
2468void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2469{
2470 u8 val;
2471 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2472 val |= SDHCI_WAKE_ON_INT;
2473 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2474}
2475
2476EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2477
2478#endif /* CONFIG_PM */
2479
2480#ifdef CONFIG_PM_RUNTIME
2481
2482static int sdhci_runtime_pm_get(struct sdhci_host *host)
2483{
2484 return pm_runtime_get_sync(host->mmc->parent);
2485}
2486
2487static int sdhci_runtime_pm_put(struct sdhci_host *host)
2488{
2489 pm_runtime_mark_last_busy(host->mmc->parent);
2490 return pm_runtime_put_autosuspend(host->mmc->parent);
2491}
2492
2493int sdhci_runtime_suspend_host(struct sdhci_host *host)
2494{
2495 unsigned long flags;
2496 int ret = 0;
2497
2498 /* Disable tuning since we are suspending */
2499 if (host->version >= SDHCI_SPEC_300 &&
2500 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2501 del_timer_sync(&host->tuning_timer);
2502 host->flags &= ~SDHCI_NEEDS_RETUNING;
2503 }
2504
2505 spin_lock_irqsave(&host->lock, flags);
2506 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2507 spin_unlock_irqrestore(&host->lock, flags);
2508
2509 synchronize_irq(host->irq);
2510
2511 spin_lock_irqsave(&host->lock, flags);
2512 host->runtime_suspended = true;
2513 spin_unlock_irqrestore(&host->lock, flags);
2514
2515 return ret;
2516}
2517EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2518
2519int sdhci_runtime_resume_host(struct sdhci_host *host)
2520{
2521 unsigned long flags;
2522 int ret = 0, host_flags = host->flags;
2523
2524 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2525 if (host->ops->enable_dma)
2526 host->ops->enable_dma(host);
2527 }
2528
2529 sdhci_init(host, 0);
2530
2531 /* Force clock and power re-program */
2532 host->pwr = 0;
2533 host->clock = 0;
2534 sdhci_do_set_ios(host, &host->mmc->ios);
2535
2536 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2537 if (host_flags & SDHCI_PV_ENABLED)
2538 sdhci_do_enable_preset_value(host, true);
2539
2540 /* Set the re-tuning expiration flag */
2541 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2542 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2543 host->flags |= SDHCI_NEEDS_RETUNING;
2544
2545 spin_lock_irqsave(&host->lock, flags);
2546
2547 host->runtime_suspended = false;
2548
2549 /* Enable SDIO IRQ */
2550 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2551 sdhci_enable_sdio_irq_nolock(host, true);
2552
2553 /* Enable Card Detection */
2554 sdhci_enable_card_detection(host);
2555
2556 spin_unlock_irqrestore(&host->lock, flags);
2557
2558 return ret;
2559}
2560EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2561
2562#endif
2563
2564/*****************************************************************************\
2565 * *
2566 * Device allocation/registration *
2567 * *
2568\*****************************************************************************/
2569
2570struct sdhci_host *sdhci_alloc_host(struct device *dev,
2571 size_t priv_size)
2572{
2573 struct mmc_host *mmc;
2574 struct sdhci_host *host;
2575
2576 WARN_ON(dev == NULL);
2577
2578 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2579 if (!mmc)
2580 return ERR_PTR(-ENOMEM);
2581
2582 host = mmc_priv(mmc);
2583 host->mmc = mmc;
2584
2585 return host;
2586}
2587
2588EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2589
2590int sdhci_add_host(struct sdhci_host *host)
2591{
2592 struct mmc_host *mmc;
2593 u32 caps[2];
2594 u32 max_current_caps;
2595 unsigned int ocr_avail;
2596 int ret;
2597
2598 WARN_ON(host == NULL);
2599 if (host == NULL)
2600 return -EINVAL;
2601
2602 mmc = host->mmc;
2603
2604 if (debug_quirks)
2605 host->quirks = debug_quirks;
2606 if (debug_quirks2)
2607 host->quirks2 = debug_quirks2;
2608
2609 sdhci_reset(host, SDHCI_RESET_ALL);
2610
2611 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2612 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2613 >> SDHCI_SPEC_VER_SHIFT;
2614 if (host->version > SDHCI_SPEC_300) {
2615 pr_err("%s: Unknown controller version (%d). "
2616 "You may experience problems.\n", mmc_hostname(mmc),
2617 host->version);
2618 }
2619
2620 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2621 sdhci_readl(host, SDHCI_CAPABILITIES);
2622
2623 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2624 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2625
2626 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2627 host->flags |= SDHCI_USE_SDMA;
2628 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2629 DBG("Controller doesn't have SDMA capability\n");
2630 else
2631 host->flags |= SDHCI_USE_SDMA;
2632
2633 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2634 (host->flags & SDHCI_USE_SDMA)) {
2635 DBG("Disabling DMA as it is marked broken\n");
2636 host->flags &= ~SDHCI_USE_SDMA;
2637 }
2638
2639 if ((host->version >= SDHCI_SPEC_200) &&
2640 (caps[0] & SDHCI_CAN_DO_ADMA2))
2641 host->flags |= SDHCI_USE_ADMA;
2642
2643 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2644 (host->flags & SDHCI_USE_ADMA)) {
2645 DBG("Disabling ADMA as it is marked broken\n");
2646 host->flags &= ~SDHCI_USE_ADMA;
2647 }
2648
2649 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2650 if (host->ops->enable_dma) {
2651 if (host->ops->enable_dma(host)) {
2652 pr_warning("%s: No suitable DMA "
2653 "available. Falling back to PIO.\n",
2654 mmc_hostname(mmc));
2655 host->flags &=
2656 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2657 }
2658 }
2659 }
2660
2661 if (host->flags & SDHCI_USE_ADMA) {
2662 /*
2663 * We need to allocate descriptors for all sg entries
2664 * (128) and potentially one alignment transfer for
2665 * each of those entries.
2666 */
2667 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2668 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2669 if (!host->adma_desc || !host->align_buffer) {
2670 kfree(host->adma_desc);
2671 kfree(host->align_buffer);
2672 pr_warning("%s: Unable to allocate ADMA "
2673 "buffers. Falling back to standard DMA.\n",
2674 mmc_hostname(mmc));
2675 host->flags &= ~SDHCI_USE_ADMA;
2676 }
2677 }
2678
2679 /*
2680 * If we use DMA, then it's up to the caller to set the DMA
2681 * mask, but PIO does not need the hw shim so we set a new
2682 * mask here in that case.
2683 */
2684 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2685 host->dma_mask = DMA_BIT_MASK(64);
2686 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2687 }
2688
2689 if (host->version >= SDHCI_SPEC_300)
2690 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2691 >> SDHCI_CLOCK_BASE_SHIFT;
2692 else
2693 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2694 >> SDHCI_CLOCK_BASE_SHIFT;
2695
2696 host->max_clk *= 1000000;
2697 if (host->max_clk == 0 || host->quirks &
2698 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2699 if (!host->ops->get_max_clock) {
2700 pr_err("%s: Hardware doesn't specify base clock "
2701 "frequency.\n", mmc_hostname(mmc));
2702 return -ENODEV;
2703 }
2704 host->max_clk = host->ops->get_max_clock(host);
2705 }
2706
2707 /*
2708 * In case of Host Controller v3.00, find out whether clock
2709 * multiplier is supported.
2710 */
2711 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2712 SDHCI_CLOCK_MUL_SHIFT;
2713
2714 /*
2715 * In case the value in Clock Multiplier is 0, then programmable
2716 * clock mode is not supported, otherwise the actual clock
2717 * multiplier is one more than the value of Clock Multiplier
2718 * in the Capabilities Register.
2719 */
2720 if (host->clk_mul)
2721 host->clk_mul += 1;
2722
2723 /*
2724 * Set host parameters.
2725 */
2726 mmc->ops = &sdhci_ops;
2727 mmc->f_max = host->max_clk;
2728 if (host->ops->get_min_clock)
2729 mmc->f_min = host->ops->get_min_clock(host);
2730 else if (host->version >= SDHCI_SPEC_300) {
2731 if (host->clk_mul) {
2732 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2733 mmc->f_max = host->max_clk * host->clk_mul;
2734 } else
2735 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2736 } else
2737 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2738
2739 host->timeout_clk =
2740 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2741 if (host->timeout_clk == 0) {
2742 if (host->ops->get_timeout_clock) {
2743 host->timeout_clk = host->ops->get_timeout_clock(host);
2744 } else if (!(host->quirks &
2745 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2746 pr_err("%s: Hardware doesn't specify timeout clock "
2747 "frequency.\n", mmc_hostname(mmc));
2748 return -ENODEV;
2749 }
2750 }
2751 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2752 host->timeout_clk *= 1000;
2753
2754 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2755 host->timeout_clk = mmc->f_max / 1000;
2756
2757 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2758
2759 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2760
2761 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2762 host->flags |= SDHCI_AUTO_CMD12;
2763
2764 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2765 if ((host->version >= SDHCI_SPEC_300) &&
2766 ((host->flags & SDHCI_USE_ADMA) ||
2767 !(host->flags & SDHCI_USE_SDMA))) {
2768 host->flags |= SDHCI_AUTO_CMD23;
2769 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2770 } else {
2771 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2772 }
2773
2774 /*
2775 * A controller may support 8-bit width, but the board itself
2776 * might not have the pins brought out. Boards that support
2777 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2778 * their platform code before calling sdhci_add_host(), and we
2779 * won't assume 8-bit width for hosts without that CAP.
2780 */
2781 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2782 mmc->caps |= MMC_CAP_4_BIT_DATA;
2783
2784 if (caps[0] & SDHCI_CAN_DO_HISPD)
2785 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2786
2787 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2788 mmc_card_is_removable(mmc))
2789 mmc->caps |= MMC_CAP_NEEDS_POLL;
2790
2791 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2792 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2793 SDHCI_SUPPORT_DDR50))
2794 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2795
2796 /* SDR104 supports also implies SDR50 support */
2797 if (caps[1] & SDHCI_SUPPORT_SDR104)
2798 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2799 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2800 mmc->caps |= MMC_CAP_UHS_SDR50;
2801
2802 if (caps[1] & SDHCI_SUPPORT_DDR50)
2803 mmc->caps |= MMC_CAP_UHS_DDR50;
2804
2805 /* Does the host need tuning for SDR50? */
2806 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2807 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2808
2809 /* Does the host need tuning for HS200? */
2810 if (mmc->caps2 & MMC_CAP2_HS200)
2811 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2812
2813 /* Driver Type(s) (A, C, D) supported by the host */
2814 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2815 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2816 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2817 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2818 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2819 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2820
2821 /*
2822 * If Power Off Notify capability is enabled by the host,
2823 * set notify to short power off notify timeout value.
2824 */
2825 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2826 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2827 else
2828 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2829
2830 /* Initial value for re-tuning timer count */
2831 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2832 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2833
2834 /*
2835 * In case Re-tuning Timer is not disabled, the actual value of
2836 * re-tuning timer will be 2 ^ (n - 1).
2837 */
2838 if (host->tuning_count)
2839 host->tuning_count = 1 << (host->tuning_count - 1);
2840
2841 /* Re-tuning mode supported by the Host Controller */
2842 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2843 SDHCI_RETUNING_MODE_SHIFT;
2844
2845 ocr_avail = 0;
2846 /*
2847 * According to SD Host Controller spec v3.00, if the Host System
2848 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2849 * the value is meaningful only if Voltage Support in the Capabilities
2850 * register is set. The actual current value is 4 times the register
2851 * value.
2852 */
2853 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2854
2855 if (caps[0] & SDHCI_CAN_VDD_330) {
2856 int max_current_330;
2857
2858 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2859
2860 max_current_330 = ((max_current_caps &
2861 SDHCI_MAX_CURRENT_330_MASK) >>
2862 SDHCI_MAX_CURRENT_330_SHIFT) *
2863 SDHCI_MAX_CURRENT_MULTIPLIER;
2864
2865 if (max_current_330 > 150)
2866 mmc->caps |= MMC_CAP_SET_XPC_330;
2867 }
2868 if (caps[0] & SDHCI_CAN_VDD_300) {
2869 int max_current_300;
2870
2871 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2872
2873 max_current_300 = ((max_current_caps &
2874 SDHCI_MAX_CURRENT_300_MASK) >>
2875 SDHCI_MAX_CURRENT_300_SHIFT) *
2876 SDHCI_MAX_CURRENT_MULTIPLIER;
2877
2878 if (max_current_300 > 150)
2879 mmc->caps |= MMC_CAP_SET_XPC_300;
2880 }
2881 if (caps[0] & SDHCI_CAN_VDD_180) {
2882 int max_current_180;
2883
2884 ocr_avail |= MMC_VDD_165_195;
2885
2886 max_current_180 = ((max_current_caps &
2887 SDHCI_MAX_CURRENT_180_MASK) >>
2888 SDHCI_MAX_CURRENT_180_SHIFT) *
2889 SDHCI_MAX_CURRENT_MULTIPLIER;
2890
2891 if (max_current_180 > 150)
2892 mmc->caps |= MMC_CAP_SET_XPC_180;
2893
2894 /* Maximum current capabilities of the host at 1.8V */
2895 if (max_current_180 >= 800)
2896 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2897 else if (max_current_180 >= 600)
2898 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2899 else if (max_current_180 >= 400)
2900 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2901 else
2902 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2903 }
2904
2905 mmc->ocr_avail = ocr_avail;
2906 mmc->ocr_avail_sdio = ocr_avail;
2907 if (host->ocr_avail_sdio)
2908 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2909 mmc->ocr_avail_sd = ocr_avail;
2910 if (host->ocr_avail_sd)
2911 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2912 else /* normal SD controllers don't support 1.8V */
2913 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2914 mmc->ocr_avail_mmc = ocr_avail;
2915 if (host->ocr_avail_mmc)
2916 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2917
2918 if (mmc->ocr_avail == 0) {
2919 pr_err("%s: Hardware doesn't report any "
2920 "support voltages.\n", mmc_hostname(mmc));
2921 return -ENODEV;
2922 }
2923
2924 spin_lock_init(&host->lock);
2925
2926 /*
2927 * Maximum number of segments. Depends on if the hardware
2928 * can do scatter/gather or not.
2929 */
2930 if (host->flags & SDHCI_USE_ADMA)
2931 mmc->max_segs = 128;
2932 else if (host->flags & SDHCI_USE_SDMA)
2933 mmc->max_segs = 1;
2934 else /* PIO */
2935 mmc->max_segs = 128;
2936
2937 /*
2938 * Maximum number of sectors in one transfer. Limited by DMA boundary
2939 * size (512KiB).
2940 */
2941 mmc->max_req_size = 524288;
2942
2943 /*
2944 * Maximum segment size. Could be one segment with the maximum number
2945 * of bytes. When doing hardware scatter/gather, each entry cannot
2946 * be larger than 64 KiB though.
2947 */
2948 if (host->flags & SDHCI_USE_ADMA) {
2949 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2950 mmc->max_seg_size = 65535;
2951 else
2952 mmc->max_seg_size = 65536;
2953 } else {
2954 mmc->max_seg_size = mmc->max_req_size;
2955 }
2956
2957 /*
2958 * Maximum block size. This varies from controller to controller and
2959 * is specified in the capabilities register.
2960 */
2961 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2962 mmc->max_blk_size = 2;
2963 } else {
2964 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2965 SDHCI_MAX_BLOCK_SHIFT;
2966 if (mmc->max_blk_size >= 3) {
2967 pr_warning("%s: Invalid maximum block size, "
2968 "assuming 512 bytes\n", mmc_hostname(mmc));
2969 mmc->max_blk_size = 0;
2970 }
2971 }
2972
2973 mmc->max_blk_size = 512 << mmc->max_blk_size;
2974
2975 /*
2976 * Maximum block count.
2977 */
2978 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2979
2980 /*
2981 * Init tasklets.
2982 */
2983 tasklet_init(&host->card_tasklet,
2984 sdhci_tasklet_card, (unsigned long)host);
2985 tasklet_init(&host->finish_tasklet,
2986 sdhci_tasklet_finish, (unsigned long)host);
2987
2988 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2989
2990 if (host->version >= SDHCI_SPEC_300) {
2991 init_waitqueue_head(&host->buf_ready_int);
2992
2993 /* Initialize re-tuning timer */
2994 init_timer(&host->tuning_timer);
2995 host->tuning_timer.data = (unsigned long)host;
2996 host->tuning_timer.function = sdhci_tuning_timer;
2997 }
2998
2999 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3000 mmc_hostname(mmc), host);
3001 if (ret)
3002 goto untasklet;
3003
3004 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3005 if (IS_ERR(host->vmmc)) {
3006 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3007 host->vmmc = NULL;
3008 }
3009
3010 sdhci_init(host, 0);
3011
3012#ifdef CONFIG_MMC_DEBUG
3013 sdhci_dumpregs(host);
3014#endif
3015
3016#ifdef SDHCI_USE_LEDS_CLASS
3017 snprintf(host->led_name, sizeof(host->led_name),
3018 "%s::", mmc_hostname(mmc));
3019 host->led.name = host->led_name;
3020 host->led.brightness = LED_OFF;
3021 host->led.default_trigger = mmc_hostname(mmc);
3022 host->led.brightness_set = sdhci_led_control;
3023
3024 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3025 if (ret)
3026 goto reset;
3027#endif
3028
3029 mmiowb();
3030
3031 mmc_add_host(mmc);
3032
3033 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3034 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3035 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3036 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3037
3038 sdhci_enable_card_detection(host);
3039
3040 return 0;
3041
3042#ifdef SDHCI_USE_LEDS_CLASS
3043reset:
3044 sdhci_reset(host, SDHCI_RESET_ALL);
3045 free_irq(host->irq, host);
3046#endif
3047untasklet:
3048 tasklet_kill(&host->card_tasklet);
3049 tasklet_kill(&host->finish_tasklet);
3050
3051 return ret;
3052}
3053
3054EXPORT_SYMBOL_GPL(sdhci_add_host);
3055
3056void sdhci_remove_host(struct sdhci_host *host, int dead)
3057{
3058 unsigned long flags;
3059
3060 if (dead) {
3061 spin_lock_irqsave(&host->lock, flags);
3062
3063 host->flags |= SDHCI_DEVICE_DEAD;
3064
3065 if (host->mrq) {
3066 pr_err("%s: Controller removed during "
3067 " transfer!\n", mmc_hostname(host->mmc));
3068
3069 host->mrq->cmd->error = -ENOMEDIUM;
3070 tasklet_schedule(&host->finish_tasklet);
3071 }
3072
3073 spin_unlock_irqrestore(&host->lock, flags);
3074 }
3075
3076 sdhci_disable_card_detection(host);
3077
3078 mmc_remove_host(host->mmc);
3079
3080#ifdef SDHCI_USE_LEDS_CLASS
3081 led_classdev_unregister(&host->led);
3082#endif
3083
3084 if (!dead)
3085 sdhci_reset(host, SDHCI_RESET_ALL);
3086
3087 free_irq(host->irq, host);
3088
3089 del_timer_sync(&host->timer);
3090 if (host->version >= SDHCI_SPEC_300)
3091 del_timer_sync(&host->tuning_timer);
3092
3093 tasklet_kill(&host->card_tasklet);
3094 tasklet_kill(&host->finish_tasklet);
3095
3096 if (host->vmmc)
3097 regulator_put(host->vmmc);
3098
3099 kfree(host->adma_desc);
3100 kfree(host->align_buffer);
3101
3102 host->adma_desc = NULL;
3103 host->align_buffer = NULL;
3104}
3105
3106EXPORT_SYMBOL_GPL(sdhci_remove_host);
3107
3108void sdhci_free_host(struct sdhci_host *host)
3109{
3110 mmc_free_host(host->mmc);
3111}
3112
3113EXPORT_SYMBOL_GPL(sdhci_free_host);
3114
3115/*****************************************************************************\
3116 * *
3117 * Driver init/exit *
3118 * *
3119\*****************************************************************************/
3120
3121static int __init sdhci_drv_init(void)
3122{
3123 pr_info(DRIVER_NAME
3124 ": Secure Digital Host Controller Interface driver\n");
3125 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3126
3127 return 0;
3128}
3129
3130static void __exit sdhci_drv_exit(void)
3131{
3132}
3133
3134module_init(sdhci_drv_init);
3135module_exit(sdhci_drv_exit);
3136
3137module_param(debug_quirks, uint, 0444);
3138module_param(debug_quirks2, uint, 0444);
3139
3140MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3141MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3142MODULE_LICENSE("GPL");
3143
3144MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3145MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/io.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/scatterlist.h>
22#include <linux/regulator/consumer.h>
23
24#include <linux/leds.h>
25
26#include <linux/mmc/mmc.h>
27#include <linux/mmc/host.h>
28
29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
32
33#define DBG(f, x...) \
34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
35
36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
41#define MAX_TUNING_LOOP 40
42
43static unsigned int debug_quirks = 0;
44
45static void sdhci_finish_data(struct sdhci_host *);
46
47static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
48static void sdhci_finish_command(struct sdhci_host *);
49static int sdhci_execute_tuning(struct mmc_host *mmc);
50static void sdhci_tuning_timer(unsigned long data);
51
52static void sdhci_dumpregs(struct sdhci_host *host)
53{
54 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
55 mmc_hostname(host->mmc));
56
57 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
60 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
63 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
66 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
69 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
72 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
75 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
78 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
81 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
82 sdhci_readw(host, SDHCI_ACMD12_ERR),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
84 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
85 sdhci_readl(host, SDHCI_CAPABILITIES),
86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
89 sdhci_readl(host, SDHCI_MAX_CURRENT));
90 printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
91 sdhci_readw(host, SDHCI_HOST_CONTROL2));
92
93 if (host->flags & SDHCI_USE_ADMA)
94 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
97
98 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
99}
100
101/*****************************************************************************\
102 * *
103 * Low level functions *
104 * *
105\*****************************************************************************/
106
107static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
108{
109 u32 ier;
110
111 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
112 ier &= ~clear;
113 ier |= set;
114 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
115 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
116}
117
118static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, 0, irqs);
121}
122
123static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
124{
125 sdhci_clear_set_irqs(host, irqs, 0);
126}
127
128static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
129{
130 u32 present, irqs;
131
132 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
133 return;
134
135 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
136 SDHCI_CARD_PRESENT;
137 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
138
139 if (enable)
140 sdhci_unmask_irqs(host, irqs);
141 else
142 sdhci_mask_irqs(host, irqs);
143}
144
145static void sdhci_enable_card_detection(struct sdhci_host *host)
146{
147 sdhci_set_card_detection(host, true);
148}
149
150static void sdhci_disable_card_detection(struct sdhci_host *host)
151{
152 sdhci_set_card_detection(host, false);
153}
154
155static void sdhci_reset(struct sdhci_host *host, u8 mask)
156{
157 unsigned long timeout;
158 u32 uninitialized_var(ier);
159
160 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
161 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
162 SDHCI_CARD_PRESENT))
163 return;
164 }
165
166 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
167 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
168
169 if (host->ops->platform_reset_enter)
170 host->ops->platform_reset_enter(host, mask);
171
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
173
174 if (mask & SDHCI_RESET_ALL)
175 host->clock = 0;
176
177 /* Wait max 100 ms */
178 timeout = 100;
179
180 /* hw clears the bit when it's done */
181 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
182 if (timeout == 0) {
183 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
184 mmc_hostname(host->mmc), (int)mask);
185 sdhci_dumpregs(host);
186 return;
187 }
188 timeout--;
189 mdelay(1);
190 }
191
192 if (host->ops->platform_reset_exit)
193 host->ops->platform_reset_exit(host, mask);
194
195 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
196 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
197}
198
199static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
200
201static void sdhci_init(struct sdhci_host *host, int soft)
202{
203 if (soft)
204 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
205 else
206 sdhci_reset(host, SDHCI_RESET_ALL);
207
208 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
209 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
210 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
211 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
212 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
213
214 if (soft) {
215 /* force clock reconfiguration */
216 host->clock = 0;
217 sdhci_set_ios(host->mmc, &host->mmc->ios);
218 }
219}
220
221static void sdhci_reinit(struct sdhci_host *host)
222{
223 sdhci_init(host, 0);
224 sdhci_enable_card_detection(host);
225}
226
227static void sdhci_activate_led(struct sdhci_host *host)
228{
229 u8 ctrl;
230
231 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
232 ctrl |= SDHCI_CTRL_LED;
233 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
234}
235
236static void sdhci_deactivate_led(struct sdhci_host *host)
237{
238 u8 ctrl;
239
240 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
241 ctrl &= ~SDHCI_CTRL_LED;
242 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
243}
244
245#ifdef SDHCI_USE_LEDS_CLASS
246static void sdhci_led_control(struct led_classdev *led,
247 enum led_brightness brightness)
248{
249 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
250 unsigned long flags;
251
252 spin_lock_irqsave(&host->lock, flags);
253
254 if (brightness == LED_OFF)
255 sdhci_deactivate_led(host);
256 else
257 sdhci_activate_led(host);
258
259 spin_unlock_irqrestore(&host->lock, flags);
260}
261#endif
262
263/*****************************************************************************\
264 * *
265 * Core functions *
266 * *
267\*****************************************************************************/
268
269static void sdhci_read_block_pio(struct sdhci_host *host)
270{
271 unsigned long flags;
272 size_t blksize, len, chunk;
273 u32 uninitialized_var(scratch);
274 u8 *buf;
275
276 DBG("PIO reading\n");
277
278 blksize = host->data->blksz;
279 chunk = 0;
280
281 local_irq_save(flags);
282
283 while (blksize) {
284 if (!sg_miter_next(&host->sg_miter))
285 BUG();
286
287 len = min(host->sg_miter.length, blksize);
288
289 blksize -= len;
290 host->sg_miter.consumed = len;
291
292 buf = host->sg_miter.addr;
293
294 while (len) {
295 if (chunk == 0) {
296 scratch = sdhci_readl(host, SDHCI_BUFFER);
297 chunk = 4;
298 }
299
300 *buf = scratch & 0xFF;
301
302 buf++;
303 scratch >>= 8;
304 chunk--;
305 len--;
306 }
307 }
308
309 sg_miter_stop(&host->sg_miter);
310
311 local_irq_restore(flags);
312}
313
314static void sdhci_write_block_pio(struct sdhci_host *host)
315{
316 unsigned long flags;
317 size_t blksize, len, chunk;
318 u32 scratch;
319 u8 *buf;
320
321 DBG("PIO writing\n");
322
323 blksize = host->data->blksz;
324 chunk = 0;
325 scratch = 0;
326
327 local_irq_save(flags);
328
329 while (blksize) {
330 if (!sg_miter_next(&host->sg_miter))
331 BUG();
332
333 len = min(host->sg_miter.length, blksize);
334
335 blksize -= len;
336 host->sg_miter.consumed = len;
337
338 buf = host->sg_miter.addr;
339
340 while (len) {
341 scratch |= (u32)*buf << (chunk * 8);
342
343 buf++;
344 chunk++;
345 len--;
346
347 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
348 sdhci_writel(host, scratch, SDHCI_BUFFER);
349 chunk = 0;
350 scratch = 0;
351 }
352 }
353 }
354
355 sg_miter_stop(&host->sg_miter);
356
357 local_irq_restore(flags);
358}
359
360static void sdhci_transfer_pio(struct sdhci_host *host)
361{
362 u32 mask;
363
364 BUG_ON(!host->data);
365
366 if (host->blocks == 0)
367 return;
368
369 if (host->data->flags & MMC_DATA_READ)
370 mask = SDHCI_DATA_AVAILABLE;
371 else
372 mask = SDHCI_SPACE_AVAILABLE;
373
374 /*
375 * Some controllers (JMicron JMB38x) mess up the buffer bits
376 * for transfers < 4 bytes. As long as it is just one block,
377 * we can ignore the bits.
378 */
379 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
380 (host->data->blocks == 1))
381 mask = ~0;
382
383 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
384 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
385 udelay(100);
386
387 if (host->data->flags & MMC_DATA_READ)
388 sdhci_read_block_pio(host);
389 else
390 sdhci_write_block_pio(host);
391
392 host->blocks--;
393 if (host->blocks == 0)
394 break;
395 }
396
397 DBG("PIO transfer complete.\n");
398}
399
400static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
401{
402 local_irq_save(*flags);
403 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
404}
405
406static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
407{
408 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
409 local_irq_restore(*flags);
410}
411
412static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
413{
414 __le32 *dataddr = (__le32 __force *)(desc + 4);
415 __le16 *cmdlen = (__le16 __force *)desc;
416
417 /* SDHCI specification says ADMA descriptors should be 4 byte
418 * aligned, so using 16 or 32bit operations should be safe. */
419
420 cmdlen[0] = cpu_to_le16(cmd);
421 cmdlen[1] = cpu_to_le16(len);
422
423 dataddr[0] = cpu_to_le32(addr);
424}
425
426static int sdhci_adma_table_pre(struct sdhci_host *host,
427 struct mmc_data *data)
428{
429 int direction;
430
431 u8 *desc;
432 u8 *align;
433 dma_addr_t addr;
434 dma_addr_t align_addr;
435 int len, offset;
436
437 struct scatterlist *sg;
438 int i;
439 char *buffer;
440 unsigned long flags;
441
442 /*
443 * The spec does not specify endianness of descriptor table.
444 * We currently guess that it is LE.
445 */
446
447 if (data->flags & MMC_DATA_READ)
448 direction = DMA_FROM_DEVICE;
449 else
450 direction = DMA_TO_DEVICE;
451
452 /*
453 * The ADMA descriptor table is mapped further down as we
454 * need to fill it with data first.
455 */
456
457 host->align_addr = dma_map_single(mmc_dev(host->mmc),
458 host->align_buffer, 128 * 4, direction);
459 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
460 goto fail;
461 BUG_ON(host->align_addr & 0x3);
462
463 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
464 data->sg, data->sg_len, direction);
465 if (host->sg_count == 0)
466 goto unmap_align;
467
468 desc = host->adma_desc;
469 align = host->align_buffer;
470
471 align_addr = host->align_addr;
472
473 for_each_sg(data->sg, sg, host->sg_count, i) {
474 addr = sg_dma_address(sg);
475 len = sg_dma_len(sg);
476
477 /*
478 * The SDHCI specification states that ADMA
479 * addresses must be 32-bit aligned. If they
480 * aren't, then we use a bounce buffer for
481 * the (up to three) bytes that screw up the
482 * alignment.
483 */
484 offset = (4 - (addr & 0x3)) & 0x3;
485 if (offset) {
486 if (data->flags & MMC_DATA_WRITE) {
487 buffer = sdhci_kmap_atomic(sg, &flags);
488 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
489 memcpy(align, buffer, offset);
490 sdhci_kunmap_atomic(buffer, &flags);
491 }
492
493 /* tran, valid */
494 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
495
496 BUG_ON(offset > 65536);
497
498 align += 4;
499 align_addr += 4;
500
501 desc += 8;
502
503 addr += offset;
504 len -= offset;
505 }
506
507 BUG_ON(len > 65536);
508
509 /* tran, valid */
510 sdhci_set_adma_desc(desc, addr, len, 0x21);
511 desc += 8;
512
513 /*
514 * If this triggers then we have a calculation bug
515 * somewhere. :/
516 */
517 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
518 }
519
520 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
521 /*
522 * Mark the last descriptor as the terminating descriptor
523 */
524 if (desc != host->adma_desc) {
525 desc -= 8;
526 desc[0] |= 0x2; /* end */
527 }
528 } else {
529 /*
530 * Add a terminating entry.
531 */
532
533 /* nop, end, valid */
534 sdhci_set_adma_desc(desc, 0, 0, 0x3);
535 }
536
537 /*
538 * Resync align buffer as we might have changed it.
539 */
540 if (data->flags & MMC_DATA_WRITE) {
541 dma_sync_single_for_device(mmc_dev(host->mmc),
542 host->align_addr, 128 * 4, direction);
543 }
544
545 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
546 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
547 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
548 goto unmap_entries;
549 BUG_ON(host->adma_addr & 0x3);
550
551 return 0;
552
553unmap_entries:
554 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
555 data->sg_len, direction);
556unmap_align:
557 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
558 128 * 4, direction);
559fail:
560 return -EINVAL;
561}
562
563static void sdhci_adma_table_post(struct sdhci_host *host,
564 struct mmc_data *data)
565{
566 int direction;
567
568 struct scatterlist *sg;
569 int i, size;
570 u8 *align;
571 char *buffer;
572 unsigned long flags;
573
574 if (data->flags & MMC_DATA_READ)
575 direction = DMA_FROM_DEVICE;
576 else
577 direction = DMA_TO_DEVICE;
578
579 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
580 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
581
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584
585 if (data->flags & MMC_DATA_READ) {
586 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588
589 align = host->align_buffer;
590
591 for_each_sg(data->sg, sg, host->sg_count, i) {
592 if (sg_dma_address(sg) & 0x3) {
593 size = 4 - (sg_dma_address(sg) & 0x3);
594
595 buffer = sdhci_kmap_atomic(sg, &flags);
596 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
597 memcpy(buffer, align, size);
598 sdhci_kunmap_atomic(buffer, &flags);
599
600 align += 4;
601 }
602 }
603 }
604
605 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
606 data->sg_len, direction);
607}
608
609static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
610{
611 u8 count;
612 struct mmc_data *data = cmd->data;
613 unsigned target_timeout, current_timeout;
614
615 /*
616 * If the host controller provides us with an incorrect timeout
617 * value, just skip the check and use 0xE. The hardware may take
618 * longer to time out, but that's much better than having a too-short
619 * timeout value.
620 */
621 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
622 return 0xE;
623
624 /* Unspecified timeout, assume max */
625 if (!data && !cmd->cmd_timeout_ms)
626 return 0xE;
627
628 /* timeout in us */
629 if (!data)
630 target_timeout = cmd->cmd_timeout_ms * 1000;
631 else {
632 target_timeout = data->timeout_ns / 1000;
633 if (host->clock)
634 target_timeout += data->timeout_clks / host->clock;
635 }
636
637 /*
638 * Figure out needed cycles.
639 * We do this in steps in order to fit inside a 32 bit int.
640 * The first step is the minimum timeout, which will have a
641 * minimum resolution of 6 bits:
642 * (1) 2^13*1000 > 2^22,
643 * (2) host->timeout_clk < 2^16
644 * =>
645 * (1) / (2) > 2^6
646 */
647 count = 0;
648 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
649 while (current_timeout < target_timeout) {
650 count++;
651 current_timeout <<= 1;
652 if (count >= 0xF)
653 break;
654 }
655
656 if (count >= 0xF) {
657 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
658 mmc_hostname(host->mmc), cmd->opcode);
659 count = 0xE;
660 }
661
662 return count;
663}
664
665static void sdhci_set_transfer_irqs(struct sdhci_host *host)
666{
667 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
668 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
669
670 if (host->flags & SDHCI_REQ_USE_DMA)
671 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
672 else
673 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
674}
675
676static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
677{
678 u8 count;
679 u8 ctrl;
680 struct mmc_data *data = cmd->data;
681 int ret;
682
683 WARN_ON(host->data);
684
685 if (data || (cmd->flags & MMC_RSP_BUSY)) {
686 count = sdhci_calc_timeout(host, cmd);
687 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
688 }
689
690 if (!data)
691 return;
692
693 /* Sanity checks */
694 BUG_ON(data->blksz * data->blocks > 524288);
695 BUG_ON(data->blksz > host->mmc->max_blk_size);
696 BUG_ON(data->blocks > 65535);
697
698 host->data = data;
699 host->data_early = 0;
700 host->data->bytes_xfered = 0;
701
702 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
703 host->flags |= SDHCI_REQ_USE_DMA;
704
705 /*
706 * FIXME: This doesn't account for merging when mapping the
707 * scatterlist.
708 */
709 if (host->flags & SDHCI_REQ_USE_DMA) {
710 int broken, i;
711 struct scatterlist *sg;
712
713 broken = 0;
714 if (host->flags & SDHCI_USE_ADMA) {
715 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
716 broken = 1;
717 } else {
718 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
719 broken = 1;
720 }
721
722 if (unlikely(broken)) {
723 for_each_sg(data->sg, sg, data->sg_len, i) {
724 if (sg->length & 0x3) {
725 DBG("Reverting to PIO because of "
726 "transfer size (%d)\n",
727 sg->length);
728 host->flags &= ~SDHCI_REQ_USE_DMA;
729 break;
730 }
731 }
732 }
733 }
734
735 /*
736 * The assumption here being that alignment is the same after
737 * translation to device address space.
738 */
739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 int broken, i;
741 struct scatterlist *sg;
742
743 broken = 0;
744 if (host->flags & SDHCI_USE_ADMA) {
745 /*
746 * As we use 3 byte chunks to work around
747 * alignment problems, we need to check this
748 * quirk.
749 */
750 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
751 broken = 1;
752 } else {
753 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
754 broken = 1;
755 }
756
757 if (unlikely(broken)) {
758 for_each_sg(data->sg, sg, data->sg_len, i) {
759 if (sg->offset & 0x3) {
760 DBG("Reverting to PIO because of "
761 "bad alignment\n");
762 host->flags &= ~SDHCI_REQ_USE_DMA;
763 break;
764 }
765 }
766 }
767 }
768
769 if (host->flags & SDHCI_REQ_USE_DMA) {
770 if (host->flags & SDHCI_USE_ADMA) {
771 ret = sdhci_adma_table_pre(host, data);
772 if (ret) {
773 /*
774 * This only happens when someone fed
775 * us an invalid request.
776 */
777 WARN_ON(1);
778 host->flags &= ~SDHCI_REQ_USE_DMA;
779 } else {
780 sdhci_writel(host, host->adma_addr,
781 SDHCI_ADMA_ADDRESS);
782 }
783 } else {
784 int sg_cnt;
785
786 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
787 data->sg, data->sg_len,
788 (data->flags & MMC_DATA_READ) ?
789 DMA_FROM_DEVICE :
790 DMA_TO_DEVICE);
791 if (sg_cnt == 0) {
792 /*
793 * This only happens when someone fed
794 * us an invalid request.
795 */
796 WARN_ON(1);
797 host->flags &= ~SDHCI_REQ_USE_DMA;
798 } else {
799 WARN_ON(sg_cnt != 1);
800 sdhci_writel(host, sg_dma_address(data->sg),
801 SDHCI_DMA_ADDRESS);
802 }
803 }
804 }
805
806 /*
807 * Always adjust the DMA selection as some controllers
808 * (e.g. JMicron) can't do PIO properly when the selection
809 * is ADMA.
810 */
811 if (host->version >= SDHCI_SPEC_200) {
812 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
813 ctrl &= ~SDHCI_CTRL_DMA_MASK;
814 if ((host->flags & SDHCI_REQ_USE_DMA) &&
815 (host->flags & SDHCI_USE_ADMA))
816 ctrl |= SDHCI_CTRL_ADMA32;
817 else
818 ctrl |= SDHCI_CTRL_SDMA;
819 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
820 }
821
822 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
823 int flags;
824
825 flags = SG_MITER_ATOMIC;
826 if (host->data->flags & MMC_DATA_READ)
827 flags |= SG_MITER_TO_SG;
828 else
829 flags |= SG_MITER_FROM_SG;
830 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
831 host->blocks = data->blocks;
832 }
833
834 sdhci_set_transfer_irqs(host);
835
836 /* Set the DMA boundary value and block size */
837 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
838 data->blksz), SDHCI_BLOCK_SIZE);
839 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
840}
841
842static void sdhci_set_transfer_mode(struct sdhci_host *host,
843 struct mmc_command *cmd)
844{
845 u16 mode;
846 struct mmc_data *data = cmd->data;
847
848 if (data == NULL)
849 return;
850
851 WARN_ON(!host->data);
852
853 mode = SDHCI_TRNS_BLK_CNT_EN;
854 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
855 mode |= SDHCI_TRNS_MULTI;
856 /*
857 * If we are sending CMD23, CMD12 never gets sent
858 * on successful completion (so no Auto-CMD12).
859 */
860 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
861 mode |= SDHCI_TRNS_AUTO_CMD12;
862 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
863 mode |= SDHCI_TRNS_AUTO_CMD23;
864 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
865 }
866 }
867
868 if (data->flags & MMC_DATA_READ)
869 mode |= SDHCI_TRNS_READ;
870 if (host->flags & SDHCI_REQ_USE_DMA)
871 mode |= SDHCI_TRNS_DMA;
872
873 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
874}
875
876static void sdhci_finish_data(struct sdhci_host *host)
877{
878 struct mmc_data *data;
879
880 BUG_ON(!host->data);
881
882 data = host->data;
883 host->data = NULL;
884
885 if (host->flags & SDHCI_REQ_USE_DMA) {
886 if (host->flags & SDHCI_USE_ADMA)
887 sdhci_adma_table_post(host, data);
888 else {
889 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
890 data->sg_len, (data->flags & MMC_DATA_READ) ?
891 DMA_FROM_DEVICE : DMA_TO_DEVICE);
892 }
893 }
894
895 /*
896 * The specification states that the block count register must
897 * be updated, but it does not specify at what point in the
898 * data flow. That makes the register entirely useless to read
899 * back so we have to assume that nothing made it to the card
900 * in the event of an error.
901 */
902 if (data->error)
903 data->bytes_xfered = 0;
904 else
905 data->bytes_xfered = data->blksz * data->blocks;
906
907 /*
908 * Need to send CMD12 if -
909 * a) open-ended multiblock transfer (no CMD23)
910 * b) error in multiblock transfer
911 */
912 if (data->stop &&
913 (data->error ||
914 !host->mrq->sbc)) {
915
916 /*
917 * The controller needs a reset of internal state machines
918 * upon error conditions.
919 */
920 if (data->error) {
921 sdhci_reset(host, SDHCI_RESET_CMD);
922 sdhci_reset(host, SDHCI_RESET_DATA);
923 }
924
925 sdhci_send_command(host, data->stop);
926 } else
927 tasklet_schedule(&host->finish_tasklet);
928}
929
930static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
931{
932 int flags;
933 u32 mask;
934 unsigned long timeout;
935
936 WARN_ON(host->cmd);
937
938 /* Wait max 10 ms */
939 timeout = 10;
940
941 mask = SDHCI_CMD_INHIBIT;
942 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
943 mask |= SDHCI_DATA_INHIBIT;
944
945 /* We shouldn't wait for data inihibit for stop commands, even
946 though they might use busy signaling */
947 if (host->mrq->data && (cmd == host->mrq->data->stop))
948 mask &= ~SDHCI_DATA_INHIBIT;
949
950 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
951 if (timeout == 0) {
952 printk(KERN_ERR "%s: Controller never released "
953 "inhibit bit(s).\n", mmc_hostname(host->mmc));
954 sdhci_dumpregs(host);
955 cmd->error = -EIO;
956 tasklet_schedule(&host->finish_tasklet);
957 return;
958 }
959 timeout--;
960 mdelay(1);
961 }
962
963 mod_timer(&host->timer, jiffies + 10 * HZ);
964
965 host->cmd = cmd;
966
967 sdhci_prepare_data(host, cmd);
968
969 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
970
971 sdhci_set_transfer_mode(host, cmd);
972
973 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
974 printk(KERN_ERR "%s: Unsupported response type!\n",
975 mmc_hostname(host->mmc));
976 cmd->error = -EINVAL;
977 tasklet_schedule(&host->finish_tasklet);
978 return;
979 }
980
981 if (!(cmd->flags & MMC_RSP_PRESENT))
982 flags = SDHCI_CMD_RESP_NONE;
983 else if (cmd->flags & MMC_RSP_136)
984 flags = SDHCI_CMD_RESP_LONG;
985 else if (cmd->flags & MMC_RSP_BUSY)
986 flags = SDHCI_CMD_RESP_SHORT_BUSY;
987 else
988 flags = SDHCI_CMD_RESP_SHORT;
989
990 if (cmd->flags & MMC_RSP_CRC)
991 flags |= SDHCI_CMD_CRC;
992 if (cmd->flags & MMC_RSP_OPCODE)
993 flags |= SDHCI_CMD_INDEX;
994
995 /* CMD19 is special in that the Data Present Select should be set */
996 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
997 flags |= SDHCI_CMD_DATA;
998
999 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1000}
1001
1002static void sdhci_finish_command(struct sdhci_host *host)
1003{
1004 int i;
1005
1006 BUG_ON(host->cmd == NULL);
1007
1008 if (host->cmd->flags & MMC_RSP_PRESENT) {
1009 if (host->cmd->flags & MMC_RSP_136) {
1010 /* CRC is stripped so we need to do some shifting. */
1011 for (i = 0;i < 4;i++) {
1012 host->cmd->resp[i] = sdhci_readl(host,
1013 SDHCI_RESPONSE + (3-i)*4) << 8;
1014 if (i != 3)
1015 host->cmd->resp[i] |=
1016 sdhci_readb(host,
1017 SDHCI_RESPONSE + (3-i)*4-1);
1018 }
1019 } else {
1020 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1021 }
1022 }
1023
1024 host->cmd->error = 0;
1025
1026 /* Finished CMD23, now send actual command. */
1027 if (host->cmd == host->mrq->sbc) {
1028 host->cmd = NULL;
1029 sdhci_send_command(host, host->mrq->cmd);
1030 } else {
1031
1032 /* Processed actual command. */
1033 if (host->data && host->data_early)
1034 sdhci_finish_data(host);
1035
1036 if (!host->cmd->data)
1037 tasklet_schedule(&host->finish_tasklet);
1038
1039 host->cmd = NULL;
1040 }
1041}
1042
1043static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1044{
1045 int div = 0; /* Initialized for compiler warning */
1046 u16 clk = 0;
1047 unsigned long timeout;
1048
1049 if (clock == host->clock)
1050 return;
1051
1052 if (host->ops->set_clock) {
1053 host->ops->set_clock(host, clock);
1054 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1055 return;
1056 }
1057
1058 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1059
1060 if (clock == 0)
1061 goto out;
1062
1063 if (host->version >= SDHCI_SPEC_300) {
1064 /*
1065 * Check if the Host Controller supports Programmable Clock
1066 * Mode.
1067 */
1068 if (host->clk_mul) {
1069 u16 ctrl;
1070
1071 /*
1072 * We need to figure out whether the Host Driver needs
1073 * to select Programmable Clock Mode, or the value can
1074 * be set automatically by the Host Controller based on
1075 * the Preset Value registers.
1076 */
1077 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1078 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1079 for (div = 1; div <= 1024; div++) {
1080 if (((host->max_clk * host->clk_mul) /
1081 div) <= clock)
1082 break;
1083 }
1084 /*
1085 * Set Programmable Clock Mode in the Clock
1086 * Control register.
1087 */
1088 clk = SDHCI_PROG_CLOCK_MODE;
1089 div--;
1090 }
1091 } else {
1092 /* Version 3.00 divisors must be a multiple of 2. */
1093 if (host->max_clk <= clock)
1094 div = 1;
1095 else {
1096 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1097 div += 2) {
1098 if ((host->max_clk / div) <= clock)
1099 break;
1100 }
1101 }
1102 div >>= 1;
1103 }
1104 } else {
1105 /* Version 2.00 divisors must be a power of 2. */
1106 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1107 if ((host->max_clk / div) <= clock)
1108 break;
1109 }
1110 div >>= 1;
1111 }
1112
1113 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1114 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1115 << SDHCI_DIVIDER_HI_SHIFT;
1116 clk |= SDHCI_CLOCK_INT_EN;
1117 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1118
1119 /* Wait max 20 ms */
1120 timeout = 20;
1121 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1122 & SDHCI_CLOCK_INT_STABLE)) {
1123 if (timeout == 0) {
1124 printk(KERN_ERR "%s: Internal clock never "
1125 "stabilised.\n", mmc_hostname(host->mmc));
1126 sdhci_dumpregs(host);
1127 return;
1128 }
1129 timeout--;
1130 mdelay(1);
1131 }
1132
1133 clk |= SDHCI_CLOCK_CARD_EN;
1134 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1135
1136out:
1137 host->clock = clock;
1138}
1139
1140static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1141{
1142 u8 pwr = 0;
1143
1144 if (power != (unsigned short)-1) {
1145 switch (1 << power) {
1146 case MMC_VDD_165_195:
1147 pwr = SDHCI_POWER_180;
1148 break;
1149 case MMC_VDD_29_30:
1150 case MMC_VDD_30_31:
1151 pwr = SDHCI_POWER_300;
1152 break;
1153 case MMC_VDD_32_33:
1154 case MMC_VDD_33_34:
1155 pwr = SDHCI_POWER_330;
1156 break;
1157 default:
1158 BUG();
1159 }
1160 }
1161
1162 if (host->pwr == pwr)
1163 return;
1164
1165 host->pwr = pwr;
1166
1167 if (pwr == 0) {
1168 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1169 return;
1170 }
1171
1172 /*
1173 * Spec says that we should clear the power reg before setting
1174 * a new value. Some controllers don't seem to like this though.
1175 */
1176 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1177 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1178
1179 /*
1180 * At least the Marvell CaFe chip gets confused if we set the voltage
1181 * and set turn on power at the same time, so set the voltage first.
1182 */
1183 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1184 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1185
1186 pwr |= SDHCI_POWER_ON;
1187
1188 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1189
1190 /*
1191 * Some controllers need an extra 10ms delay of 10ms before they
1192 * can apply clock after applying power
1193 */
1194 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1195 mdelay(10);
1196}
1197
1198/*****************************************************************************\
1199 * *
1200 * MMC callbacks *
1201 * *
1202\*****************************************************************************/
1203
1204static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1205{
1206 struct sdhci_host *host;
1207 bool present;
1208 unsigned long flags;
1209
1210 host = mmc_priv(mmc);
1211
1212 spin_lock_irqsave(&host->lock, flags);
1213
1214 WARN_ON(host->mrq != NULL);
1215
1216#ifndef SDHCI_USE_LEDS_CLASS
1217 sdhci_activate_led(host);
1218#endif
1219
1220 /*
1221 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1222 * requests if Auto-CMD12 is enabled.
1223 */
1224 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1225 if (mrq->stop) {
1226 mrq->data->stop = NULL;
1227 mrq->stop = NULL;
1228 }
1229 }
1230
1231 host->mrq = mrq;
1232
1233 /* If polling, assume that the card is always present. */
1234 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1235 present = true;
1236 else
1237 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1238 SDHCI_CARD_PRESENT;
1239
1240 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1241 host->mrq->cmd->error = -ENOMEDIUM;
1242 tasklet_schedule(&host->finish_tasklet);
1243 } else {
1244 u32 present_state;
1245
1246 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1247 /*
1248 * Check if the re-tuning timer has already expired and there
1249 * is no on-going data transfer. If so, we need to execute
1250 * tuning procedure before sending command.
1251 */
1252 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1253 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1254 spin_unlock_irqrestore(&host->lock, flags);
1255 sdhci_execute_tuning(mmc);
1256 spin_lock_irqsave(&host->lock, flags);
1257
1258 /* Restore original mmc_request structure */
1259 host->mrq = mrq;
1260 }
1261
1262 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1263 sdhci_send_command(host, mrq->sbc);
1264 else
1265 sdhci_send_command(host, mrq->cmd);
1266 }
1267
1268 mmiowb();
1269 spin_unlock_irqrestore(&host->lock, flags);
1270}
1271
1272static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1273{
1274 struct sdhci_host *host;
1275 unsigned long flags;
1276 u8 ctrl;
1277
1278 host = mmc_priv(mmc);
1279
1280 spin_lock_irqsave(&host->lock, flags);
1281
1282 if (host->flags & SDHCI_DEVICE_DEAD)
1283 goto out;
1284
1285 /*
1286 * Reset the chip on each power off.
1287 * Should clear out any weird states.
1288 */
1289 if (ios->power_mode == MMC_POWER_OFF) {
1290 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1291 sdhci_reinit(host);
1292 }
1293
1294 sdhci_set_clock(host, ios->clock);
1295
1296 if (ios->power_mode == MMC_POWER_OFF)
1297 sdhci_set_power(host, -1);
1298 else
1299 sdhci_set_power(host, ios->vdd);
1300
1301 if (host->ops->platform_send_init_74_clocks)
1302 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1303
1304 /*
1305 * If your platform has 8-bit width support but is not a v3 controller,
1306 * or if it requires special setup code, you should implement that in
1307 * platform_8bit_width().
1308 */
1309 if (host->ops->platform_8bit_width)
1310 host->ops->platform_8bit_width(host, ios->bus_width);
1311 else {
1312 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1313 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1314 ctrl &= ~SDHCI_CTRL_4BITBUS;
1315 if (host->version >= SDHCI_SPEC_300)
1316 ctrl |= SDHCI_CTRL_8BITBUS;
1317 } else {
1318 if (host->version >= SDHCI_SPEC_300)
1319 ctrl &= ~SDHCI_CTRL_8BITBUS;
1320 if (ios->bus_width == MMC_BUS_WIDTH_4)
1321 ctrl |= SDHCI_CTRL_4BITBUS;
1322 else
1323 ctrl &= ~SDHCI_CTRL_4BITBUS;
1324 }
1325 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1326 }
1327
1328 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1329
1330 if ((ios->timing == MMC_TIMING_SD_HS ||
1331 ios->timing == MMC_TIMING_MMC_HS)
1332 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1333 ctrl |= SDHCI_CTRL_HISPD;
1334 else
1335 ctrl &= ~SDHCI_CTRL_HISPD;
1336
1337 if (host->version >= SDHCI_SPEC_300) {
1338 u16 clk, ctrl_2;
1339 unsigned int clock;
1340
1341 /* In case of UHS-I modes, set High Speed Enable */
1342 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1343 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1344 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1345 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1346 (ios->timing == MMC_TIMING_UHS_SDR12))
1347 ctrl |= SDHCI_CTRL_HISPD;
1348
1349 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1350 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1351 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1352 /*
1353 * We only need to set Driver Strength if the
1354 * preset value enable is not set.
1355 */
1356 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1357 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1358 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1359 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1360 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1361
1362 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1363 } else {
1364 /*
1365 * According to SDHC Spec v3.00, if the Preset Value
1366 * Enable in the Host Control 2 register is set, we
1367 * need to reset SD Clock Enable before changing High
1368 * Speed Enable to avoid generating clock gliches.
1369 */
1370
1371 /* Reset SD Clock Enable */
1372 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1373 clk &= ~SDHCI_CLOCK_CARD_EN;
1374 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1375
1376 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1377
1378 /* Re-enable SD Clock */
1379 clock = host->clock;
1380 host->clock = 0;
1381 sdhci_set_clock(host, clock);
1382 }
1383
1384
1385 /* Reset SD Clock Enable */
1386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1387 clk &= ~SDHCI_CLOCK_CARD_EN;
1388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1389
1390 if (host->ops->set_uhs_signaling)
1391 host->ops->set_uhs_signaling(host, ios->timing);
1392 else {
1393 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1394 /* Select Bus Speed Mode for host */
1395 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1396 if (ios->timing == MMC_TIMING_UHS_SDR12)
1397 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1398 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1399 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1400 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1401 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1402 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1403 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1404 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1405 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1406 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1407 }
1408
1409 /* Re-enable SD Clock */
1410 clock = host->clock;
1411 host->clock = 0;
1412 sdhci_set_clock(host, clock);
1413 } else
1414 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1415
1416 /*
1417 * Some (ENE) controllers go apeshit on some ios operation,
1418 * signalling timeout and CRC errors even on CMD0. Resetting
1419 * it on each ios seems to solve the problem.
1420 */
1421 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1422 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1423
1424out:
1425 mmiowb();
1426 spin_unlock_irqrestore(&host->lock, flags);
1427}
1428
1429static int check_ro(struct sdhci_host *host)
1430{
1431 unsigned long flags;
1432 int is_readonly;
1433
1434 spin_lock_irqsave(&host->lock, flags);
1435
1436 if (host->flags & SDHCI_DEVICE_DEAD)
1437 is_readonly = 0;
1438 else if (host->ops->get_ro)
1439 is_readonly = host->ops->get_ro(host);
1440 else
1441 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1442 & SDHCI_WRITE_PROTECT);
1443
1444 spin_unlock_irqrestore(&host->lock, flags);
1445
1446 /* This quirk needs to be replaced by a callback-function later */
1447 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1448 !is_readonly : is_readonly;
1449}
1450
1451#define SAMPLE_COUNT 5
1452
1453static int sdhci_get_ro(struct mmc_host *mmc)
1454{
1455 struct sdhci_host *host;
1456 int i, ro_count;
1457
1458 host = mmc_priv(mmc);
1459
1460 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1461 return check_ro(host);
1462
1463 ro_count = 0;
1464 for (i = 0; i < SAMPLE_COUNT; i++) {
1465 if (check_ro(host)) {
1466 if (++ro_count > SAMPLE_COUNT / 2)
1467 return 1;
1468 }
1469 msleep(30);
1470 }
1471 return 0;
1472}
1473
1474static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1475{
1476 struct sdhci_host *host;
1477 unsigned long flags;
1478
1479 host = mmc_priv(mmc);
1480
1481 spin_lock_irqsave(&host->lock, flags);
1482
1483 if (host->flags & SDHCI_DEVICE_DEAD)
1484 goto out;
1485
1486 if (enable)
1487 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1488 else
1489 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1490out:
1491 mmiowb();
1492
1493 spin_unlock_irqrestore(&host->lock, flags);
1494}
1495
1496static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1497 struct mmc_ios *ios)
1498{
1499 struct sdhci_host *host;
1500 u8 pwr;
1501 u16 clk, ctrl;
1502 u32 present_state;
1503
1504 host = mmc_priv(mmc);
1505
1506 /*
1507 * Signal Voltage Switching is only applicable for Host Controllers
1508 * v3.00 and above.
1509 */
1510 if (host->version < SDHCI_SPEC_300)
1511 return 0;
1512
1513 /*
1514 * We first check whether the request is to set signalling voltage
1515 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1516 */
1517 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1518 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1519 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1520 ctrl &= ~SDHCI_CTRL_VDD_180;
1521 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1522
1523 /* Wait for 5ms */
1524 usleep_range(5000, 5500);
1525
1526 /* 3.3V regulator output should be stable within 5 ms */
1527 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1528 if (!(ctrl & SDHCI_CTRL_VDD_180))
1529 return 0;
1530 else {
1531 printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1532 "signalling voltage failed\n");
1533 return -EIO;
1534 }
1535 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1536 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1537 /* Stop SDCLK */
1538 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1539 clk &= ~SDHCI_CLOCK_CARD_EN;
1540 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1541
1542 /* Check whether DAT[3:0] is 0000 */
1543 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1544 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1545 SDHCI_DATA_LVL_SHIFT)) {
1546 /*
1547 * Enable 1.8V Signal Enable in the Host Control2
1548 * register
1549 */
1550 ctrl |= SDHCI_CTRL_VDD_180;
1551 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1552
1553 /* Wait for 5ms */
1554 usleep_range(5000, 5500);
1555
1556 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1557 if (ctrl & SDHCI_CTRL_VDD_180) {
1558 /* Provide SDCLK again and wait for 1ms*/
1559 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1560 clk |= SDHCI_CLOCK_CARD_EN;
1561 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1562 usleep_range(1000, 1500);
1563
1564 /*
1565 * If DAT[3:0] level is 1111b, then the card
1566 * was successfully switched to 1.8V signaling.
1567 */
1568 present_state = sdhci_readl(host,
1569 SDHCI_PRESENT_STATE);
1570 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1571 SDHCI_DATA_LVL_MASK)
1572 return 0;
1573 }
1574 }
1575
1576 /*
1577 * If we are here, that means the switch to 1.8V signaling
1578 * failed. We power cycle the card, and retry initialization
1579 * sequence by setting S18R to 0.
1580 */
1581 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1582 pwr &= ~SDHCI_POWER_ON;
1583 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1584
1585 /* Wait for 1ms as per the spec */
1586 usleep_range(1000, 1500);
1587 pwr |= SDHCI_POWER_ON;
1588 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1589
1590 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1591 "voltage failed, retrying with S18R set to 0\n");
1592 return -EAGAIN;
1593 } else
1594 /* No signal voltage switch required */
1595 return 0;
1596}
1597
1598static int sdhci_execute_tuning(struct mmc_host *mmc)
1599{
1600 struct sdhci_host *host;
1601 u16 ctrl;
1602 u32 ier;
1603 int tuning_loop_counter = MAX_TUNING_LOOP;
1604 unsigned long timeout;
1605 int err = 0;
1606
1607 host = mmc_priv(mmc);
1608
1609 disable_irq(host->irq);
1610 spin_lock(&host->lock);
1611
1612 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1613
1614 /*
1615 * Host Controller needs tuning only in case of SDR104 mode
1616 * and for SDR50 mode when Use Tuning for SDR50 is set in
1617 * Capabilities register.
1618 */
1619 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1620 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1621 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1622 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1623 else {
1624 spin_unlock(&host->lock);
1625 enable_irq(host->irq);
1626 return 0;
1627 }
1628
1629 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1630
1631 /*
1632 * As per the Host Controller spec v3.00, tuning command
1633 * generates Buffer Read Ready interrupt, so enable that.
1634 *
1635 * Note: The spec clearly says that when tuning sequence
1636 * is being performed, the controller does not generate
1637 * interrupts other than Buffer Read Ready interrupt. But
1638 * to make sure we don't hit a controller bug, we _only_
1639 * enable Buffer Read Ready interrupt here.
1640 */
1641 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1642 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1643
1644 /*
1645 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1646 * of loops reaches 40 times or a timeout of 150ms occurs.
1647 */
1648 timeout = 150;
1649 do {
1650 struct mmc_command cmd = {0};
1651 struct mmc_request mrq = {0};
1652
1653 if (!tuning_loop_counter && !timeout)
1654 break;
1655
1656 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1657 cmd.arg = 0;
1658 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1659 cmd.retries = 0;
1660 cmd.data = NULL;
1661 cmd.error = 0;
1662
1663 mrq.cmd = &cmd;
1664 host->mrq = &mrq;
1665
1666 /*
1667 * In response to CMD19, the card sends 64 bytes of tuning
1668 * block to the Host Controller. So we set the block size
1669 * to 64 here.
1670 */
1671 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1672
1673 /*
1674 * The tuning block is sent by the card to the host controller.
1675 * So we set the TRNS_READ bit in the Transfer Mode register.
1676 * This also takes care of setting DMA Enable and Multi Block
1677 * Select in the same register to 0.
1678 */
1679 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1680
1681 sdhci_send_command(host, &cmd);
1682
1683 host->cmd = NULL;
1684 host->mrq = NULL;
1685
1686 spin_unlock(&host->lock);
1687 enable_irq(host->irq);
1688
1689 /* Wait for Buffer Read Ready interrupt */
1690 wait_event_interruptible_timeout(host->buf_ready_int,
1691 (host->tuning_done == 1),
1692 msecs_to_jiffies(50));
1693 disable_irq(host->irq);
1694 spin_lock(&host->lock);
1695
1696 if (!host->tuning_done) {
1697 printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1698 "Buffer Read Ready interrupt during tuning "
1699 "procedure, falling back to fixed sampling "
1700 "clock\n");
1701 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1702 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1703 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1704 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1705
1706 err = -EIO;
1707 goto out;
1708 }
1709
1710 host->tuning_done = 0;
1711
1712 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1713 tuning_loop_counter--;
1714 timeout--;
1715 mdelay(1);
1716 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1717
1718 /*
1719 * The Host Driver has exhausted the maximum number of loops allowed,
1720 * so use fixed sampling frequency.
1721 */
1722 if (!tuning_loop_counter || !timeout) {
1723 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1724 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1725 } else {
1726 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1727 printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1728 " failed, falling back to fixed sampling"
1729 " clock\n");
1730 err = -EIO;
1731 }
1732 }
1733
1734out:
1735 /*
1736 * If this is the very first time we are here, we start the retuning
1737 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1738 * flag won't be set, we check this condition before actually starting
1739 * the timer.
1740 */
1741 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1742 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1743 mod_timer(&host->tuning_timer, jiffies +
1744 host->tuning_count * HZ);
1745 /* Tuning mode 1 limits the maximum data length to 4MB */
1746 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1747 } else {
1748 host->flags &= ~SDHCI_NEEDS_RETUNING;
1749 /* Reload the new initial value for timer */
1750 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1751 mod_timer(&host->tuning_timer, jiffies +
1752 host->tuning_count * HZ);
1753 }
1754
1755 /*
1756 * In case tuning fails, host controllers which support re-tuning can
1757 * try tuning again at a later time, when the re-tuning timer expires.
1758 * So for these controllers, we return 0. Since there might be other
1759 * controllers who do not have this capability, we return error for
1760 * them.
1761 */
1762 if (err && host->tuning_count &&
1763 host->tuning_mode == SDHCI_TUNING_MODE_1)
1764 err = 0;
1765
1766 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1767 spin_unlock(&host->lock);
1768 enable_irq(host->irq);
1769
1770 return err;
1771}
1772
1773static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1774{
1775 struct sdhci_host *host;
1776 u16 ctrl;
1777 unsigned long flags;
1778
1779 host = mmc_priv(mmc);
1780
1781 /* Host Controller v3.00 defines preset value registers */
1782 if (host->version < SDHCI_SPEC_300)
1783 return;
1784
1785 spin_lock_irqsave(&host->lock, flags);
1786
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788
1789 /*
1790 * We only enable or disable Preset Value if they are not already
1791 * enabled or disabled respectively. Otherwise, we bail out.
1792 */
1793 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1794 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1795 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1796 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1797 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1798 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1799 }
1800
1801 spin_unlock_irqrestore(&host->lock, flags);
1802}
1803
1804static const struct mmc_host_ops sdhci_ops = {
1805 .request = sdhci_request,
1806 .set_ios = sdhci_set_ios,
1807 .get_ro = sdhci_get_ro,
1808 .enable_sdio_irq = sdhci_enable_sdio_irq,
1809 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
1810 .execute_tuning = sdhci_execute_tuning,
1811 .enable_preset_value = sdhci_enable_preset_value,
1812};
1813
1814/*****************************************************************************\
1815 * *
1816 * Tasklets *
1817 * *
1818\*****************************************************************************/
1819
1820static void sdhci_tasklet_card(unsigned long param)
1821{
1822 struct sdhci_host *host;
1823 unsigned long flags;
1824
1825 host = (struct sdhci_host*)param;
1826
1827 spin_lock_irqsave(&host->lock, flags);
1828
1829 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1830 if (host->mrq) {
1831 printk(KERN_ERR "%s: Card removed during transfer!\n",
1832 mmc_hostname(host->mmc));
1833 printk(KERN_ERR "%s: Resetting controller.\n",
1834 mmc_hostname(host->mmc));
1835
1836 sdhci_reset(host, SDHCI_RESET_CMD);
1837 sdhci_reset(host, SDHCI_RESET_DATA);
1838
1839 host->mrq->cmd->error = -ENOMEDIUM;
1840 tasklet_schedule(&host->finish_tasklet);
1841 }
1842 }
1843
1844 spin_unlock_irqrestore(&host->lock, flags);
1845
1846 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1847}
1848
1849static void sdhci_tasklet_finish(unsigned long param)
1850{
1851 struct sdhci_host *host;
1852 unsigned long flags;
1853 struct mmc_request *mrq;
1854
1855 host = (struct sdhci_host*)param;
1856
1857 /*
1858 * If this tasklet gets rescheduled while running, it will
1859 * be run again afterwards but without any active request.
1860 */
1861 if (!host->mrq)
1862 return;
1863
1864 spin_lock_irqsave(&host->lock, flags);
1865
1866 del_timer(&host->timer);
1867
1868 mrq = host->mrq;
1869
1870 /*
1871 * The controller needs a reset of internal state machines
1872 * upon error conditions.
1873 */
1874 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1875 ((mrq->cmd && mrq->cmd->error) ||
1876 (mrq->data && (mrq->data->error ||
1877 (mrq->data->stop && mrq->data->stop->error))) ||
1878 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1879
1880 /* Some controllers need this kick or reset won't work here */
1881 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1882 unsigned int clock;
1883
1884 /* This is to force an update */
1885 clock = host->clock;
1886 host->clock = 0;
1887 sdhci_set_clock(host, clock);
1888 }
1889
1890 /* Spec says we should do both at the same time, but Ricoh
1891 controllers do not like that. */
1892 sdhci_reset(host, SDHCI_RESET_CMD);
1893 sdhci_reset(host, SDHCI_RESET_DATA);
1894 }
1895
1896 host->mrq = NULL;
1897 host->cmd = NULL;
1898 host->data = NULL;
1899
1900#ifndef SDHCI_USE_LEDS_CLASS
1901 sdhci_deactivate_led(host);
1902#endif
1903
1904 mmiowb();
1905 spin_unlock_irqrestore(&host->lock, flags);
1906
1907 mmc_request_done(host->mmc, mrq);
1908}
1909
1910static void sdhci_timeout_timer(unsigned long data)
1911{
1912 struct sdhci_host *host;
1913 unsigned long flags;
1914
1915 host = (struct sdhci_host*)data;
1916
1917 spin_lock_irqsave(&host->lock, flags);
1918
1919 if (host->mrq) {
1920 printk(KERN_ERR "%s: Timeout waiting for hardware "
1921 "interrupt.\n", mmc_hostname(host->mmc));
1922 sdhci_dumpregs(host);
1923
1924 if (host->data) {
1925 host->data->error = -ETIMEDOUT;
1926 sdhci_finish_data(host);
1927 } else {
1928 if (host->cmd)
1929 host->cmd->error = -ETIMEDOUT;
1930 else
1931 host->mrq->cmd->error = -ETIMEDOUT;
1932
1933 tasklet_schedule(&host->finish_tasklet);
1934 }
1935 }
1936
1937 mmiowb();
1938 spin_unlock_irqrestore(&host->lock, flags);
1939}
1940
1941static void sdhci_tuning_timer(unsigned long data)
1942{
1943 struct sdhci_host *host;
1944 unsigned long flags;
1945
1946 host = (struct sdhci_host *)data;
1947
1948 spin_lock_irqsave(&host->lock, flags);
1949
1950 host->flags |= SDHCI_NEEDS_RETUNING;
1951
1952 spin_unlock_irqrestore(&host->lock, flags);
1953}
1954
1955/*****************************************************************************\
1956 * *
1957 * Interrupt handling *
1958 * *
1959\*****************************************************************************/
1960
1961static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1962{
1963 BUG_ON(intmask == 0);
1964
1965 if (!host->cmd) {
1966 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1967 "though no command operation was in progress.\n",
1968 mmc_hostname(host->mmc), (unsigned)intmask);
1969 sdhci_dumpregs(host);
1970 return;
1971 }
1972
1973 if (intmask & SDHCI_INT_TIMEOUT)
1974 host->cmd->error = -ETIMEDOUT;
1975 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1976 SDHCI_INT_INDEX))
1977 host->cmd->error = -EILSEQ;
1978
1979 if (host->cmd->error) {
1980 tasklet_schedule(&host->finish_tasklet);
1981 return;
1982 }
1983
1984 /*
1985 * The host can send and interrupt when the busy state has
1986 * ended, allowing us to wait without wasting CPU cycles.
1987 * Unfortunately this is overloaded on the "data complete"
1988 * interrupt, so we need to take some care when handling
1989 * it.
1990 *
1991 * Note: The 1.0 specification is a bit ambiguous about this
1992 * feature so there might be some problems with older
1993 * controllers.
1994 */
1995 if (host->cmd->flags & MMC_RSP_BUSY) {
1996 if (host->cmd->data)
1997 DBG("Cannot wait for busy signal when also "
1998 "doing a data transfer");
1999 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2000 return;
2001
2002 /* The controller does not support the end-of-busy IRQ,
2003 * fall through and take the SDHCI_INT_RESPONSE */
2004 }
2005
2006 if (intmask & SDHCI_INT_RESPONSE)
2007 sdhci_finish_command(host);
2008}
2009
2010#ifdef CONFIG_MMC_DEBUG
2011static void sdhci_show_adma_error(struct sdhci_host *host)
2012{
2013 const char *name = mmc_hostname(host->mmc);
2014 u8 *desc = host->adma_desc;
2015 __le32 *dma;
2016 __le16 *len;
2017 u8 attr;
2018
2019 sdhci_dumpregs(host);
2020
2021 while (true) {
2022 dma = (__le32 *)(desc + 4);
2023 len = (__le16 *)(desc + 2);
2024 attr = *desc;
2025
2026 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2027 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2028
2029 desc += 8;
2030
2031 if (attr & 2)
2032 break;
2033 }
2034}
2035#else
2036static void sdhci_show_adma_error(struct sdhci_host *host) { }
2037#endif
2038
2039static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2040{
2041 BUG_ON(intmask == 0);
2042
2043 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2044 if (intmask & SDHCI_INT_DATA_AVAIL) {
2045 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2046 MMC_SEND_TUNING_BLOCK) {
2047 host->tuning_done = 1;
2048 wake_up(&host->buf_ready_int);
2049 return;
2050 }
2051 }
2052
2053 if (!host->data) {
2054 /*
2055 * The "data complete" interrupt is also used to
2056 * indicate that a busy state has ended. See comment
2057 * above in sdhci_cmd_irq().
2058 */
2059 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2060 if (intmask & SDHCI_INT_DATA_END) {
2061 sdhci_finish_command(host);
2062 return;
2063 }
2064 }
2065
2066 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2067 "though no data operation was in progress.\n",
2068 mmc_hostname(host->mmc), (unsigned)intmask);
2069 sdhci_dumpregs(host);
2070
2071 return;
2072 }
2073
2074 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2075 host->data->error = -ETIMEDOUT;
2076 else if (intmask & SDHCI_INT_DATA_END_BIT)
2077 host->data->error = -EILSEQ;
2078 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2079 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2080 != MMC_BUS_TEST_R)
2081 host->data->error = -EILSEQ;
2082 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2083 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2084 sdhci_show_adma_error(host);
2085 host->data->error = -EIO;
2086 }
2087
2088 if (host->data->error)
2089 sdhci_finish_data(host);
2090 else {
2091 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2092 sdhci_transfer_pio(host);
2093
2094 /*
2095 * We currently don't do anything fancy with DMA
2096 * boundaries, but as we can't disable the feature
2097 * we need to at least restart the transfer.
2098 *
2099 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2100 * should return a valid address to continue from, but as
2101 * some controllers are faulty, don't trust them.
2102 */
2103 if (intmask & SDHCI_INT_DMA_END) {
2104 u32 dmastart, dmanow;
2105 dmastart = sg_dma_address(host->data->sg);
2106 dmanow = dmastart + host->data->bytes_xfered;
2107 /*
2108 * Force update to the next DMA block boundary.
2109 */
2110 dmanow = (dmanow &
2111 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2112 SDHCI_DEFAULT_BOUNDARY_SIZE;
2113 host->data->bytes_xfered = dmanow - dmastart;
2114 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2115 " next 0x%08x\n",
2116 mmc_hostname(host->mmc), dmastart,
2117 host->data->bytes_xfered, dmanow);
2118 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2119 }
2120
2121 if (intmask & SDHCI_INT_DATA_END) {
2122 if (host->cmd) {
2123 /*
2124 * Data managed to finish before the
2125 * command completed. Make sure we do
2126 * things in the proper order.
2127 */
2128 host->data_early = 1;
2129 } else {
2130 sdhci_finish_data(host);
2131 }
2132 }
2133 }
2134}
2135
2136static irqreturn_t sdhci_irq(int irq, void *dev_id)
2137{
2138 irqreturn_t result;
2139 struct sdhci_host* host = dev_id;
2140 u32 intmask;
2141 int cardint = 0;
2142
2143 spin_lock(&host->lock);
2144
2145 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2146
2147 if (!intmask || intmask == 0xffffffff) {
2148 result = IRQ_NONE;
2149 goto out;
2150 }
2151
2152 DBG("*** %s got interrupt: 0x%08x\n",
2153 mmc_hostname(host->mmc), intmask);
2154
2155 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2156 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2157 SDHCI_CARD_PRESENT;
2158
2159 /*
2160 * There is a observation on i.mx esdhc. INSERT bit will be
2161 * immediately set again when it gets cleared, if a card is
2162 * inserted. We have to mask the irq to prevent interrupt
2163 * storm which will freeze the system. And the REMOVE gets
2164 * the same situation.
2165 *
2166 * More testing are needed here to ensure it works for other
2167 * platforms though.
2168 */
2169 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2170 SDHCI_INT_CARD_REMOVE);
2171 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2172 SDHCI_INT_CARD_INSERT);
2173
2174 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2175 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2176 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2177 tasklet_schedule(&host->card_tasklet);
2178 }
2179
2180 if (intmask & SDHCI_INT_CMD_MASK) {
2181 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2182 SDHCI_INT_STATUS);
2183 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2184 }
2185
2186 if (intmask & SDHCI_INT_DATA_MASK) {
2187 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2188 SDHCI_INT_STATUS);
2189 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2190 }
2191
2192 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2193
2194 intmask &= ~SDHCI_INT_ERROR;
2195
2196 if (intmask & SDHCI_INT_BUS_POWER) {
2197 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2198 mmc_hostname(host->mmc));
2199 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2200 }
2201
2202 intmask &= ~SDHCI_INT_BUS_POWER;
2203
2204 if (intmask & SDHCI_INT_CARD_INT)
2205 cardint = 1;
2206
2207 intmask &= ~SDHCI_INT_CARD_INT;
2208
2209 if (intmask) {
2210 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2211 mmc_hostname(host->mmc), intmask);
2212 sdhci_dumpregs(host);
2213
2214 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2215 }
2216
2217 result = IRQ_HANDLED;
2218
2219 mmiowb();
2220out:
2221 spin_unlock(&host->lock);
2222
2223 /*
2224 * We have to delay this as it calls back into the driver.
2225 */
2226 if (cardint)
2227 mmc_signal_sdio_irq(host->mmc);
2228
2229 return result;
2230}
2231
2232/*****************************************************************************\
2233 * *
2234 * Suspend/resume *
2235 * *
2236\*****************************************************************************/
2237
2238#ifdef CONFIG_PM
2239
2240int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2241{
2242 int ret;
2243
2244 sdhci_disable_card_detection(host);
2245
2246 /* Disable tuning since we are suspending */
2247 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2248 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2249 host->flags &= ~SDHCI_NEEDS_RETUNING;
2250 mod_timer(&host->tuning_timer, jiffies +
2251 host->tuning_count * HZ);
2252 }
2253
2254 ret = mmc_suspend_host(host->mmc);
2255 if (ret)
2256 return ret;
2257
2258 free_irq(host->irq, host);
2259
2260 if (host->vmmc)
2261 ret = regulator_disable(host->vmmc);
2262
2263 return ret;
2264}
2265
2266EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2267
2268int sdhci_resume_host(struct sdhci_host *host)
2269{
2270 int ret;
2271
2272 if (host->vmmc) {
2273 int ret = regulator_enable(host->vmmc);
2274 if (ret)
2275 return ret;
2276 }
2277
2278
2279 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2280 if (host->ops->enable_dma)
2281 host->ops->enable_dma(host);
2282 }
2283
2284 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2285 mmc_hostname(host->mmc), host);
2286 if (ret)
2287 return ret;
2288
2289 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2290 mmiowb();
2291
2292 ret = mmc_resume_host(host->mmc);
2293 sdhci_enable_card_detection(host);
2294
2295 /* Set the re-tuning expiration flag */
2296 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2297 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2298 host->flags |= SDHCI_NEEDS_RETUNING;
2299
2300 return ret;
2301}
2302
2303EXPORT_SYMBOL_GPL(sdhci_resume_host);
2304
2305void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2306{
2307 u8 val;
2308 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2309 val |= SDHCI_WAKE_ON_INT;
2310 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2311}
2312
2313EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2314
2315#endif /* CONFIG_PM */
2316
2317/*****************************************************************************\
2318 * *
2319 * Device allocation/registration *
2320 * *
2321\*****************************************************************************/
2322
2323struct sdhci_host *sdhci_alloc_host(struct device *dev,
2324 size_t priv_size)
2325{
2326 struct mmc_host *mmc;
2327 struct sdhci_host *host;
2328
2329 WARN_ON(dev == NULL);
2330
2331 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2332 if (!mmc)
2333 return ERR_PTR(-ENOMEM);
2334
2335 host = mmc_priv(mmc);
2336 host->mmc = mmc;
2337
2338 return host;
2339}
2340
2341EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2342
2343int sdhci_add_host(struct sdhci_host *host)
2344{
2345 struct mmc_host *mmc;
2346 u32 caps[2];
2347 u32 max_current_caps;
2348 unsigned int ocr_avail;
2349 int ret;
2350
2351 WARN_ON(host == NULL);
2352 if (host == NULL)
2353 return -EINVAL;
2354
2355 mmc = host->mmc;
2356
2357 if (debug_quirks)
2358 host->quirks = debug_quirks;
2359
2360 sdhci_reset(host, SDHCI_RESET_ALL);
2361
2362 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2363 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2364 >> SDHCI_SPEC_VER_SHIFT;
2365 if (host->version > SDHCI_SPEC_300) {
2366 printk(KERN_ERR "%s: Unknown controller version (%d). "
2367 "You may experience problems.\n", mmc_hostname(mmc),
2368 host->version);
2369 }
2370
2371 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2372 sdhci_readl(host, SDHCI_CAPABILITIES);
2373
2374 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2375 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2376
2377 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2378 host->flags |= SDHCI_USE_SDMA;
2379 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2380 DBG("Controller doesn't have SDMA capability\n");
2381 else
2382 host->flags |= SDHCI_USE_SDMA;
2383
2384 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2385 (host->flags & SDHCI_USE_SDMA)) {
2386 DBG("Disabling DMA as it is marked broken\n");
2387 host->flags &= ~SDHCI_USE_SDMA;
2388 }
2389
2390 if ((host->version >= SDHCI_SPEC_200) &&
2391 (caps[0] & SDHCI_CAN_DO_ADMA2))
2392 host->flags |= SDHCI_USE_ADMA;
2393
2394 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2395 (host->flags & SDHCI_USE_ADMA)) {
2396 DBG("Disabling ADMA as it is marked broken\n");
2397 host->flags &= ~SDHCI_USE_ADMA;
2398 }
2399
2400 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2401 if (host->ops->enable_dma) {
2402 if (host->ops->enable_dma(host)) {
2403 printk(KERN_WARNING "%s: No suitable DMA "
2404 "available. Falling back to PIO.\n",
2405 mmc_hostname(mmc));
2406 host->flags &=
2407 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2408 }
2409 }
2410 }
2411
2412 if (host->flags & SDHCI_USE_ADMA) {
2413 /*
2414 * We need to allocate descriptors for all sg entries
2415 * (128) and potentially one alignment transfer for
2416 * each of those entries.
2417 */
2418 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2419 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2420 if (!host->adma_desc || !host->align_buffer) {
2421 kfree(host->adma_desc);
2422 kfree(host->align_buffer);
2423 printk(KERN_WARNING "%s: Unable to allocate ADMA "
2424 "buffers. Falling back to standard DMA.\n",
2425 mmc_hostname(mmc));
2426 host->flags &= ~SDHCI_USE_ADMA;
2427 }
2428 }
2429
2430 /*
2431 * If we use DMA, then it's up to the caller to set the DMA
2432 * mask, but PIO does not need the hw shim so we set a new
2433 * mask here in that case.
2434 */
2435 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2436 host->dma_mask = DMA_BIT_MASK(64);
2437 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2438 }
2439
2440 if (host->version >= SDHCI_SPEC_300)
2441 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2442 >> SDHCI_CLOCK_BASE_SHIFT;
2443 else
2444 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2445 >> SDHCI_CLOCK_BASE_SHIFT;
2446
2447 host->max_clk *= 1000000;
2448 if (host->max_clk == 0 || host->quirks &
2449 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2450 if (!host->ops->get_max_clock) {
2451 printk(KERN_ERR
2452 "%s: Hardware doesn't specify base clock "
2453 "frequency.\n", mmc_hostname(mmc));
2454 return -ENODEV;
2455 }
2456 host->max_clk = host->ops->get_max_clock(host);
2457 }
2458
2459 /*
2460 * In case of Host Controller v3.00, find out whether clock
2461 * multiplier is supported.
2462 */
2463 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2464 SDHCI_CLOCK_MUL_SHIFT;
2465
2466 /*
2467 * In case the value in Clock Multiplier is 0, then programmable
2468 * clock mode is not supported, otherwise the actual clock
2469 * multiplier is one more than the value of Clock Multiplier
2470 * in the Capabilities Register.
2471 */
2472 if (host->clk_mul)
2473 host->clk_mul += 1;
2474
2475 /*
2476 * Set host parameters.
2477 */
2478 mmc->ops = &sdhci_ops;
2479 mmc->f_max = host->max_clk;
2480 if (host->ops->get_min_clock)
2481 mmc->f_min = host->ops->get_min_clock(host);
2482 else if (host->version >= SDHCI_SPEC_300) {
2483 if (host->clk_mul) {
2484 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2485 mmc->f_max = host->max_clk * host->clk_mul;
2486 } else
2487 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2488 } else
2489 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2490
2491 host->timeout_clk =
2492 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2493 if (host->timeout_clk == 0) {
2494 if (host->ops->get_timeout_clock) {
2495 host->timeout_clk = host->ops->get_timeout_clock(host);
2496 } else if (!(host->quirks &
2497 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2498 printk(KERN_ERR
2499 "%s: Hardware doesn't specify timeout clock "
2500 "frequency.\n", mmc_hostname(mmc));
2501 return -ENODEV;
2502 }
2503 }
2504 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2505 host->timeout_clk *= 1000;
2506
2507 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2508 host->timeout_clk = mmc->f_max / 1000;
2509
2510 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2511
2512 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2513
2514 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2515 host->flags |= SDHCI_AUTO_CMD12;
2516
2517 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2518 if ((host->version >= SDHCI_SPEC_300) &&
2519 ((host->flags & SDHCI_USE_ADMA) ||
2520 !(host->flags & SDHCI_USE_SDMA))) {
2521 host->flags |= SDHCI_AUTO_CMD23;
2522 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2523 } else {
2524 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2525 }
2526
2527 /*
2528 * A controller may support 8-bit width, but the board itself
2529 * might not have the pins brought out. Boards that support
2530 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2531 * their platform code before calling sdhci_add_host(), and we
2532 * won't assume 8-bit width for hosts without that CAP.
2533 */
2534 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2535 mmc->caps |= MMC_CAP_4_BIT_DATA;
2536
2537 if (caps[0] & SDHCI_CAN_DO_HISPD)
2538 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2539
2540 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2541 mmc_card_is_removable(mmc))
2542 mmc->caps |= MMC_CAP_NEEDS_POLL;
2543
2544 /* UHS-I mode(s) supported by the host controller. */
2545 if (host->version >= SDHCI_SPEC_300)
2546 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2547
2548 /* SDR104 supports also implies SDR50 support */
2549 if (caps[1] & SDHCI_SUPPORT_SDR104)
2550 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2551 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2552 mmc->caps |= MMC_CAP_UHS_SDR50;
2553
2554 if (caps[1] & SDHCI_SUPPORT_DDR50)
2555 mmc->caps |= MMC_CAP_UHS_DDR50;
2556
2557 /* Does the host needs tuning for SDR50? */
2558 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2559 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2560
2561 /* Driver Type(s) (A, C, D) supported by the host */
2562 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2563 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2564 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2565 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2566 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2567 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2568
2569 /* Initial value for re-tuning timer count */
2570 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2571 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2572
2573 /*
2574 * In case Re-tuning Timer is not disabled, the actual value of
2575 * re-tuning timer will be 2 ^ (n - 1).
2576 */
2577 if (host->tuning_count)
2578 host->tuning_count = 1 << (host->tuning_count - 1);
2579
2580 /* Re-tuning mode supported by the Host Controller */
2581 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2582 SDHCI_RETUNING_MODE_SHIFT;
2583
2584 ocr_avail = 0;
2585 /*
2586 * According to SD Host Controller spec v3.00, if the Host System
2587 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2588 * the value is meaningful only if Voltage Support in the Capabilities
2589 * register is set. The actual current value is 4 times the register
2590 * value.
2591 */
2592 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2593
2594 if (caps[0] & SDHCI_CAN_VDD_330) {
2595 int max_current_330;
2596
2597 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2598
2599 max_current_330 = ((max_current_caps &
2600 SDHCI_MAX_CURRENT_330_MASK) >>
2601 SDHCI_MAX_CURRENT_330_SHIFT) *
2602 SDHCI_MAX_CURRENT_MULTIPLIER;
2603
2604 if (max_current_330 > 150)
2605 mmc->caps |= MMC_CAP_SET_XPC_330;
2606 }
2607 if (caps[0] & SDHCI_CAN_VDD_300) {
2608 int max_current_300;
2609
2610 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2611
2612 max_current_300 = ((max_current_caps &
2613 SDHCI_MAX_CURRENT_300_MASK) >>
2614 SDHCI_MAX_CURRENT_300_SHIFT) *
2615 SDHCI_MAX_CURRENT_MULTIPLIER;
2616
2617 if (max_current_300 > 150)
2618 mmc->caps |= MMC_CAP_SET_XPC_300;
2619 }
2620 if (caps[0] & SDHCI_CAN_VDD_180) {
2621 int max_current_180;
2622
2623 ocr_avail |= MMC_VDD_165_195;
2624
2625 max_current_180 = ((max_current_caps &
2626 SDHCI_MAX_CURRENT_180_MASK) >>
2627 SDHCI_MAX_CURRENT_180_SHIFT) *
2628 SDHCI_MAX_CURRENT_MULTIPLIER;
2629
2630 if (max_current_180 > 150)
2631 mmc->caps |= MMC_CAP_SET_XPC_180;
2632
2633 /* Maximum current capabilities of the host at 1.8V */
2634 if (max_current_180 >= 800)
2635 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2636 else if (max_current_180 >= 600)
2637 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2638 else if (max_current_180 >= 400)
2639 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2640 else
2641 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2642 }
2643
2644 mmc->ocr_avail = ocr_avail;
2645 mmc->ocr_avail_sdio = ocr_avail;
2646 if (host->ocr_avail_sdio)
2647 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2648 mmc->ocr_avail_sd = ocr_avail;
2649 if (host->ocr_avail_sd)
2650 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2651 else /* normal SD controllers don't support 1.8V */
2652 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2653 mmc->ocr_avail_mmc = ocr_avail;
2654 if (host->ocr_avail_mmc)
2655 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2656
2657 if (mmc->ocr_avail == 0) {
2658 printk(KERN_ERR "%s: Hardware doesn't report any "
2659 "support voltages.\n", mmc_hostname(mmc));
2660 return -ENODEV;
2661 }
2662
2663 spin_lock_init(&host->lock);
2664
2665 /*
2666 * Maximum number of segments. Depends on if the hardware
2667 * can do scatter/gather or not.
2668 */
2669 if (host->flags & SDHCI_USE_ADMA)
2670 mmc->max_segs = 128;
2671 else if (host->flags & SDHCI_USE_SDMA)
2672 mmc->max_segs = 1;
2673 else /* PIO */
2674 mmc->max_segs = 128;
2675
2676 /*
2677 * Maximum number of sectors in one transfer. Limited by DMA boundary
2678 * size (512KiB).
2679 */
2680 mmc->max_req_size = 524288;
2681
2682 /*
2683 * Maximum segment size. Could be one segment with the maximum number
2684 * of bytes. When doing hardware scatter/gather, each entry cannot
2685 * be larger than 64 KiB though.
2686 */
2687 if (host->flags & SDHCI_USE_ADMA) {
2688 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2689 mmc->max_seg_size = 65535;
2690 else
2691 mmc->max_seg_size = 65536;
2692 } else {
2693 mmc->max_seg_size = mmc->max_req_size;
2694 }
2695
2696 /*
2697 * Maximum block size. This varies from controller to controller and
2698 * is specified in the capabilities register.
2699 */
2700 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2701 mmc->max_blk_size = 2;
2702 } else {
2703 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2704 SDHCI_MAX_BLOCK_SHIFT;
2705 if (mmc->max_blk_size >= 3) {
2706 printk(KERN_WARNING "%s: Invalid maximum block size, "
2707 "assuming 512 bytes\n", mmc_hostname(mmc));
2708 mmc->max_blk_size = 0;
2709 }
2710 }
2711
2712 mmc->max_blk_size = 512 << mmc->max_blk_size;
2713
2714 /*
2715 * Maximum block count.
2716 */
2717 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2718
2719 /*
2720 * Init tasklets.
2721 */
2722 tasklet_init(&host->card_tasklet,
2723 sdhci_tasklet_card, (unsigned long)host);
2724 tasklet_init(&host->finish_tasklet,
2725 sdhci_tasklet_finish, (unsigned long)host);
2726
2727 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2728
2729 if (host->version >= SDHCI_SPEC_300) {
2730 init_waitqueue_head(&host->buf_ready_int);
2731
2732 /* Initialize re-tuning timer */
2733 init_timer(&host->tuning_timer);
2734 host->tuning_timer.data = (unsigned long)host;
2735 host->tuning_timer.function = sdhci_tuning_timer;
2736 }
2737
2738 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2739 mmc_hostname(mmc), host);
2740 if (ret)
2741 goto untasklet;
2742
2743 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2744 if (IS_ERR(host->vmmc)) {
2745 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2746 host->vmmc = NULL;
2747 } else {
2748 regulator_enable(host->vmmc);
2749 }
2750
2751 sdhci_init(host, 0);
2752
2753#ifdef CONFIG_MMC_DEBUG
2754 sdhci_dumpregs(host);
2755#endif
2756
2757#ifdef SDHCI_USE_LEDS_CLASS
2758 snprintf(host->led_name, sizeof(host->led_name),
2759 "%s::", mmc_hostname(mmc));
2760 host->led.name = host->led_name;
2761 host->led.brightness = LED_OFF;
2762 host->led.default_trigger = mmc_hostname(mmc);
2763 host->led.brightness_set = sdhci_led_control;
2764
2765 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2766 if (ret)
2767 goto reset;
2768#endif
2769
2770 mmiowb();
2771
2772 mmc_add_host(mmc);
2773
2774 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2775 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2776 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2777 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2778
2779 sdhci_enable_card_detection(host);
2780
2781 return 0;
2782
2783#ifdef SDHCI_USE_LEDS_CLASS
2784reset:
2785 sdhci_reset(host, SDHCI_RESET_ALL);
2786 free_irq(host->irq, host);
2787#endif
2788untasklet:
2789 tasklet_kill(&host->card_tasklet);
2790 tasklet_kill(&host->finish_tasklet);
2791
2792 return ret;
2793}
2794
2795EXPORT_SYMBOL_GPL(sdhci_add_host);
2796
2797void sdhci_remove_host(struct sdhci_host *host, int dead)
2798{
2799 unsigned long flags;
2800
2801 if (dead) {
2802 spin_lock_irqsave(&host->lock, flags);
2803
2804 host->flags |= SDHCI_DEVICE_DEAD;
2805
2806 if (host->mrq) {
2807 printk(KERN_ERR "%s: Controller removed during "
2808 " transfer!\n", mmc_hostname(host->mmc));
2809
2810 host->mrq->cmd->error = -ENOMEDIUM;
2811 tasklet_schedule(&host->finish_tasklet);
2812 }
2813
2814 spin_unlock_irqrestore(&host->lock, flags);
2815 }
2816
2817 sdhci_disable_card_detection(host);
2818
2819 mmc_remove_host(host->mmc);
2820
2821#ifdef SDHCI_USE_LEDS_CLASS
2822 led_classdev_unregister(&host->led);
2823#endif
2824
2825 if (!dead)
2826 sdhci_reset(host, SDHCI_RESET_ALL);
2827
2828 free_irq(host->irq, host);
2829
2830 del_timer_sync(&host->timer);
2831 if (host->version >= SDHCI_SPEC_300)
2832 del_timer_sync(&host->tuning_timer);
2833
2834 tasklet_kill(&host->card_tasklet);
2835 tasklet_kill(&host->finish_tasklet);
2836
2837 if (host->vmmc) {
2838 regulator_disable(host->vmmc);
2839 regulator_put(host->vmmc);
2840 }
2841
2842 kfree(host->adma_desc);
2843 kfree(host->align_buffer);
2844
2845 host->adma_desc = NULL;
2846 host->align_buffer = NULL;
2847}
2848
2849EXPORT_SYMBOL_GPL(sdhci_remove_host);
2850
2851void sdhci_free_host(struct sdhci_host *host)
2852{
2853 mmc_free_host(host->mmc);
2854}
2855
2856EXPORT_SYMBOL_GPL(sdhci_free_host);
2857
2858/*****************************************************************************\
2859 * *
2860 * Driver init/exit *
2861 * *
2862\*****************************************************************************/
2863
2864static int __init sdhci_drv_init(void)
2865{
2866 printk(KERN_INFO DRIVER_NAME
2867 ": Secure Digital Host Controller Interface driver\n");
2868 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2869
2870 return 0;
2871}
2872
2873static void __exit sdhci_drv_exit(void)
2874{
2875}
2876
2877module_init(sdhci_drv_init);
2878module_exit(sdhci_drv_exit);
2879
2880module_param(debug_quirks, uint, 0444);
2881
2882MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2883MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2884MODULE_LICENSE("GPL");
2885
2886MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");