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1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Jun Nie <njun@marvell.com>
6 * Qiming Wu <wuqm@marvell.com>
7 * Philip Rakity <prakity@marvell.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/gpio.h>
27#include <linux/mmc/card.h>
28#include <linux/mmc/host.h>
29#include <linux/platform_data/pxa_sdhci.h>
30#include <linux/slab.h>
31#include "sdhci.h"
32#include "sdhci-pltfm.h"
33
34#define SD_FIFO_PARAM 0xe0
35#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
36#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
37#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
38#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
39 CLK_GATE_ON | CLK_GATE_CTL)
40
41#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
42#define SDCLK_SEL_SHIFT 8
43#define SDCLK_SEL_MASK 0x3
44#define SDCLK_DELAY_SHIFT 10
45#define SDCLK_DELAY_MASK 0x3c
46
47#define SD_CE_ATA_2 0xea
48#define MMC_CARD 0x1000
49#define MMC_WIDTH 0x0100
50
51static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
52{
53 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
54 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
55
56 if (mask == SDHCI_RESET_ALL) {
57 u16 tmp = 0;
58
59 /*
60 * tune timing of read data/command when crc error happen
61 * no performance impact
62 */
63 if (pdata && pdata->clk_delay_sel == 1) {
64 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
65
66 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
67 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
68 << SDCLK_DELAY_SHIFT;
69 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
70 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
71
72 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
73 }
74
75 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
76 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
77 tmp &= ~CLK_GATE_SETTING_BITS;
78 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
79 } else {
80 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
81 tmp &= ~CLK_GATE_SETTING_BITS;
82 tmp |= CLK_GATE_SETTING_BITS;
83 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
84 }
85 }
86}
87
88static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
89{
90 u8 ctrl;
91 u16 tmp;
92
93 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
94 tmp = readw(host->ioaddr + SD_CE_ATA_2);
95 if (width == MMC_BUS_WIDTH_8) {
96 ctrl &= ~SDHCI_CTRL_4BITBUS;
97 tmp |= MMC_CARD | MMC_WIDTH;
98 } else {
99 tmp &= ~(MMC_CARD | MMC_WIDTH);
100 if (width == MMC_BUS_WIDTH_4)
101 ctrl |= SDHCI_CTRL_4BITBUS;
102 else
103 ctrl &= ~SDHCI_CTRL_4BITBUS;
104 }
105 writew(tmp, host->ioaddr + SD_CE_ATA_2);
106 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
107
108 return 0;
109}
110
111static u32 pxav2_get_max_clock(struct sdhci_host *host)
112{
113 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
114
115 return clk_get_rate(pltfm_host->clk);
116}
117
118static struct sdhci_ops pxav2_sdhci_ops = {
119 .get_max_clock = pxav2_get_max_clock,
120 .platform_reset_exit = pxav2_set_private_registers,
121 .platform_8bit_width = pxav2_mmc_set_width,
122};
123
124static int __devinit sdhci_pxav2_probe(struct platform_device *pdev)
125{
126 struct sdhci_pltfm_host *pltfm_host;
127 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
128 struct device *dev = &pdev->dev;
129 struct sdhci_host *host = NULL;
130 struct sdhci_pxa *pxa = NULL;
131 int ret;
132 struct clk *clk;
133
134 pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
135 if (!pxa)
136 return -ENOMEM;
137
138 host = sdhci_pltfm_init(pdev, NULL);
139 if (IS_ERR(host)) {
140 kfree(pxa);
141 return PTR_ERR(host);
142 }
143 pltfm_host = sdhci_priv(host);
144 pltfm_host->priv = pxa;
145
146 clk = clk_get(dev, "PXA-SDHCLK");
147 if (IS_ERR(clk)) {
148 dev_err(dev, "failed to get io clock\n");
149 ret = PTR_ERR(clk);
150 goto err_clk_get;
151 }
152 pltfm_host->clk = clk;
153 clk_enable(clk);
154
155 host->quirks = SDHCI_QUIRK_BROKEN_ADMA
156 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
157 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
158
159 if (pdata) {
160 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
161 /* on-chip device */
162 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
163 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
164 }
165
166 /* If slot design supports 8 bit data, indicate this to MMC. */
167 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
168 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
169
170 if (pdata->quirks)
171 host->quirks |= pdata->quirks;
172 if (pdata->host_caps)
173 host->mmc->caps |= pdata->host_caps;
174 if (pdata->pm_caps)
175 host->mmc->pm_caps |= pdata->pm_caps;
176 }
177
178 host->ops = &pxav2_sdhci_ops;
179
180 ret = sdhci_add_host(host);
181 if (ret) {
182 dev_err(&pdev->dev, "failed to add host\n");
183 goto err_add_host;
184 }
185
186 platform_set_drvdata(pdev, host);
187
188 return 0;
189
190err_add_host:
191 clk_disable(clk);
192 clk_put(clk);
193err_clk_get:
194 sdhci_pltfm_free(pdev);
195 kfree(pxa);
196 return ret;
197}
198
199static int __devexit sdhci_pxav2_remove(struct platform_device *pdev)
200{
201 struct sdhci_host *host = platform_get_drvdata(pdev);
202 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
203 struct sdhci_pxa *pxa = pltfm_host->priv;
204
205 sdhci_remove_host(host, 1);
206
207 clk_disable(pltfm_host->clk);
208 clk_put(pltfm_host->clk);
209 sdhci_pltfm_free(pdev);
210 kfree(pxa);
211
212 platform_set_drvdata(pdev, NULL);
213
214 return 0;
215}
216
217static struct platform_driver sdhci_pxav2_driver = {
218 .driver = {
219 .name = "sdhci-pxav2",
220 .owner = THIS_MODULE,
221 .pm = SDHCI_PLTFM_PMOPS,
222 },
223 .probe = sdhci_pxav2_probe,
224 .remove = __devexit_p(sdhci_pxav2_remove),
225};
226
227module_platform_driver(sdhci_pxav2_driver);
228
229MODULE_DESCRIPTION("SDHCI driver for pxav2");
230MODULE_AUTHOR("Marvell International Ltd.");
231MODULE_LICENSE("GPL v2");
232
1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 * Zhangfei Gao <zhangfei.gao@marvell.com>
4 * Kevin Wang <dwang4@marvell.com>
5 * Jun Nie <njun@marvell.com>
6 * Qiming Wu <wuqm@marvell.com>
7 * Philip Rakity <prakity@marvell.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/mmc/card.h>
27#include <linux/mmc/host.h>
28#include <linux/platform_data/pxa_sdhci.h>
29#include <linux/slab.h>
30#include "sdhci.h"
31#include "sdhci-pltfm.h"
32
33#define SD_FIFO_PARAM 0xe0
34#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
35#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
36#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
37#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
38 CLK_GATE_ON | CLK_GATE_CTL)
39
40#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
41#define SDCLK_SEL_SHIFT 8
42#define SDCLK_SEL_MASK 0x3
43#define SDCLK_DELAY_SHIFT 10
44#define SDCLK_DELAY_MASK 0x3c
45
46#define SD_CE_ATA_2 0xea
47#define MMC_CARD 0x1000
48#define MMC_WIDTH 0x0100
49
50static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
51{
52 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
53 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
54
55 if (mask == SDHCI_RESET_ALL) {
56 u16 tmp = 0;
57
58 /*
59 * tune timing of read data/command when crc error happen
60 * no performance impact
61 */
62 if (pdata->clk_delay_sel == 1) {
63 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
64
65 tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
66 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
67 << SDCLK_DELAY_SHIFT;
68 tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
69 tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
70
71 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
72 }
73
74 if (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING) {
75 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
76 tmp &= ~CLK_GATE_SETTING_BITS;
77 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
78 } else {
79 tmp = readw(host->ioaddr + SD_FIFO_PARAM);
80 tmp &= ~CLK_GATE_SETTING_BITS;
81 tmp |= CLK_GATE_SETTING_BITS;
82 writew(tmp, host->ioaddr + SD_FIFO_PARAM);
83 }
84 }
85}
86
87static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
88{
89 u8 ctrl;
90 u16 tmp;
91
92 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
93 tmp = readw(host->ioaddr + SD_CE_ATA_2);
94 if (width == MMC_BUS_WIDTH_8) {
95 ctrl &= ~SDHCI_CTRL_4BITBUS;
96 tmp |= MMC_CARD | MMC_WIDTH;
97 } else {
98 tmp &= ~(MMC_CARD | MMC_WIDTH);
99 if (width == MMC_BUS_WIDTH_4)
100 ctrl |= SDHCI_CTRL_4BITBUS;
101 else
102 ctrl &= ~SDHCI_CTRL_4BITBUS;
103 }
104 writew(tmp, host->ioaddr + SD_CE_ATA_2);
105 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
106
107 return 0;
108}
109
110static u32 pxav2_get_max_clock(struct sdhci_host *host)
111{
112 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
113
114 return clk_get_rate(pltfm_host->clk);
115}
116
117static struct sdhci_ops pxav2_sdhci_ops = {
118 .get_max_clock = pxav2_get_max_clock,
119 .platform_reset_exit = pxav2_set_private_registers,
120 .platform_8bit_width = pxav2_mmc_set_width,
121};
122
123static int __devinit sdhci_pxav2_probe(struct platform_device *pdev)
124{
125 struct sdhci_pltfm_host *pltfm_host;
126 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
127 struct device *dev = &pdev->dev;
128 struct sdhci_host *host = NULL;
129 struct sdhci_pxa *pxa = NULL;
130 int ret;
131 struct clk *clk;
132
133 pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
134 if (!pxa)
135 return -ENOMEM;
136
137 host = sdhci_pltfm_init(pdev, NULL);
138 if (IS_ERR(host)) {
139 kfree(pxa);
140 return PTR_ERR(host);
141 }
142 pltfm_host = sdhci_priv(host);
143 pltfm_host->priv = pxa;
144
145 clk = clk_get(dev, "PXA-SDHCLK");
146 if (IS_ERR(clk)) {
147 dev_err(dev, "failed to get io clock\n");
148 ret = PTR_ERR(clk);
149 goto err_clk_get;
150 }
151 pltfm_host->clk = clk;
152 clk_enable(clk);
153
154 host->quirks = SDHCI_QUIRK_BROKEN_ADMA
155 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
156 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
157
158 if (pdata) {
159 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
160 /* on-chip device */
161 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
162 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
163 }
164
165 /* If slot design supports 8 bit data, indicate this to MMC. */
166 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
167 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
168
169 if (pdata->quirks)
170 host->quirks |= pdata->quirks;
171 if (pdata->host_caps)
172 host->mmc->caps |= pdata->host_caps;
173 if (pdata->pm_caps)
174 host->mmc->pm_caps |= pdata->pm_caps;
175 }
176
177 host->ops = &pxav2_sdhci_ops;
178
179 ret = sdhci_add_host(host);
180 if (ret) {
181 dev_err(&pdev->dev, "failed to add host\n");
182 goto err_add_host;
183 }
184
185 platform_set_drvdata(pdev, host);
186
187 return 0;
188
189err_add_host:
190 clk_disable(clk);
191 clk_put(clk);
192err_clk_get:
193 sdhci_pltfm_free(pdev);
194 kfree(pxa);
195 return ret;
196}
197
198static int __devexit sdhci_pxav2_remove(struct platform_device *pdev)
199{
200 struct sdhci_host *host = platform_get_drvdata(pdev);
201 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
202 struct sdhci_pxa *pxa = pltfm_host->priv;
203
204 sdhci_remove_host(host, 1);
205
206 clk_disable(pltfm_host->clk);
207 clk_put(pltfm_host->clk);
208 sdhci_pltfm_free(pdev);
209 kfree(pxa);
210
211 platform_set_drvdata(pdev, NULL);
212
213 return 0;
214}
215
216static struct platform_driver sdhci_pxav2_driver = {
217 .driver = {
218 .name = "sdhci-pxav2",
219 .owner = THIS_MODULE,
220 },
221 .probe = sdhci_pxav2_probe,
222 .remove = __devexit_p(sdhci_pxav2_remove),
223#ifdef CONFIG_PM
224 .suspend = sdhci_pltfm_suspend,
225 .resume = sdhci_pltfm_resume,
226#endif
227};
228static int __init sdhci_pxav2_init(void)
229{
230 return platform_driver_register(&sdhci_pxav2_driver);
231}
232
233static void __exit sdhci_pxav2_exit(void)
234{
235 platform_driver_unregister(&sdhci_pxav2_driver);
236}
237
238module_init(sdhci_pxav2_init);
239module_exit(sdhci_pxav2_exit);
240
241MODULE_DESCRIPTION("SDHCI driver for pxav2");
242MODULE_AUTHOR("Marvell International Ltd.");
243MODULE_LICENSE("GPL v2");
244