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1/*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/platform_device.h>
30#include <linux/delay.h>
31#include <linux/interrupt.h>
32#include <linux/dma-mapping.h>
33#include <linux/dmaengine.h>
34#include <linux/highmem.h>
35#include <linux/clk.h>
36#include <linux/err.h>
37#include <linux/completion.h>
38#include <linux/mmc/host.h>
39#include <linux/mmc/mmc.h>
40#include <linux/mmc/sdio.h>
41#include <linux/gpio.h>
42#include <linux/regulator/consumer.h>
43#include <linux/module.h>
44#include <linux/fsl/mxs-dma.h>
45#include <linux/pinctrl/consumer.h>
46#include <linux/stmp_device.h>
47#include <linux/mmc/mxs-mmc.h>
48
49#define DRIVER_NAME "mxs-mmc"
50
51/* card detect polling timeout */
52#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
53
54#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
55
56/* SSP registers */
57#define HW_SSP_CTRL0 0x000
58#define BM_SSP_CTRL0_RUN (1 << 29)
59#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
60#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
61#define BM_SSP_CTRL0_READ (1 << 25)
62#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
63#define BP_SSP_CTRL0_BUS_WIDTH (22)
64#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
65#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
66#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
67#define BM_SSP_CTRL0_GET_RESP (1 << 17)
68#define BM_SSP_CTRL0_ENABLE (1 << 16)
69#define BP_SSP_CTRL0_XFER_COUNT (0)
70#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
71#define HW_SSP_CMD0 0x010
72#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
73#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
74#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
75#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
76#define BP_SSP_CMD0_BLOCK_SIZE (16)
77#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
78#define BP_SSP_CMD0_BLOCK_COUNT (8)
79#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
80#define BP_SSP_CMD0_CMD (0)
81#define BM_SSP_CMD0_CMD (0xff)
82#define HW_SSP_CMD1 0x020
83#define HW_SSP_XFER_SIZE 0x030
84#define HW_SSP_BLOCK_SIZE 0x040
85#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
86#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
87#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
88#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
89#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
90#define BP_SSP_TIMING_TIMEOUT (16)
91#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
92#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
93#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
94#define BP_SSP_TIMING_CLOCK_RATE (0)
95#define BM_SSP_TIMING_CLOCK_RATE (0xff)
96#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
97#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
98#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
99#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
100#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
101#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
102#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
103#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
104#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
105#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
106#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
107#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
108#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
109#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
110#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
111#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
112#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
113#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
114#define BM_SSP_CTRL1_POLARITY (1 << 9)
115#define BP_SSP_CTRL1_WORD_LENGTH (4)
116#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
117#define BP_SSP_CTRL1_SSP_MODE (0)
118#define BM_SSP_CTRL1_SSP_MODE (0xf)
119#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
120#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
121#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
122#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
123#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
124#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
125#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
126
127#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
128
129#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
130 BM_SSP_CTRL1_RESP_ERR_IRQ | \
131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
132 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_CRC_IRQ | \
134 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
137
138#define SSP_PIO_NUM 3
139
140enum mxs_mmc_id {
141 IMX23_MMC,
142 IMX28_MMC,
143};
144
145struct mxs_mmc_host {
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150
151 void __iomem *base;
152 int dma_channel;
153 struct clk *clk;
154 unsigned int clk_rate;
155
156 struct dma_chan *dmach;
157 struct mxs_dma_data dma_data;
158 unsigned int dma_dir;
159 enum dma_transfer_direction slave_dirn;
160 u32 ssp_pio_words[SSP_PIO_NUM];
161
162 enum mxs_mmc_id devid;
163 unsigned char bus_width;
164 spinlock_t lock;
165 int sdio_irq_en;
166 int wp_gpio;
167};
168
169static int mxs_mmc_get_ro(struct mmc_host *mmc)
170{
171 struct mxs_mmc_host *host = mmc_priv(mmc);
172
173 if (!gpio_is_valid(host->wp_gpio))
174 return -EINVAL;
175
176 return gpio_get_value(host->wp_gpio);
177}
178
179static int mxs_mmc_get_cd(struct mmc_host *mmc)
180{
181 struct mxs_mmc_host *host = mmc_priv(mmc);
182
183 return !(readl(host->base + HW_SSP_STATUS(host)) &
184 BM_SSP_STATUS_CARD_DETECT);
185}
186
187static void mxs_mmc_reset(struct mxs_mmc_host *host)
188{
189 u32 ctrl0, ctrl1;
190
191 stmp_reset_block(host->base);
192
193 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
194 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
195 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
196 BM_SSP_CTRL1_DMA_ENABLE |
197 BM_SSP_CTRL1_POLARITY |
198 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
199 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
200 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
201 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
202 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
203
204 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
205 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
206 BF_SSP(0, TIMING_CLOCK_RATE),
207 host->base + HW_SSP_TIMING(host));
208
209 if (host->sdio_irq_en) {
210 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
211 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
212 }
213
214 writel(ctrl0, host->base + HW_SSP_CTRL0);
215 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
216}
217
218static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
219 struct mmc_command *cmd);
220
221static void mxs_mmc_request_done(struct mxs_mmc_host *host)
222{
223 struct mmc_command *cmd = host->cmd;
224 struct mmc_data *data = host->data;
225 struct mmc_request *mrq = host->mrq;
226
227 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
228 if (mmc_resp_type(cmd) & MMC_RSP_136) {
229 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
230 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
231 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
232 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
233 } else {
234 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
235 }
236 }
237
238 if (data) {
239 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
240 data->sg_len, host->dma_dir);
241 /*
242 * If there was an error on any block, we mark all
243 * data blocks as being in error.
244 */
245 if (!data->error)
246 data->bytes_xfered = data->blocks * data->blksz;
247 else
248 data->bytes_xfered = 0;
249
250 host->data = NULL;
251 if (mrq->stop) {
252 mxs_mmc_start_cmd(host, mrq->stop);
253 return;
254 }
255 }
256
257 host->mrq = NULL;
258 mmc_request_done(host->mmc, mrq);
259}
260
261static void mxs_mmc_dma_irq_callback(void *param)
262{
263 struct mxs_mmc_host *host = param;
264
265 mxs_mmc_request_done(host);
266}
267
268static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
269{
270 struct mxs_mmc_host *host = dev_id;
271 struct mmc_command *cmd = host->cmd;
272 struct mmc_data *data = host->data;
273 u32 stat;
274
275 spin_lock(&host->lock);
276
277 stat = readl(host->base + HW_SSP_CTRL1(host));
278 writel(stat & MXS_MMC_IRQ_BITS,
279 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
280
281 spin_unlock(&host->lock);
282
283 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
284 mmc_signal_sdio_irq(host->mmc);
285
286 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
287 cmd->error = -ETIMEDOUT;
288 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
289 cmd->error = -EIO;
290
291 if (data) {
292 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
293 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
294 data->error = -ETIMEDOUT;
295 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
296 data->error = -EILSEQ;
297 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
298 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
299 data->error = -EIO;
300 }
301
302 return IRQ_HANDLED;
303}
304
305static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
306 struct mxs_mmc_host *host, unsigned long flags)
307{
308 struct dma_async_tx_descriptor *desc;
309 struct mmc_data *data = host->data;
310 struct scatterlist * sgl;
311 unsigned int sg_len;
312
313 if (data) {
314 /* data */
315 dma_map_sg(mmc_dev(host->mmc), data->sg,
316 data->sg_len, host->dma_dir);
317 sgl = data->sg;
318 sg_len = data->sg_len;
319 } else {
320 /* pio */
321 sgl = (struct scatterlist *) host->ssp_pio_words;
322 sg_len = SSP_PIO_NUM;
323 }
324
325 desc = dmaengine_prep_slave_sg(host->dmach,
326 sgl, sg_len, host->slave_dirn, flags);
327 if (desc) {
328 desc->callback = mxs_mmc_dma_irq_callback;
329 desc->callback_param = host;
330 } else {
331 if (data)
332 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
333 data->sg_len, host->dma_dir);
334 }
335
336 return desc;
337}
338
339static void mxs_mmc_bc(struct mxs_mmc_host *host)
340{
341 struct mmc_command *cmd = host->cmd;
342 struct dma_async_tx_descriptor *desc;
343 u32 ctrl0, cmd0, cmd1;
344
345 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
346 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
347 cmd1 = cmd->arg;
348
349 if (host->sdio_irq_en) {
350 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
351 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
352 }
353
354 host->ssp_pio_words[0] = ctrl0;
355 host->ssp_pio_words[1] = cmd0;
356 host->ssp_pio_words[2] = cmd1;
357 host->dma_dir = DMA_NONE;
358 host->slave_dirn = DMA_TRANS_NONE;
359 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
360 if (!desc)
361 goto out;
362
363 dmaengine_submit(desc);
364 dma_async_issue_pending(host->dmach);
365 return;
366
367out:
368 dev_warn(mmc_dev(host->mmc),
369 "%s: failed to prep dma\n", __func__);
370}
371
372static void mxs_mmc_ac(struct mxs_mmc_host *host)
373{
374 struct mmc_command *cmd = host->cmd;
375 struct dma_async_tx_descriptor *desc;
376 u32 ignore_crc, get_resp, long_resp;
377 u32 ctrl0, cmd0, cmd1;
378
379 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
380 0 : BM_SSP_CTRL0_IGNORE_CRC;
381 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
382 BM_SSP_CTRL0_GET_RESP : 0;
383 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
384 BM_SSP_CTRL0_LONG_RESP : 0;
385
386 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
387 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
388 cmd1 = cmd->arg;
389
390 if (host->sdio_irq_en) {
391 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
392 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
393 }
394
395 host->ssp_pio_words[0] = ctrl0;
396 host->ssp_pio_words[1] = cmd0;
397 host->ssp_pio_words[2] = cmd1;
398 host->dma_dir = DMA_NONE;
399 host->slave_dirn = DMA_TRANS_NONE;
400 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
401 if (!desc)
402 goto out;
403
404 dmaengine_submit(desc);
405 dma_async_issue_pending(host->dmach);
406 return;
407
408out:
409 dev_warn(mmc_dev(host->mmc),
410 "%s: failed to prep dma\n", __func__);
411}
412
413static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
414{
415 const unsigned int ssp_timeout_mul = 4096;
416 /*
417 * Calculate ticks in ms since ns are large numbers
418 * and might overflow
419 */
420 const unsigned int clock_per_ms = clock_rate / 1000;
421 const unsigned int ms = ns / 1000;
422 const unsigned int ticks = ms * clock_per_ms;
423 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
424
425 WARN_ON(ssp_ticks == 0);
426 return ssp_ticks;
427}
428
429static void mxs_mmc_adtc(struct mxs_mmc_host *host)
430{
431 struct mmc_command *cmd = host->cmd;
432 struct mmc_data *data = cmd->data;
433 struct dma_async_tx_descriptor *desc;
434 struct scatterlist *sgl = data->sg, *sg;
435 unsigned int sg_len = data->sg_len;
436 int i;
437
438 unsigned short dma_data_dir, timeout;
439 enum dma_transfer_direction slave_dirn;
440 unsigned int data_size = 0, log2_blksz;
441 unsigned int blocks = data->blocks;
442
443 u32 ignore_crc, get_resp, long_resp, read;
444 u32 ctrl0, cmd0, cmd1, val;
445
446 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
447 0 : BM_SSP_CTRL0_IGNORE_CRC;
448 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
449 BM_SSP_CTRL0_GET_RESP : 0;
450 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
451 BM_SSP_CTRL0_LONG_RESP : 0;
452
453 if (data->flags & MMC_DATA_WRITE) {
454 dma_data_dir = DMA_TO_DEVICE;
455 slave_dirn = DMA_MEM_TO_DEV;
456 read = 0;
457 } else {
458 dma_data_dir = DMA_FROM_DEVICE;
459 slave_dirn = DMA_DEV_TO_MEM;
460 read = BM_SSP_CTRL0_READ;
461 }
462
463 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
464 ignore_crc | get_resp | long_resp |
465 BM_SSP_CTRL0_DATA_XFER | read |
466 BM_SSP_CTRL0_WAIT_FOR_IRQ |
467 BM_SSP_CTRL0_ENABLE;
468
469 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
470
471 /* get logarithm to base 2 of block size for setting register */
472 log2_blksz = ilog2(data->blksz);
473
474 /*
475 * take special care of the case that data size from data->sg
476 * is not equal to blocks x blksz
477 */
478 for_each_sg(sgl, sg, sg_len, i)
479 data_size += sg->length;
480
481 if (data_size != data->blocks * data->blksz)
482 blocks = 1;
483
484 /* xfer count, block size and count need to be set differently */
485 if (ssp_is_old(host)) {
486 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
487 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
488 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
489 } else {
490 writel(data_size, host->base + HW_SSP_XFER_SIZE);
491 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
492 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
493 host->base + HW_SSP_BLOCK_SIZE);
494 }
495
496 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
497 (cmd->opcode == SD_IO_RW_EXTENDED))
498 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
499
500 cmd1 = cmd->arg;
501
502 if (host->sdio_irq_en) {
503 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
504 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
505 }
506
507 /* set the timeout count */
508 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
509 val = readl(host->base + HW_SSP_TIMING(host));
510 val &= ~(BM_SSP_TIMING_TIMEOUT);
511 val |= BF_SSP(timeout, TIMING_TIMEOUT);
512 writel(val, host->base + HW_SSP_TIMING(host));
513
514 /* pio */
515 host->ssp_pio_words[0] = ctrl0;
516 host->ssp_pio_words[1] = cmd0;
517 host->ssp_pio_words[2] = cmd1;
518 host->dma_dir = DMA_NONE;
519 host->slave_dirn = DMA_TRANS_NONE;
520 desc = mxs_mmc_prep_dma(host, 0);
521 if (!desc)
522 goto out;
523
524 /* append data sg */
525 WARN_ON(host->data != NULL);
526 host->data = data;
527 host->dma_dir = dma_data_dir;
528 host->slave_dirn = slave_dirn;
529 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
530 if (!desc)
531 goto out;
532
533 dmaengine_submit(desc);
534 dma_async_issue_pending(host->dmach);
535 return;
536out:
537 dev_warn(mmc_dev(host->mmc),
538 "%s: failed to prep dma\n", __func__);
539}
540
541static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
542 struct mmc_command *cmd)
543{
544 host->cmd = cmd;
545
546 switch (mmc_cmd_type(cmd)) {
547 case MMC_CMD_BC:
548 mxs_mmc_bc(host);
549 break;
550 case MMC_CMD_BCR:
551 mxs_mmc_ac(host);
552 break;
553 case MMC_CMD_AC:
554 mxs_mmc_ac(host);
555 break;
556 case MMC_CMD_ADTC:
557 mxs_mmc_adtc(host);
558 break;
559 default:
560 dev_warn(mmc_dev(host->mmc),
561 "%s: unknown MMC command\n", __func__);
562 break;
563 }
564}
565
566static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
567{
568 struct mxs_mmc_host *host = mmc_priv(mmc);
569
570 WARN_ON(host->mrq != NULL);
571 host->mrq = mrq;
572 mxs_mmc_start_cmd(host, mrq->cmd);
573}
574
575static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
576{
577 unsigned int ssp_clk, ssp_sck;
578 u32 clock_divide, clock_rate;
579 u32 val;
580
581 ssp_clk = clk_get_rate(host->clk);
582
583 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
584 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
585 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
586 if (clock_rate <= 255)
587 break;
588 }
589
590 if (clock_divide > 254) {
591 dev_err(mmc_dev(host->mmc),
592 "%s: cannot set clock to %d\n", __func__, rate);
593 return;
594 }
595
596 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
597
598 val = readl(host->base + HW_SSP_TIMING(host));
599 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
600 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
601 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
602 writel(val, host->base + HW_SSP_TIMING(host));
603
604 host->clk_rate = ssp_sck;
605
606 dev_dbg(mmc_dev(host->mmc),
607 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
608 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
609}
610
611static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
612{
613 struct mxs_mmc_host *host = mmc_priv(mmc);
614
615 if (ios->bus_width == MMC_BUS_WIDTH_8)
616 host->bus_width = 2;
617 else if (ios->bus_width == MMC_BUS_WIDTH_4)
618 host->bus_width = 1;
619 else
620 host->bus_width = 0;
621
622 if (ios->clock)
623 mxs_mmc_set_clk_rate(host, ios->clock);
624}
625
626static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
627{
628 struct mxs_mmc_host *host = mmc_priv(mmc);
629 unsigned long flags;
630
631 spin_lock_irqsave(&host->lock, flags);
632
633 host->sdio_irq_en = enable;
634
635 if (enable) {
636 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
637 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
638 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
639 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
640 } else {
641 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
642 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
643 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
644 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
645 }
646
647 spin_unlock_irqrestore(&host->lock, flags);
648
649 if (enable && readl(host->base + HW_SSP_STATUS(host)) &
650 BM_SSP_STATUS_SDIO_IRQ)
651 mmc_signal_sdio_irq(host->mmc);
652
653}
654
655static const struct mmc_host_ops mxs_mmc_ops = {
656 .request = mxs_mmc_request,
657 .get_ro = mxs_mmc_get_ro,
658 .get_cd = mxs_mmc_get_cd,
659 .set_ios = mxs_mmc_set_ios,
660 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
661};
662
663static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
664{
665 struct mxs_mmc_host *host = param;
666
667 if (!mxs_dma_is_apbh(chan))
668 return false;
669
670 if (chan->chan_id != host->dma_channel)
671 return false;
672
673 chan->private = &host->dma_data;
674
675 return true;
676}
677
678static struct platform_device_id mxs_mmc_ids[] = {
679 {
680 .name = "imx23-mmc",
681 .driver_data = IMX23_MMC,
682 }, {
683 .name = "imx28-mmc",
684 .driver_data = IMX28_MMC,
685 }, {
686 /* sentinel */
687 }
688};
689MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
690
691static const struct of_device_id mxs_mmc_dt_ids[] = {
692 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, },
693 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, },
694 { /* sentinel */ }
695};
696MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
697
698static int mxs_mmc_probe(struct platform_device *pdev)
699{
700 const struct of_device_id *of_id =
701 of_match_device(mxs_mmc_dt_ids, &pdev->dev);
702 struct device_node *np = pdev->dev.of_node;
703 struct mxs_mmc_host *host;
704 struct mmc_host *mmc;
705 struct resource *iores, *dmares;
706 struct mxs_mmc_platform_data *pdata;
707 struct pinctrl *pinctrl;
708 int ret = 0, irq_err, irq_dma;
709 dma_cap_mask_t mask;
710
711 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
713 irq_err = platform_get_irq(pdev, 0);
714 irq_dma = platform_get_irq(pdev, 1);
715 if (!iores || irq_err < 0 || irq_dma < 0)
716 return -EINVAL;
717
718 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
719 if (!mmc)
720 return -ENOMEM;
721
722 host = mmc_priv(mmc);
723 host->base = devm_request_and_ioremap(&pdev->dev, iores);
724 if (!host->base) {
725 ret = -EADDRNOTAVAIL;
726 goto out_mmc_free;
727 }
728
729 if (np) {
730 host->devid = (enum mxs_mmc_id) of_id->data;
731 /*
732 * TODO: This is a temporary solution and should be changed
733 * to use generic DMA binding later when the helpers get in.
734 */
735 ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
736 &host->dma_channel);
737 if (ret) {
738 dev_err(mmc_dev(host->mmc),
739 "failed to get dma channel\n");
740 goto out_mmc_free;
741 }
742 } else {
743 host->devid = pdev->id_entry->driver_data;
744 host->dma_channel = dmares->start;
745 }
746
747 host->mmc = mmc;
748 host->sdio_irq_en = 0;
749
750 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
751 if (IS_ERR(pinctrl)) {
752 ret = PTR_ERR(pinctrl);
753 goto out_mmc_free;
754 }
755
756 host->clk = clk_get(&pdev->dev, NULL);
757 if (IS_ERR(host->clk)) {
758 ret = PTR_ERR(host->clk);
759 goto out_mmc_free;
760 }
761 clk_prepare_enable(host->clk);
762
763 mxs_mmc_reset(host);
764
765 dma_cap_zero(mask);
766 dma_cap_set(DMA_SLAVE, mask);
767 host->dma_data.chan_irq = irq_dma;
768 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
769 if (!host->dmach) {
770 dev_err(mmc_dev(host->mmc),
771 "%s: failed to request dma\n", __func__);
772 goto out_clk_put;
773 }
774
775 /* set mmc core parameters */
776 mmc->ops = &mxs_mmc_ops;
777 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
778 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
779
780 pdata = mmc_dev(host->mmc)->platform_data;
781 if (!pdata) {
782 u32 bus_width = 0;
783 of_property_read_u32(np, "bus-width", &bus_width);
784 if (bus_width == 4)
785 mmc->caps |= MMC_CAP_4_BIT_DATA;
786 else if (bus_width == 8)
787 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
788 host->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
789 } else {
790 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
791 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
792 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
793 mmc->caps |= MMC_CAP_4_BIT_DATA;
794 host->wp_gpio = pdata->wp_gpio;
795 }
796
797 mmc->f_min = 400000;
798 mmc->f_max = 288000000;
799 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
800
801 mmc->max_segs = 52;
802 mmc->max_blk_size = 1 << 0xf;
803 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
804 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
805 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
806
807 platform_set_drvdata(pdev, mmc);
808
809 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
810 DRIVER_NAME, host);
811 if (ret)
812 goto out_free_dma;
813
814 spin_lock_init(&host->lock);
815
816 ret = mmc_add_host(mmc);
817 if (ret)
818 goto out_free_dma;
819
820 dev_info(mmc_dev(host->mmc), "initialized\n");
821
822 return 0;
823
824out_free_dma:
825 if (host->dmach)
826 dma_release_channel(host->dmach);
827out_clk_put:
828 clk_disable_unprepare(host->clk);
829 clk_put(host->clk);
830out_mmc_free:
831 mmc_free_host(mmc);
832 return ret;
833}
834
835static int mxs_mmc_remove(struct platform_device *pdev)
836{
837 struct mmc_host *mmc = platform_get_drvdata(pdev);
838 struct mxs_mmc_host *host = mmc_priv(mmc);
839
840 mmc_remove_host(mmc);
841
842 platform_set_drvdata(pdev, NULL);
843
844 if (host->dmach)
845 dma_release_channel(host->dmach);
846
847 clk_disable_unprepare(host->clk);
848 clk_put(host->clk);
849
850 mmc_free_host(mmc);
851
852 return 0;
853}
854
855#ifdef CONFIG_PM
856static int mxs_mmc_suspend(struct device *dev)
857{
858 struct mmc_host *mmc = dev_get_drvdata(dev);
859 struct mxs_mmc_host *host = mmc_priv(mmc);
860 int ret = 0;
861
862 ret = mmc_suspend_host(mmc);
863
864 clk_disable_unprepare(host->clk);
865
866 return ret;
867}
868
869static int mxs_mmc_resume(struct device *dev)
870{
871 struct mmc_host *mmc = dev_get_drvdata(dev);
872 struct mxs_mmc_host *host = mmc_priv(mmc);
873 int ret = 0;
874
875 clk_prepare_enable(host->clk);
876
877 ret = mmc_resume_host(mmc);
878
879 return ret;
880}
881
882static const struct dev_pm_ops mxs_mmc_pm_ops = {
883 .suspend = mxs_mmc_suspend,
884 .resume = mxs_mmc_resume,
885};
886#endif
887
888static struct platform_driver mxs_mmc_driver = {
889 .probe = mxs_mmc_probe,
890 .remove = mxs_mmc_remove,
891 .id_table = mxs_mmc_ids,
892 .driver = {
893 .name = DRIVER_NAME,
894 .owner = THIS_MODULE,
895#ifdef CONFIG_PM
896 .pm = &mxs_mmc_pm_ops,
897#endif
898 .of_match_table = mxs_mmc_dt_ids,
899 },
900};
901
902module_platform_driver(mxs_mmc_driver);
903
904MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
905MODULE_AUTHOR("Freescale Semiconductor");
906MODULE_LICENSE("GPL");
1/*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmaengine.h>
31#include <linux/highmem.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/completion.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/sdio.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
40
41#include <mach/mxs.h>
42#include <mach/common.h>
43#include <mach/dma.h>
44#include <mach/mmc.h>
45
46#define DRIVER_NAME "mxs-mmc"
47
48/* card detect polling timeout */
49#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
50
51#define SSP_VERSION_LATEST 4
52#define ssp_is_old() (host->version < SSP_VERSION_LATEST)
53
54/* SSP registers */
55#define HW_SSP_CTRL0 0x000
56#define BM_SSP_CTRL0_RUN (1 << 29)
57#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
58#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
59#define BM_SSP_CTRL0_READ (1 << 25)
60#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
61#define BP_SSP_CTRL0_BUS_WIDTH (22)
62#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
63#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
64#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
65#define BM_SSP_CTRL0_GET_RESP (1 << 17)
66#define BM_SSP_CTRL0_ENABLE (1 << 16)
67#define BP_SSP_CTRL0_XFER_COUNT (0)
68#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
69#define HW_SSP_CMD0 0x010
70#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
71#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
72#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
73#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
74#define BP_SSP_CMD0_BLOCK_SIZE (16)
75#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
76#define BP_SSP_CMD0_BLOCK_COUNT (8)
77#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
78#define BP_SSP_CMD0_CMD (0)
79#define BM_SSP_CMD0_CMD (0xff)
80#define HW_SSP_CMD1 0x020
81#define HW_SSP_XFER_SIZE 0x030
82#define HW_SSP_BLOCK_SIZE 0x040
83#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
84#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
85#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
86#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
87#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
88#define BP_SSP_TIMING_TIMEOUT (16)
89#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
90#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
91#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
92#define BP_SSP_TIMING_CLOCK_RATE (0)
93#define BM_SSP_TIMING_CLOCK_RATE (0xff)
94#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
95#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
96#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
97#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
98#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
99#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
100#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
101#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
102#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
103#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
104#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
105#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
106#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
107#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
108#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
109#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
110#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
111#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
112#define BM_SSP_CTRL1_POLARITY (1 << 9)
113#define BP_SSP_CTRL1_WORD_LENGTH (4)
114#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
115#define BP_SSP_CTRL1_SSP_MODE (0)
116#define BM_SSP_CTRL1_SSP_MODE (0xf)
117#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
118#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
119#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
120#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
121#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
122#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
123#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
124#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
125#define BP_SSP_VERSION_MAJOR (24)
126
127#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
128
129#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
130 BM_SSP_CTRL1_RESP_ERR_IRQ | \
131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
132 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_CRC_IRQ | \
134 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
137
138#define SSP_PIO_NUM 3
139
140struct mxs_mmc_host {
141 struct mmc_host *mmc;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
145
146 void __iomem *base;
147 int irq;
148 struct resource *res;
149 struct resource *dma_res;
150 struct clk *clk;
151 unsigned int clk_rate;
152
153 struct dma_chan *dmach;
154 struct mxs_dma_data dma_data;
155 unsigned int dma_dir;
156 u32 ssp_pio_words[SSP_PIO_NUM];
157
158 unsigned int version;
159 unsigned char bus_width;
160 spinlock_t lock;
161 int sdio_irq_en;
162};
163
164static int mxs_mmc_get_ro(struct mmc_host *mmc)
165{
166 struct mxs_mmc_host *host = mmc_priv(mmc);
167 struct mxs_mmc_platform_data *pdata =
168 mmc_dev(host->mmc)->platform_data;
169
170 if (!pdata)
171 return -EFAULT;
172
173 if (!gpio_is_valid(pdata->wp_gpio))
174 return -EINVAL;
175
176 return gpio_get_value(pdata->wp_gpio);
177}
178
179static int mxs_mmc_get_cd(struct mmc_host *mmc)
180{
181 struct mxs_mmc_host *host = mmc_priv(mmc);
182
183 return !(readl(host->base + HW_SSP_STATUS) &
184 BM_SSP_STATUS_CARD_DETECT);
185}
186
187static void mxs_mmc_reset(struct mxs_mmc_host *host)
188{
189 u32 ctrl0, ctrl1;
190
191 mxs_reset_block(host->base);
192
193 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
194 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
195 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
196 BM_SSP_CTRL1_DMA_ENABLE |
197 BM_SSP_CTRL1_POLARITY |
198 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
199 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
200 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
201 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
202 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
203
204 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
205 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
206 BF_SSP(0, TIMING_CLOCK_RATE),
207 host->base + HW_SSP_TIMING);
208
209 if (host->sdio_irq_en) {
210 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
211 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
212 }
213
214 writel(ctrl0, host->base + HW_SSP_CTRL0);
215 writel(ctrl1, host->base + HW_SSP_CTRL1);
216}
217
218static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
219 struct mmc_command *cmd);
220
221static void mxs_mmc_request_done(struct mxs_mmc_host *host)
222{
223 struct mmc_command *cmd = host->cmd;
224 struct mmc_data *data = host->data;
225 struct mmc_request *mrq = host->mrq;
226
227 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
228 if (mmc_resp_type(cmd) & MMC_RSP_136) {
229 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
230 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
231 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
232 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
233 } else {
234 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
235 }
236 }
237
238 if (data) {
239 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
240 data->sg_len, host->dma_dir);
241 /*
242 * If there was an error on any block, we mark all
243 * data blocks as being in error.
244 */
245 if (!data->error)
246 data->bytes_xfered = data->blocks * data->blksz;
247 else
248 data->bytes_xfered = 0;
249
250 host->data = NULL;
251 if (mrq->stop) {
252 mxs_mmc_start_cmd(host, mrq->stop);
253 return;
254 }
255 }
256
257 host->mrq = NULL;
258 mmc_request_done(host->mmc, mrq);
259}
260
261static void mxs_mmc_dma_irq_callback(void *param)
262{
263 struct mxs_mmc_host *host = param;
264
265 mxs_mmc_request_done(host);
266}
267
268static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
269{
270 struct mxs_mmc_host *host = dev_id;
271 struct mmc_command *cmd = host->cmd;
272 struct mmc_data *data = host->data;
273 u32 stat;
274
275 spin_lock(&host->lock);
276
277 stat = readl(host->base + HW_SSP_CTRL1);
278 writel(stat & MXS_MMC_IRQ_BITS,
279 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
280
281 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
282 mmc_signal_sdio_irq(host->mmc);
283
284 spin_unlock(&host->lock);
285
286 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
287 cmd->error = -ETIMEDOUT;
288 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
289 cmd->error = -EIO;
290
291 if (data) {
292 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
293 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
294 data->error = -ETIMEDOUT;
295 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
296 data->error = -EILSEQ;
297 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
298 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
299 data->error = -EIO;
300 }
301
302 return IRQ_HANDLED;
303}
304
305static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
306 struct mxs_mmc_host *host, unsigned int append)
307{
308 struct dma_async_tx_descriptor *desc;
309 struct mmc_data *data = host->data;
310 struct scatterlist * sgl;
311 unsigned int sg_len;
312
313 if (data) {
314 /* data */
315 dma_map_sg(mmc_dev(host->mmc), data->sg,
316 data->sg_len, host->dma_dir);
317 sgl = data->sg;
318 sg_len = data->sg_len;
319 } else {
320 /* pio */
321 sgl = (struct scatterlist *) host->ssp_pio_words;
322 sg_len = SSP_PIO_NUM;
323 }
324
325 desc = host->dmach->device->device_prep_slave_sg(host->dmach,
326 sgl, sg_len, host->dma_dir, append);
327 if (desc) {
328 desc->callback = mxs_mmc_dma_irq_callback;
329 desc->callback_param = host;
330 } else {
331 if (data)
332 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
333 data->sg_len, host->dma_dir);
334 }
335
336 return desc;
337}
338
339static void mxs_mmc_bc(struct mxs_mmc_host *host)
340{
341 struct mmc_command *cmd = host->cmd;
342 struct dma_async_tx_descriptor *desc;
343 u32 ctrl0, cmd0, cmd1;
344
345 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
346 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
347 cmd1 = cmd->arg;
348
349 if (host->sdio_irq_en) {
350 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
351 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
352 }
353
354 host->ssp_pio_words[0] = ctrl0;
355 host->ssp_pio_words[1] = cmd0;
356 host->ssp_pio_words[2] = cmd1;
357 host->dma_dir = DMA_NONE;
358 desc = mxs_mmc_prep_dma(host, 0);
359 if (!desc)
360 goto out;
361
362 dmaengine_submit(desc);
363 return;
364
365out:
366 dev_warn(mmc_dev(host->mmc),
367 "%s: failed to prep dma\n", __func__);
368}
369
370static void mxs_mmc_ac(struct mxs_mmc_host *host)
371{
372 struct mmc_command *cmd = host->cmd;
373 struct dma_async_tx_descriptor *desc;
374 u32 ignore_crc, get_resp, long_resp;
375 u32 ctrl0, cmd0, cmd1;
376
377 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
378 0 : BM_SSP_CTRL0_IGNORE_CRC;
379 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
380 BM_SSP_CTRL0_GET_RESP : 0;
381 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
382 BM_SSP_CTRL0_LONG_RESP : 0;
383
384 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
385 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
386 cmd1 = cmd->arg;
387
388 if (host->sdio_irq_en) {
389 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
390 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
391 }
392
393 host->ssp_pio_words[0] = ctrl0;
394 host->ssp_pio_words[1] = cmd0;
395 host->ssp_pio_words[2] = cmd1;
396 host->dma_dir = DMA_NONE;
397 desc = mxs_mmc_prep_dma(host, 0);
398 if (!desc)
399 goto out;
400
401 dmaengine_submit(desc);
402 return;
403
404out:
405 dev_warn(mmc_dev(host->mmc),
406 "%s: failed to prep dma\n", __func__);
407}
408
409static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
410{
411 const unsigned int ssp_timeout_mul = 4096;
412 /*
413 * Calculate ticks in ms since ns are large numbers
414 * and might overflow
415 */
416 const unsigned int clock_per_ms = clock_rate / 1000;
417 const unsigned int ms = ns / 1000;
418 const unsigned int ticks = ms * clock_per_ms;
419 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
420
421 WARN_ON(ssp_ticks == 0);
422 return ssp_ticks;
423}
424
425static void mxs_mmc_adtc(struct mxs_mmc_host *host)
426{
427 struct mmc_command *cmd = host->cmd;
428 struct mmc_data *data = cmd->data;
429 struct dma_async_tx_descriptor *desc;
430 struct scatterlist *sgl = data->sg, *sg;
431 unsigned int sg_len = data->sg_len;
432 int i;
433
434 unsigned short dma_data_dir, timeout;
435 unsigned int data_size = 0, log2_blksz;
436 unsigned int blocks = data->blocks;
437
438 u32 ignore_crc, get_resp, long_resp, read;
439 u32 ctrl0, cmd0, cmd1, val;
440
441 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
442 0 : BM_SSP_CTRL0_IGNORE_CRC;
443 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
444 BM_SSP_CTRL0_GET_RESP : 0;
445 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
446 BM_SSP_CTRL0_LONG_RESP : 0;
447
448 if (data->flags & MMC_DATA_WRITE) {
449 dma_data_dir = DMA_TO_DEVICE;
450 read = 0;
451 } else {
452 dma_data_dir = DMA_FROM_DEVICE;
453 read = BM_SSP_CTRL0_READ;
454 }
455
456 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
457 ignore_crc | get_resp | long_resp |
458 BM_SSP_CTRL0_DATA_XFER | read |
459 BM_SSP_CTRL0_WAIT_FOR_IRQ |
460 BM_SSP_CTRL0_ENABLE;
461
462 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
463
464 /* get logarithm to base 2 of block size for setting register */
465 log2_blksz = ilog2(data->blksz);
466
467 /*
468 * take special care of the case that data size from data->sg
469 * is not equal to blocks x blksz
470 */
471 for_each_sg(sgl, sg, sg_len, i)
472 data_size += sg->length;
473
474 if (data_size != data->blocks * data->blksz)
475 blocks = 1;
476
477 /* xfer count, block size and count need to be set differently */
478 if (ssp_is_old()) {
479 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
480 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
481 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
482 } else {
483 writel(data_size, host->base + HW_SSP_XFER_SIZE);
484 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
485 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
486 host->base + HW_SSP_BLOCK_SIZE);
487 }
488
489 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
490 (cmd->opcode == SD_IO_RW_EXTENDED))
491 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
492
493 cmd1 = cmd->arg;
494
495 if (host->sdio_irq_en) {
496 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
497 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
498 }
499
500 /* set the timeout count */
501 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
502 val = readl(host->base + HW_SSP_TIMING);
503 val &= ~(BM_SSP_TIMING_TIMEOUT);
504 val |= BF_SSP(timeout, TIMING_TIMEOUT);
505 writel(val, host->base + HW_SSP_TIMING);
506
507 /* pio */
508 host->ssp_pio_words[0] = ctrl0;
509 host->ssp_pio_words[1] = cmd0;
510 host->ssp_pio_words[2] = cmd1;
511 host->dma_dir = DMA_NONE;
512 desc = mxs_mmc_prep_dma(host, 0);
513 if (!desc)
514 goto out;
515
516 /* append data sg */
517 WARN_ON(host->data != NULL);
518 host->data = data;
519 host->dma_dir = dma_data_dir;
520 desc = mxs_mmc_prep_dma(host, 1);
521 if (!desc)
522 goto out;
523
524 dmaengine_submit(desc);
525 return;
526out:
527 dev_warn(mmc_dev(host->mmc),
528 "%s: failed to prep dma\n", __func__);
529}
530
531static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
532 struct mmc_command *cmd)
533{
534 host->cmd = cmd;
535
536 switch (mmc_cmd_type(cmd)) {
537 case MMC_CMD_BC:
538 mxs_mmc_bc(host);
539 break;
540 case MMC_CMD_BCR:
541 mxs_mmc_ac(host);
542 break;
543 case MMC_CMD_AC:
544 mxs_mmc_ac(host);
545 break;
546 case MMC_CMD_ADTC:
547 mxs_mmc_adtc(host);
548 break;
549 default:
550 dev_warn(mmc_dev(host->mmc),
551 "%s: unknown MMC command\n", __func__);
552 break;
553 }
554}
555
556static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
557{
558 struct mxs_mmc_host *host = mmc_priv(mmc);
559
560 WARN_ON(host->mrq != NULL);
561 host->mrq = mrq;
562 mxs_mmc_start_cmd(host, mrq->cmd);
563}
564
565static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
566{
567 unsigned int ssp_clk, ssp_sck;
568 u32 clock_divide, clock_rate;
569 u32 val;
570
571 ssp_clk = clk_get_rate(host->clk);
572
573 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
574 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
575 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
576 if (clock_rate <= 255)
577 break;
578 }
579
580 if (clock_divide > 254) {
581 dev_err(mmc_dev(host->mmc),
582 "%s: cannot set clock to %d\n", __func__, rate);
583 return;
584 }
585
586 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
587
588 val = readl(host->base + HW_SSP_TIMING);
589 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
590 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
591 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
592 writel(val, host->base + HW_SSP_TIMING);
593
594 host->clk_rate = ssp_sck;
595
596 dev_dbg(mmc_dev(host->mmc),
597 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
598 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
599}
600
601static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
602{
603 struct mxs_mmc_host *host = mmc_priv(mmc);
604
605 if (ios->bus_width == MMC_BUS_WIDTH_8)
606 host->bus_width = 2;
607 else if (ios->bus_width == MMC_BUS_WIDTH_4)
608 host->bus_width = 1;
609 else
610 host->bus_width = 0;
611
612 if (ios->clock)
613 mxs_mmc_set_clk_rate(host, ios->clock);
614}
615
616static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
617{
618 struct mxs_mmc_host *host = mmc_priv(mmc);
619 unsigned long flags;
620
621 spin_lock_irqsave(&host->lock, flags);
622
623 host->sdio_irq_en = enable;
624
625 if (enable) {
626 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
627 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
628 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
629 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
630
631 if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
632 mmc_signal_sdio_irq(host->mmc);
633
634 } else {
635 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
636 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
637 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
638 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
639 }
640
641 spin_unlock_irqrestore(&host->lock, flags);
642}
643
644static const struct mmc_host_ops mxs_mmc_ops = {
645 .request = mxs_mmc_request,
646 .get_ro = mxs_mmc_get_ro,
647 .get_cd = mxs_mmc_get_cd,
648 .set_ios = mxs_mmc_set_ios,
649 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
650};
651
652static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
653{
654 struct mxs_mmc_host *host = param;
655
656 if (!mxs_dma_is_apbh(chan))
657 return false;
658
659 if (chan->chan_id != host->dma_res->start)
660 return false;
661
662 chan->private = &host->dma_data;
663
664 return true;
665}
666
667static int mxs_mmc_probe(struct platform_device *pdev)
668{
669 struct mxs_mmc_host *host;
670 struct mmc_host *mmc;
671 struct resource *iores, *dmares, *r;
672 struct mxs_mmc_platform_data *pdata;
673 int ret = 0, irq_err, irq_dma;
674 dma_cap_mask_t mask;
675
676 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
677 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
678 irq_err = platform_get_irq(pdev, 0);
679 irq_dma = platform_get_irq(pdev, 1);
680 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
681 return -EINVAL;
682
683 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
684 if (!r)
685 return -EBUSY;
686
687 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
688 if (!mmc) {
689 ret = -ENOMEM;
690 goto out_release_mem;
691 }
692
693 host = mmc_priv(mmc);
694 host->base = ioremap(r->start, resource_size(r));
695 if (!host->base) {
696 ret = -ENOMEM;
697 goto out_mmc_free;
698 }
699
700 /* only major verion does matter */
701 host->version = readl(host->base + HW_SSP_VERSION) >>
702 BP_SSP_VERSION_MAJOR;
703
704 host->mmc = mmc;
705 host->res = r;
706 host->dma_res = dmares;
707 host->irq = irq_err;
708 host->sdio_irq_en = 0;
709
710 host->clk = clk_get(&pdev->dev, NULL);
711 if (IS_ERR(host->clk)) {
712 ret = PTR_ERR(host->clk);
713 goto out_iounmap;
714 }
715 clk_enable(host->clk);
716
717 mxs_mmc_reset(host);
718
719 dma_cap_zero(mask);
720 dma_cap_set(DMA_SLAVE, mask);
721 host->dma_data.chan_irq = irq_dma;
722 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
723 if (!host->dmach) {
724 dev_err(mmc_dev(host->mmc),
725 "%s: failed to request dma\n", __func__);
726 goto out_clk_put;
727 }
728
729 /* set mmc core parameters */
730 mmc->ops = &mxs_mmc_ops;
731 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
732 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
733
734 pdata = mmc_dev(host->mmc)->platform_data;
735 if (pdata) {
736 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
737 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
738 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
739 mmc->caps |= MMC_CAP_4_BIT_DATA;
740 }
741
742 mmc->f_min = 400000;
743 mmc->f_max = 288000000;
744 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
745
746 mmc->max_segs = 52;
747 mmc->max_blk_size = 1 << 0xf;
748 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
749 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
750 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
751
752 platform_set_drvdata(pdev, mmc);
753
754 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
755 if (ret)
756 goto out_free_dma;
757
758 spin_lock_init(&host->lock);
759
760 ret = mmc_add_host(mmc);
761 if (ret)
762 goto out_free_irq;
763
764 dev_info(mmc_dev(host->mmc), "initialized\n");
765
766 return 0;
767
768out_free_irq:
769 free_irq(host->irq, host);
770out_free_dma:
771 if (host->dmach)
772 dma_release_channel(host->dmach);
773out_clk_put:
774 clk_disable(host->clk);
775 clk_put(host->clk);
776out_iounmap:
777 iounmap(host->base);
778out_mmc_free:
779 mmc_free_host(mmc);
780out_release_mem:
781 release_mem_region(iores->start, resource_size(iores));
782 return ret;
783}
784
785static int mxs_mmc_remove(struct platform_device *pdev)
786{
787 struct mmc_host *mmc = platform_get_drvdata(pdev);
788 struct mxs_mmc_host *host = mmc_priv(mmc);
789 struct resource *res = host->res;
790
791 mmc_remove_host(mmc);
792
793 free_irq(host->irq, host);
794
795 platform_set_drvdata(pdev, NULL);
796
797 if (host->dmach)
798 dma_release_channel(host->dmach);
799
800 clk_disable(host->clk);
801 clk_put(host->clk);
802
803 iounmap(host->base);
804
805 mmc_free_host(mmc);
806
807 release_mem_region(res->start, resource_size(res));
808
809 return 0;
810}
811
812#ifdef CONFIG_PM
813static int mxs_mmc_suspend(struct device *dev)
814{
815 struct mmc_host *mmc = dev_get_drvdata(dev);
816 struct mxs_mmc_host *host = mmc_priv(mmc);
817 int ret = 0;
818
819 ret = mmc_suspend_host(mmc);
820
821 clk_disable(host->clk);
822
823 return ret;
824}
825
826static int mxs_mmc_resume(struct device *dev)
827{
828 struct mmc_host *mmc = dev_get_drvdata(dev);
829 struct mxs_mmc_host *host = mmc_priv(mmc);
830 int ret = 0;
831
832 clk_enable(host->clk);
833
834 ret = mmc_resume_host(mmc);
835
836 return ret;
837}
838
839static const struct dev_pm_ops mxs_mmc_pm_ops = {
840 .suspend = mxs_mmc_suspend,
841 .resume = mxs_mmc_resume,
842};
843#endif
844
845static struct platform_driver mxs_mmc_driver = {
846 .probe = mxs_mmc_probe,
847 .remove = mxs_mmc_remove,
848 .driver = {
849 .name = DRIVER_NAME,
850 .owner = THIS_MODULE,
851#ifdef CONFIG_PM
852 .pm = &mxs_mmc_pm_ops,
853#endif
854 },
855};
856
857static int __init mxs_mmc_init(void)
858{
859 return platform_driver_register(&mxs_mmc_driver);
860}
861
862static void __exit mxs_mmc_exit(void)
863{
864 platform_driver_unregister(&mxs_mmc_driver);
865}
866
867module_init(mxs_mmc_init);
868module_exit(mxs_mmc_exit);
869
870MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
871MODULE_AUTHOR("Freescale Semiconductor");
872MODULE_LICENSE("GPL");