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1#include <linux/bitops.h>
2#include <linux/types.h>
3#include <linux/slab.h>
4
5#include <asm/perf_event.h>
6#include <asm/insn.h>
7
8#include "perf_event.h"
9
10/* The size of a BTS record in bytes: */
11#define BTS_RECORD_SIZE 24
12
13#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14#define PEBS_BUFFER_SIZE PAGE_SIZE
15
16/*
17 * pebs_record_32 for p4 and core not supported
18
19struct pebs_record_32 {
20 u32 flags, ip;
21 u32 ax, bc, cx, dx;
22 u32 si, di, bp, sp;
23};
24
25 */
26
27struct pebs_record_core {
28 u64 flags, ip;
29 u64 ax, bx, cx, dx;
30 u64 si, di, bp, sp;
31 u64 r8, r9, r10, r11;
32 u64 r12, r13, r14, r15;
33};
34
35struct pebs_record_nhm {
36 u64 flags, ip;
37 u64 ax, bx, cx, dx;
38 u64 si, di, bp, sp;
39 u64 r8, r9, r10, r11;
40 u64 r12, r13, r14, r15;
41 u64 status, dla, dse, lat;
42};
43
44void init_debug_store_on_cpu(int cpu)
45{
46 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
47
48 if (!ds)
49 return;
50
51 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
52 (u32)((u64)(unsigned long)ds),
53 (u32)((u64)(unsigned long)ds >> 32));
54}
55
56void fini_debug_store_on_cpu(int cpu)
57{
58 if (!per_cpu(cpu_hw_events, cpu).ds)
59 return;
60
61 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
62}
63
64static int alloc_pebs_buffer(int cpu)
65{
66 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
67 int node = cpu_to_node(cpu);
68 int max, thresh = 1; /* always use a single PEBS record */
69 void *buffer;
70
71 if (!x86_pmu.pebs)
72 return 0;
73
74 buffer = kmalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
75 if (unlikely(!buffer))
76 return -ENOMEM;
77
78 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
79
80 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
81 ds->pebs_index = ds->pebs_buffer_base;
82 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
83 max * x86_pmu.pebs_record_size;
84
85 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
86 thresh * x86_pmu.pebs_record_size;
87
88 return 0;
89}
90
91static void release_pebs_buffer(int cpu)
92{
93 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
94
95 if (!ds || !x86_pmu.pebs)
96 return;
97
98 kfree((void *)(unsigned long)ds->pebs_buffer_base);
99 ds->pebs_buffer_base = 0;
100}
101
102static int alloc_bts_buffer(int cpu)
103{
104 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
105 int node = cpu_to_node(cpu);
106 int max, thresh;
107 void *buffer;
108
109 if (!x86_pmu.bts)
110 return 0;
111
112 buffer = kmalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
113 if (unlikely(!buffer))
114 return -ENOMEM;
115
116 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
117 thresh = max / 16;
118
119 ds->bts_buffer_base = (u64)(unsigned long)buffer;
120 ds->bts_index = ds->bts_buffer_base;
121 ds->bts_absolute_maximum = ds->bts_buffer_base +
122 max * BTS_RECORD_SIZE;
123 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
124 thresh * BTS_RECORD_SIZE;
125
126 return 0;
127}
128
129static void release_bts_buffer(int cpu)
130{
131 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
132
133 if (!ds || !x86_pmu.bts)
134 return;
135
136 kfree((void *)(unsigned long)ds->bts_buffer_base);
137 ds->bts_buffer_base = 0;
138}
139
140static int alloc_ds_buffer(int cpu)
141{
142 int node = cpu_to_node(cpu);
143 struct debug_store *ds;
144
145 ds = kmalloc_node(sizeof(*ds), GFP_KERNEL | __GFP_ZERO, node);
146 if (unlikely(!ds))
147 return -ENOMEM;
148
149 per_cpu(cpu_hw_events, cpu).ds = ds;
150
151 return 0;
152}
153
154static void release_ds_buffer(int cpu)
155{
156 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
157
158 if (!ds)
159 return;
160
161 per_cpu(cpu_hw_events, cpu).ds = NULL;
162 kfree(ds);
163}
164
165void release_ds_buffers(void)
166{
167 int cpu;
168
169 if (!x86_pmu.bts && !x86_pmu.pebs)
170 return;
171
172 get_online_cpus();
173 for_each_online_cpu(cpu)
174 fini_debug_store_on_cpu(cpu);
175
176 for_each_possible_cpu(cpu) {
177 release_pebs_buffer(cpu);
178 release_bts_buffer(cpu);
179 release_ds_buffer(cpu);
180 }
181 put_online_cpus();
182}
183
184void reserve_ds_buffers(void)
185{
186 int bts_err = 0, pebs_err = 0;
187 int cpu;
188
189 x86_pmu.bts_active = 0;
190 x86_pmu.pebs_active = 0;
191
192 if (!x86_pmu.bts && !x86_pmu.pebs)
193 return;
194
195 if (!x86_pmu.bts)
196 bts_err = 1;
197
198 if (!x86_pmu.pebs)
199 pebs_err = 1;
200
201 get_online_cpus();
202
203 for_each_possible_cpu(cpu) {
204 if (alloc_ds_buffer(cpu)) {
205 bts_err = 1;
206 pebs_err = 1;
207 }
208
209 if (!bts_err && alloc_bts_buffer(cpu))
210 bts_err = 1;
211
212 if (!pebs_err && alloc_pebs_buffer(cpu))
213 pebs_err = 1;
214
215 if (bts_err && pebs_err)
216 break;
217 }
218
219 if (bts_err) {
220 for_each_possible_cpu(cpu)
221 release_bts_buffer(cpu);
222 }
223
224 if (pebs_err) {
225 for_each_possible_cpu(cpu)
226 release_pebs_buffer(cpu);
227 }
228
229 if (bts_err && pebs_err) {
230 for_each_possible_cpu(cpu)
231 release_ds_buffer(cpu);
232 } else {
233 if (x86_pmu.bts && !bts_err)
234 x86_pmu.bts_active = 1;
235
236 if (x86_pmu.pebs && !pebs_err)
237 x86_pmu.pebs_active = 1;
238
239 for_each_online_cpu(cpu)
240 init_debug_store_on_cpu(cpu);
241 }
242
243 put_online_cpus();
244}
245
246/*
247 * BTS
248 */
249
250struct event_constraint bts_constraint =
251 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
252
253void intel_pmu_enable_bts(u64 config)
254{
255 unsigned long debugctlmsr;
256
257 debugctlmsr = get_debugctlmsr();
258
259 debugctlmsr |= DEBUGCTLMSR_TR;
260 debugctlmsr |= DEBUGCTLMSR_BTS;
261 debugctlmsr |= DEBUGCTLMSR_BTINT;
262
263 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
264 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
265
266 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
267 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
268
269 update_debugctlmsr(debugctlmsr);
270}
271
272void intel_pmu_disable_bts(void)
273{
274 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
275 unsigned long debugctlmsr;
276
277 if (!cpuc->ds)
278 return;
279
280 debugctlmsr = get_debugctlmsr();
281
282 debugctlmsr &=
283 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
284 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
285
286 update_debugctlmsr(debugctlmsr);
287}
288
289int intel_pmu_drain_bts_buffer(void)
290{
291 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
292 struct debug_store *ds = cpuc->ds;
293 struct bts_record {
294 u64 from;
295 u64 to;
296 u64 flags;
297 };
298 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
299 struct bts_record *at, *top;
300 struct perf_output_handle handle;
301 struct perf_event_header header;
302 struct perf_sample_data data;
303 struct pt_regs regs;
304
305 if (!event)
306 return 0;
307
308 if (!x86_pmu.bts_active)
309 return 0;
310
311 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
312 top = (struct bts_record *)(unsigned long)ds->bts_index;
313
314 if (top <= at)
315 return 0;
316
317 ds->bts_index = ds->bts_buffer_base;
318
319 perf_sample_data_init(&data, 0, event->hw.last_period);
320 regs.ip = 0;
321
322 /*
323 * Prepare a generic sample, i.e. fill in the invariant fields.
324 * We will overwrite the from and to address before we output
325 * the sample.
326 */
327 perf_prepare_sample(&header, &data, event, ®s);
328
329 if (perf_output_begin(&handle, event, header.size * (top - at)))
330 return 1;
331
332 for (; at < top; at++) {
333 data.ip = at->from;
334 data.addr = at->to;
335
336 perf_output_sample(&handle, &header, &data, event);
337 }
338
339 perf_output_end(&handle);
340
341 /* There's new data available. */
342 event->hw.interrupts++;
343 event->pending_kill = POLL_IN;
344 return 1;
345}
346
347/*
348 * PEBS
349 */
350struct event_constraint intel_core2_pebs_event_constraints[] = {
351 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
352 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
353 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
354 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
355 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
356 EVENT_CONSTRAINT_END
357};
358
359struct event_constraint intel_atom_pebs_event_constraints[] = {
360 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
361 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
362 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
363 EVENT_CONSTRAINT_END
364};
365
366struct event_constraint intel_nehalem_pebs_event_constraints[] = {
367 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
368 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
369 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
370 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
371 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
372 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
373 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
374 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
375 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
376 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
377 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
378 EVENT_CONSTRAINT_END
379};
380
381struct event_constraint intel_westmere_pebs_event_constraints[] = {
382 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
383 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
384 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
385 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
386 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
387 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
388 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
389 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
390 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
391 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
392 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
393 EVENT_CONSTRAINT_END
394};
395
396struct event_constraint intel_snb_pebs_event_constraints[] = {
397 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
398 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
399 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
400 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
401 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
402 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
403 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
404 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
405 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
406 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
407 EVENT_CONSTRAINT_END
408};
409
410struct event_constraint *intel_pebs_constraints(struct perf_event *event)
411{
412 struct event_constraint *c;
413
414 if (!event->attr.precise_ip)
415 return NULL;
416
417 if (x86_pmu.pebs_constraints) {
418 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
419 if ((event->hw.config & c->cmask) == c->code)
420 return c;
421 }
422 }
423
424 return &emptyconstraint;
425}
426
427void intel_pmu_pebs_enable(struct perf_event *event)
428{
429 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
430 struct hw_perf_event *hwc = &event->hw;
431
432 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
433
434 cpuc->pebs_enabled |= 1ULL << hwc->idx;
435}
436
437void intel_pmu_pebs_disable(struct perf_event *event)
438{
439 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
440 struct hw_perf_event *hwc = &event->hw;
441
442 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
443 if (cpuc->enabled)
444 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
445
446 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
447}
448
449void intel_pmu_pebs_enable_all(void)
450{
451 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
452
453 if (cpuc->pebs_enabled)
454 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
455}
456
457void intel_pmu_pebs_disable_all(void)
458{
459 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
460
461 if (cpuc->pebs_enabled)
462 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
463}
464
465static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
466{
467 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
468 unsigned long from = cpuc->lbr_entries[0].from;
469 unsigned long old_to, to = cpuc->lbr_entries[0].to;
470 unsigned long ip = regs->ip;
471 int is_64bit = 0;
472
473 /*
474 * We don't need to fixup if the PEBS assist is fault like
475 */
476 if (!x86_pmu.intel_cap.pebs_trap)
477 return 1;
478
479 /*
480 * No LBR entry, no basic block, no rewinding
481 */
482 if (!cpuc->lbr_stack.nr || !from || !to)
483 return 0;
484
485 /*
486 * Basic blocks should never cross user/kernel boundaries
487 */
488 if (kernel_ip(ip) != kernel_ip(to))
489 return 0;
490
491 /*
492 * unsigned math, either ip is before the start (impossible) or
493 * the basic block is larger than 1 page (sanity)
494 */
495 if ((ip - to) > PAGE_SIZE)
496 return 0;
497
498 /*
499 * We sampled a branch insn, rewind using the LBR stack
500 */
501 if (ip == to) {
502 regs->ip = from;
503 return 1;
504 }
505
506 do {
507 struct insn insn;
508 u8 buf[MAX_INSN_SIZE];
509 void *kaddr;
510
511 old_to = to;
512 if (!kernel_ip(ip)) {
513 int bytes, size = MAX_INSN_SIZE;
514
515 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
516 if (bytes != size)
517 return 0;
518
519 kaddr = buf;
520 } else
521 kaddr = (void *)to;
522
523#ifdef CONFIG_X86_64
524 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
525#endif
526 insn_init(&insn, kaddr, is_64bit);
527 insn_get_length(&insn);
528 to += insn.length;
529 } while (to < ip);
530
531 if (to == ip) {
532 regs->ip = old_to;
533 return 1;
534 }
535
536 /*
537 * Even though we decoded the basic block, the instruction stream
538 * never matched the given IP, either the TO or the IP got corrupted.
539 */
540 return 0;
541}
542
543static void __intel_pmu_pebs_event(struct perf_event *event,
544 struct pt_regs *iregs, void *__pebs)
545{
546 /*
547 * We cast to pebs_record_core since that is a subset of
548 * both formats and we don't use the other fields in this
549 * routine.
550 */
551 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
552 struct pebs_record_core *pebs = __pebs;
553 struct perf_sample_data data;
554 struct pt_regs regs;
555
556 if (!intel_pmu_save_and_restart(event))
557 return;
558
559 perf_sample_data_init(&data, 0, event->hw.last_period);
560
561 /*
562 * We use the interrupt regs as a base because the PEBS record
563 * does not contain a full regs set, specifically it seems to
564 * lack segment descriptors, which get used by things like
565 * user_mode().
566 *
567 * In the simple case fix up only the IP and BP,SP regs, for
568 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
569 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
570 */
571 regs = *iregs;
572 regs.ip = pebs->ip;
573 regs.bp = pebs->bp;
574 regs.sp = pebs->sp;
575
576 if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
577 regs.flags |= PERF_EFLAGS_EXACT;
578 else
579 regs.flags &= ~PERF_EFLAGS_EXACT;
580
581 if (has_branch_stack(event))
582 data.br_stack = &cpuc->lbr_stack;
583
584 if (perf_event_overflow(event, &data, ®s))
585 x86_pmu_stop(event, 0);
586}
587
588static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
589{
590 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
591 struct debug_store *ds = cpuc->ds;
592 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
593 struct pebs_record_core *at, *top;
594 int n;
595
596 if (!x86_pmu.pebs_active)
597 return;
598
599 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
600 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
601
602 /*
603 * Whatever else happens, drain the thing
604 */
605 ds->pebs_index = ds->pebs_buffer_base;
606
607 if (!test_bit(0, cpuc->active_mask))
608 return;
609
610 WARN_ON_ONCE(!event);
611
612 if (!event->attr.precise_ip)
613 return;
614
615 n = top - at;
616 if (n <= 0)
617 return;
618
619 /*
620 * Should not happen, we program the threshold at 1 and do not
621 * set a reset value.
622 */
623 WARN_ON_ONCE(n > 1);
624 at += n - 1;
625
626 __intel_pmu_pebs_event(event, iregs, at);
627}
628
629static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
630{
631 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
632 struct debug_store *ds = cpuc->ds;
633 struct pebs_record_nhm *at, *top;
634 struct perf_event *event = NULL;
635 u64 status = 0;
636 int bit, n;
637
638 if (!x86_pmu.pebs_active)
639 return;
640
641 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
642 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
643
644 ds->pebs_index = ds->pebs_buffer_base;
645
646 n = top - at;
647 if (n <= 0)
648 return;
649
650 /*
651 * Should not happen, we program the threshold at 1 and do not
652 * set a reset value.
653 */
654 WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
655
656 for ( ; at < top; at++) {
657 for_each_set_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
658 event = cpuc->events[bit];
659 if (!test_bit(bit, cpuc->active_mask))
660 continue;
661
662 WARN_ON_ONCE(!event);
663
664 if (!event->attr.precise_ip)
665 continue;
666
667 if (__test_and_set_bit(bit, (unsigned long *)&status))
668 continue;
669
670 break;
671 }
672
673 if (!event || bit >= MAX_PEBS_EVENTS)
674 continue;
675
676 __intel_pmu_pebs_event(event, iregs, at);
677 }
678}
679
680/*
681 * BTS, PEBS probe and setup
682 */
683
684void intel_ds_init(void)
685{
686 /*
687 * No support for 32bit formats
688 */
689 if (!boot_cpu_has(X86_FEATURE_DTES64))
690 return;
691
692 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
693 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
694 if (x86_pmu.pebs) {
695 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
696 int format = x86_pmu.intel_cap.pebs_format;
697
698 switch (format) {
699 case 0:
700 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
701 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
702 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
703 break;
704
705 case 1:
706 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
707 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
708 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
709 break;
710
711 default:
712 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
713 x86_pmu.pebs = 0;
714 }
715 }
716}
1#ifdef CONFIG_CPU_SUP_INTEL
2
3/* The maximal number of PEBS events: */
4#define MAX_PEBS_EVENTS 4
5
6/* The size of a BTS record in bytes: */
7#define BTS_RECORD_SIZE 24
8
9#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
10#define PEBS_BUFFER_SIZE PAGE_SIZE
11
12/*
13 * pebs_record_32 for p4 and core not supported
14
15struct pebs_record_32 {
16 u32 flags, ip;
17 u32 ax, bc, cx, dx;
18 u32 si, di, bp, sp;
19};
20
21 */
22
23struct pebs_record_core {
24 u64 flags, ip;
25 u64 ax, bx, cx, dx;
26 u64 si, di, bp, sp;
27 u64 r8, r9, r10, r11;
28 u64 r12, r13, r14, r15;
29};
30
31struct pebs_record_nhm {
32 u64 flags, ip;
33 u64 ax, bx, cx, dx;
34 u64 si, di, bp, sp;
35 u64 r8, r9, r10, r11;
36 u64 r12, r13, r14, r15;
37 u64 status, dla, dse, lat;
38};
39
40/*
41 * A debug store configuration.
42 *
43 * We only support architectures that use 64bit fields.
44 */
45struct debug_store {
46 u64 bts_buffer_base;
47 u64 bts_index;
48 u64 bts_absolute_maximum;
49 u64 bts_interrupt_threshold;
50 u64 pebs_buffer_base;
51 u64 pebs_index;
52 u64 pebs_absolute_maximum;
53 u64 pebs_interrupt_threshold;
54 u64 pebs_event_reset[MAX_PEBS_EVENTS];
55};
56
57static void init_debug_store_on_cpu(int cpu)
58{
59 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
60
61 if (!ds)
62 return;
63
64 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
65 (u32)((u64)(unsigned long)ds),
66 (u32)((u64)(unsigned long)ds >> 32));
67}
68
69static void fini_debug_store_on_cpu(int cpu)
70{
71 if (!per_cpu(cpu_hw_events, cpu).ds)
72 return;
73
74 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
75}
76
77static int alloc_pebs_buffer(int cpu)
78{
79 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
80 int node = cpu_to_node(cpu);
81 int max, thresh = 1; /* always use a single PEBS record */
82 void *buffer;
83
84 if (!x86_pmu.pebs)
85 return 0;
86
87 buffer = kmalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
88 if (unlikely(!buffer))
89 return -ENOMEM;
90
91 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
92
93 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
94 ds->pebs_index = ds->pebs_buffer_base;
95 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
96 max * x86_pmu.pebs_record_size;
97
98 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
99 thresh * x86_pmu.pebs_record_size;
100
101 return 0;
102}
103
104static void release_pebs_buffer(int cpu)
105{
106 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
107
108 if (!ds || !x86_pmu.pebs)
109 return;
110
111 kfree((void *)(unsigned long)ds->pebs_buffer_base);
112 ds->pebs_buffer_base = 0;
113}
114
115static int alloc_bts_buffer(int cpu)
116{
117 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
118 int node = cpu_to_node(cpu);
119 int max, thresh;
120 void *buffer;
121
122 if (!x86_pmu.bts)
123 return 0;
124
125 buffer = kmalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_ZERO, node);
126 if (unlikely(!buffer))
127 return -ENOMEM;
128
129 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
130 thresh = max / 16;
131
132 ds->bts_buffer_base = (u64)(unsigned long)buffer;
133 ds->bts_index = ds->bts_buffer_base;
134 ds->bts_absolute_maximum = ds->bts_buffer_base +
135 max * BTS_RECORD_SIZE;
136 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
137 thresh * BTS_RECORD_SIZE;
138
139 return 0;
140}
141
142static void release_bts_buffer(int cpu)
143{
144 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
145
146 if (!ds || !x86_pmu.bts)
147 return;
148
149 kfree((void *)(unsigned long)ds->bts_buffer_base);
150 ds->bts_buffer_base = 0;
151}
152
153static int alloc_ds_buffer(int cpu)
154{
155 int node = cpu_to_node(cpu);
156 struct debug_store *ds;
157
158 ds = kmalloc_node(sizeof(*ds), GFP_KERNEL | __GFP_ZERO, node);
159 if (unlikely(!ds))
160 return -ENOMEM;
161
162 per_cpu(cpu_hw_events, cpu).ds = ds;
163
164 return 0;
165}
166
167static void release_ds_buffer(int cpu)
168{
169 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
170
171 if (!ds)
172 return;
173
174 per_cpu(cpu_hw_events, cpu).ds = NULL;
175 kfree(ds);
176}
177
178static void release_ds_buffers(void)
179{
180 int cpu;
181
182 if (!x86_pmu.bts && !x86_pmu.pebs)
183 return;
184
185 get_online_cpus();
186 for_each_online_cpu(cpu)
187 fini_debug_store_on_cpu(cpu);
188
189 for_each_possible_cpu(cpu) {
190 release_pebs_buffer(cpu);
191 release_bts_buffer(cpu);
192 release_ds_buffer(cpu);
193 }
194 put_online_cpus();
195}
196
197static void reserve_ds_buffers(void)
198{
199 int bts_err = 0, pebs_err = 0;
200 int cpu;
201
202 x86_pmu.bts_active = 0;
203 x86_pmu.pebs_active = 0;
204
205 if (!x86_pmu.bts && !x86_pmu.pebs)
206 return;
207
208 if (!x86_pmu.bts)
209 bts_err = 1;
210
211 if (!x86_pmu.pebs)
212 pebs_err = 1;
213
214 get_online_cpus();
215
216 for_each_possible_cpu(cpu) {
217 if (alloc_ds_buffer(cpu)) {
218 bts_err = 1;
219 pebs_err = 1;
220 }
221
222 if (!bts_err && alloc_bts_buffer(cpu))
223 bts_err = 1;
224
225 if (!pebs_err && alloc_pebs_buffer(cpu))
226 pebs_err = 1;
227
228 if (bts_err && pebs_err)
229 break;
230 }
231
232 if (bts_err) {
233 for_each_possible_cpu(cpu)
234 release_bts_buffer(cpu);
235 }
236
237 if (pebs_err) {
238 for_each_possible_cpu(cpu)
239 release_pebs_buffer(cpu);
240 }
241
242 if (bts_err && pebs_err) {
243 for_each_possible_cpu(cpu)
244 release_ds_buffer(cpu);
245 } else {
246 if (x86_pmu.bts && !bts_err)
247 x86_pmu.bts_active = 1;
248
249 if (x86_pmu.pebs && !pebs_err)
250 x86_pmu.pebs_active = 1;
251
252 for_each_online_cpu(cpu)
253 init_debug_store_on_cpu(cpu);
254 }
255
256 put_online_cpus();
257}
258
259/*
260 * BTS
261 */
262
263static struct event_constraint bts_constraint =
264 EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
265
266static void intel_pmu_enable_bts(u64 config)
267{
268 unsigned long debugctlmsr;
269
270 debugctlmsr = get_debugctlmsr();
271
272 debugctlmsr |= DEBUGCTLMSR_TR;
273 debugctlmsr |= DEBUGCTLMSR_BTS;
274 debugctlmsr |= DEBUGCTLMSR_BTINT;
275
276 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
277 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
278
279 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
280 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
281
282 update_debugctlmsr(debugctlmsr);
283}
284
285static void intel_pmu_disable_bts(void)
286{
287 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
288 unsigned long debugctlmsr;
289
290 if (!cpuc->ds)
291 return;
292
293 debugctlmsr = get_debugctlmsr();
294
295 debugctlmsr &=
296 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
297 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
298
299 update_debugctlmsr(debugctlmsr);
300}
301
302static int intel_pmu_drain_bts_buffer(void)
303{
304 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
305 struct debug_store *ds = cpuc->ds;
306 struct bts_record {
307 u64 from;
308 u64 to;
309 u64 flags;
310 };
311 struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
312 struct bts_record *at, *top;
313 struct perf_output_handle handle;
314 struct perf_event_header header;
315 struct perf_sample_data data;
316 struct pt_regs regs;
317
318 if (!event)
319 return 0;
320
321 if (!x86_pmu.bts_active)
322 return 0;
323
324 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
325 top = (struct bts_record *)(unsigned long)ds->bts_index;
326
327 if (top <= at)
328 return 0;
329
330 ds->bts_index = ds->bts_buffer_base;
331
332 perf_sample_data_init(&data, 0);
333 data.period = event->hw.last_period;
334 regs.ip = 0;
335
336 /*
337 * Prepare a generic sample, i.e. fill in the invariant fields.
338 * We will overwrite the from and to address before we output
339 * the sample.
340 */
341 perf_prepare_sample(&header, &data, event, ®s);
342
343 if (perf_output_begin(&handle, event, header.size * (top - at)))
344 return 1;
345
346 for (; at < top; at++) {
347 data.ip = at->from;
348 data.addr = at->to;
349
350 perf_output_sample(&handle, &header, &data, event);
351 }
352
353 perf_output_end(&handle);
354
355 /* There's new data available. */
356 event->hw.interrupts++;
357 event->pending_kill = POLL_IN;
358 return 1;
359}
360
361/*
362 * PEBS
363 */
364static struct event_constraint intel_core2_pebs_event_constraints[] = {
365 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
366 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
367 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
368 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
369 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
370 EVENT_CONSTRAINT_END
371};
372
373static struct event_constraint intel_atom_pebs_event_constraints[] = {
374 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
375 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
376 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
377 EVENT_CONSTRAINT_END
378};
379
380static struct event_constraint intel_nehalem_pebs_event_constraints[] = {
381 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
382 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
383 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
384 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
385 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
386 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
387 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
388 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
389 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
390 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
391 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
392 EVENT_CONSTRAINT_END
393};
394
395static struct event_constraint intel_westmere_pebs_event_constraints[] = {
396 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
397 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
398 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
399 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
400 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
401 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
402 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
403 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
404 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
405 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
406 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
407 EVENT_CONSTRAINT_END
408};
409
410static struct event_constraint intel_snb_pebs_events[] = {
411 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
412 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
413 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
414 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
415 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
416 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
417 INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_LOADS */
418 INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_STORES */
419 INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOP_RETIRED.LOCK_LOADS */
420 INTEL_UEVENT_CONSTRAINT(0x22d0, 0xf), /* MEM_UOP_RETIRED.LOCK_STORES */
421 INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_LOADS */
422 INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_STORES */
423 INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOP_RETIRED.ANY_LOADS */
424 INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOP_RETIRED.ANY_STORES */
425 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
426 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
427 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
428 EVENT_CONSTRAINT_END
429};
430
431static struct event_constraint *
432intel_pebs_constraints(struct perf_event *event)
433{
434 struct event_constraint *c;
435
436 if (!event->attr.precise_ip)
437 return NULL;
438
439 if (x86_pmu.pebs_constraints) {
440 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
441 if ((event->hw.config & c->cmask) == c->code)
442 return c;
443 }
444 }
445
446 return &emptyconstraint;
447}
448
449static void intel_pmu_pebs_enable(struct perf_event *event)
450{
451 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
452 struct hw_perf_event *hwc = &event->hw;
453
454 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
455
456 cpuc->pebs_enabled |= 1ULL << hwc->idx;
457 WARN_ON_ONCE(cpuc->enabled);
458
459 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
460 intel_pmu_lbr_enable(event);
461}
462
463static void intel_pmu_pebs_disable(struct perf_event *event)
464{
465 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
466 struct hw_perf_event *hwc = &event->hw;
467
468 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
469 if (cpuc->enabled)
470 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
471
472 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
473
474 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
475 intel_pmu_lbr_disable(event);
476}
477
478static void intel_pmu_pebs_enable_all(void)
479{
480 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
481
482 if (cpuc->pebs_enabled)
483 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
484}
485
486static void intel_pmu_pebs_disable_all(void)
487{
488 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
489
490 if (cpuc->pebs_enabled)
491 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
492}
493
494#include <asm/insn.h>
495
496static inline bool kernel_ip(unsigned long ip)
497{
498#ifdef CONFIG_X86_32
499 return ip > PAGE_OFFSET;
500#else
501 return (long)ip < 0;
502#endif
503}
504
505static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
506{
507 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
508 unsigned long from = cpuc->lbr_entries[0].from;
509 unsigned long old_to, to = cpuc->lbr_entries[0].to;
510 unsigned long ip = regs->ip;
511
512 /*
513 * We don't need to fixup if the PEBS assist is fault like
514 */
515 if (!x86_pmu.intel_cap.pebs_trap)
516 return 1;
517
518 /*
519 * No LBR entry, no basic block, no rewinding
520 */
521 if (!cpuc->lbr_stack.nr || !from || !to)
522 return 0;
523
524 /*
525 * Basic blocks should never cross user/kernel boundaries
526 */
527 if (kernel_ip(ip) != kernel_ip(to))
528 return 0;
529
530 /*
531 * unsigned math, either ip is before the start (impossible) or
532 * the basic block is larger than 1 page (sanity)
533 */
534 if ((ip - to) > PAGE_SIZE)
535 return 0;
536
537 /*
538 * We sampled a branch insn, rewind using the LBR stack
539 */
540 if (ip == to) {
541 regs->ip = from;
542 return 1;
543 }
544
545 do {
546 struct insn insn;
547 u8 buf[MAX_INSN_SIZE];
548 void *kaddr;
549
550 old_to = to;
551 if (!kernel_ip(ip)) {
552 int bytes, size = MAX_INSN_SIZE;
553
554 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
555 if (bytes != size)
556 return 0;
557
558 kaddr = buf;
559 } else
560 kaddr = (void *)to;
561
562 kernel_insn_init(&insn, kaddr);
563 insn_get_length(&insn);
564 to += insn.length;
565 } while (to < ip);
566
567 if (to == ip) {
568 regs->ip = old_to;
569 return 1;
570 }
571
572 /*
573 * Even though we decoded the basic block, the instruction stream
574 * never matched the given IP, either the TO or the IP got corrupted.
575 */
576 return 0;
577}
578
579static int intel_pmu_save_and_restart(struct perf_event *event);
580
581static void __intel_pmu_pebs_event(struct perf_event *event,
582 struct pt_regs *iregs, void *__pebs)
583{
584 /*
585 * We cast to pebs_record_core since that is a subset of
586 * both formats and we don't use the other fields in this
587 * routine.
588 */
589 struct pebs_record_core *pebs = __pebs;
590 struct perf_sample_data data;
591 struct pt_regs regs;
592
593 if (!intel_pmu_save_and_restart(event))
594 return;
595
596 perf_sample_data_init(&data, 0);
597 data.period = event->hw.last_period;
598
599 /*
600 * We use the interrupt regs as a base because the PEBS record
601 * does not contain a full regs set, specifically it seems to
602 * lack segment descriptors, which get used by things like
603 * user_mode().
604 *
605 * In the simple case fix up only the IP and BP,SP regs, for
606 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
607 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
608 */
609 regs = *iregs;
610 regs.ip = pebs->ip;
611 regs.bp = pebs->bp;
612 regs.sp = pebs->sp;
613
614 if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(®s))
615 regs.flags |= PERF_EFLAGS_EXACT;
616 else
617 regs.flags &= ~PERF_EFLAGS_EXACT;
618
619 if (perf_event_overflow(event, &data, ®s))
620 x86_pmu_stop(event, 0);
621}
622
623static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
624{
625 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
626 struct debug_store *ds = cpuc->ds;
627 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
628 struct pebs_record_core *at, *top;
629 int n;
630
631 if (!x86_pmu.pebs_active)
632 return;
633
634 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
635 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
636
637 /*
638 * Whatever else happens, drain the thing
639 */
640 ds->pebs_index = ds->pebs_buffer_base;
641
642 if (!test_bit(0, cpuc->active_mask))
643 return;
644
645 WARN_ON_ONCE(!event);
646
647 if (!event->attr.precise_ip)
648 return;
649
650 n = top - at;
651 if (n <= 0)
652 return;
653
654 /*
655 * Should not happen, we program the threshold at 1 and do not
656 * set a reset value.
657 */
658 WARN_ON_ONCE(n > 1);
659 at += n - 1;
660
661 __intel_pmu_pebs_event(event, iregs, at);
662}
663
664static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
665{
666 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
667 struct debug_store *ds = cpuc->ds;
668 struct pebs_record_nhm *at, *top;
669 struct perf_event *event = NULL;
670 u64 status = 0;
671 int bit, n;
672
673 if (!x86_pmu.pebs_active)
674 return;
675
676 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
677 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
678
679 ds->pebs_index = ds->pebs_buffer_base;
680
681 n = top - at;
682 if (n <= 0)
683 return;
684
685 /*
686 * Should not happen, we program the threshold at 1 and do not
687 * set a reset value.
688 */
689 WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
690
691 for ( ; at < top; at++) {
692 for_each_set_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
693 event = cpuc->events[bit];
694 if (!test_bit(bit, cpuc->active_mask))
695 continue;
696
697 WARN_ON_ONCE(!event);
698
699 if (!event->attr.precise_ip)
700 continue;
701
702 if (__test_and_set_bit(bit, (unsigned long *)&status))
703 continue;
704
705 break;
706 }
707
708 if (!event || bit >= MAX_PEBS_EVENTS)
709 continue;
710
711 __intel_pmu_pebs_event(event, iregs, at);
712 }
713}
714
715/*
716 * BTS, PEBS probe and setup
717 */
718
719static void intel_ds_init(void)
720{
721 /*
722 * No support for 32bit formats
723 */
724 if (!boot_cpu_has(X86_FEATURE_DTES64))
725 return;
726
727 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
728 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
729 if (x86_pmu.pebs) {
730 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
731 int format = x86_pmu.intel_cap.pebs_format;
732
733 switch (format) {
734 case 0:
735 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
736 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
737 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
738 break;
739
740 case 1:
741 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
742 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
743 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
744 break;
745
746 default:
747 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
748 x86_pmu.pebs = 0;
749 }
750 }
751}
752
753#else /* CONFIG_CPU_SUP_INTEL */
754
755static void reserve_ds_buffers(void)
756{
757}
758
759static void release_ds_buffers(void)
760{
761}
762
763#endif /* CONFIG_CPU_SUP_INTEL */