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1/*
2 * pcic.c: MicroSPARC-IIep PCI controller support
3 *
4 * Copyright (C) 1998 V. Roganov and G. Raiko
5 *
6 * Code is derived from Ultra/PCI PSYCHO controller support, see that
7 * for author info.
8 *
9 * Support for diverse IIep based platforms by Pete Zaitcev.
10 * CP-1200 by Eric Brower.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/slab.h>
18#include <linux/jiffies.h>
19
20#include <asm/swift.h> /* for cache flushing. */
21#include <asm/io.h>
22
23#include <linux/ctype.h>
24#include <linux/pci.h>
25#include <linux/time.h>
26#include <linux/timex.h>
27#include <linux/interrupt.h>
28#include <linux/export.h>
29
30#include <asm/irq.h>
31#include <asm/oplib.h>
32#include <asm/prom.h>
33#include <asm/pcic.h>
34#include <asm/timex.h>
35#include <asm/timer.h>
36#include <asm/uaccess.h>
37#include <asm/irq_regs.h>
38
39#include "irq.h"
40
41/*
42 * I studied different documents and many live PROMs both from 2.30
43 * family and 3.xx versions. I came to the amazing conclusion: there is
44 * absolutely no way to route interrupts in IIep systems relying on
45 * information which PROM presents. We must hardcode interrupt routing
46 * schematics. And this actually sucks. -- zaitcev 1999/05/12
47 *
48 * To find irq for a device we determine which routing map
49 * is in effect or, in other words, on which machine we are running.
50 * We use PROM name for this although other techniques may be used
51 * in special cases (Gleb reports a PROMless IIep based system).
52 * Once we know the map we take device configuration address and
53 * find PCIC pin number where INT line goes. Then we may either program
54 * preferred irq into the PCIC or supply the preexisting irq to the device.
55 */
56struct pcic_ca2irq {
57 unsigned char busno; /* PCI bus number */
58 unsigned char devfn; /* Configuration address */
59 unsigned char pin; /* PCIC external interrupt pin */
60 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
61 unsigned int force; /* Enforce preferred IRQ */
62};
63
64struct pcic_sn2list {
65 char *sysname;
66 struct pcic_ca2irq *intmap;
67 int mapdim;
68};
69
70/*
71 * JavaEngine-1 apparently has different versions.
72 *
73 * According to communications with Sun folks, for P2 build 501-4628-03:
74 * pin 0 - parallel, audio;
75 * pin 1 - Ethernet;
76 * pin 2 - su;
77 * pin 3 - PS/2 kbd and mouse.
78 *
79 * OEM manual (805-1486):
80 * pin 0: Ethernet
81 * pin 1: All EBus
82 * pin 2: IGA (unused)
83 * pin 3: Not connected
84 * OEM manual says that 501-4628 & 501-4811 are the same thing,
85 * only the latter has NAND flash in place.
86 *
87 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
88 */
89static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
90 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
91 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
92 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
93};
94
95/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
96static struct pcic_ca2irq pcic_i_jse[] = {
97 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
98 { 0, 0x01, 1, 6, 0 }, /* hme */
99 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
100 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
101 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
102 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
103 { 0, 0x80, 5, 11, 0 }, /* EIDE */
104 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
105 { 0, 0xA0, 4, 9, 0 }, /* USB */
106 /*
107 * Some pins belong to non-PCI devices, we hardcode them in drivers.
108 * sun4m timers - irq 10, 14
109 * PC style RTC - pin 7, irq 4 ?
110 * Smart card, Parallel - pin 4 shared with USB, ISA
111 * audio - pin 3, irq 5 ?
112 */
113};
114
115/* SPARCengine-6 was the original release name of CP1200.
116 * The documentation differs between the two versions
117 */
118static struct pcic_ca2irq pcic_i_se6[] = {
119 { 0, 0x08, 0, 2, 0 }, /* SCSI */
120 { 0, 0x01, 1, 6, 0 }, /* HME */
121 { 0, 0x00, 3, 13, 0 }, /* EBus */
122};
123
124/*
125 * Krups (courtesy of Varol Kaptan)
126 * No documentation available, but it was easy to guess
127 * because it was very similar to Espresso.
128 *
129 * pin 0 - kbd, mouse, serial;
130 * pin 1 - Ethernet;
131 * pin 2 - igs (we do not use it);
132 * pin 3 - audio;
133 * pin 4,5,6 - unused;
134 * pin 7 - RTC (from P2 onwards as David B. says).
135 */
136static struct pcic_ca2irq pcic_i_jk[] = {
137 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
138 { 0, 0x01, 1, 6, 0 }, /* hme */
139};
140
141/*
142 * Several entries in this list may point to the same routing map
143 * as several PROMs may be installed on the same physical board.
144 */
145#define SN2L_INIT(name, map) \
146 { name, map, ARRAY_SIZE(map) }
147
148static struct pcic_sn2list pcic_known_sysnames[] = {
149 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
150 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
151 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
152 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
153 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
154 { NULL, NULL, 0 }
155};
156
157/*
158 * Only one PCIC per IIep,
159 * and since we have no SMP IIep, only one per system.
160 */
161static int pcic0_up;
162static struct linux_pcic pcic0;
163
164void __iomem *pcic_regs;
165volatile int pcic_speculative;
166volatile int pcic_trapped;
167
168/* forward */
169unsigned int pcic_build_device_irq(struct platform_device *op,
170 unsigned int real_irq);
171
172#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
173
174static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
175 int where, u32 *value)
176{
177 struct linux_pcic *pcic;
178 unsigned long flags;
179
180 pcic = &pcic0;
181
182 local_irq_save(flags);
183#if 0 /* does not fail here */
184 pcic_speculative = 1;
185 pcic_trapped = 0;
186#endif
187 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
188#if 0 /* does not fail here */
189 nop();
190 if (pcic_trapped) {
191 local_irq_restore(flags);
192 *value = ~0;
193 return 0;
194 }
195#endif
196 pcic_speculative = 2;
197 pcic_trapped = 0;
198 *value = readl(pcic->pcic_config_space_data + (where&4));
199 nop();
200 if (pcic_trapped) {
201 pcic_speculative = 0;
202 local_irq_restore(flags);
203 *value = ~0;
204 return 0;
205 }
206 pcic_speculative = 0;
207 local_irq_restore(flags);
208 return 0;
209}
210
211static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
212 int where, int size, u32 *val)
213{
214 unsigned int v;
215
216 if (bus->number != 0) return -EINVAL;
217 switch (size) {
218 case 1:
219 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
220 *val = 0xff & (v >> (8*(where & 3)));
221 return 0;
222 case 2:
223 if (where&1) return -EINVAL;
224 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
225 *val = 0xffff & (v >> (8*(where & 3)));
226 return 0;
227 case 4:
228 if (where&3) return -EINVAL;
229 pcic_read_config_dword(bus->number, devfn, where&~3, val);
230 return 0;
231 }
232 return -EINVAL;
233}
234
235static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
236 int where, u32 value)
237{
238 struct linux_pcic *pcic;
239 unsigned long flags;
240
241 pcic = &pcic0;
242
243 local_irq_save(flags);
244 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
245 writel(value, pcic->pcic_config_space_data + (where&4));
246 local_irq_restore(flags);
247 return 0;
248}
249
250static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
251 int where, int size, u32 val)
252{
253 unsigned int v;
254
255 if (bus->number != 0) return -EINVAL;
256 switch (size) {
257 case 1:
258 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
259 v = (v & ~(0xff << (8*(where&3)))) |
260 ((0xff&val) << (8*(where&3)));
261 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
262 case 2:
263 if (where&1) return -EINVAL;
264 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
265 v = (v & ~(0xffff << (8*(where&3)))) |
266 ((0xffff&val) << (8*(where&3)));
267 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
268 case 4:
269 if (where&3) return -EINVAL;
270 return pcic_write_config_dword(bus->number, devfn, where, val);
271 }
272 return -EINVAL;
273}
274
275static struct pci_ops pcic_ops = {
276 .read = pcic_read_config,
277 .write = pcic_write_config,
278};
279
280/*
281 * On sparc64 pcibios_init() calls pci_controller_probe().
282 * We want PCIC probed little ahead so that interrupt controller
283 * would be operational.
284 */
285int __init pcic_probe(void)
286{
287 struct linux_pcic *pcic;
288 struct linux_prom_registers regs[PROMREG_MAX];
289 struct linux_pbm_info* pbm;
290 char namebuf[64];
291 phandle node;
292 int err;
293
294 if (pcic0_up) {
295 prom_printf("PCIC: called twice!\n");
296 prom_halt();
297 }
298 pcic = &pcic0;
299
300 node = prom_getchild (prom_root_node);
301 node = prom_searchsiblings (node, "pci");
302 if (node == 0)
303 return -ENODEV;
304 /*
305 * Map in PCIC register set, config space, and IO base
306 */
307 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
308 if (err == 0 || err == -1) {
309 prom_printf("PCIC: Error, cannot get PCIC registers "
310 "from PROM.\n");
311 prom_halt();
312 }
313
314 pcic0_up = 1;
315
316 pcic->pcic_res_regs.name = "pcic_registers";
317 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
318 if (!pcic->pcic_regs) {
319 prom_printf("PCIC: Error, cannot map PCIC registers.\n");
320 prom_halt();
321 }
322
323 pcic->pcic_res_io.name = "pcic_io";
324 if ((pcic->pcic_io = (unsigned long)
325 ioremap(regs[1].phys_addr, 0x10000)) == 0) {
326 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
327 prom_halt();
328 }
329
330 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
331 if ((pcic->pcic_config_space_addr =
332 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) {
333 prom_printf("PCIC: Error, cannot map "
334 "PCI Configuration Space Address.\n");
335 prom_halt();
336 }
337
338 /*
339 * Docs say three least significant bits in address and data
340 * must be the same. Thus, we need adjust size of data.
341 */
342 pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
343 if ((pcic->pcic_config_space_data =
344 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) {
345 prom_printf("PCIC: Error, cannot map "
346 "PCI Configuration Space Data.\n");
347 prom_halt();
348 }
349
350 pbm = &pcic->pbm;
351 pbm->prom_node = node;
352 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
353 strcpy(pbm->prom_name, namebuf);
354
355 {
356 extern volatile int t_nmi[4];
357 extern int pcic_nmi_trap_patch[4];
358
359 t_nmi[0] = pcic_nmi_trap_patch[0];
360 t_nmi[1] = pcic_nmi_trap_patch[1];
361 t_nmi[2] = pcic_nmi_trap_patch[2];
362 t_nmi[3] = pcic_nmi_trap_patch[3];
363 swift_flush_dcache();
364 pcic_regs = pcic->pcic_regs;
365 }
366
367 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
368 {
369 struct pcic_sn2list *p;
370
371 for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
372 if (strcmp(namebuf, p->sysname) == 0)
373 break;
374 }
375 pcic->pcic_imap = p->intmap;
376 pcic->pcic_imdim = p->mapdim;
377 }
378 if (pcic->pcic_imap == NULL) {
379 /*
380 * We do not panic here for the sake of embedded systems.
381 */
382 printk("PCIC: System %s is unknown, cannot route interrupts\n",
383 namebuf);
384 }
385
386 return 0;
387}
388
389static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
390{
391 struct linux_pbm_info *pbm = &pcic->pbm;
392
393 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
394#if 0 /* deadwood transplanted from sparc64 */
395 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
396 pci_record_assignments(pbm, pbm->pci_bus);
397 pci_assign_unassigned(pbm, pbm->pci_bus);
398 pci_fixup_irq(pbm, pbm->pci_bus);
399#endif
400}
401
402/*
403 * Main entry point from the PCI subsystem.
404 */
405static int __init pcic_init(void)
406{
407 struct linux_pcic *pcic;
408
409 /*
410 * PCIC should be initialized at start of the timer.
411 * So, here we report the presence of PCIC and do some magic passes.
412 */
413 if(!pcic0_up)
414 return 0;
415 pcic = &pcic0;
416
417 /*
418 * Switch off IOTLB translation.
419 */
420 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
421 pcic->pcic_regs+PCI_DVMA_CONTROL);
422
423 /*
424 * Increase mapped size for PCI memory space (DMA access).
425 * Should be done in that order (size first, address second).
426 * Why we couldn't set up 4GB and forget about it? XXX
427 */
428 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
429 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
430 pcic->pcic_regs+PCI_BASE_ADDRESS_0);
431
432 pcic_pbm_scan_bus(pcic);
433
434 return 0;
435}
436
437int pcic_present(void)
438{
439 return pcic0_up;
440}
441
442static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm,
443 struct pci_dev *pdev)
444{
445 struct linux_prom_pci_registers regs[PROMREG_MAX];
446 int err;
447 phandle node = prom_getchild(pbm->prom_node);
448
449 while(node) {
450 err = prom_getproperty(node, "reg",
451 (char *)®s[0], sizeof(regs));
452 if(err != 0 && err != -1) {
453 unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
454 if(devfn == pdev->devfn)
455 return node;
456 }
457 node = prom_getsibling(node);
458 }
459 return 0;
460}
461
462static inline struct pcidev_cookie *pci_devcookie_alloc(void)
463{
464 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
465}
466
467static void pcic_map_pci_device(struct linux_pcic *pcic,
468 struct pci_dev *dev, int node)
469{
470 char namebuf[64];
471 unsigned long address;
472 unsigned long flags;
473 int j;
474
475 if (node == 0 || node == -1) {
476 strcpy(namebuf, "???");
477 } else {
478 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
479 }
480
481 for (j = 0; j < 6; j++) {
482 address = dev->resource[j].start;
483 if (address == 0) break; /* are sequential */
484 flags = dev->resource[j].flags;
485 if ((flags & IORESOURCE_IO) != 0) {
486 if (address < 0x10000) {
487 /*
488 * A device responds to I/O cycles on PCI.
489 * We generate these cycles with memory
490 * access into the fixed map (phys 0x30000000).
491 *
492 * Since a device driver does not want to
493 * do ioremap() before accessing PC-style I/O,
494 * we supply virtual, ready to access address.
495 *
496 * Note that request_region()
497 * works for these devices.
498 *
499 * XXX Neat trick, but it's a *bad* idea
500 * to shit into regions like that.
501 * What if we want to allocate one more
502 * PCI base address...
503 */
504 dev->resource[j].start =
505 pcic->pcic_io + address;
506 dev->resource[j].end = 1; /* XXX */
507 dev->resource[j].flags =
508 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
509 } else {
510 /*
511 * OOPS... PCI Spec allows this. Sun does
512 * not have any devices getting above 64K
513 * so it must be user with a weird I/O
514 * board in a PCI slot. We must remap it
515 * under 64K but it is not done yet. XXX
516 */
517 printk("PCIC: Skipping I/O space at 0x%lx, "
518 "this will Oops if a driver attaches "
519 "device '%s' at %02x:%02x)\n", address,
520 namebuf, dev->bus->number, dev->devfn);
521 }
522 }
523 }
524}
525
526static void
527pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
528{
529 struct pcic_ca2irq *p;
530 unsigned int real_irq;
531 int i, ivec;
532 char namebuf[64];
533
534 if (node == 0 || node == -1) {
535 strcpy(namebuf, "???");
536 } else {
537 prom_getstring(node, "name", namebuf, sizeof(namebuf));
538 }
539
540 if ((p = pcic->pcic_imap) == 0) {
541 dev->irq = 0;
542 return;
543 }
544 for (i = 0; i < pcic->pcic_imdim; i++) {
545 if (p->busno == dev->bus->number && p->devfn == dev->devfn)
546 break;
547 p++;
548 }
549 if (i >= pcic->pcic_imdim) {
550 printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
551 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
552 dev->irq = 0;
553 return;
554 }
555
556 i = p->pin;
557 if (i >= 0 && i < 4) {
558 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
559 real_irq = ivec >> (i << 2) & 0xF;
560 } else if (i >= 4 && i < 8) {
561 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
562 real_irq = ivec >> ((i-4) << 2) & 0xF;
563 } else { /* Corrupted map */
564 printk("PCIC: BAD PIN %d\n", i); for (;;) {}
565 }
566/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
567
568 /* real_irq means PROM did not bother to program the upper
569 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
570 */
571 if (real_irq == 0 || p->force) {
572 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
573 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
574 }
575 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
576 p->irq, p->pin, dev->bus->number, dev->devfn);
577 real_irq = p->irq;
578
579 i = p->pin;
580 if (i >= 4) {
581 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
582 ivec &= ~(0xF << ((i - 4) << 2));
583 ivec |= p->irq << ((i - 4) << 2);
584 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
585 } else {
586 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
587 ivec &= ~(0xF << (i << 2));
588 ivec |= p->irq << (i << 2);
589 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
590 }
591 }
592 dev->irq = pcic_build_device_irq(NULL, real_irq);
593}
594
595/*
596 * Normally called from {do_}pci_scan_bus...
597 */
598void __devinit pcibios_fixup_bus(struct pci_bus *bus)
599{
600 struct pci_dev *dev;
601 int i, has_io, has_mem;
602 unsigned int cmd;
603 struct linux_pcic *pcic;
604 /* struct linux_pbm_info* pbm = &pcic->pbm; */
605 int node;
606 struct pcidev_cookie *pcp;
607
608 if (!pcic0_up) {
609 printk("pcibios_fixup_bus: no PCIC\n");
610 return;
611 }
612 pcic = &pcic0;
613
614 /*
615 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
616 */
617 if (bus->number != 0) {
618 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
619 return;
620 }
621
622 list_for_each_entry(dev, &bus->devices, bus_list) {
623
624 /*
625 * Comment from i386 branch:
626 * There are buggy BIOSes that forget to enable I/O and memory
627 * access to PCI devices. We try to fix this, but we need to
628 * be sure that the BIOS didn't forget to assign an address
629 * to the device. [mj]
630 * OBP is a case of such BIOS :-)
631 */
632 has_io = has_mem = 0;
633 for(i=0; i<6; i++) {
634 unsigned long f = dev->resource[i].flags;
635 if (f & IORESOURCE_IO) {
636 has_io = 1;
637 } else if (f & IORESOURCE_MEM)
638 has_mem = 1;
639 }
640 pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
641 if (has_io && !(cmd & PCI_COMMAND_IO)) {
642 printk("PCIC: Enabling I/O for device %02x:%02x\n",
643 dev->bus->number, dev->devfn);
644 cmd |= PCI_COMMAND_IO;
645 pcic_write_config(dev->bus, dev->devfn,
646 PCI_COMMAND, 2, cmd);
647 }
648 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
649 printk("PCIC: Enabling memory for device %02x:%02x\n",
650 dev->bus->number, dev->devfn);
651 cmd |= PCI_COMMAND_MEMORY;
652 pcic_write_config(dev->bus, dev->devfn,
653 PCI_COMMAND, 2, cmd);
654 }
655
656 node = pdev_to_pnode(&pcic->pbm, dev);
657 if(node == 0)
658 node = -1;
659
660 /* cookies */
661 pcp = pci_devcookie_alloc();
662 pcp->pbm = &pcic->pbm;
663 pcp->prom_node = of_find_node_by_phandle(node);
664 dev->sysdata = pcp;
665
666 /* fixing I/O to look like memory */
667 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
668 pcic_map_pci_device(pcic, dev, node);
669
670 pcic_fill_irq(pcic, dev, node);
671 }
672}
673
674/*
675 * pcic_pin_to_irq() is exported to bus probing code
676 */
677unsigned int
678pcic_pin_to_irq(unsigned int pin, const char *name)
679{
680 struct linux_pcic *pcic = &pcic0;
681 unsigned int irq;
682 unsigned int ivec;
683
684 if (pin < 4) {
685 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
686 irq = ivec >> (pin << 2) & 0xF;
687 } else if (pin < 8) {
688 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
689 irq = ivec >> ((pin-4) << 2) & 0xF;
690 } else { /* Corrupted map */
691 printk("PCIC: BAD PIN %d FOR %s\n", pin, name);
692 for (;;) {} /* XXX Cannot panic properly in case of PROLL */
693 }
694/* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */
695 return irq;
696}
697
698/* Makes compiler happy */
699static volatile int pcic_timer_dummy;
700
701static void pcic_clear_clock_irq(void)
702{
703 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
704}
705
706/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
707#define USECS_PER_JIFFY (1000000 / HZ)
708#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
709
710static unsigned int pcic_cycles_offset(void)
711{
712 u32 value, count;
713
714 value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
715 count = value & ~PCI_SYS_COUNTER_OVERFLOW;
716
717 if (value & PCI_SYS_COUNTER_OVERFLOW)
718 count += TICK_TIMER_LIMIT;
719 /*
720 * We divide all by HZ
721 * to have microsecond resolution and to avoid overflow
722 */
723 count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
724
725 /* Coordinate with the sparc_config.clock_rate setting */
726 return count * 2;
727}
728
729void __init pci_time_init(void)
730{
731 struct linux_pcic *pcic = &pcic0;
732 unsigned long v;
733 int timer_irq, irq;
734 int err;
735
736#ifndef CONFIG_SMP
737 /*
738 * The clock_rate is in SBUS dimension.
739 * We take into account this in pcic_cycles_offset()
740 */
741 sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
742 sparc_config.features |= FEAT_L10_CLOCKEVENT;
743#endif
744 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
745 sparc_config.get_cycles_offset = pcic_cycles_offset;
746
747 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
748 /* PROM should set appropriate irq */
749 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
750 timer_irq = PCI_COUNTER_IRQ_SYS(v);
751 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
752 pcic->pcic_regs+PCI_COUNTER_IRQ);
753 irq = pcic_build_device_irq(NULL, timer_irq);
754 err = request_irq(irq, timer_interrupt,
755 IRQF_TIMER, "timer", NULL);
756 if (err) {
757 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
758 prom_halt();
759 }
760 local_irq_enable();
761}
762
763
764#if 0
765static void watchdog_reset() {
766 writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
767}
768#endif
769
770/*
771 * Other archs parse arguments here.
772 */
773char * __devinit pcibios_setup(char *str)
774{
775 return str;
776}
777
778resource_size_t pcibios_align_resource(void *data, const struct resource *res,
779 resource_size_t size, resource_size_t align)
780{
781 return res->start;
782}
783
784int pcibios_enable_device(struct pci_dev *pdev, int mask)
785{
786 return 0;
787}
788
789/*
790 * NMI
791 */
792void pcic_nmi(unsigned int pend, struct pt_regs *regs)
793{
794
795 pend = flip_dword(pend);
796
797 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
798 /*
799 * XXX On CP-1200 PCI #SERR may happen, we do not know
800 * what to do about it yet.
801 */
802 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
803 pend, (int)regs->pc, pcic_speculative);
804 for (;;) { }
805 }
806 pcic_speculative = 0;
807 pcic_trapped = 1;
808 regs->pc = regs->npc;
809 regs->npc += 4;
810}
811
812static inline unsigned long get_irqmask(int irq_nr)
813{
814 return 1 << irq_nr;
815}
816
817static void pcic_mask_irq(struct irq_data *data)
818{
819 unsigned long mask, flags;
820
821 mask = (unsigned long)data->chip_data;
822 local_irq_save(flags);
823 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
824 local_irq_restore(flags);
825}
826
827static void pcic_unmask_irq(struct irq_data *data)
828{
829 unsigned long mask, flags;
830
831 mask = (unsigned long)data->chip_data;
832 local_irq_save(flags);
833 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
834 local_irq_restore(flags);
835}
836
837static unsigned int pcic_startup_irq(struct irq_data *data)
838{
839 irq_link(data->irq);
840 pcic_unmask_irq(data);
841 return 0;
842}
843
844static struct irq_chip pcic_irq = {
845 .name = "pcic",
846 .irq_startup = pcic_startup_irq,
847 .irq_mask = pcic_mask_irq,
848 .irq_unmask = pcic_unmask_irq,
849};
850
851unsigned int pcic_build_device_irq(struct platform_device *op,
852 unsigned int real_irq)
853{
854 unsigned int irq;
855 unsigned long mask;
856
857 irq = 0;
858 mask = get_irqmask(real_irq);
859 if (mask == 0)
860 goto out;
861
862 irq = irq_alloc(real_irq, real_irq);
863 if (irq == 0)
864 goto out;
865
866 irq_set_chip_and_handler_name(irq, &pcic_irq,
867 handle_level_irq, "PCIC");
868 irq_set_chip_data(irq, (void *)mask);
869
870out:
871 return irq;
872}
873
874
875static void pcic_load_profile_irq(int cpu, unsigned int limit)
876{
877 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
878}
879
880void __init sun4m_pci_init_IRQ(void)
881{
882 sparc_config.build_device_irq = pcic_build_device_irq;
883 sparc_config.clear_clock_irq = pcic_clear_clock_irq;
884 sparc_config.load_profile_irq = pcic_load_profile_irq;
885}
886
887int pcibios_assign_resource(struct pci_dev *pdev, int resource)
888{
889 return -ENXIO;
890}
891
892/*
893 * This probably belongs here rather than ioport.c because
894 * we do not want this crud linked into SBus kernels.
895 * Also, think for a moment about likes of floppy.c that
896 * include architecture specific parts. They may want to redefine ins/outs.
897 *
898 * We do not use horrible macros here because we want to
899 * advance pointer by sizeof(size).
900 */
901void outsb(unsigned long addr, const void *src, unsigned long count)
902{
903 while (count) {
904 count -= 1;
905 outb(*(const char *)src, addr);
906 src += 1;
907 /* addr += 1; */
908 }
909}
910EXPORT_SYMBOL(outsb);
911
912void outsw(unsigned long addr, const void *src, unsigned long count)
913{
914 while (count) {
915 count -= 2;
916 outw(*(const short *)src, addr);
917 src += 2;
918 /* addr += 2; */
919 }
920}
921EXPORT_SYMBOL(outsw);
922
923void outsl(unsigned long addr, const void *src, unsigned long count)
924{
925 while (count) {
926 count -= 4;
927 outl(*(const long *)src, addr);
928 src += 4;
929 /* addr += 4; */
930 }
931}
932EXPORT_SYMBOL(outsl);
933
934void insb(unsigned long addr, void *dst, unsigned long count)
935{
936 while (count) {
937 count -= 1;
938 *(unsigned char *)dst = inb(addr);
939 dst += 1;
940 /* addr += 1; */
941 }
942}
943EXPORT_SYMBOL(insb);
944
945void insw(unsigned long addr, void *dst, unsigned long count)
946{
947 while (count) {
948 count -= 2;
949 *(unsigned short *)dst = inw(addr);
950 dst += 2;
951 /* addr += 2; */
952 }
953}
954EXPORT_SYMBOL(insw);
955
956void insl(unsigned long addr, void *dst, unsigned long count)
957{
958 while (count) {
959 count -= 4;
960 /*
961 * XXX I am sure we are in for an unaligned trap here.
962 */
963 *(unsigned long *)dst = inl(addr);
964 dst += 4;
965 /* addr += 4; */
966 }
967}
968EXPORT_SYMBOL(insl);
969
970subsys_initcall(pcic_init);
1/*
2 * pcic.c: MicroSPARC-IIep PCI controller support
3 *
4 * Copyright (C) 1998 V. Roganov and G. Raiko
5 *
6 * Code is derived from Ultra/PCI PSYCHO controller support, see that
7 * for author info.
8 *
9 * Support for diverse IIep based platforms by Pete Zaitcev.
10 * CP-1200 by Eric Brower.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/slab.h>
18#include <linux/jiffies.h>
19
20#include <asm/swift.h> /* for cache flushing. */
21#include <asm/io.h>
22
23#include <linux/ctype.h>
24#include <linux/pci.h>
25#include <linux/time.h>
26#include <linux/timex.h>
27#include <linux/interrupt.h>
28
29#include <asm/irq.h>
30#include <asm/oplib.h>
31#include <asm/prom.h>
32#include <asm/pcic.h>
33#include <asm/timex.h>
34#include <asm/timer.h>
35#include <asm/uaccess.h>
36#include <asm/irq_regs.h>
37
38#include "irq.h"
39
40/*
41 * I studied different documents and many live PROMs both from 2.30
42 * family and 3.xx versions. I came to the amazing conclusion: there is
43 * absolutely no way to route interrupts in IIep systems relying on
44 * information which PROM presents. We must hardcode interrupt routing
45 * schematics. And this actually sucks. -- zaitcev 1999/05/12
46 *
47 * To find irq for a device we determine which routing map
48 * is in effect or, in other words, on which machine we are running.
49 * We use PROM name for this although other techniques may be used
50 * in special cases (Gleb reports a PROMless IIep based system).
51 * Once we know the map we take device configuration address and
52 * find PCIC pin number where INT line goes. Then we may either program
53 * preferred irq into the PCIC or supply the preexisting irq to the device.
54 */
55struct pcic_ca2irq {
56 unsigned char busno; /* PCI bus number */
57 unsigned char devfn; /* Configuration address */
58 unsigned char pin; /* PCIC external interrupt pin */
59 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */
60 unsigned int force; /* Enforce preferred IRQ */
61};
62
63struct pcic_sn2list {
64 char *sysname;
65 struct pcic_ca2irq *intmap;
66 int mapdim;
67};
68
69/*
70 * JavaEngine-1 apparently has different versions.
71 *
72 * According to communications with Sun folks, for P2 build 501-4628-03:
73 * pin 0 - parallel, audio;
74 * pin 1 - Ethernet;
75 * pin 2 - su;
76 * pin 3 - PS/2 kbd and mouse.
77 *
78 * OEM manual (805-1486):
79 * pin 0: Ethernet
80 * pin 1: All EBus
81 * pin 2: IGA (unused)
82 * pin 3: Not connected
83 * OEM manual says that 501-4628 & 501-4811 are the same thing,
84 * only the latter has NAND flash in place.
85 *
86 * So far unofficial Sun wins over the OEM manual. Poor OEMs...
87 */
88static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */
89 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */
90 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */
91 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */
92};
93
94/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */
95static struct pcic_ca2irq pcic_i_jse[] = {
96 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
97 { 0, 0x01, 1, 6, 0 }, /* hme */
98 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */
99 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */
100 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */
101 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */
102 { 0, 0x80, 5, 11, 0 }, /* EIDE */
103 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */
104 { 0, 0xA0, 4, 9, 0 }, /* USB */
105 /*
106 * Some pins belong to non-PCI devices, we hardcode them in drivers.
107 * sun4m timers - irq 10, 14
108 * PC style RTC - pin 7, irq 4 ?
109 * Smart card, Parallel - pin 4 shared with USB, ISA
110 * audio - pin 3, irq 5 ?
111 */
112};
113
114/* SPARCengine-6 was the original release name of CP1200.
115 * The documentation differs between the two versions
116 */
117static struct pcic_ca2irq pcic_i_se6[] = {
118 { 0, 0x08, 0, 2, 0 }, /* SCSI */
119 { 0, 0x01, 1, 6, 0 }, /* HME */
120 { 0, 0x00, 3, 13, 0 }, /* EBus */
121};
122
123/*
124 * Krups (courtesy of Varol Kaptan)
125 * No documentation available, but it was easy to guess
126 * because it was very similar to Espresso.
127 *
128 * pin 0 - kbd, mouse, serial;
129 * pin 1 - Ethernet;
130 * pin 2 - igs (we do not use it);
131 * pin 3 - audio;
132 * pin 4,5,6 - unused;
133 * pin 7 - RTC (from P2 onwards as David B. says).
134 */
135static struct pcic_ca2irq pcic_i_jk[] = {
136 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */
137 { 0, 0x01, 1, 6, 0 }, /* hme */
138};
139
140/*
141 * Several entries in this list may point to the same routing map
142 * as several PROMs may be installed on the same physical board.
143 */
144#define SN2L_INIT(name, map) \
145 { name, map, ARRAY_SIZE(map) }
146
147static struct pcic_sn2list pcic_known_sysnames[] = {
148 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */
149 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */
150 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */
151 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */
152 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */
153 { NULL, NULL, 0 }
154};
155
156/*
157 * Only one PCIC per IIep,
158 * and since we have no SMP IIep, only one per system.
159 */
160static int pcic0_up;
161static struct linux_pcic pcic0;
162
163void __iomem *pcic_regs;
164volatile int pcic_speculative;
165volatile int pcic_trapped;
166
167/* forward */
168unsigned int pcic_build_device_irq(struct platform_device *op,
169 unsigned int real_irq);
170
171#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3))
172
173static int pcic_read_config_dword(unsigned int busno, unsigned int devfn,
174 int where, u32 *value)
175{
176 struct linux_pcic *pcic;
177 unsigned long flags;
178
179 pcic = &pcic0;
180
181 local_irq_save(flags);
182#if 0 /* does not fail here */
183 pcic_speculative = 1;
184 pcic_trapped = 0;
185#endif
186 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
187#if 0 /* does not fail here */
188 nop();
189 if (pcic_trapped) {
190 local_irq_restore(flags);
191 *value = ~0;
192 return 0;
193 }
194#endif
195 pcic_speculative = 2;
196 pcic_trapped = 0;
197 *value = readl(pcic->pcic_config_space_data + (where&4));
198 nop();
199 if (pcic_trapped) {
200 pcic_speculative = 0;
201 local_irq_restore(flags);
202 *value = ~0;
203 return 0;
204 }
205 pcic_speculative = 0;
206 local_irq_restore(flags);
207 return 0;
208}
209
210static int pcic_read_config(struct pci_bus *bus, unsigned int devfn,
211 int where, int size, u32 *val)
212{
213 unsigned int v;
214
215 if (bus->number != 0) return -EINVAL;
216 switch (size) {
217 case 1:
218 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
219 *val = 0xff & (v >> (8*(where & 3)));
220 return 0;
221 case 2:
222 if (where&1) return -EINVAL;
223 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
224 *val = 0xffff & (v >> (8*(where & 3)));
225 return 0;
226 case 4:
227 if (where&3) return -EINVAL;
228 pcic_read_config_dword(bus->number, devfn, where&~3, val);
229 return 0;
230 }
231 return -EINVAL;
232}
233
234static int pcic_write_config_dword(unsigned int busno, unsigned int devfn,
235 int where, u32 value)
236{
237 struct linux_pcic *pcic;
238 unsigned long flags;
239
240 pcic = &pcic0;
241
242 local_irq_save(flags);
243 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr);
244 writel(value, pcic->pcic_config_space_data + (where&4));
245 local_irq_restore(flags);
246 return 0;
247}
248
249static int pcic_write_config(struct pci_bus *bus, unsigned int devfn,
250 int where, int size, u32 val)
251{
252 unsigned int v;
253
254 if (bus->number != 0) return -EINVAL;
255 switch (size) {
256 case 1:
257 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
258 v = (v & ~(0xff << (8*(where&3)))) |
259 ((0xff&val) << (8*(where&3)));
260 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
261 case 2:
262 if (where&1) return -EINVAL;
263 pcic_read_config_dword(bus->number, devfn, where&~3, &v);
264 v = (v & ~(0xffff << (8*(where&3)))) |
265 ((0xffff&val) << (8*(where&3)));
266 return pcic_write_config_dword(bus->number, devfn, where&~3, v);
267 case 4:
268 if (where&3) return -EINVAL;
269 return pcic_write_config_dword(bus->number, devfn, where, val);
270 }
271 return -EINVAL;
272}
273
274static struct pci_ops pcic_ops = {
275 .read = pcic_read_config,
276 .write = pcic_write_config,
277};
278
279/*
280 * On sparc64 pcibios_init() calls pci_controller_probe().
281 * We want PCIC probed little ahead so that interrupt controller
282 * would be operational.
283 */
284int __init pcic_probe(void)
285{
286 struct linux_pcic *pcic;
287 struct linux_prom_registers regs[PROMREG_MAX];
288 struct linux_pbm_info* pbm;
289 char namebuf[64];
290 phandle node;
291 int err;
292
293 if (pcic0_up) {
294 prom_printf("PCIC: called twice!\n");
295 prom_halt();
296 }
297 pcic = &pcic0;
298
299 node = prom_getchild (prom_root_node);
300 node = prom_searchsiblings (node, "pci");
301 if (node == 0)
302 return -ENODEV;
303 /*
304 * Map in PCIC register set, config space, and IO base
305 */
306 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs));
307 if (err == 0 || err == -1) {
308 prom_printf("PCIC: Error, cannot get PCIC registers "
309 "from PROM.\n");
310 prom_halt();
311 }
312
313 pcic0_up = 1;
314
315 pcic->pcic_res_regs.name = "pcic_registers";
316 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size);
317 if (!pcic->pcic_regs) {
318 prom_printf("PCIC: Error, cannot map PCIC registers.\n");
319 prom_halt();
320 }
321
322 pcic->pcic_res_io.name = "pcic_io";
323 if ((pcic->pcic_io = (unsigned long)
324 ioremap(regs[1].phys_addr, 0x10000)) == 0) {
325 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n");
326 prom_halt();
327 }
328
329 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr";
330 if ((pcic->pcic_config_space_addr =
331 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == 0) {
332 prom_printf("PCIC: Error, cannot map "
333 "PCI Configuration Space Address.\n");
334 prom_halt();
335 }
336
337 /*
338 * Docs say three least significant bits in address and data
339 * must be the same. Thus, we need adjust size of data.
340 */
341 pcic->pcic_res_cfg_data.name = "pcic_cfg_data";
342 if ((pcic->pcic_config_space_data =
343 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == 0) {
344 prom_printf("PCIC: Error, cannot map "
345 "PCI Configuration Space Data.\n");
346 prom_halt();
347 }
348
349 pbm = &pcic->pbm;
350 pbm->prom_node = node;
351 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
352 strcpy(pbm->prom_name, namebuf);
353
354 {
355 extern volatile int t_nmi[4];
356 extern int pcic_nmi_trap_patch[4];
357
358 t_nmi[0] = pcic_nmi_trap_patch[0];
359 t_nmi[1] = pcic_nmi_trap_patch[1];
360 t_nmi[2] = pcic_nmi_trap_patch[2];
361 t_nmi[3] = pcic_nmi_trap_patch[3];
362 swift_flush_dcache();
363 pcic_regs = pcic->pcic_regs;
364 }
365
366 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0;
367 {
368 struct pcic_sn2list *p;
369
370 for (p = pcic_known_sysnames; p->sysname != NULL; p++) {
371 if (strcmp(namebuf, p->sysname) == 0)
372 break;
373 }
374 pcic->pcic_imap = p->intmap;
375 pcic->pcic_imdim = p->mapdim;
376 }
377 if (pcic->pcic_imap == NULL) {
378 /*
379 * We do not panic here for the sake of embedded systems.
380 */
381 printk("PCIC: System %s is unknown, cannot route interrupts\n",
382 namebuf);
383 }
384
385 return 0;
386}
387
388static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic)
389{
390 struct linux_pbm_info *pbm = &pcic->pbm;
391
392 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm);
393#if 0 /* deadwood transplanted from sparc64 */
394 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
395 pci_record_assignments(pbm, pbm->pci_bus);
396 pci_assign_unassigned(pbm, pbm->pci_bus);
397 pci_fixup_irq(pbm, pbm->pci_bus);
398#endif
399}
400
401/*
402 * Main entry point from the PCI subsystem.
403 */
404static int __init pcic_init(void)
405{
406 struct linux_pcic *pcic;
407
408 /*
409 * PCIC should be initialized at start of the timer.
410 * So, here we report the presence of PCIC and do some magic passes.
411 */
412 if(!pcic0_up)
413 return 0;
414 pcic = &pcic0;
415
416 /*
417 * Switch off IOTLB translation.
418 */
419 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE,
420 pcic->pcic_regs+PCI_DVMA_CONTROL);
421
422 /*
423 * Increase mapped size for PCI memory space (DMA access).
424 * Should be done in that order (size first, address second).
425 * Why we couldn't set up 4GB and forget about it? XXX
426 */
427 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);
428 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY,
429 pcic->pcic_regs+PCI_BASE_ADDRESS_0);
430
431 pcic_pbm_scan_bus(pcic);
432
433 return 0;
434}
435
436int pcic_present(void)
437{
438 return pcic0_up;
439}
440
441static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm,
442 struct pci_dev *pdev)
443{
444 struct linux_prom_pci_registers regs[PROMREG_MAX];
445 int err;
446 phandle node = prom_getchild(pbm->prom_node);
447
448 while(node) {
449 err = prom_getproperty(node, "reg",
450 (char *)®s[0], sizeof(regs));
451 if(err != 0 && err != -1) {
452 unsigned long devfn = (regs[0].which_io >> 8) & 0xff;
453 if(devfn == pdev->devfn)
454 return node;
455 }
456 node = prom_getsibling(node);
457 }
458 return 0;
459}
460
461static inline struct pcidev_cookie *pci_devcookie_alloc(void)
462{
463 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC);
464}
465
466static void pcic_map_pci_device(struct linux_pcic *pcic,
467 struct pci_dev *dev, int node)
468{
469 char namebuf[64];
470 unsigned long address;
471 unsigned long flags;
472 int j;
473
474 if (node == 0 || node == -1) {
475 strcpy(namebuf, "???");
476 } else {
477 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0;
478 }
479
480 for (j = 0; j < 6; j++) {
481 address = dev->resource[j].start;
482 if (address == 0) break; /* are sequential */
483 flags = dev->resource[j].flags;
484 if ((flags & IORESOURCE_IO) != 0) {
485 if (address < 0x10000) {
486 /*
487 * A device responds to I/O cycles on PCI.
488 * We generate these cycles with memory
489 * access into the fixed map (phys 0x30000000).
490 *
491 * Since a device driver does not want to
492 * do ioremap() before accessing PC-style I/O,
493 * we supply virtual, ready to access address.
494 *
495 * Note that request_region()
496 * works for these devices.
497 *
498 * XXX Neat trick, but it's a *bad* idea
499 * to shit into regions like that.
500 * What if we want to allocate one more
501 * PCI base address...
502 */
503 dev->resource[j].start =
504 pcic->pcic_io + address;
505 dev->resource[j].end = 1; /* XXX */
506 dev->resource[j].flags =
507 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM;
508 } else {
509 /*
510 * OOPS... PCI Spec allows this. Sun does
511 * not have any devices getting above 64K
512 * so it must be user with a weird I/O
513 * board in a PCI slot. We must remap it
514 * under 64K but it is not done yet. XXX
515 */
516 printk("PCIC: Skipping I/O space at 0x%lx, "
517 "this will Oops if a driver attaches "
518 "device '%s' at %02x:%02x)\n", address,
519 namebuf, dev->bus->number, dev->devfn);
520 }
521 }
522 }
523}
524
525static void
526pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node)
527{
528 struct pcic_ca2irq *p;
529 unsigned int real_irq;
530 int i, ivec;
531 char namebuf[64];
532
533 if (node == 0 || node == -1) {
534 strcpy(namebuf, "???");
535 } else {
536 prom_getstring(node, "name", namebuf, sizeof(namebuf));
537 }
538
539 if ((p = pcic->pcic_imap) == 0) {
540 dev->irq = 0;
541 return;
542 }
543 for (i = 0; i < pcic->pcic_imdim; i++) {
544 if (p->busno == dev->bus->number && p->devfn == dev->devfn)
545 break;
546 p++;
547 }
548 if (i >= pcic->pcic_imdim) {
549 printk("PCIC: device %s devfn %02x:%02x not found in %d\n",
550 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim);
551 dev->irq = 0;
552 return;
553 }
554
555 i = p->pin;
556 if (i >= 0 && i < 4) {
557 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
558 real_irq = ivec >> (i << 2) & 0xF;
559 } else if (i >= 4 && i < 8) {
560 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
561 real_irq = ivec >> ((i-4) << 2) & 0xF;
562 } else { /* Corrupted map */
563 printk("PCIC: BAD PIN %d\n", i); for (;;) {}
564 }
565/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */
566
567 /* real_irq means PROM did not bother to program the upper
568 * half of PCIC. This happens on JS-E with PROM 3.11, for instance.
569 */
570 if (real_irq == 0 || p->force) {
571 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */
572 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {}
573 }
574 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n",
575 p->irq, p->pin, dev->bus->number, dev->devfn);
576 real_irq = p->irq;
577
578 i = p->pin;
579 if (i >= 4) {
580 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
581 ivec &= ~(0xF << ((i - 4) << 2));
582 ivec |= p->irq << ((i - 4) << 2);
583 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);
584 } else {
585 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
586 ivec &= ~(0xF << (i << 2));
587 ivec |= p->irq << (i << 2);
588 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);
589 }
590 }
591 dev->irq = pcic_build_device_irq(NULL, real_irq);
592}
593
594/*
595 * Normally called from {do_}pci_scan_bus...
596 */
597void __devinit pcibios_fixup_bus(struct pci_bus *bus)
598{
599 struct pci_dev *dev;
600 int i, has_io, has_mem;
601 unsigned int cmd;
602 struct linux_pcic *pcic;
603 /* struct linux_pbm_info* pbm = &pcic->pbm; */
604 int node;
605 struct pcidev_cookie *pcp;
606
607 if (!pcic0_up) {
608 printk("pcibios_fixup_bus: no PCIC\n");
609 return;
610 }
611 pcic = &pcic0;
612
613 /*
614 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus);
615 */
616 if (bus->number != 0) {
617 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number);
618 return;
619 }
620
621 list_for_each_entry(dev, &bus->devices, bus_list) {
622
623 /*
624 * Comment from i386 branch:
625 * There are buggy BIOSes that forget to enable I/O and memory
626 * access to PCI devices. We try to fix this, but we need to
627 * be sure that the BIOS didn't forget to assign an address
628 * to the device. [mj]
629 * OBP is a case of such BIOS :-)
630 */
631 has_io = has_mem = 0;
632 for(i=0; i<6; i++) {
633 unsigned long f = dev->resource[i].flags;
634 if (f & IORESOURCE_IO) {
635 has_io = 1;
636 } else if (f & IORESOURCE_MEM)
637 has_mem = 1;
638 }
639 pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
640 if (has_io && !(cmd & PCI_COMMAND_IO)) {
641 printk("PCIC: Enabling I/O for device %02x:%02x\n",
642 dev->bus->number, dev->devfn);
643 cmd |= PCI_COMMAND_IO;
644 pcic_write_config(dev->bus, dev->devfn,
645 PCI_COMMAND, 2, cmd);
646 }
647 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
648 printk("PCIC: Enabling memory for device %02x:%02x\n",
649 dev->bus->number, dev->devfn);
650 cmd |= PCI_COMMAND_MEMORY;
651 pcic_write_config(dev->bus, dev->devfn,
652 PCI_COMMAND, 2, cmd);
653 }
654
655 node = pdev_to_pnode(&pcic->pbm, dev);
656 if(node == 0)
657 node = -1;
658
659 /* cookies */
660 pcp = pci_devcookie_alloc();
661 pcp->pbm = &pcic->pbm;
662 pcp->prom_node = of_find_node_by_phandle(node);
663 dev->sysdata = pcp;
664
665 /* fixing I/O to look like memory */
666 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE)
667 pcic_map_pci_device(pcic, dev, node);
668
669 pcic_fill_irq(pcic, dev, node);
670 }
671}
672
673/*
674 * pcic_pin_to_irq() is exported to bus probing code
675 */
676unsigned int
677pcic_pin_to_irq(unsigned int pin, const char *name)
678{
679 struct linux_pcic *pcic = &pcic0;
680 unsigned int irq;
681 unsigned int ivec;
682
683 if (pin < 4) {
684 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);
685 irq = ivec >> (pin << 2) & 0xF;
686 } else if (pin < 8) {
687 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);
688 irq = ivec >> ((pin-4) << 2) & 0xF;
689 } else { /* Corrupted map */
690 printk("PCIC: BAD PIN %d FOR %s\n", pin, name);
691 for (;;) {} /* XXX Cannot panic properly in case of PROLL */
692 }
693/* P3 */ /* printk("PCIC: dev %s pin %d ivec 0x%x irq %x\n", name, pin, ivec, irq); */
694 return irq;
695}
696
697/* Makes compiler happy */
698static volatile int pcic_timer_dummy;
699
700static void pcic_clear_clock_irq(void)
701{
702 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
703}
704
705static irqreturn_t pcic_timer_handler (int irq, void *h)
706{
707 pcic_clear_clock_irq();
708 xtime_update(1);
709#ifndef CONFIG_SMP
710 update_process_times(user_mode(get_irq_regs()));
711#endif
712 return IRQ_HANDLED;
713}
714
715#define USECS_PER_JIFFY 10000 /* We have 100HZ "standard" timer for sparc */
716#define TICK_TIMER_LIMIT ((100*1000000/4)/100)
717
718u32 pci_gettimeoffset(void)
719{
720 /*
721 * We divide all by 100
722 * to have microsecond resolution and to avoid overflow
723 */
724 unsigned long count =
725 readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
726 count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
727 return count * 1000;
728}
729
730
731void __init pci_time_init(void)
732{
733 struct linux_pcic *pcic = &pcic0;
734 unsigned long v;
735 int timer_irq, irq;
736 int err;
737
738 do_arch_gettimeoffset = pci_gettimeoffset;
739
740 btfixup();
741
742 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
743 /* PROM should set appropriate irq */
744 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);
745 timer_irq = PCI_COUNTER_IRQ_SYS(v);
746 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
747 pcic->pcic_regs+PCI_COUNTER_IRQ);
748 irq = pcic_build_device_irq(NULL, timer_irq);
749 err = request_irq(irq, pcic_timer_handler,
750 IRQF_TIMER, "timer", NULL);
751 if (err) {
752 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
753 prom_halt();
754 }
755 local_irq_enable();
756}
757
758
759#if 0
760static void watchdog_reset() {
761 writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
762}
763#endif
764
765/*
766 * Other archs parse arguments here.
767 */
768char * __devinit pcibios_setup(char *str)
769{
770 return str;
771}
772
773resource_size_t pcibios_align_resource(void *data, const struct resource *res,
774 resource_size_t size, resource_size_t align)
775{
776 return res->start;
777}
778
779int pcibios_enable_device(struct pci_dev *pdev, int mask)
780{
781 return 0;
782}
783
784/*
785 * NMI
786 */
787void pcic_nmi(unsigned int pend, struct pt_regs *regs)
788{
789
790 pend = flip_dword(pend);
791
792 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) {
793 /*
794 * XXX On CP-1200 PCI #SERR may happen, we do not know
795 * what to do about it yet.
796 */
797 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n",
798 pend, (int)regs->pc, pcic_speculative);
799 for (;;) { }
800 }
801 pcic_speculative = 0;
802 pcic_trapped = 1;
803 regs->pc = regs->npc;
804 regs->npc += 4;
805}
806
807static inline unsigned long get_irqmask(int irq_nr)
808{
809 return 1 << irq_nr;
810}
811
812static void pcic_mask_irq(struct irq_data *data)
813{
814 unsigned long mask, flags;
815
816 mask = (unsigned long)data->chip_data;
817 local_irq_save(flags);
818 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);
819 local_irq_restore(flags);
820}
821
822static void pcic_unmask_irq(struct irq_data *data)
823{
824 unsigned long mask, flags;
825
826 mask = (unsigned long)data->chip_data;
827 local_irq_save(flags);
828 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);
829 local_irq_restore(flags);
830}
831
832static unsigned int pcic_startup_irq(struct irq_data *data)
833{
834 irq_link(data->irq);
835 pcic_unmask_irq(data);
836 return 0;
837}
838
839static struct irq_chip pcic_irq = {
840 .name = "pcic",
841 .irq_startup = pcic_startup_irq,
842 .irq_mask = pcic_mask_irq,
843 .irq_unmask = pcic_unmask_irq,
844};
845
846unsigned int pcic_build_device_irq(struct platform_device *op,
847 unsigned int real_irq)
848{
849 unsigned int irq;
850 unsigned long mask;
851
852 irq = 0;
853 mask = get_irqmask(real_irq);
854 if (mask == 0)
855 goto out;
856
857 irq = irq_alloc(real_irq, real_irq);
858 if (irq == 0)
859 goto out;
860
861 irq_set_chip_and_handler_name(irq, &pcic_irq,
862 handle_level_irq, "PCIC");
863 irq_set_chip_data(irq, (void *)mask);
864
865out:
866 return irq;
867}
868
869
870static void pcic_load_profile_irq(int cpu, unsigned int limit)
871{
872 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__);
873}
874
875void __init sun4m_pci_init_IRQ(void)
876{
877 sparc_irq_config.build_device_irq = pcic_build_device_irq;
878
879 BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM);
880 BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM);
881}
882
883int pcibios_assign_resource(struct pci_dev *pdev, int resource)
884{
885 return -ENXIO;
886}
887
888/*
889 * This probably belongs here rather than ioport.c because
890 * we do not want this crud linked into SBus kernels.
891 * Also, think for a moment about likes of floppy.c that
892 * include architecture specific parts. They may want to redefine ins/outs.
893 *
894 * We do not use horrible macros here because we want to
895 * advance pointer by sizeof(size).
896 */
897void outsb(unsigned long addr, const void *src, unsigned long count)
898{
899 while (count) {
900 count -= 1;
901 outb(*(const char *)src, addr);
902 src += 1;
903 /* addr += 1; */
904 }
905}
906EXPORT_SYMBOL(outsb);
907
908void outsw(unsigned long addr, const void *src, unsigned long count)
909{
910 while (count) {
911 count -= 2;
912 outw(*(const short *)src, addr);
913 src += 2;
914 /* addr += 2; */
915 }
916}
917EXPORT_SYMBOL(outsw);
918
919void outsl(unsigned long addr, const void *src, unsigned long count)
920{
921 while (count) {
922 count -= 4;
923 outl(*(const long *)src, addr);
924 src += 4;
925 /* addr += 4; */
926 }
927}
928EXPORT_SYMBOL(outsl);
929
930void insb(unsigned long addr, void *dst, unsigned long count)
931{
932 while (count) {
933 count -= 1;
934 *(unsigned char *)dst = inb(addr);
935 dst += 1;
936 /* addr += 1; */
937 }
938}
939EXPORT_SYMBOL(insb);
940
941void insw(unsigned long addr, void *dst, unsigned long count)
942{
943 while (count) {
944 count -= 2;
945 *(unsigned short *)dst = inw(addr);
946 dst += 2;
947 /* addr += 2; */
948 }
949}
950EXPORT_SYMBOL(insw);
951
952void insl(unsigned long addr, void *dst, unsigned long count)
953{
954 while (count) {
955 count -= 4;
956 /*
957 * XXX I am sure we are in for an unaligned trap here.
958 */
959 *(unsigned long *)dst = inl(addr);
960 dst += 4;
961 /* addr += 4; */
962 }
963}
964EXPORT_SYMBOL(insl);
965
966subsys_initcall(pcic_init);