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1/*
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
3 *
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/page.h>
13#include <asm/spitfire.h>
14#include <asm/head.h>
15#include <asm/processor.h>
16#include <asm/mmu.h>
17
18#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19#define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV)
20#define ETRAP_PSTATE2 \
21 (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
22
23/*
24 * On entry, %g7 is return address - 0x4.
25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
26 */
27
28 .text
29 .align 64
30 .globl etrap_syscall, etrap, etrap_irq, etraptl1
31etrap: rdpr %pil, %g2
32etrap_irq: clr %g3
33etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
34 rdpr %tstate, %g1
35 or %g1, %g3, %g1
36 sllx %g2, 20, %g3
37 andcc %g1, TSTATE_PRIV, %g0
38 or %g1, %g3, %g1
39 bne,pn %xcc, 1f
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
42
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
46 and %g1, %g3, %g3
47 brnz,pn %g3, 1f
48 add %g6, %g2, %g2
49 wr %g0, 0, %fprs
501: rdpr %tpc, %g3
51
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
53 rdpr %tnpc, %g1
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
55 rd %y, %g3
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
57 rdpr %tt, %g1
58 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
59 sethi %hi(PT_REGS_MAGIC), %g3
60 or %g3, %g1, %g1
61 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
62
63 rdpr %cansave, %g1
64 brnz,pt %g1, etrap_save
65 nop
66
67 rdpr %cwp, %g1
68 add %g1, 2, %g1
69 wrpr %g1, %cwp
70 be,pt %xcc, etrap_user_spill
71 mov ASI_AIUP, %g3
72
73 rdpr %otherwin, %g3
74 brz %g3, etrap_kernel_spill
75 mov ASI_AIUS, %g3
76
77etrap_user_spill:
78
79 wr %g3, 0x0, %asi
80 ldx [%g6 + TI_FLAGS], %g3
81 and %g3, _TIF_32BIT, %g3
82 brnz,pt %g3, etrap_user_spill_32bit
83 nop
84 ba,a,pt %xcc, etrap_user_spill_64bit
85
86etrap_save: save %g2, -STACK_BIAS, %sp
87 mov %g6, %l6
88
89 bne,pn %xcc, 3f
90 mov PRIMARY_CONTEXT, %l4
91 rdpr %canrestore, %g3
92 rdpr %wstate, %g2
93 wrpr %g0, 0, %canrestore
94 sll %g2, 3, %g2
95 mov 1, %l5
96 stb %l5, [%l6 + TI_FPDEPTH]
97
98 wrpr %g3, 0, %otherwin
99 wrpr %g2, 0, %wstate
100 sethi %hi(sparc64_kern_pri_context), %g2
101 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
102
103661: stxa %g3, [%l4] ASI_DMMU
104 .section .sun4v_1insn_patch, "ax"
105 .word 661b
106 stxa %g3, [%l4] ASI_MMU
107 .previous
108
109 sethi %hi(KERNBASE), %l4
110 flush %l4
111 mov ASI_AIUS, %l7
1122: mov %g4, %l4
113 mov %g5, %l5
114 add %g7, 4, %l2
115
116 /* Go to trap time globals so we can save them. */
117661: wrpr %g0, ETRAP_PSTATE1, %pstate
118 .section .sun4v_1insn_patch, "ax"
119 .word 661b
120 SET_GL(0)
121 .previous
122
123 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
124 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
125 sllx %l7, 24, %l7
126 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
127 rdpr %cwp, %l0
128 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
129 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
130 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
131 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
132 or %l7, %l0, %l7
133 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
134 or %l7, %l0, %l7
135 wrpr %l2, %tnpc
136 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
137 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
138 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
139 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
140 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
141 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
142 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
143 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
144 mov %l6, %g6
145 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
146 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
147 ldx [%g6 + TI_TASK], %g4
148 done
149
1503: mov ASI_P, %l7
151 ldub [%l6 + TI_FPDEPTH], %l5
152 add %l6, TI_FPSAVED + 1, %l4
153 srl %l5, 1, %l3
154 add %l5, 2, %l5
155 stb %l5, [%l6 + TI_FPDEPTH]
156 ba,pt %xcc, 2b
157 stb %g0, [%l4 + %l3]
158 nop
159
160etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
161 * We place this right after pt_regs on the trap stack.
162 * The layout is:
163 * 0x00 TL1's TSTATE
164 * 0x08 TL1's TPC
165 * 0x10 TL1's TNPC
166 * 0x18 TL1's TT
167 * ...
168 * 0x58 TL4's TT
169 * 0x60 TL
170 */
171 TRAP_LOAD_THREAD_REG(%g6, %g1)
172 sub %sp, ((4 * 8) * 4) + 8, %g2
173 rdpr %tl, %g1
174
175 wrpr %g0, 1, %tl
176 rdpr %tstate, %g3
177 stx %g3, [%g2 + STACK_BIAS + 0x00]
178 rdpr %tpc, %g3
179 stx %g3, [%g2 + STACK_BIAS + 0x08]
180 rdpr %tnpc, %g3
181 stx %g3, [%g2 + STACK_BIAS + 0x10]
182 rdpr %tt, %g3
183 stx %g3, [%g2 + STACK_BIAS + 0x18]
184
185 wrpr %g0, 2, %tl
186 rdpr %tstate, %g3
187 stx %g3, [%g2 + STACK_BIAS + 0x20]
188 rdpr %tpc, %g3
189 stx %g3, [%g2 + STACK_BIAS + 0x28]
190 rdpr %tnpc, %g3
191 stx %g3, [%g2 + STACK_BIAS + 0x30]
192 rdpr %tt, %g3
193 stx %g3, [%g2 + STACK_BIAS + 0x38]
194
195 sethi %hi(is_sun4v), %g3
196 lduw [%g3 + %lo(is_sun4v)], %g3
197 brnz,pn %g3, finish_tl1_capture
198 nop
199
200 wrpr %g0, 3, %tl
201 rdpr %tstate, %g3
202 stx %g3, [%g2 + STACK_BIAS + 0x40]
203 rdpr %tpc, %g3
204 stx %g3, [%g2 + STACK_BIAS + 0x48]
205 rdpr %tnpc, %g3
206 stx %g3, [%g2 + STACK_BIAS + 0x50]
207 rdpr %tt, %g3
208 stx %g3, [%g2 + STACK_BIAS + 0x58]
209
210 wrpr %g0, 4, %tl
211 rdpr %tstate, %g3
212 stx %g3, [%g2 + STACK_BIAS + 0x60]
213 rdpr %tpc, %g3
214 stx %g3, [%g2 + STACK_BIAS + 0x68]
215 rdpr %tnpc, %g3
216 stx %g3, [%g2 + STACK_BIAS + 0x70]
217 rdpr %tt, %g3
218 stx %g3, [%g2 + STACK_BIAS + 0x78]
219
220 stx %g1, [%g2 + STACK_BIAS + 0x80]
221
222finish_tl1_capture:
223 wrpr %g0, 1, %tl
224661: nop
225 .section .sun4v_1insn_patch, "ax"
226 .word 661b
227 SET_GL(1)
228 .previous
229
230 rdpr %tstate, %g1
231 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
232 ba,pt %xcc, 1b
233 andcc %g1, TSTATE_PRIV, %g0
234
235#undef TASK_REGOFF
236#undef ETRAP_PSTATE1
1/*
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
3 *
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/page.h>
13#include <asm/spitfire.h>
14#include <asm/head.h>
15#include <asm/processor.h>
16#include <asm/mmu.h>
17
18#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19#define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV)
20#define ETRAP_PSTATE2 \
21 (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
22
23/*
24 * On entry, %g7 is return address - 0x4.
25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
26 */
27
28 .text
29 .align 64
30 .globl etrap_syscall, etrap, etrap_irq, etraptl1
31etrap: rdpr %pil, %g2
32etrap_irq: clr %g3
33etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
34 rdpr %tstate, %g1
35 or %g1, %g3, %g1
36 sllx %g2, 20, %g3
37 andcc %g1, TSTATE_PRIV, %g0
38 or %g1, %g3, %g1
39 bne,pn %xcc, 1f
40 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
41 wrpr %g0, 7, %cleanwin
42
43 sethi %hi(TASK_REGOFF), %g2
44 sethi %hi(TSTATE_PEF), %g3
45 or %g2, %lo(TASK_REGOFF), %g2
46 and %g1, %g3, %g3
47 brnz,pn %g3, 1f
48 add %g6, %g2, %g2
49 wr %g0, 0, %fprs
501: rdpr %tpc, %g3
51
52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
53 rdpr %tnpc, %g1
54 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
55 rd %y, %g3
56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
57 rdpr %tt, %g1
58 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
59 sethi %hi(PT_REGS_MAGIC), %g3
60 or %g3, %g1, %g1
61 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
62
63 rdpr %cansave, %g1
64 brnz,pt %g1, etrap_save
65 nop
66
67 rdpr %cwp, %g1
68 add %g1, 2, %g1
69 wrpr %g1, %cwp
70 be,pt %xcc, etrap_user_spill
71 mov ASI_AIUP, %g3
72
73 rdpr %otherwin, %g3
74 brz %g3, etrap_kernel_spill
75 mov ASI_AIUS, %g3
76
77etrap_user_spill:
78
79 wr %g3, 0x0, %asi
80 ldx [%g6 + TI_FLAGS], %g3
81 and %g3, _TIF_32BIT, %g3
82 brnz,pt %g3, etrap_user_spill_32bit
83 nop
84 ba,a,pt %xcc, etrap_user_spill_64bit
85
86etrap_save: save %g2, -STACK_BIAS, %sp
87 mov %g6, %l6
88
89 bne,pn %xcc, 3f
90 mov PRIMARY_CONTEXT, %l4
91 rdpr %canrestore, %g3
92 rdpr %wstate, %g2
93 wrpr %g0, 0, %canrestore
94 sll %g2, 3, %g2
95 mov 1, %l5
96 stb %l5, [%l6 + TI_FPDEPTH]
97
98 wrpr %g3, 0, %otherwin
99 wrpr %g2, 0, %wstate
100 sethi %hi(sparc64_kern_pri_context), %g2
101 ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
102
103661: stxa %g3, [%l4] ASI_DMMU
104 .section .sun4v_1insn_patch, "ax"
105 .word 661b
106 stxa %g3, [%l4] ASI_MMU
107 .previous
108
109 sethi %hi(KERNBASE), %l4
110 flush %l4
111 mov ASI_AIUS, %l7
1122: mov %g4, %l4
113 mov %g5, %l5
114 add %g7, 4, %l2
115
116 /* Go to trap time globals so we can save them. */
117661: wrpr %g0, ETRAP_PSTATE1, %pstate
118 .section .sun4v_1insn_patch, "ax"
119 .word 661b
120 SET_GL(0)
121 .previous
122
123 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
124 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
125 sllx %l7, 24, %l7
126 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
127 rdpr %cwp, %l0
128 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
129 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
130 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
131 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
132 or %l7, %l0, %l7
133 sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
134 or %l7, %l0, %l7
135 wrpr %l2, %tnpc
136 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
137 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
138 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
139 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
140 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
141 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
142 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
143 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
144 mov %l6, %g6
145 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
146 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
147 ldx [%g6 + TI_TASK], %g4
148 done
149
1503: mov ASI_P, %l7
151 ldub [%l6 + TI_FPDEPTH], %l5
152 add %l6, TI_FPSAVED + 1, %l4
153 srl %l5, 1, %l3
154 add %l5, 2, %l5
155 stb %l5, [%l6 + TI_FPDEPTH]
156 ba,pt %xcc, 2b
157 stb %g0, [%l4 + %l3]
158 nop
159
160etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
161 * We place this right after pt_regs on the trap stack.
162 * The layout is:
163 * 0x00 TL1's TSTATE
164 * 0x08 TL1's TPC
165 * 0x10 TL1's TNPC
166 * 0x18 TL1's TT
167 * ...
168 * 0x58 TL4's TT
169 * 0x60 TL
170 */
171 TRAP_LOAD_THREAD_REG(%g6, %g1)
172 sub %sp, ((4 * 8) * 4) + 8, %g2
173 rdpr %tl, %g1
174
175 wrpr %g0, 1, %tl
176 rdpr %tstate, %g3
177 stx %g3, [%g2 + STACK_BIAS + 0x00]
178 rdpr %tpc, %g3
179 stx %g3, [%g2 + STACK_BIAS + 0x08]
180 rdpr %tnpc, %g3
181 stx %g3, [%g2 + STACK_BIAS + 0x10]
182 rdpr %tt, %g3
183 stx %g3, [%g2 + STACK_BIAS + 0x18]
184
185 wrpr %g0, 2, %tl
186 rdpr %tstate, %g3
187 stx %g3, [%g2 + STACK_BIAS + 0x20]
188 rdpr %tpc, %g3
189 stx %g3, [%g2 + STACK_BIAS + 0x28]
190 rdpr %tnpc, %g3
191 stx %g3, [%g2 + STACK_BIAS + 0x30]
192 rdpr %tt, %g3
193 stx %g3, [%g2 + STACK_BIAS + 0x38]
194
195 sethi %hi(is_sun4v), %g3
196 lduw [%g3 + %lo(is_sun4v)], %g3
197 brnz,pn %g3, finish_tl1_capture
198 nop
199
200 wrpr %g0, 3, %tl
201 rdpr %tstate, %g3
202 stx %g3, [%g2 + STACK_BIAS + 0x40]
203 rdpr %tpc, %g3
204 stx %g3, [%g2 + STACK_BIAS + 0x48]
205 rdpr %tnpc, %g3
206 stx %g3, [%g2 + STACK_BIAS + 0x50]
207 rdpr %tt, %g3
208 stx %g3, [%g2 + STACK_BIAS + 0x58]
209
210 wrpr %g0, 4, %tl
211 rdpr %tstate, %g3
212 stx %g3, [%g2 + STACK_BIAS + 0x60]
213 rdpr %tpc, %g3
214 stx %g3, [%g2 + STACK_BIAS + 0x68]
215 rdpr %tnpc, %g3
216 stx %g3, [%g2 + STACK_BIAS + 0x70]
217 rdpr %tt, %g3
218 stx %g3, [%g2 + STACK_BIAS + 0x78]
219
220 stx %g1, [%g2 + STACK_BIAS + 0x80]
221
222finish_tl1_capture:
223 wrpr %g0, 1, %tl
224661: nop
225 .section .sun4v_1insn_patch, "ax"
226 .word 661b
227 SET_GL(1)
228 .previous
229
230 rdpr %tstate, %g1
231 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
232 ba,pt %xcc, 1b
233 andcc %g1, TSTATE_PRIV, %g0
234
235#undef TASK_REGOFF
236#undef ETRAP_PSTATE1