1#include <linux/clk.h>
 2#include <linux/compiler.h>
 3#include <linux/slab.h>
 4#include <linux/io.h>
 5#include <linux/clkdev.h>
 6#include <asm/clock.h>
 7
 8static struct clk master_clk = {
 9	.flags		= CLK_ENABLE_ON_INIT,
10	.rate		= CONFIG_SH_PCLK_FREQ,
11};
12
13static struct clk peripheral_clk = {
14	.parent		= &master_clk,
15	.flags		= CLK_ENABLE_ON_INIT,
16};
17
18static struct clk bus_clk = {
19	.parent		= &master_clk,
20	.flags		= CLK_ENABLE_ON_INIT,
21};
22
23static struct clk cpu_clk = {
24	.parent		= &master_clk,
25	.flags		= CLK_ENABLE_ON_INIT,
26};
27
28/*
29 * The ordering of these clocks matters, do not change it.
30 */
31static struct clk *onchip_clocks[] = {
32	&master_clk,
33	&peripheral_clk,
34	&bus_clk,
35	&cpu_clk,
36};
37
38static struct clk_lookup lookups[] = {
39	/* main clocks */
40	CLKDEV_CON_ID("master_clk", &master_clk),
41	CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
42	CLKDEV_CON_ID("bus_clk", &bus_clk),
43	CLKDEV_CON_ID("cpu_clk", &cpu_clk),
44};
45
46int __init __deprecated cpg_clk_init(void)
47{
48	int i, ret = 0;
49
50	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
51		struct clk *clk = onchip_clocks[i];
52		arch_init_clk_ops(&clk->ops, i);
53		if (clk->ops)
54			ret |= clk_register(clk);
55	}
56
57	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
58
59	clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
60	clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
61	clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
62	clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
63
64	return ret;
65}
66
67/*
68 * Placeholder for compatibility, until the lazy CPUs do this
69 * on their own.
70 */
71int __init __weak arch_clk_init(void)
72{
73	return cpg_clk_init();
74}

 1#include <linux/clk.h>
 2#include <linux/compiler.h>
 3#include <linux/slab.h>
 4#include <linux/io.h>
 5#include <linux/clkdev.h>
 6#include <asm/clock.h>
 7
 8static struct clk master_clk = {
 9	.flags		= CLK_ENABLE_ON_INIT,
10	.rate		= CONFIG_SH_PCLK_FREQ,
11};
12
13static struct clk peripheral_clk = {
14	.parent		= &master_clk,
15	.flags		= CLK_ENABLE_ON_INIT,
16};
17
18static struct clk bus_clk = {
19	.parent		= &master_clk,
20	.flags		= CLK_ENABLE_ON_INIT,
21};
22
23static struct clk cpu_clk = {
24	.parent		= &master_clk,
25	.flags		= CLK_ENABLE_ON_INIT,
26};
27
28/*
29 * The ordering of these clocks matters, do not change it.
30 */
31static struct clk *onchip_clocks[] = {
32	&master_clk,
33	&peripheral_clk,
34	&bus_clk,
35	&cpu_clk,
36};
37
38static struct clk_lookup lookups[] = {
39	/* main clocks */
40	CLKDEV_CON_ID("master_clk", &master_clk),
41	CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
42	CLKDEV_CON_ID("bus_clk", &bus_clk),
43	CLKDEV_CON_ID("cpu_clk", &cpu_clk),
44};
45
46int __init __deprecated cpg_clk_init(void)
47{
48	int i, ret = 0;
49
50	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
51		struct clk *clk = onchip_clocks[i];
52		arch_init_clk_ops(&clk->ops, i);
53		if (clk->ops)
54			ret |= clk_register(clk);
55	}
56
57	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
58
59	clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
60	clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
61	clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
62	clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
63
64	return ret;
65}
66
67/*
68 * Placeholder for compatibility, until the lazy CPUs do this
69 * on their own.
70 */
71int __init __weak arch_clk_init(void)
72{
73	return cpg_clk_init();
74}