1/*
   2 *  arch/powerpc/kernel/mpic.c
   3 *
   4 *  Driver for interrupt controllers following the OpenPIC standard, the
   5 *  common implementation beeing IBM's MPIC. This driver also can deal
   6 *  with various broken implementations of this HW.
   7 *
   8 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9 *  Copyright 2010-2011 Freescale Semiconductor, Inc.
  10 *
  11 *  This file is subject to the terms and conditions of the GNU General Public
  12 *  License.  See the file COPYING in the main directory of this archive
  13 *  for more details.
  14 */
  15
  16#undef DEBUG
  17#undef DEBUG_IPI
  18#undef DEBUG_IRQ
  19#undef DEBUG_LOW
  20
  21#include <linux/types.h>
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24#include <linux/irq.h>
  25#include <linux/smp.h>
  26#include <linux/interrupt.h>
  27#include <linux/bootmem.h>
  28#include <linux/spinlock.h>
  29#include <linux/pci.h>
  30#include <linux/slab.h>
  31#include <linux/syscore_ops.h>
  32#include <linux/ratelimit.h>
  33
  34#include <asm/ptrace.h>
  35#include <asm/signal.h>
  36#include <asm/io.h>
  37#include <asm/pgtable.h>
  38#include <asm/irq.h>
  39#include <asm/machdep.h>
  40#include <asm/mpic.h>
  41#include <asm/smp.h>
  42
  43#include "mpic.h"
  44
  45#ifdef DEBUG
  46#define DBG(fmt...) printk(fmt)
  47#else
  48#define DBG(fmt...)
  49#endif
  50
  51static struct mpic *mpics;
  52static struct mpic *mpic_primary;
  53static DEFINE_RAW_SPINLOCK(mpic_lock);
  54
  55#ifdef CONFIG_PPC32	/* XXX for now */
  56#ifdef CONFIG_IRQ_ALL_CPUS
  57#define distribute_irqs	(1)
  58#else
  59#define distribute_irqs	(0)
  60#endif
  61#endif
  62
  63#ifdef CONFIG_MPIC_WEIRD
  64static u32 mpic_infos[][MPIC_IDX_END] = {
  65	[0] = {	/* Original OpenPIC compatible MPIC */
  66		MPIC_GREG_BASE,
  67		MPIC_GREG_FEATURE_0,
  68		MPIC_GREG_GLOBAL_CONF_0,
  69		MPIC_GREG_VENDOR_ID,
  70		MPIC_GREG_IPI_VECTOR_PRI_0,
  71		MPIC_GREG_IPI_STRIDE,
  72		MPIC_GREG_SPURIOUS,
  73		MPIC_GREG_TIMER_FREQ,
  74
  75		MPIC_TIMER_BASE,
  76		MPIC_TIMER_STRIDE,
  77		MPIC_TIMER_CURRENT_CNT,
  78		MPIC_TIMER_BASE_CNT,
  79		MPIC_TIMER_VECTOR_PRI,
  80		MPIC_TIMER_DESTINATION,
  81
  82		MPIC_CPU_BASE,
  83		MPIC_CPU_STRIDE,
  84		MPIC_CPU_IPI_DISPATCH_0,
  85		MPIC_CPU_IPI_DISPATCH_STRIDE,
  86		MPIC_CPU_CURRENT_TASK_PRI,
  87		MPIC_CPU_WHOAMI,
  88		MPIC_CPU_INTACK,
  89		MPIC_CPU_EOI,
  90		MPIC_CPU_MCACK,
  91
  92		MPIC_IRQ_BASE,
  93		MPIC_IRQ_STRIDE,
  94		MPIC_IRQ_VECTOR_PRI,
  95		MPIC_VECPRI_VECTOR_MASK,
  96		MPIC_VECPRI_POLARITY_POSITIVE,
  97		MPIC_VECPRI_POLARITY_NEGATIVE,
  98		MPIC_VECPRI_SENSE_LEVEL,
  99		MPIC_VECPRI_SENSE_EDGE,
 100		MPIC_VECPRI_POLARITY_MASK,
 101		MPIC_VECPRI_SENSE_MASK,
 102		MPIC_IRQ_DESTINATION
 103	},
 104	[1] = {	/* Tsi108/109 PIC */
 105		TSI108_GREG_BASE,
 106		TSI108_GREG_FEATURE_0,
 107		TSI108_GREG_GLOBAL_CONF_0,
 108		TSI108_GREG_VENDOR_ID,
 109		TSI108_GREG_IPI_VECTOR_PRI_0,
 110		TSI108_GREG_IPI_STRIDE,
 111		TSI108_GREG_SPURIOUS,
 112		TSI108_GREG_TIMER_FREQ,
 113
 114		TSI108_TIMER_BASE,
 115		TSI108_TIMER_STRIDE,
 116		TSI108_TIMER_CURRENT_CNT,
 117		TSI108_TIMER_BASE_CNT,
 118		TSI108_TIMER_VECTOR_PRI,
 119		TSI108_TIMER_DESTINATION,
 120
 121		TSI108_CPU_BASE,
 122		TSI108_CPU_STRIDE,
 123		TSI108_CPU_IPI_DISPATCH_0,
 124		TSI108_CPU_IPI_DISPATCH_STRIDE,
 125		TSI108_CPU_CURRENT_TASK_PRI,
 126		TSI108_CPU_WHOAMI,
 127		TSI108_CPU_INTACK,
 128		TSI108_CPU_EOI,
 129		TSI108_CPU_MCACK,
 130
 131		TSI108_IRQ_BASE,
 132		TSI108_IRQ_STRIDE,
 133		TSI108_IRQ_VECTOR_PRI,
 134		TSI108_VECPRI_VECTOR_MASK,
 135		TSI108_VECPRI_POLARITY_POSITIVE,
 136		TSI108_VECPRI_POLARITY_NEGATIVE,
 137		TSI108_VECPRI_SENSE_LEVEL,
 138		TSI108_VECPRI_SENSE_EDGE,
 139		TSI108_VECPRI_POLARITY_MASK,
 140		TSI108_VECPRI_SENSE_MASK,
 141		TSI108_IRQ_DESTINATION
 142	},
 143};
 144
 145#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 146
 147#else /* CONFIG_MPIC_WEIRD */
 148
 149#define MPIC_INFO(name) MPIC_##name
 150
 151#endif /* CONFIG_MPIC_WEIRD */
 152
 153static inline unsigned int mpic_processor_id(struct mpic *mpic)
 154{
 155	unsigned int cpu = 0;
 156
 157	if (!(mpic->flags & MPIC_SECONDARY))
 158		cpu = hard_smp_processor_id();
 159
 160	return cpu;
 161}
 162
 163/*
 164 * Register accessor functions
 165 */
 166
 167
 168static inline u32 _mpic_read(enum mpic_reg_type type,
 169			     struct mpic_reg_bank *rb,
 170			     unsigned int reg)
 171{
 172	switch(type) {
 173#ifdef CONFIG_PPC_DCR
 174	case mpic_access_dcr:
 175		return dcr_read(rb->dhost, reg);
 176#endif
 177	case mpic_access_mmio_be:
 178		return in_be32(rb->base + (reg >> 2));
 179	case mpic_access_mmio_le:
 180	default:
 181		return in_le32(rb->base + (reg >> 2));
 182	}
 183}
 184
 185static inline void _mpic_write(enum mpic_reg_type type,
 186			       struct mpic_reg_bank *rb,
 187 			       unsigned int reg, u32 value)
 188{
 189	switch(type) {
 190#ifdef CONFIG_PPC_DCR
 191	case mpic_access_dcr:
 192		dcr_write(rb->dhost, reg, value);
 193		break;
 194#endif
 195	case mpic_access_mmio_be:
 196		out_be32(rb->base + (reg >> 2), value);
 197		break;
 198	case mpic_access_mmio_le:
 199	default:
 200		out_le32(rb->base + (reg >> 2), value);
 201		break;
 202	}
 203}
 204
 205static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 206{
 207	enum mpic_reg_type type = mpic->reg_type;
 208	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 209			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 210
 211	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 212		type = mpic_access_mmio_be;
 213	return _mpic_read(type, &mpic->gregs, offset);
 214}
 215
 216static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 217{
 218	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 219			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 220
 221	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 222}
 223
 224static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
 225{
 226	unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
 227			      ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
 228
 229	if (tm >= 4)
 230		offset += 0x1000 / 4;
 231
 232	return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
 233}
 234
 235static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
 236{
 237	unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
 238			      ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
 239
 240	if (tm >= 4)
 241		offset += 0x1000 / 4;
 242
 243	_mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
 244}
 245
 246static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 247{
 248	unsigned int cpu = mpic_processor_id(mpic);
 249
 250	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 251}
 252
 253static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 254{
 255	unsigned int cpu = mpic_processor_id(mpic);
 256
 257	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 258}
 259
 260static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 261{
 262	unsigned int	isu = src_no >> mpic->isu_shift;
 263	unsigned int	idx = src_no & mpic->isu_mask;
 264	unsigned int	val;
 265
 266	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 267			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 268#ifdef CONFIG_MPIC_BROKEN_REGREAD
 269	if (reg == 0)
 270		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 271			mpic->isu_reg0_shadow[src_no];
 272#endif
 273	return val;
 274}
 275
 276static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 277				   unsigned int reg, u32 value)
 278{
 279	unsigned int	isu = src_no >> mpic->isu_shift;
 280	unsigned int	idx = src_no & mpic->isu_mask;
 281
 282	_mpic_write(mpic->reg_type, &mpic->isus[isu],
 283		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 284
 285#ifdef CONFIG_MPIC_BROKEN_REGREAD
 286	if (reg == 0)
 287		mpic->isu_reg0_shadow[src_no] =
 288			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 289#endif
 290}
 291
 292#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
 293#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
 294#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
 295#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
 296#define mpic_tm_read(i)		_mpic_tm_read(mpic,(i))
 297#define mpic_tm_write(i,v)	_mpic_tm_write(mpic,(i),(v))
 298#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
 299#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
 300#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
 301#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))
 302
 303
 304/*
 305 * Low level utility functions
 306 */
 307
 308
 309static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 310			   struct mpic_reg_bank *rb, unsigned int offset,
 311			   unsigned int size)
 312{
 313	rb->base = ioremap(phys_addr + offset, size);
 314	BUG_ON(rb->base == NULL);
 315}
 316
 317#ifdef CONFIG_PPC_DCR
 318static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
 
 319			  unsigned int offset, unsigned int size)
 320{
 321	phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
 322	rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
 
 
 
 323	BUG_ON(!DCR_MAP_OK(rb->dhost));
 324}
 325
 326static inline void mpic_map(struct mpic *mpic,
 327			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 328			    unsigned int offset, unsigned int size)
 329{
 330	if (mpic->flags & MPIC_USES_DCR)
 331		_mpic_map_dcr(mpic, rb, offset, size);
 332	else
 333		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 334}
 335#else /* CONFIG_PPC_DCR */
 336#define mpic_map(m,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
 337#endif /* !CONFIG_PPC_DCR */
 338
 339
 340
 341/* Check if we have one of those nice broken MPICs with a flipped endian on
 342 * reads from IPI registers
 343 */
 344static void __init mpic_test_broken_ipi(struct mpic *mpic)
 345{
 346	u32 r;
 347
 348	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 349	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 350
 351	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 352		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 353		mpic->flags |= MPIC_BROKEN_IPI;
 354	}
 355}
 356
 357#ifdef CONFIG_MPIC_U3_HT_IRQS
 358
 359/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 360 * to force the edge setting on the MPIC and do the ack workaround.
 361 */
 362static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 363{
 364	if (source >= 128 || !mpic->fixups)
 365		return 0;
 366	return mpic->fixups[source].base != NULL;
 367}
 368
 369
 370static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 371{
 372	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 373
 374	if (fixup->applebase) {
 375		unsigned int soff = (fixup->index >> 3) & ~3;
 376		unsigned int mask = 1U << (fixup->index & 0x1f);
 377		writel(mask, fixup->applebase + soff);
 378	} else {
 379		raw_spin_lock(&mpic->fixup_lock);
 380		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 381		writel(fixup->data, fixup->base + 4);
 382		raw_spin_unlock(&mpic->fixup_lock);
 383	}
 384}
 385
 386static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 387				      bool level)
 388{
 389	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 390	unsigned long flags;
 391	u32 tmp;
 392
 393	if (fixup->base == NULL)
 394		return;
 395
 396	DBG("startup_ht_interrupt(0x%x) index: %d\n",
 397	    source, fixup->index);
 398	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 399	/* Enable and configure */
 400	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 401	tmp = readl(fixup->base + 4);
 402	tmp &= ~(0x23U);
 403	if (level)
 404		tmp |= 0x22;
 405	writel(tmp, fixup->base + 4);
 406	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 407
 408#ifdef CONFIG_PM
 409	/* use the lowest bit inverted to the actual HW,
 410	 * set if this fixup was enabled, clear otherwise */
 411	mpic->save_data[source].fixup_data = tmp | 1;
 412#endif
 413}
 414
 415static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 416{
 417	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 418	unsigned long flags;
 419	u32 tmp;
 420
 421	if (fixup->base == NULL)
 422		return;
 423
 424	DBG("shutdown_ht_interrupt(0x%x)\n", source);
 425
 426	/* Disable */
 427	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
 428	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 429	tmp = readl(fixup->base + 4);
 430	tmp |= 1;
 431	writel(tmp, fixup->base + 4);
 432	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 433
 434#ifdef CONFIG_PM
 435	/* use the lowest bit inverted to the actual HW,
 436	 * set if this fixup was enabled, clear otherwise */
 437	mpic->save_data[source].fixup_data = tmp & ~1;
 438#endif
 439}
 440
 441#ifdef CONFIG_PCI_MSI
 442static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 443				    unsigned int devfn)
 444{
 445	u8 __iomem *base;
 446	u8 pos, flags;
 447	u64 addr = 0;
 448
 449	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 450	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 451		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 452		if (id == PCI_CAP_ID_HT) {
 453			id = readb(devbase + pos + 3);
 454			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 455				break;
 456		}
 457	}
 458
 459	if (pos == 0)
 460		return;
 461
 462	base = devbase + pos;
 463
 464	flags = readb(base + HT_MSI_FLAGS);
 465	if (!(flags & HT_MSI_FLAGS_FIXED)) {
 466		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 467		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 468	}
 469
 470	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 471		PCI_SLOT(devfn), PCI_FUNC(devfn),
 472		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 473
 474	if (!(flags & HT_MSI_FLAGS_ENABLE))
 475		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 476}
 477#else
 478static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 479				    unsigned int devfn)
 480{
 481	return;
 482}
 483#endif
 484
 485static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 486				    unsigned int devfn, u32 vdid)
 487{
 488	int i, irq, n;
 489	u8 __iomem *base;
 490	u32 tmp;
 491	u8 pos;
 492
 493	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 494	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 495		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 496		if (id == PCI_CAP_ID_HT) {
 497			id = readb(devbase + pos + 3);
 498			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 499				break;
 500		}
 501	}
 502	if (pos == 0)
 503		return;
 504
 505	base = devbase + pos;
 506	writeb(0x01, base + 2);
 507	n = (readl(base + 4) >> 16) & 0xff;
 508
 509	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 510	       " has %d irqs\n",
 511	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 512
 513	for (i = 0; i <= n; i++) {
 514		writeb(0x10 + 2 * i, base + 2);
 515		tmp = readl(base + 4);
 516		irq = (tmp >> 16) & 0xff;
 517		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 518		/* mask it , will be unmasked later */
 519		tmp |= 0x1;
 520		writel(tmp, base + 4);
 521		mpic->fixups[irq].index = i;
 522		mpic->fixups[irq].base = base;
 523		/* Apple HT PIC has a non-standard way of doing EOIs */
 524		if ((vdid & 0xffff) == 0x106b)
 525			mpic->fixups[irq].applebase = devbase + 0x60;
 526		else
 527			mpic->fixups[irq].applebase = NULL;
 528		writeb(0x11 + 2 * i, base + 2);
 529		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 530	}
 531}
 532 
 533
 534static void __init mpic_scan_ht_pics(struct mpic *mpic)
 535{
 536	unsigned int devfn;
 537	u8 __iomem *cfgspace;
 538
 539	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 540
 541	/* Allocate fixups array */
 542	mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 543	BUG_ON(mpic->fixups == NULL);
 544
 545	/* Init spinlock */
 546	raw_spin_lock_init(&mpic->fixup_lock);
 547
 548	/* Map U3 config space. We assume all IO-APICs are on the primary bus
 549	 * so we only need to map 64kB.
 550	 */
 551	cfgspace = ioremap(0xf2000000, 0x10000);
 552	BUG_ON(cfgspace == NULL);
 553
 554	/* Now we scan all slots. We do a very quick scan, we read the header
 555	 * type, vendor ID and device ID only, that's plenty enough
 556	 */
 557	for (devfn = 0; devfn < 0x100; devfn++) {
 558		u8 __iomem *devbase = cfgspace + (devfn << 8);
 559		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 560		u32 l = readl(devbase + PCI_VENDOR_ID);
 561		u16 s;
 562
 563		DBG("devfn %x, l: %x\n", devfn, l);
 564
 565		/* If no device, skip */
 566		if (l == 0xffffffff || l == 0x00000000 ||
 567		    l == 0x0000ffff || l == 0xffff0000)
 568			goto next;
 569		/* Check if is supports capability lists */
 570		s = readw(devbase + PCI_STATUS);
 571		if (!(s & PCI_STATUS_CAP_LIST))
 572			goto next;
 573
 574		mpic_scan_ht_pic(mpic, devbase, devfn, l);
 575		mpic_scan_ht_msi(mpic, devbase, devfn);
 576
 577	next:
 578		/* next device, if function 0 */
 579		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 580			devfn += 7;
 581	}
 582}
 583
 584#else /* CONFIG_MPIC_U3_HT_IRQS */
 585
 586static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 587{
 588	return 0;
 589}
 590
 591static void __init mpic_scan_ht_pics(struct mpic *mpic)
 592{
 593}
 594
 595#endif /* CONFIG_MPIC_U3_HT_IRQS */
 596
 597/* Find an mpic associated with a given linux interrupt */
 598static struct mpic *mpic_find(unsigned int irq)
 599{
 600	if (irq < NUM_ISA_INTERRUPTS)
 601		return NULL;
 602
 603	return irq_get_chip_data(irq);
 604}
 605
 606/* Determine if the linux irq is an IPI */
 607static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 608{
 
 
 609	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 610}
 611
 612/* Determine if the linux irq is a timer */
 613static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 614{
 
 
 615	return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 616}
 617
 618/* Convert a cpu mask from logical to physical cpu numbers. */
 619static inline u32 mpic_physmask(u32 cpumask)
 620{
 621	int i;
 622	u32 mask = 0;
 623
 624	for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
 625		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 626	return mask;
 627}
 628
 629#ifdef CONFIG_SMP
 630/* Get the mpic structure from the IPI number */
 631static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 632{
 633	return irq_data_get_irq_chip_data(d);
 634}
 635#endif
 636
 637/* Get the mpic structure from the irq number */
 638static inline struct mpic * mpic_from_irq(unsigned int irq)
 639{
 640	return irq_get_chip_data(irq);
 641}
 642
 643/* Get the mpic structure from the irq data */
 644static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
 645{
 646	return irq_data_get_irq_chip_data(d);
 647}
 648
 649/* Send an EOI */
 650static inline void mpic_eoi(struct mpic *mpic)
 651{
 652	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 653	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 654}
 655
 656/*
 657 * Linux descriptor level callbacks
 658 */
 659
 660
 661void mpic_unmask_irq(struct irq_data *d)
 662{
 663	unsigned int loops = 100000;
 664	struct mpic *mpic = mpic_from_irq_data(d);
 665	unsigned int src = irqd_to_hwirq(d);
 666
 667	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
 668
 669	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 670		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 671		       ~MPIC_VECPRI_MASK);
 672	/* make sure mask gets to controller before we return to user */
 673	do {
 674		if (!loops--) {
 675			printk(KERN_ERR "%s: timeout on hwirq %u\n",
 676			       __func__, src);
 677			break;
 678		}
 679	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 680}
 681
 682void mpic_mask_irq(struct irq_data *d)
 683{
 684	unsigned int loops = 100000;
 685	struct mpic *mpic = mpic_from_irq_data(d);
 686	unsigned int src = irqd_to_hwirq(d);
 687
 688	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
 689
 690	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 691		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 692		       MPIC_VECPRI_MASK);
 693
 694	/* make sure mask gets to controller before we return to user */
 695	do {
 696		if (!loops--) {
 697			printk(KERN_ERR "%s: timeout on hwirq %u\n",
 698			       __func__, src);
 699			break;
 700		}
 701	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 702}
 703
 704void mpic_end_irq(struct irq_data *d)
 705{
 706	struct mpic *mpic = mpic_from_irq_data(d);
 707
 708#ifdef DEBUG_IRQ
 709	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 710#endif
 711	/* We always EOI on end_irq() even for edge interrupts since that
 712	 * should only lower the priority, the MPIC should have properly
 713	 * latched another edge interrupt coming in anyway
 714	 */
 715
 716	mpic_eoi(mpic);
 717}
 718
 719#ifdef CONFIG_MPIC_U3_HT_IRQS
 720
 721static void mpic_unmask_ht_irq(struct irq_data *d)
 722{
 723	struct mpic *mpic = mpic_from_irq_data(d);
 724	unsigned int src = irqd_to_hwirq(d);
 725
 726	mpic_unmask_irq(d);
 727
 728	if (irqd_is_level_type(d))
 729		mpic_ht_end_irq(mpic, src);
 730}
 731
 732static unsigned int mpic_startup_ht_irq(struct irq_data *d)
 733{
 734	struct mpic *mpic = mpic_from_irq_data(d);
 735	unsigned int src = irqd_to_hwirq(d);
 736
 737	mpic_unmask_irq(d);
 738	mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 739
 740	return 0;
 741}
 742
 743static void mpic_shutdown_ht_irq(struct irq_data *d)
 744{
 745	struct mpic *mpic = mpic_from_irq_data(d);
 746	unsigned int src = irqd_to_hwirq(d);
 747
 748	mpic_shutdown_ht_interrupt(mpic, src);
 749	mpic_mask_irq(d);
 750}
 751
 752static void mpic_end_ht_irq(struct irq_data *d)
 753{
 754	struct mpic *mpic = mpic_from_irq_data(d);
 755	unsigned int src = irqd_to_hwirq(d);
 756
 757#ifdef DEBUG_IRQ
 758	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
 759#endif
 760	/* We always EOI on end_irq() even for edge interrupts since that
 761	 * should only lower the priority, the MPIC should have properly
 762	 * latched another edge interrupt coming in anyway
 763	 */
 764
 765	if (irqd_is_level_type(d))
 766		mpic_ht_end_irq(mpic, src);
 767	mpic_eoi(mpic);
 768}
 769#endif /* !CONFIG_MPIC_U3_HT_IRQS */
 770
 771#ifdef CONFIG_SMP
 772
 773static void mpic_unmask_ipi(struct irq_data *d)
 774{
 775	struct mpic *mpic = mpic_from_ipi(d);
 776	unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
 777
 778	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
 779	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 780}
 781
 782static void mpic_mask_ipi(struct irq_data *d)
 783{
 784	/* NEVER disable an IPI... that's just plain wrong! */
 785}
 786
 787static void mpic_end_ipi(struct irq_data *d)
 788{
 789	struct mpic *mpic = mpic_from_ipi(d);
 790
 791	/*
 792	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
 793	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 794	 * applying to them. We EOI them late to avoid re-entering.
 
 
 795	 */
 796	mpic_eoi(mpic);
 797}
 798
 799#endif /* CONFIG_SMP */
 800
 801static void mpic_unmask_tm(struct irq_data *d)
 802{
 803	struct mpic *mpic = mpic_from_irq_data(d);
 804	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 805
 806	DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
 807	mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
 808	mpic_tm_read(src);
 809}
 810
 811static void mpic_mask_tm(struct irq_data *d)
 812{
 813	struct mpic *mpic = mpic_from_irq_data(d);
 814	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
 815
 816	mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
 817	mpic_tm_read(src);
 818}
 819
 820int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 821		      bool force)
 822{
 823	struct mpic *mpic = mpic_from_irq_data(d);
 824	unsigned int src = irqd_to_hwirq(d);
 825
 826	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 827		int cpuid = irq_choose_cpu(cpumask);
 828
 829		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 830	} else {
 831		u32 mask = cpumask_bits(cpumask)[0];
 832
 833		mask &= cpumask_bits(cpu_online_mask)[0];
 834
 835		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 836			       mpic_physmask(mask));
 837	}
 838
 839	return 0;
 840}
 841
 842static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 843{
 844	/* Now convert sense value */
 845	switch(type & IRQ_TYPE_SENSE_MASK) {
 846	case IRQ_TYPE_EDGE_RISING:
 847		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 848		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 849	case IRQ_TYPE_EDGE_FALLING:
 850	case IRQ_TYPE_EDGE_BOTH:
 851		return MPIC_INFO(VECPRI_SENSE_EDGE) |
 852		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 853	case IRQ_TYPE_LEVEL_HIGH:
 854		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 855		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 856	case IRQ_TYPE_LEVEL_LOW:
 857	default:
 858		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 859		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 860	}
 861}
 862
 863int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 864{
 865	struct mpic *mpic = mpic_from_irq_data(d);
 866	unsigned int src = irqd_to_hwirq(d);
 867	unsigned int vecpri, vold, vnew;
 868
 869	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 870	    mpic, d->irq, src, flow_type);
 871
 872	if (src >= mpic->num_sources)
 873		return -EINVAL;
 874
 875	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 876
 877	/* We don't support "none" type */
 878	if (flow_type == IRQ_TYPE_NONE)
 879		flow_type = IRQ_TYPE_DEFAULT;
 880
 881	/* Default: read HW settings */
 882	if (flow_type == IRQ_TYPE_DEFAULT) {
 883		switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
 884			       MPIC_INFO(VECPRI_SENSE_MASK))) {
 885			case MPIC_INFO(VECPRI_SENSE_EDGE) |
 886			     MPIC_INFO(VECPRI_POLARITY_POSITIVE):
 887				flow_type = IRQ_TYPE_EDGE_RISING;
 888				break;
 889			case MPIC_INFO(VECPRI_SENSE_EDGE) |
 890			     MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
 891				flow_type = IRQ_TYPE_EDGE_FALLING;
 892				break;
 893			case MPIC_INFO(VECPRI_SENSE_LEVEL) |
 894			     MPIC_INFO(VECPRI_POLARITY_POSITIVE):
 895				flow_type = IRQ_TYPE_LEVEL_HIGH;
 896				break;
 897			case MPIC_INFO(VECPRI_SENSE_LEVEL) |
 898			     MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
 899				flow_type = IRQ_TYPE_LEVEL_LOW;
 900				break;
 901		}
 902	}
 903
 904	/* Apply to irq desc */
 905	irqd_set_trigger_type(d, flow_type);
 906
 907	/* Apply to HW */
 908	if (mpic_is_ht_interrupt(mpic, src))
 909		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 910			MPIC_VECPRI_SENSE_EDGE;
 911	else
 912		vecpri = mpic_type_to_vecpri(mpic, flow_type);
 913
 
 914	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 915			MPIC_INFO(VECPRI_SENSE_MASK));
 916	vnew |= vecpri;
 917	if (vold != vnew)
 918		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 919
 920	return IRQ_SET_MASK_OK_NOCOPY;
 921}
 922
 923void mpic_set_vector(unsigned int virq, unsigned int vector)
 924{
 925	struct mpic *mpic = mpic_from_irq(virq);
 926	unsigned int src = virq_to_hw(virq);
 927	unsigned int vecpri;
 928
 929	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 930	    mpic, virq, src, vector);
 931
 932	if (src >= mpic->num_sources)
 933		return;
 934
 935	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 936	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 937	vecpri |= vector;
 938	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 939}
 940
 941void mpic_set_destination(unsigned int virq, unsigned int cpuid)
 942{
 943	struct mpic *mpic = mpic_from_irq(virq);
 944	unsigned int src = virq_to_hw(virq);
 945
 946	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
 947	    mpic, virq, src, cpuid);
 948
 949	if (src >= mpic->num_sources)
 950		return;
 951
 952	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 953}
 954
 955static struct irq_chip mpic_irq_chip = {
 956	.irq_mask	= mpic_mask_irq,
 957	.irq_unmask	= mpic_unmask_irq,
 958	.irq_eoi	= mpic_end_irq,
 959	.irq_set_type	= mpic_set_irq_type,
 960};
 961
 962#ifdef CONFIG_SMP
 963static struct irq_chip mpic_ipi_chip = {
 964	.irq_mask	= mpic_mask_ipi,
 965	.irq_unmask	= mpic_unmask_ipi,
 966	.irq_eoi	= mpic_end_ipi,
 967};
 968#endif /* CONFIG_SMP */
 969
 970static struct irq_chip mpic_tm_chip = {
 971	.irq_mask	= mpic_mask_tm,
 972	.irq_unmask	= mpic_unmask_tm,
 973	.irq_eoi	= mpic_end_irq,
 974};
 975
 976#ifdef CONFIG_MPIC_U3_HT_IRQS
 977static struct irq_chip mpic_irq_ht_chip = {
 978	.irq_startup	= mpic_startup_ht_irq,
 979	.irq_shutdown	= mpic_shutdown_ht_irq,
 980	.irq_mask	= mpic_mask_irq,
 981	.irq_unmask	= mpic_unmask_ht_irq,
 982	.irq_eoi	= mpic_end_ht_irq,
 983	.irq_set_type	= mpic_set_irq_type,
 984};
 985#endif /* CONFIG_MPIC_U3_HT_IRQS */
 986
 987
 988static int mpic_host_match(struct irq_domain *h, struct device_node *node)
 989{
 990	/* Exact match, unless mpic node is NULL */
 991	return h->of_node == NULL || h->of_node == node;
 992}
 993
 994static int mpic_host_map(struct irq_domain *h, unsigned int virq,
 995			 irq_hw_number_t hw)
 996{
 997	struct mpic *mpic = h->host_data;
 998	struct irq_chip *chip;
 999
1000	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1001
1002	if (hw == mpic->spurious_vec)
1003		return -EINVAL;
1004	if (mpic->protected && test_bit(hw, mpic->protected))
1005		return -EINVAL;
1006
1007#ifdef CONFIG_SMP
1008	else if (hw >= mpic->ipi_vecs[0]) {
1009		WARN_ON(mpic->flags & MPIC_SECONDARY);
1010
1011		DBG("mpic: mapping as IPI\n");
1012		irq_set_chip_data(virq, mpic);
1013		irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1014					 handle_percpu_irq);
1015		return 0;
1016	}
1017#endif /* CONFIG_SMP */
1018
1019	if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1020		WARN_ON(mpic->flags & MPIC_SECONDARY);
1021
1022		DBG("mpic: mapping as timer\n");
1023		irq_set_chip_data(virq, mpic);
1024		irq_set_chip_and_handler(virq, &mpic->hc_tm,
1025					 handle_fasteoi_irq);
1026		return 0;
1027	}
1028
1029	if (hw >= mpic->num_sources)
1030		return -EINVAL;
1031
1032	mpic_msi_reserve_hwirq(mpic, hw);
1033
1034	/* Default chip */
1035	chip = &mpic->hc_irq;
1036
1037#ifdef CONFIG_MPIC_U3_HT_IRQS
1038	/* Check for HT interrupts, override vecpri */
1039	if (mpic_is_ht_interrupt(mpic, hw))
1040		chip = &mpic->hc_ht_irq;
1041#endif /* CONFIG_MPIC_U3_HT_IRQS */
1042
1043	DBG("mpic: mapping to irq chip @%p\n", chip);
1044
1045	irq_set_chip_data(virq, mpic);
1046	irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1047
1048	/* Set default irq type */
1049	irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1050
1051	/* If the MPIC was reset, then all vectors have already been
1052	 * initialized.  Otherwise, a per source lazy initialization
1053	 * is done here.
1054	 */
1055	if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1056		mpic_set_vector(virq, hw);
1057		mpic_set_destination(virq, mpic_processor_id(mpic));
1058		mpic_irq_set_priority(virq, 8);
1059	}
1060
1061	return 0;
1062}
1063
1064static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1065			   const u32 *intspec, unsigned int intsize,
1066			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1067
1068{
1069	struct mpic *mpic = h->host_data;
1070	static unsigned char map_mpic_senses[4] = {
1071		IRQ_TYPE_EDGE_RISING,
1072		IRQ_TYPE_LEVEL_LOW,
1073		IRQ_TYPE_LEVEL_HIGH,
1074		IRQ_TYPE_EDGE_FALLING,
1075	};
1076
1077	*out_hwirq = intspec[0];
1078	if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1079		/*
1080		 * Freescale MPIC with extended intspec:
1081		 * First two cells are as usual.  Third specifies
1082		 * an "interrupt type".  Fourth is type-specific data.
1083		 *
1084		 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1085		 */
1086		switch (intspec[2]) {
1087		case 0:
1088		case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1089			break;
1090		case 2:
1091			if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1092				return -EINVAL;
1093
1094			*out_hwirq = mpic->ipi_vecs[intspec[0]];
1095			break;
1096		case 3:
1097			if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1098				return -EINVAL;
1099
1100			*out_hwirq = mpic->timer_vecs[intspec[0]];
1101			break;
1102		default:
1103			pr_debug("%s: unknown irq type %u\n",
1104				 __func__, intspec[2]);
1105			return -EINVAL;
1106		}
1107
1108		*out_flags = map_mpic_senses[intspec[1] & 3];
1109	} else if (intsize > 1) {
1110		u32 mask = 0x3;
1111
1112		/* Apple invented a new race of encoding on machines with
1113		 * an HT APIC. They encode, among others, the index within
1114		 * the HT APIC. We don't care about it here since thankfully,
1115		 * it appears that they have the APIC already properly
1116		 * configured, and thus our current fixup code that reads the
1117		 * APIC config works fine. However, we still need to mask out
1118		 * bits in the specifier to make sure we only get bit 0 which
1119		 * is the level/edge bit (the only sense bit exposed by Apple),
1120		 * as their bit 1 means something else.
1121		 */
1122		if (machine_is(powermac))
1123			mask = 0x1;
1124		*out_flags = map_mpic_senses[intspec[1] & mask];
1125	} else
1126		*out_flags = IRQ_TYPE_NONE;
1127
1128	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1129	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1130
1131	return 0;
1132}
1133
1134/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1135static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1136{
1137	struct irq_chip *chip = irq_desc_get_chip(desc);
1138	struct mpic *mpic = irq_desc_get_handler_data(desc);
1139	unsigned int virq;
1140
1141	BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1142
1143	virq = mpic_get_one_irq(mpic);
1144	if (virq)
1145		generic_handle_irq(virq);
1146
1147	chip->irq_eoi(&desc->irq_data);
1148}
1149
1150static struct irq_domain_ops mpic_host_ops = {
1151	.match = mpic_host_match,
1152	.map = mpic_host_map,
1153	.xlate = mpic_host_xlate,
1154};
1155
 
 
 
 
 
1156/*
1157 * Exported functions
1158 */
1159
1160struct mpic * __init mpic_alloc(struct device_node *node,
1161				phys_addr_t phys_addr,
1162				unsigned int flags,
1163				unsigned int isu_size,
1164				unsigned int irq_count,
1165				const char *name)
1166{
1167	int i, psize, intvec_top;
1168	struct mpic *mpic;
1169	u32 greg_feature;
1170	const char *vers;
1171	const u32 *psrc;
1172	u32 last_irq;
1173
1174	/* Default MPIC search parameters */
1175	static const struct of_device_id __initconst mpic_device_id[] = {
1176		{ .type	      = "open-pic", },
1177		{ .compatible = "open-pic", },
1178		{},
1179	};
1180
1181	/*
1182	 * If we were not passed a device-tree node, then perform the default
1183	 * search for standardized a standardized OpenPIC.
1184	 */
1185	if (node) {
1186		node = of_node_get(node);
1187	} else {
1188		node = of_find_matching_node(NULL, mpic_device_id);
1189		if (!node)
1190			return NULL;
1191	}
1192
1193	/* Pick the physical address from the device tree if unspecified */
1194	if (!phys_addr) {
1195		/* Check if it is DCR-based */
1196		if (of_get_property(node, "dcr-reg", NULL)) {
1197			flags |= MPIC_USES_DCR;
1198		} else {
1199			struct resource r;
1200			if (of_address_to_resource(node, 0, &r))
1201				goto err_of_node_put;
1202			phys_addr = r.start;
1203		}
1204	}
1205
1206	/* Read extra device-tree properties into the flags variable */
1207	if (of_get_property(node, "big-endian", NULL))
1208		flags |= MPIC_BIG_ENDIAN;
1209	if (of_get_property(node, "pic-no-reset", NULL))
1210		flags |= MPIC_NO_RESET;
1211	if (of_get_property(node, "single-cpu-affinity", NULL))
1212		flags |= MPIC_SINGLE_DEST_CPU;
1213	if (of_device_is_compatible(node, "fsl,mpic"))
1214		flags |= MPIC_FSL;
1215
1216	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1217	if (mpic == NULL)
1218		goto err_of_node_put;
1219
1220	mpic->name = name;
1221	mpic->node = node;
1222	mpic->paddr = phys_addr;
1223	mpic->flags = flags;
1224
1225	mpic->hc_irq = mpic_irq_chip;
1226	mpic->hc_irq.name = name;
1227	if (!(mpic->flags & MPIC_SECONDARY))
1228		mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1229#ifdef CONFIG_MPIC_U3_HT_IRQS
1230	mpic->hc_ht_irq = mpic_irq_ht_chip;
1231	mpic->hc_ht_irq.name = name;
1232	if (!(mpic->flags & MPIC_SECONDARY))
1233		mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1234#endif /* CONFIG_MPIC_U3_HT_IRQS */
1235
1236#ifdef CONFIG_SMP
1237	mpic->hc_ipi = mpic_ipi_chip;
1238	mpic->hc_ipi.name = name;
1239#endif /* CONFIG_SMP */
1240
1241	mpic->hc_tm = mpic_tm_chip;
1242	mpic->hc_tm.name = name;
1243
 
 
 
1244	mpic->num_sources = 0; /* so far */
1245
1246	if (mpic->flags & MPIC_LARGE_VECTORS)
1247		intvec_top = 2047;
1248	else
1249		intvec_top = 255;
1250
1251	mpic->timer_vecs[0] = intvec_top - 12;
1252	mpic->timer_vecs[1] = intvec_top - 11;
1253	mpic->timer_vecs[2] = intvec_top - 10;
1254	mpic->timer_vecs[3] = intvec_top - 9;
1255	mpic->timer_vecs[4] = intvec_top - 8;
1256	mpic->timer_vecs[5] = intvec_top - 7;
1257	mpic->timer_vecs[6] = intvec_top - 6;
1258	mpic->timer_vecs[7] = intvec_top - 5;
1259	mpic->ipi_vecs[0]   = intvec_top - 4;
1260	mpic->ipi_vecs[1]   = intvec_top - 3;
1261	mpic->ipi_vecs[2]   = intvec_top - 2;
1262	mpic->ipi_vecs[3]   = intvec_top - 1;
1263	mpic->spurious_vec  = intvec_top;
1264
 
 
 
 
 
 
1265	/* Look for protected sources */
1266	psrc = of_get_property(mpic->node, "protected-sources", &psize);
1267	if (psrc) {
1268		/* Allocate a bitmap with one bit per interrupt */
1269		unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1270		mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1271		BUG_ON(mpic->protected == NULL);
1272		for (i = 0; i < psize/sizeof(u32); i++) {
1273			if (psrc[i] > intvec_top)
1274				continue;
1275			__set_bit(psrc[i], mpic->protected);
 
 
 
 
 
 
1276		}
1277	}
1278
1279#ifdef CONFIG_MPIC_WEIRD
1280	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1281#endif
1282
1283	/* default register type */
1284	if (mpic->flags & MPIC_BIG_ENDIAN)
1285		mpic->reg_type = mpic_access_mmio_be;
1286	else
1287		mpic->reg_type = mpic_access_mmio_le;
1288
1289	/*
1290	 * An MPIC with a "dcr-reg" property must be accessed that way, but
1291	 * only if the kernel includes DCR support.
1292	 */
 
1293#ifdef CONFIG_PPC_DCR
1294	if (mpic->flags & MPIC_USES_DCR)
1295		mpic->reg_type = mpic_access_dcr;
1296#else
1297	BUG_ON(mpic->flags & MPIC_USES_DCR);
1298#endif
 
 
 
 
 
 
 
 
 
 
 
1299
1300	/* Map the global registers */
1301	mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1302	mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1303
1304	/* Reset */
1305
1306	/* When using a device-node, reset requests are only honored if the MPIC
1307	 * is allowed to reset.
1308	 */
1309	if (!(mpic->flags & MPIC_NO_RESET)) {
 
 
 
1310		printk(KERN_DEBUG "mpic: Resetting\n");
1311		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1312			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1313			   | MPIC_GREG_GCONF_RESET);
1314		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1315		       & MPIC_GREG_GCONF_RESET)
1316			mb();
1317	}
1318
1319	/* CoreInt */
1320	if (mpic->flags & MPIC_ENABLE_COREINT)
1321		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1322			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1323			   | MPIC_GREG_GCONF_COREINT);
1324
1325	if (mpic->flags & MPIC_ENABLE_MCK)
1326		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1327			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1328			   | MPIC_GREG_GCONF_MCK);
1329
1330	/*
1331	 * The MPIC driver will crash if there are more cores than we
1332	 * can initialize, so we may as well catch that problem here.
1333	 */
1334	BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
 
 
 
 
 
 
 
 
 
 
1335
1336	/* Map the per-CPU registers */
1337	for_each_possible_cpu(i) {
1338		unsigned int cpu = get_hard_smp_processor_id(i);
1339
1340		mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1341			 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1342			 0x1000);
1343	}
1344
1345	/*
1346	 * Read feature register.  For non-ISU MPICs, num sources as well. On
1347	 * ISU MPICs, sources are counted as ISUs are added
1348	 */
1349	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1350
1351	/*
1352	 * By default, the last source number comes from the MPIC, but the
1353	 * device-tree and board support code can override it on buggy hw.
1354	 * If we get passed an isu_size (multi-isu MPIC) then we use that
1355	 * as a default instead of the value read from the HW.
1356	 */
1357	last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1358				>> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;	
1359	if (isu_size)
1360		last_irq = isu_size  * MPIC_MAX_ISU - 1;
1361	of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1362	if (irq_count)
1363		last_irq = irq_count - 1;
1364
1365	/* Initialize main ISU if none provided */
1366	if (!isu_size) {
1367		isu_size = last_irq + 1;
1368		mpic->num_sources = isu_size;
1369		mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1370				MPIC_INFO(IRQ_BASE),
1371				MPIC_INFO(IRQ_STRIDE) * isu_size);
1372	}
1373
1374	mpic->isu_size = isu_size;
1375	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1376	mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1377
1378	mpic->irqhost = irq_domain_add_linear(mpic->node,
1379				       last_irq + 1,
1380				       &mpic_host_ops, mpic);
1381
1382	/*
1383	 * FIXME: The code leaks the MPIC object and mappings here; this
1384	 * is very unlikely to fail but it ought to be fixed anyways.
1385	 */
1386	if (mpic->irqhost == NULL)
1387		return NULL;
1388
 
 
1389	/* Display version */
1390	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1391	case 1:
1392		vers = "1.0";
1393		break;
1394	case 2:
1395		vers = "1.2";
1396		break;
1397	case 3:
1398		vers = "1.3";
1399		break;
1400	default:
1401		vers = "<unknown>";
1402		break;
1403	}
1404	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1405	       " max %d CPUs\n",
1406	       name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1407	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1408	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1409
1410	mpic->next = mpics;
1411	mpics = mpic;
1412
1413	if (!(mpic->flags & MPIC_SECONDARY)) {
1414		mpic_primary = mpic;
1415		irq_set_default_host(mpic->irqhost);
1416	}
1417
1418	return mpic;
1419
1420err_of_node_put:
1421	of_node_put(node);
1422	return NULL;
1423}
1424
1425void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1426			    phys_addr_t paddr)
1427{
1428	unsigned int isu_first = isu_num * mpic->isu_size;
1429
1430	BUG_ON(isu_num >= MPIC_MAX_ISU);
1431
1432	mpic_map(mpic,
1433		 paddr, &mpic->isus[isu_num], 0,
1434		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1435
1436	if ((isu_first + mpic->isu_size) > mpic->num_sources)
1437		mpic->num_sources = isu_first + mpic->isu_size;
1438}
1439
 
 
 
 
 
 
1440void __init mpic_init(struct mpic *mpic)
1441{
1442	int i, cpu;
 
1443
1444	BUG_ON(mpic->num_sources == 0);
1445
1446	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1447
1448	/* Set current processor priority to max */
1449	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1450
1451	/* Initialize timers to our reserved vectors and mask them for now */
1452	for (i = 0; i < 4; i++) {
1453		mpic_write(mpic->tmregs,
1454			   i * MPIC_INFO(TIMER_STRIDE) +
1455			   MPIC_INFO(TIMER_DESTINATION),
1456			   1 << hard_smp_processor_id());
1457		mpic_write(mpic->tmregs,
1458			   i * MPIC_INFO(TIMER_STRIDE) +
1459			   MPIC_INFO(TIMER_VECTOR_PRI),
1460			   MPIC_VECPRI_MASK |
1461			   (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1462			   (mpic->timer_vecs[0] + i));
1463	}
1464
1465	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
1466	mpic_test_broken_ipi(mpic);
1467	for (i = 0; i < 4; i++) {
1468		mpic_ipi_write(i,
1469			       MPIC_VECPRI_MASK |
1470			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1471			       (mpic->ipi_vecs[0] + i));
1472	}
1473
 
 
 
 
1474	/* Do the HT PIC fixups on U3 broken mpic */
1475	DBG("MPIC flags: %x\n", mpic->flags);
1476	if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1477		mpic_scan_ht_pics(mpic);
1478		mpic_u3msi_init(mpic);
1479	}
1480
1481	mpic_pasemi_msi_init(mpic);
1482
1483	cpu = mpic_processor_id(mpic);
1484
1485	if (!(mpic->flags & MPIC_NO_RESET)) {
1486		for (i = 0; i < mpic->num_sources; i++) {
1487			/* start with vector = source number, and masked */
1488			u32 vecpri = MPIC_VECPRI_MASK | i |
1489				(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1490		
1491			/* check if protected */
1492			if (mpic->protected && test_bit(i, mpic->protected))
1493				continue;
1494			/* init hw */
1495			mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1496			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1497		}
1498	}
1499	
1500	/* Init spurious vector */
1501	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1502
1503	/* Disable 8259 passthrough, if supported */
1504	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1505		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1506			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1507			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1508
1509	if (mpic->flags & MPIC_NO_BIAS)
1510		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1511			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1512			| MPIC_GREG_GCONF_NO_BIAS);
1513
1514	/* Set current processor priority to 0 */
1515	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1516
1517#ifdef CONFIG_PM
1518	/* allocate memory to save mpic state */
1519	mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1520				  GFP_KERNEL);
1521	BUG_ON(mpic->save_data == NULL);
1522#endif
1523
1524	/* Check if this MPIC is chained from a parent interrupt controller */
1525	if (mpic->flags & MPIC_SECONDARY) {
1526		int virq = irq_of_parse_and_map(mpic->node, 0);
1527		if (virq != NO_IRQ) {
1528			printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1529					mpic->node->full_name, virq);
1530			irq_set_handler_data(virq, mpic);
1531			irq_set_chained_handler(virq, &mpic_cascade);
1532		}
1533	}
1534}
1535
1536void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1537{
1538	u32 v;
1539
1540	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1541	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1542	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1543	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1544}
1545
1546void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1547{
1548	unsigned long flags;
1549	u32 v;
1550
1551	raw_spin_lock_irqsave(&mpic_lock, flags);
1552	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1553	if (enable)
1554		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1555	else
1556		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1557	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1558	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1559}
1560
1561void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1562{
1563	struct mpic *mpic = mpic_find(irq);
1564	unsigned int src = virq_to_hw(irq);
1565	unsigned long flags;
1566	u32 reg;
1567
1568	if (!mpic)
1569		return;
1570
1571	raw_spin_lock_irqsave(&mpic_lock, flags);
1572	if (mpic_is_ipi(mpic, src)) {
1573		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1574			~MPIC_VECPRI_PRIORITY_MASK;
1575		mpic_ipi_write(src - mpic->ipi_vecs[0],
1576			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1577	} else if (mpic_is_tm(mpic, src)) {
1578		reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1579			~MPIC_VECPRI_PRIORITY_MASK;
1580		mpic_tm_write(src - mpic->timer_vecs[0],
1581			      reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1582	} else {
1583		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1584			& ~MPIC_VECPRI_PRIORITY_MASK;
1585		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1586			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1587	}
1588	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1589}
1590
1591void mpic_setup_this_cpu(void)
1592{
1593#ifdef CONFIG_SMP
1594	struct mpic *mpic = mpic_primary;
1595	unsigned long flags;
1596	u32 msk = 1 << hard_smp_processor_id();
1597	unsigned int i;
1598
1599	BUG_ON(mpic == NULL);
1600
1601	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1602
1603	raw_spin_lock_irqsave(&mpic_lock, flags);
1604
1605 	/* let the mpic know we want intrs. default affinity is 0xffffffff
1606	 * until changed via /proc. That's how it's done on x86. If we want
1607	 * it differently, then we should make sure we also change the default
1608	 * values of irq_desc[].affinity in irq.c.
1609 	 */
1610	if (distribute_irqs) {
1611	 	for (i = 0; i < mpic->num_sources ; i++)
1612			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1613				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1614	}
1615
1616	/* Set current processor priority to 0 */
1617	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1618
1619	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1620#endif /* CONFIG_SMP */
1621}
1622
1623int mpic_cpu_get_priority(void)
1624{
1625	struct mpic *mpic = mpic_primary;
1626
1627	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1628}
1629
1630void mpic_cpu_set_priority(int prio)
1631{
1632	struct mpic *mpic = mpic_primary;
1633
1634	prio &= MPIC_CPU_TASKPRI_MASK;
1635	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1636}
1637
1638void mpic_teardown_this_cpu(int secondary)
1639{
1640	struct mpic *mpic = mpic_primary;
1641	unsigned long flags;
1642	u32 msk = 1 << hard_smp_processor_id();
1643	unsigned int i;
1644
1645	BUG_ON(mpic == NULL);
1646
1647	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1648	raw_spin_lock_irqsave(&mpic_lock, flags);
1649
1650	/* let the mpic know we don't want intrs.  */
1651	for (i = 0; i < mpic->num_sources ; i++)
1652		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1653			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1654
1655	/* Set current processor priority to max */
1656	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1657	/* We need to EOI the IPI since not all platforms reset the MPIC
1658	 * on boot and new interrupts wouldn't get delivered otherwise.
1659	 */
1660	mpic_eoi(mpic);
1661
1662	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1663}
1664
1665
1666static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1667{
1668	u32 src;
1669
1670	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1671#ifdef DEBUG_LOW
1672	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1673#endif
1674	if (unlikely(src == mpic->spurious_vec)) {
1675		if (mpic->flags & MPIC_SPV_EOI)
1676			mpic_eoi(mpic);
1677		return NO_IRQ;
1678	}
1679	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1680		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1681				   mpic->name, (int)src);
1682		mpic_eoi(mpic);
1683		return NO_IRQ;
1684	}
1685
1686	return irq_linear_revmap(mpic->irqhost, src);
1687}
1688
1689unsigned int mpic_get_one_irq(struct mpic *mpic)
1690{
1691	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1692}
1693
1694unsigned int mpic_get_irq(void)
1695{
1696	struct mpic *mpic = mpic_primary;
1697
1698	BUG_ON(mpic == NULL);
1699
1700	return mpic_get_one_irq(mpic);
1701}
1702
1703unsigned int mpic_get_coreint_irq(void)
1704{
1705#ifdef CONFIG_BOOKE
1706	struct mpic *mpic = mpic_primary;
1707	u32 src;
1708
1709	BUG_ON(mpic == NULL);
1710
1711	src = mfspr(SPRN_EPR);
1712
1713	if (unlikely(src == mpic->spurious_vec)) {
1714		if (mpic->flags & MPIC_SPV_EOI)
1715			mpic_eoi(mpic);
1716		return NO_IRQ;
1717	}
1718	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1719		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1720				   mpic->name, (int)src);
1721		return NO_IRQ;
1722	}
1723
1724	return irq_linear_revmap(mpic->irqhost, src);
1725#else
1726	return NO_IRQ;
1727#endif
1728}
1729
1730unsigned int mpic_get_mcirq(void)
1731{
1732	struct mpic *mpic = mpic_primary;
1733
1734	BUG_ON(mpic == NULL);
1735
1736	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1737}
1738
1739#ifdef CONFIG_SMP
1740void mpic_request_ipis(void)
1741{
1742	struct mpic *mpic = mpic_primary;
1743	int i;
1744	BUG_ON(mpic == NULL);
1745
1746	printk(KERN_INFO "mpic: requesting IPIs...\n");
1747
1748	for (i = 0; i < 4; i++) {
1749		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1750						       mpic->ipi_vecs[0] + i);
1751		if (vipi == NO_IRQ) {
1752			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1753			continue;
1754		}
1755		smp_request_message_ipi(vipi, i);
1756	}
1757}
1758
1759void smp_mpic_message_pass(int cpu, int msg)
1760{
1761	struct mpic *mpic = mpic_primary;
1762	u32 physmask;
1763
1764	BUG_ON(mpic == NULL);
1765
1766	/* make sure we're sending something that translates to an IPI */
1767	if ((unsigned int)msg > 3) {
1768		printk("SMP %d: smp_message_pass: unknown msg %d\n",
1769		       smp_processor_id(), msg);
1770		return;
1771	}
1772
1773#ifdef DEBUG_IPI
1774	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1775#endif
1776
1777	physmask = 1 << get_hard_smp_processor_id(cpu);
1778
1779	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1780		       msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1781}
1782
1783int __init smp_mpic_probe(void)
1784{
1785	int nr_cpus;
1786
1787	DBG("smp_mpic_probe()...\n");
1788
1789	nr_cpus = cpumask_weight(cpu_possible_mask);
1790
1791	DBG("nr_cpus: %d\n", nr_cpus);
1792
1793	if (nr_cpus > 1)
1794		mpic_request_ipis();
1795
1796	return nr_cpus;
1797}
1798
1799void __devinit smp_mpic_setup_cpu(int cpu)
1800{
1801	mpic_setup_this_cpu();
1802}
1803
1804void mpic_reset_core(int cpu)
1805{
1806	struct mpic *mpic = mpic_primary;
1807	u32 pir;
1808	int cpuid = get_hard_smp_processor_id(cpu);
1809	int i;
1810
1811	/* Set target bit for core reset */
1812	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1813	pir |= (1 << cpuid);
1814	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1815	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1816
1817	/* Restore target bit after reset complete */
1818	pir &= ~(1 << cpuid);
1819	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1820	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1821
1822	/* Perform 15 EOI on each reset core to clear pending interrupts.
1823	 * This is required for FSL CoreNet based devices */
1824	if (mpic->flags & MPIC_FSL) {
1825		for (i = 0; i < 15; i++) {
1826			_mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1827				      MPIC_CPU_EOI, 0);
1828		}
1829	}
1830}
1831#endif /* CONFIG_SMP */
1832
1833#ifdef CONFIG_PM
1834static void mpic_suspend_one(struct mpic *mpic)
1835{
1836	int i;
1837
1838	for (i = 0; i < mpic->num_sources; i++) {
1839		mpic->save_data[i].vecprio =
1840			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1841		mpic->save_data[i].dest =
1842			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1843	}
1844}
1845
1846static int mpic_suspend(void)
1847{
1848	struct mpic *mpic = mpics;
1849
1850	while (mpic) {
1851		mpic_suspend_one(mpic);
1852		mpic = mpic->next;
1853	}
1854
1855	return 0;
1856}
1857
1858static void mpic_resume_one(struct mpic *mpic)
1859{
1860	int i;
1861
1862	for (i = 0; i < mpic->num_sources; i++) {
1863		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1864			       mpic->save_data[i].vecprio);
1865		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1866			       mpic->save_data[i].dest);
1867
1868#ifdef CONFIG_MPIC_U3_HT_IRQS
1869	if (mpic->fixups) {
1870		struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1871
1872		if (fixup->base) {
1873			/* we use the lowest bit in an inverted meaning */
1874			if ((mpic->save_data[i].fixup_data & 1) == 0)
1875				continue;
1876
1877			/* Enable and configure */
1878			writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1879
1880			writel(mpic->save_data[i].fixup_data & ~1,
1881			       fixup->base + 4);
1882		}
1883	}
1884#endif
1885	} /* end for loop */
1886}
1887
1888static void mpic_resume(void)
1889{
1890	struct mpic *mpic = mpics;
1891
1892	while (mpic) {
1893		mpic_resume_one(mpic);
1894		mpic = mpic->next;
1895	}
1896}
1897
1898static struct syscore_ops mpic_syscore_ops = {
1899	.resume = mpic_resume,
1900	.suspend = mpic_suspend,
1901};
1902
1903static int mpic_init_sys(void)
1904{
1905	register_syscore_ops(&mpic_syscore_ops);
1906	return 0;
1907}
1908
1909device_initcall(mpic_init_sys);
1910#endif