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1/*
2 * arch/arm/plat-orion/gpio.c
3 *
4 * Marvell Orion SoC GPIO handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/bitops.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20
21/*
22 * GPIO unit register offsets.
23 */
24#define GPIO_OUT_OFF 0x0000
25#define GPIO_IO_CONF_OFF 0x0004
26#define GPIO_BLINK_EN_OFF 0x0008
27#define GPIO_IN_POL_OFF 0x000c
28#define GPIO_DATA_IN_OFF 0x0010
29#define GPIO_EDGE_CAUSE_OFF 0x0014
30#define GPIO_EDGE_MASK_OFF 0x0018
31#define GPIO_LEVEL_MASK_OFF 0x001c
32
33struct orion_gpio_chip {
34 struct gpio_chip chip;
35 spinlock_t lock;
36 void __iomem *base;
37 unsigned long valid_input;
38 unsigned long valid_output;
39 int mask_offset;
40 int secondary_irq_base;
41};
42
43static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
44{
45 return ochip->base + GPIO_OUT_OFF;
46}
47
48static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
49{
50 return ochip->base + GPIO_IO_CONF_OFF;
51}
52
53static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
54{
55 return ochip->base + GPIO_BLINK_EN_OFF;
56}
57
58static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
59{
60 return ochip->base + GPIO_IN_POL_OFF;
61}
62
63static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
64{
65 return ochip->base + GPIO_DATA_IN_OFF;
66}
67
68static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
69{
70 return ochip->base + GPIO_EDGE_CAUSE_OFF;
71}
72
73static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
74{
75 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
76}
77
78static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
79{
80 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
81}
82
83
84static struct orion_gpio_chip orion_gpio_chips[2];
85static int orion_gpio_chip_count;
86
87static inline void
88__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
89{
90 u32 u;
91
92 u = readl(GPIO_IO_CONF(ochip));
93 if (input)
94 u |= 1 << pin;
95 else
96 u &= ~(1 << pin);
97 writel(u, GPIO_IO_CONF(ochip));
98}
99
100static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
101{
102 u32 u;
103
104 u = readl(GPIO_OUT(ochip));
105 if (high)
106 u |= 1 << pin;
107 else
108 u &= ~(1 << pin);
109 writel(u, GPIO_OUT(ochip));
110}
111
112static inline void
113__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
114{
115 u32 u;
116
117 u = readl(GPIO_BLINK_EN(ochip));
118 if (blink)
119 u |= 1 << pin;
120 else
121 u &= ~(1 << pin);
122 writel(u, GPIO_BLINK_EN(ochip));
123}
124
125static inline int
126orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
127{
128 if (pin >= ochip->chip.ngpio)
129 goto err_out;
130
131 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
132 goto err_out;
133
134 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
135 goto err_out;
136
137 return 1;
138
139err_out:
140 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
141 return false;
142}
143
144/*
145 * GENERIC_GPIO primitives.
146 */
147static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
148{
149 struct orion_gpio_chip *ochip =
150 container_of(chip, struct orion_gpio_chip, chip);
151
152 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
153 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
154 return 0;
155
156 return -EINVAL;
157}
158
159static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
160{
161 struct orion_gpio_chip *ochip =
162 container_of(chip, struct orion_gpio_chip, chip);
163 unsigned long flags;
164
165 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
166 return -EINVAL;
167
168 spin_lock_irqsave(&ochip->lock, flags);
169 __set_direction(ochip, pin, 1);
170 spin_unlock_irqrestore(&ochip->lock, flags);
171
172 return 0;
173}
174
175static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
176{
177 struct orion_gpio_chip *ochip =
178 container_of(chip, struct orion_gpio_chip, chip);
179 int val;
180
181 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
182 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
183 } else {
184 val = readl(GPIO_OUT(ochip));
185 }
186
187 return (val >> pin) & 1;
188}
189
190static int
191orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
192{
193 struct orion_gpio_chip *ochip =
194 container_of(chip, struct orion_gpio_chip, chip);
195 unsigned long flags;
196
197 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
198 return -EINVAL;
199
200 spin_lock_irqsave(&ochip->lock, flags);
201 __set_blinking(ochip, pin, 0);
202 __set_level(ochip, pin, value);
203 __set_direction(ochip, pin, 0);
204 spin_unlock_irqrestore(&ochip->lock, flags);
205
206 return 0;
207}
208
209static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
210{
211 struct orion_gpio_chip *ochip =
212 container_of(chip, struct orion_gpio_chip, chip);
213 unsigned long flags;
214
215 spin_lock_irqsave(&ochip->lock, flags);
216 __set_level(ochip, pin, value);
217 spin_unlock_irqrestore(&ochip->lock, flags);
218}
219
220static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
221{
222 struct orion_gpio_chip *ochip =
223 container_of(chip, struct orion_gpio_chip, chip);
224
225 return ochip->secondary_irq_base + pin;
226}
227
228
229/*
230 * Orion-specific GPIO API extensions.
231 */
232static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
233{
234 int i;
235
236 for (i = 0; i < orion_gpio_chip_count; i++) {
237 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
238 struct gpio_chip *chip = &ochip->chip;
239
240 if (pin >= chip->base && pin < chip->base + chip->ngpio)
241 return ochip;
242 }
243
244 return NULL;
245}
246
247void __init orion_gpio_set_unused(unsigned pin)
248{
249 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
250
251 if (ochip == NULL)
252 return;
253
254 pin -= ochip->chip.base;
255
256 /* Configure as output, drive low. */
257 __set_level(ochip, pin, 0);
258 __set_direction(ochip, pin, 0);
259}
260
261void __init orion_gpio_set_valid(unsigned pin, int mode)
262{
263 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
264
265 if (ochip == NULL)
266 return;
267
268 pin -= ochip->chip.base;
269
270 if (mode == 1)
271 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
272
273 if (mode & GPIO_INPUT_OK)
274 __set_bit(pin, &ochip->valid_input);
275 else
276 __clear_bit(pin, &ochip->valid_input);
277
278 if (mode & GPIO_OUTPUT_OK)
279 __set_bit(pin, &ochip->valid_output);
280 else
281 __clear_bit(pin, &ochip->valid_output);
282}
283
284void orion_gpio_set_blink(unsigned pin, int blink)
285{
286 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
287 unsigned long flags;
288
289 if (ochip == NULL)
290 return;
291
292 spin_lock_irqsave(&ochip->lock, flags);
293 __set_level(ochip, pin & 31, 0);
294 __set_blinking(ochip, pin & 31, blink);
295 spin_unlock_irqrestore(&ochip->lock, flags);
296}
297EXPORT_SYMBOL(orion_gpio_set_blink);
298
299#define ORION_BLINK_HALF_PERIOD 100 /* ms */
300
301int orion_gpio_led_blink_set(unsigned gpio, int state,
302 unsigned long *delay_on, unsigned long *delay_off)
303{
304
305 if (delay_on && delay_off && !*delay_on && !*delay_off)
306 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
307
308 switch (state) {
309 case GPIO_LED_NO_BLINK_LOW:
310 case GPIO_LED_NO_BLINK_HIGH:
311 orion_gpio_set_blink(gpio, 0);
312 gpio_set_value(gpio, state);
313 break;
314 case GPIO_LED_BLINK:
315 orion_gpio_set_blink(gpio, 1);
316 }
317 return 0;
318}
319EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
320
321
322/*****************************************************************************
323 * Orion GPIO IRQ
324 *
325 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
326 * value of the line or the opposite value.
327 *
328 * Level IRQ handlers: DATA_IN is used directly as cause register.
329 * Interrupt are masked by LEVEL_MASK registers.
330 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
331 * Interrupt are masked by EDGE_MASK registers.
332 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
333 * the polarity to catch the next line transaction.
334 * This is a race condition that might not perfectly
335 * work on some use cases.
336 *
337 * Every eight GPIO lines are grouped (OR'ed) before going up to main
338 * cause register.
339 *
340 * EDGE cause mask
341 * data-in /--------| |-----| |----\
342 * -----| |----- ---- to main cause reg
343 * X \----------------| |----/
344 * polarity LEVEL mask
345 *
346 ****************************************************************************/
347
348static int gpio_irq_set_type(struct irq_data *d, u32 type)
349{
350 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
351 struct irq_chip_type *ct = irq_data_get_chip_type(d);
352 struct orion_gpio_chip *ochip = gc->private;
353 int pin;
354 u32 u;
355
356 pin = d->irq - gc->irq_base;
357
358 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
359 if (!u) {
360 printk(KERN_ERR "orion gpio_irq_set_type failed "
361 "(irq %d, pin %d).\n", d->irq, pin);
362 return -EINVAL;
363 }
364
365 type &= IRQ_TYPE_SENSE_MASK;
366 if (type == IRQ_TYPE_NONE)
367 return -EINVAL;
368
369 /* Check if we need to change chip and handler */
370 if (!(ct->type & type))
371 if (irq_setup_alt_chip(d, type))
372 return -EINVAL;
373
374 /*
375 * Configure interrupt polarity.
376 */
377 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
378 u = readl(GPIO_IN_POL(ochip));
379 u &= ~(1 << pin);
380 writel(u, GPIO_IN_POL(ochip));
381 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
382 u = readl(GPIO_IN_POL(ochip));
383 u |= 1 << pin;
384 writel(u, GPIO_IN_POL(ochip));
385 } else if (type == IRQ_TYPE_EDGE_BOTH) {
386 u32 v;
387
388 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
389
390 /*
391 * set initial polarity based on current input level
392 */
393 u = readl(GPIO_IN_POL(ochip));
394 if (v & (1 << pin))
395 u |= 1 << pin; /* falling */
396 else
397 u &= ~(1 << pin); /* rising */
398 writel(u, GPIO_IN_POL(ochip));
399 }
400
401 return 0;
402}
403
404void __init orion_gpio_init(int gpio_base, int ngpio,
405 u32 base, int mask_offset, int secondary_irq_base)
406{
407 struct orion_gpio_chip *ochip;
408 struct irq_chip_generic *gc;
409 struct irq_chip_type *ct;
410 char gc_label[16];
411
412 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
413 return;
414
415 snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
416 orion_gpio_chip_count);
417
418 ochip = orion_gpio_chips + orion_gpio_chip_count;
419 ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
420 ochip->chip.request = orion_gpio_request;
421 ochip->chip.direction_input = orion_gpio_direction_input;
422 ochip->chip.get = orion_gpio_get;
423 ochip->chip.direction_output = orion_gpio_direction_output;
424 ochip->chip.set = orion_gpio_set;
425 ochip->chip.to_irq = orion_gpio_to_irq;
426 ochip->chip.base = gpio_base;
427 ochip->chip.ngpio = ngpio;
428 ochip->chip.can_sleep = 0;
429 spin_lock_init(&ochip->lock);
430 ochip->base = (void __iomem *)base;
431 ochip->valid_input = 0;
432 ochip->valid_output = 0;
433 ochip->mask_offset = mask_offset;
434 ochip->secondary_irq_base = secondary_irq_base;
435
436 gpiochip_add(&ochip->chip);
437
438 orion_gpio_chip_count++;
439
440 /*
441 * Mask and clear GPIO interrupts.
442 */
443 writel(0, GPIO_EDGE_CAUSE(ochip));
444 writel(0, GPIO_EDGE_MASK(ochip));
445 writel(0, GPIO_LEVEL_MASK(ochip));
446
447 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
448 ochip->base, handle_level_irq);
449 gc->private = ochip;
450
451 ct = gc->chip_types;
452 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
453 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
454 ct->chip.irq_mask = irq_gc_mask_clr_bit;
455 ct->chip.irq_unmask = irq_gc_mask_set_bit;
456 ct->chip.irq_set_type = gpio_irq_set_type;
457
458 ct++;
459 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
460 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
461 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
462 ct->chip.irq_ack = irq_gc_ack_clr_bit;
463 ct->chip.irq_mask = irq_gc_mask_clr_bit;
464 ct->chip.irq_unmask = irq_gc_mask_set_bit;
465 ct->chip.irq_set_type = gpio_irq_set_type;
466 ct->handler = handle_edge_irq;
467
468 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
469 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
470}
471
472void orion_gpio_irq_handler(int pinoff)
473{
474 struct orion_gpio_chip *ochip;
475 u32 cause, type;
476 int i;
477
478 ochip = orion_gpio_chip_find(pinoff);
479 if (ochip == NULL)
480 return;
481
482 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
483 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
484
485 for (i = 0; i < ochip->chip.ngpio; i++) {
486 int irq;
487
488 irq = ochip->secondary_irq_base + i;
489
490 if (!(cause & (1 << i)))
491 continue;
492
493 type = irqd_get_trigger_type(irq_get_irq_data(irq));
494 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
495 /* Swap polarity (race with GPIO line) */
496 u32 polarity;
497
498 polarity = readl(GPIO_IN_POL(ochip));
499 polarity ^= 1 << i;
500 writel(polarity, GPIO_IN_POL(ochip));
501 }
502 generic_handle_irq(irq);
503 }
504}
1/*
2 * arch/arm/plat-orion/gpio.c
3 *
4 * Marvell Orion SoC GPIO handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/bitops.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19
20/*
21 * GPIO unit register offsets.
22 */
23#define GPIO_OUT_OFF 0x0000
24#define GPIO_IO_CONF_OFF 0x0004
25#define GPIO_BLINK_EN_OFF 0x0008
26#define GPIO_IN_POL_OFF 0x000c
27#define GPIO_DATA_IN_OFF 0x0010
28#define GPIO_EDGE_CAUSE_OFF 0x0014
29#define GPIO_EDGE_MASK_OFF 0x0018
30#define GPIO_LEVEL_MASK_OFF 0x001c
31
32struct orion_gpio_chip {
33 struct gpio_chip chip;
34 spinlock_t lock;
35 void __iomem *base;
36 unsigned long valid_input;
37 unsigned long valid_output;
38 int mask_offset;
39 int secondary_irq_base;
40};
41
42static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
43{
44 return ochip->base + GPIO_OUT_OFF;
45}
46
47static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
48{
49 return ochip->base + GPIO_IO_CONF_OFF;
50}
51
52static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
53{
54 return ochip->base + GPIO_BLINK_EN_OFF;
55}
56
57static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
58{
59 return ochip->base + GPIO_IN_POL_OFF;
60}
61
62static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
63{
64 return ochip->base + GPIO_DATA_IN_OFF;
65}
66
67static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
68{
69 return ochip->base + GPIO_EDGE_CAUSE_OFF;
70}
71
72static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
73{
74 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
75}
76
77static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
78{
79 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
80}
81
82
83static struct orion_gpio_chip orion_gpio_chips[2];
84static int orion_gpio_chip_count;
85
86static inline void
87__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
88{
89 u32 u;
90
91 u = readl(GPIO_IO_CONF(ochip));
92 if (input)
93 u |= 1 << pin;
94 else
95 u &= ~(1 << pin);
96 writel(u, GPIO_IO_CONF(ochip));
97}
98
99static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
100{
101 u32 u;
102
103 u = readl(GPIO_OUT(ochip));
104 if (high)
105 u |= 1 << pin;
106 else
107 u &= ~(1 << pin);
108 writel(u, GPIO_OUT(ochip));
109}
110
111static inline void
112__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
113{
114 u32 u;
115
116 u = readl(GPIO_BLINK_EN(ochip));
117 if (blink)
118 u |= 1 << pin;
119 else
120 u &= ~(1 << pin);
121 writel(u, GPIO_BLINK_EN(ochip));
122}
123
124static inline int
125orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
126{
127 if (pin >= ochip->chip.ngpio)
128 goto err_out;
129
130 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
131 goto err_out;
132
133 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
134 goto err_out;
135
136 return 1;
137
138err_out:
139 pr_debug("%s: invalid GPIO %d\n", __func__, pin);
140 return false;
141}
142
143/*
144 * GENERIC_GPIO primitives.
145 */
146static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
147{
148 struct orion_gpio_chip *ochip =
149 container_of(chip, struct orion_gpio_chip, chip);
150
151 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
152 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
153 return 0;
154
155 return -EINVAL;
156}
157
158static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
159{
160 struct orion_gpio_chip *ochip =
161 container_of(chip, struct orion_gpio_chip, chip);
162 unsigned long flags;
163
164 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
165 return -EINVAL;
166
167 spin_lock_irqsave(&ochip->lock, flags);
168 __set_direction(ochip, pin, 1);
169 spin_unlock_irqrestore(&ochip->lock, flags);
170
171 return 0;
172}
173
174static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
175{
176 struct orion_gpio_chip *ochip =
177 container_of(chip, struct orion_gpio_chip, chip);
178 int val;
179
180 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
181 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
182 } else {
183 val = readl(GPIO_OUT(ochip));
184 }
185
186 return (val >> pin) & 1;
187}
188
189static int
190orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
191{
192 struct orion_gpio_chip *ochip =
193 container_of(chip, struct orion_gpio_chip, chip);
194 unsigned long flags;
195
196 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
197 return -EINVAL;
198
199 spin_lock_irqsave(&ochip->lock, flags);
200 __set_blinking(ochip, pin, 0);
201 __set_level(ochip, pin, value);
202 __set_direction(ochip, pin, 0);
203 spin_unlock_irqrestore(&ochip->lock, flags);
204
205 return 0;
206}
207
208static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
209{
210 struct orion_gpio_chip *ochip =
211 container_of(chip, struct orion_gpio_chip, chip);
212 unsigned long flags;
213
214 spin_lock_irqsave(&ochip->lock, flags);
215 __set_level(ochip, pin, value);
216 spin_unlock_irqrestore(&ochip->lock, flags);
217}
218
219static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
220{
221 struct orion_gpio_chip *ochip =
222 container_of(chip, struct orion_gpio_chip, chip);
223
224 return ochip->secondary_irq_base + pin;
225}
226
227
228/*
229 * Orion-specific GPIO API extensions.
230 */
231static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
232{
233 int i;
234
235 for (i = 0; i < orion_gpio_chip_count; i++) {
236 struct orion_gpio_chip *ochip = orion_gpio_chips + i;
237 struct gpio_chip *chip = &ochip->chip;
238
239 if (pin >= chip->base && pin < chip->base + chip->ngpio)
240 return ochip;
241 }
242
243 return NULL;
244}
245
246void __init orion_gpio_set_unused(unsigned pin)
247{
248 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
249
250 if (ochip == NULL)
251 return;
252
253 pin -= ochip->chip.base;
254
255 /* Configure as output, drive low. */
256 __set_level(ochip, pin, 0);
257 __set_direction(ochip, pin, 0);
258}
259
260void __init orion_gpio_set_valid(unsigned pin, int mode)
261{
262 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
263
264 if (ochip == NULL)
265 return;
266
267 pin -= ochip->chip.base;
268
269 if (mode == 1)
270 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
271
272 if (mode & GPIO_INPUT_OK)
273 __set_bit(pin, &ochip->valid_input);
274 else
275 __clear_bit(pin, &ochip->valid_input);
276
277 if (mode & GPIO_OUTPUT_OK)
278 __set_bit(pin, &ochip->valid_output);
279 else
280 __clear_bit(pin, &ochip->valid_output);
281}
282
283void orion_gpio_set_blink(unsigned pin, int blink)
284{
285 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
286 unsigned long flags;
287
288 if (ochip == NULL)
289 return;
290
291 spin_lock_irqsave(&ochip->lock, flags);
292 __set_level(ochip, pin, 0);
293 __set_blinking(ochip, pin, blink);
294 spin_unlock_irqrestore(&ochip->lock, flags);
295}
296EXPORT_SYMBOL(orion_gpio_set_blink);
297
298
299/*****************************************************************************
300 * Orion GPIO IRQ
301 *
302 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
303 * value of the line or the opposite value.
304 *
305 * Level IRQ handlers: DATA_IN is used directly as cause register.
306 * Interrupt are masked by LEVEL_MASK registers.
307 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
308 * Interrupt are masked by EDGE_MASK registers.
309 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
310 * the polarity to catch the next line transaction.
311 * This is a race condition that might not perfectly
312 * work on some use cases.
313 *
314 * Every eight GPIO lines are grouped (OR'ed) before going up to main
315 * cause register.
316 *
317 * EDGE cause mask
318 * data-in /--------| |-----| |----\
319 * -----| |----- ---- to main cause reg
320 * X \----------------| |----/
321 * polarity LEVEL mask
322 *
323 ****************************************************************************/
324
325static int gpio_irq_set_type(struct irq_data *d, u32 type)
326{
327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct irq_chip_type *ct = irq_data_get_chip_type(d);
329 struct orion_gpio_chip *ochip = gc->private;
330 int pin;
331 u32 u;
332
333 pin = d->irq - gc->irq_base;
334
335 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
336 if (!u) {
337 printk(KERN_ERR "orion gpio_irq_set_type failed "
338 "(irq %d, pin %d).\n", d->irq, pin);
339 return -EINVAL;
340 }
341
342 type &= IRQ_TYPE_SENSE_MASK;
343 if (type == IRQ_TYPE_NONE)
344 return -EINVAL;
345
346 /* Check if we need to change chip and handler */
347 if (!(ct->type & type))
348 if (irq_setup_alt_chip(d, type))
349 return -EINVAL;
350
351 /*
352 * Configure interrupt polarity.
353 */
354 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
355 u = readl(GPIO_IN_POL(ochip));
356 u &= ~(1 << pin);
357 writel(u, GPIO_IN_POL(ochip));
358 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
359 u = readl(GPIO_IN_POL(ochip));
360 u |= 1 << pin;
361 writel(u, GPIO_IN_POL(ochip));
362 } else if (type == IRQ_TYPE_EDGE_BOTH) {
363 u32 v;
364
365 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
366
367 /*
368 * set initial polarity based on current input level
369 */
370 u = readl(GPIO_IN_POL(ochip));
371 if (v & (1 << pin))
372 u |= 1 << pin; /* falling */
373 else
374 u &= ~(1 << pin); /* rising */
375 writel(u, GPIO_IN_POL(ochip));
376 }
377
378 return 0;
379}
380
381void __init orion_gpio_init(int gpio_base, int ngpio,
382 u32 base, int mask_offset, int secondary_irq_base)
383{
384 struct orion_gpio_chip *ochip;
385 struct irq_chip_generic *gc;
386 struct irq_chip_type *ct;
387
388 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
389 return;
390
391 ochip = orion_gpio_chips + orion_gpio_chip_count;
392 ochip->chip.label = "orion_gpio";
393 ochip->chip.request = orion_gpio_request;
394 ochip->chip.direction_input = orion_gpio_direction_input;
395 ochip->chip.get = orion_gpio_get;
396 ochip->chip.direction_output = orion_gpio_direction_output;
397 ochip->chip.set = orion_gpio_set;
398 ochip->chip.to_irq = orion_gpio_to_irq;
399 ochip->chip.base = gpio_base;
400 ochip->chip.ngpio = ngpio;
401 ochip->chip.can_sleep = 0;
402 spin_lock_init(&ochip->lock);
403 ochip->base = (void __iomem *)base;
404 ochip->valid_input = 0;
405 ochip->valid_output = 0;
406 ochip->mask_offset = mask_offset;
407 ochip->secondary_irq_base = secondary_irq_base;
408
409 gpiochip_add(&ochip->chip);
410
411 orion_gpio_chip_count++;
412
413 /*
414 * Mask and clear GPIO interrupts.
415 */
416 writel(0, GPIO_EDGE_CAUSE(ochip));
417 writel(0, GPIO_EDGE_MASK(ochip));
418 writel(0, GPIO_LEVEL_MASK(ochip));
419
420 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
421 ochip->base, handle_level_irq);
422 gc->private = ochip;
423
424 ct = gc->chip_types;
425 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
426 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
427 ct->chip.irq_mask = irq_gc_mask_clr_bit;
428 ct->chip.irq_unmask = irq_gc_mask_set_bit;
429 ct->chip.irq_set_type = gpio_irq_set_type;
430
431 ct++;
432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435 ct->chip.irq_ack = irq_gc_ack_clr_bit;
436 ct->chip.irq_mask = irq_gc_mask_clr_bit;
437 ct->chip.irq_unmask = irq_gc_mask_set_bit;
438 ct->chip.irq_set_type = gpio_irq_set_type;
439 ct->handler = handle_edge_irq;
440
441 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
442 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
443}
444
445void orion_gpio_irq_handler(int pinoff)
446{
447 struct orion_gpio_chip *ochip;
448 u32 cause, type;
449 int i;
450
451 ochip = orion_gpio_chip_find(pinoff);
452 if (ochip == NULL)
453 return;
454
455 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
456 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
457
458 for (i = 0; i < ochip->chip.ngpio; i++) {
459 int irq;
460
461 irq = ochip->secondary_irq_base + i;
462
463 if (!(cause & (1 << i)))
464 continue;
465
466 type = irqd_get_trigger_type(irq_get_irq_data(irq));
467 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
468 /* Swap polarity (race with GPIO line) */
469 u32 polarity;
470
471 polarity = readl(GPIO_IN_POL(ochip));
472 polarity ^= 1 << i;
473 writel(polarity, GPIO_IN_POL(ochip));
474 }
475 generic_handle_irq(irq);
476 }
477}