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1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/irqs.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38
39static struct map_desc sh7367_io_desc[] __initdata = {
40 /* create a 1:1 entity map for 0xe6xxxxxx
41 * used by CPGA, INTC and PFC.
42 */
43 {
44 .virtual = 0xe6000000,
45 .pfn = __phys_to_pfn(0xe6000000),
46 .length = 256 << 20,
47 .type = MT_DEVICE_NONSHARED
48 },
49};
50
51void __init sh7367_map_io(void)
52{
53 iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
54}
55
56/* SCIFA0 */
57static struct plat_sci_port scif0_platform_data = {
58 .mapbase = 0xe6c40000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
62 .type = PORT_SCIFA,
63 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
64 evt2irq(0xc00), evt2irq(0xc00) },
65};
66
67static struct platform_device scif0_device = {
68 .name = "sh-sci",
69 .id = 0,
70 .dev = {
71 .platform_data = &scif0_platform_data,
72 },
73};
74
75/* SCIFA1 */
76static struct plat_sci_port scif1_platform_data = {
77 .mapbase = 0xe6c50000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
81 .type = PORT_SCIFA,
82 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
83 evt2irq(0xc20), evt2irq(0xc20) },
84};
85
86static struct platform_device scif1_device = {
87 .name = "sh-sci",
88 .id = 1,
89 .dev = {
90 .platform_data = &scif1_platform_data,
91 },
92};
93
94/* SCIFA2 */
95static struct plat_sci_port scif2_platform_data = {
96 .mapbase = 0xe6c60000,
97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
100 .type = PORT_SCIFA,
101 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
102 evt2irq(0xc40), evt2irq(0xc40) },
103};
104
105static struct platform_device scif2_device = {
106 .name = "sh-sci",
107 .id = 2,
108 .dev = {
109 .platform_data = &scif2_platform_data,
110 },
111};
112
113/* SCIFA3 */
114static struct plat_sci_port scif3_platform_data = {
115 .mapbase = 0xe6c70000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA,
120 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
121 evt2irq(0xc60), evt2irq(0xc60) },
122};
123
124static struct platform_device scif3_device = {
125 .name = "sh-sci",
126 .id = 3,
127 .dev = {
128 .platform_data = &scif3_platform_data,
129 },
130};
131
132/* SCIFA4 */
133static struct plat_sci_port scif4_platform_data = {
134 .mapbase = 0xe6c80000,
135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
138 .type = PORT_SCIFA,
139 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
140 evt2irq(0xd20), evt2irq(0xd20) },
141};
142
143static struct platform_device scif4_device = {
144 .name = "sh-sci",
145 .id = 4,
146 .dev = {
147 .platform_data = &scif4_platform_data,
148 },
149};
150
151/* SCIFA5 */
152static struct plat_sci_port scif5_platform_data = {
153 .mapbase = 0xe6cb0000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA,
158 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
159 evt2irq(0xd40), evt2irq(0xd40) },
160};
161
162static struct platform_device scif5_device = {
163 .name = "sh-sci",
164 .id = 5,
165 .dev = {
166 .platform_data = &scif5_platform_data,
167 },
168};
169
170/* SCIFB */
171static struct plat_sci_port scif6_platform_data = {
172 .mapbase = 0xe6c30000,
173 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE,
175 .scbrr_algo_id = SCBRR_ALGO_4,
176 .type = PORT_SCIFB,
177 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
178 evt2irq(0xd60), evt2irq(0xd60) },
179};
180
181static struct platform_device scif6_device = {
182 .name = "sh-sci",
183 .id = 6,
184 .dev = {
185 .platform_data = &scif6_platform_data,
186 },
187};
188
189static struct sh_timer_config cmt10_platform_data = {
190 .name = "CMT10",
191 .channel_offset = 0x10,
192 .timer_bit = 0,
193 .clockevent_rating = 125,
194 .clocksource_rating = 125,
195};
196
197static struct resource cmt10_resources[] = {
198 [0] = {
199 .name = "CMT10",
200 .start = 0xe6138010,
201 .end = 0xe613801b,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = evt2irq(0xb00), /* CMT1_CMT10 */
206 .flags = IORESOURCE_IRQ,
207 },
208};
209
210static struct platform_device cmt10_device = {
211 .name = "sh_cmt",
212 .id = 10,
213 .dev = {
214 .platform_data = &cmt10_platform_data,
215 },
216 .resource = cmt10_resources,
217 .num_resources = ARRAY_SIZE(cmt10_resources),
218};
219
220/* VPU */
221static struct uio_info vpu_platform_data = {
222 .name = "VPU5",
223 .version = "0",
224 .irq = intcs_evt2irq(0x980),
225};
226
227static struct resource vpu_resources[] = {
228 [0] = {
229 .name = "VPU",
230 .start = 0xfe900000,
231 .end = 0xfe902807,
232 .flags = IORESOURCE_MEM,
233 },
234};
235
236static struct platform_device vpu_device = {
237 .name = "uio_pdrv_genirq",
238 .id = 0,
239 .dev = {
240 .platform_data = &vpu_platform_data,
241 },
242 .resource = vpu_resources,
243 .num_resources = ARRAY_SIZE(vpu_resources),
244};
245
246/* VEU0 */
247static struct uio_info veu0_platform_data = {
248 .name = "VEU0",
249 .version = "0",
250 .irq = intcs_evt2irq(0x700),
251};
252
253static struct resource veu0_resources[] = {
254 [0] = {
255 .name = "VEU0",
256 .start = 0xfe920000,
257 .end = 0xfe9200b7,
258 .flags = IORESOURCE_MEM,
259 },
260};
261
262static struct platform_device veu0_device = {
263 .name = "uio_pdrv_genirq",
264 .id = 1,
265 .dev = {
266 .platform_data = &veu0_platform_data,
267 },
268 .resource = veu0_resources,
269 .num_resources = ARRAY_SIZE(veu0_resources),
270};
271
272/* VEU1 */
273static struct uio_info veu1_platform_data = {
274 .name = "VEU1",
275 .version = "0",
276 .irq = intcs_evt2irq(0x720),
277};
278
279static struct resource veu1_resources[] = {
280 [0] = {
281 .name = "VEU1",
282 .start = 0xfe924000,
283 .end = 0xfe9240b7,
284 .flags = IORESOURCE_MEM,
285 },
286};
287
288static struct platform_device veu1_device = {
289 .name = "uio_pdrv_genirq",
290 .id = 2,
291 .dev = {
292 .platform_data = &veu1_platform_data,
293 },
294 .resource = veu1_resources,
295 .num_resources = ARRAY_SIZE(veu1_resources),
296};
297
298/* VEU2 */
299static struct uio_info veu2_platform_data = {
300 .name = "VEU2",
301 .version = "0",
302 .irq = intcs_evt2irq(0x740),
303};
304
305static struct resource veu2_resources[] = {
306 [0] = {
307 .name = "VEU2",
308 .start = 0xfe928000,
309 .end = 0xfe9280b7,
310 .flags = IORESOURCE_MEM,
311 },
312};
313
314static struct platform_device veu2_device = {
315 .name = "uio_pdrv_genirq",
316 .id = 3,
317 .dev = {
318 .platform_data = &veu2_platform_data,
319 },
320 .resource = veu2_resources,
321 .num_resources = ARRAY_SIZE(veu2_resources),
322};
323
324/* VEU3 */
325static struct uio_info veu3_platform_data = {
326 .name = "VEU3",
327 .version = "0",
328 .irq = intcs_evt2irq(0x760),
329};
330
331static struct resource veu3_resources[] = {
332 [0] = {
333 .name = "VEU3",
334 .start = 0xfe92c000,
335 .end = 0xfe92c0b7,
336 .flags = IORESOURCE_MEM,
337 },
338};
339
340static struct platform_device veu3_device = {
341 .name = "uio_pdrv_genirq",
342 .id = 4,
343 .dev = {
344 .platform_data = &veu3_platform_data,
345 },
346 .resource = veu3_resources,
347 .num_resources = ARRAY_SIZE(veu3_resources),
348};
349
350/* VEU2H */
351static struct uio_info veu2h_platform_data = {
352 .name = "VEU2H",
353 .version = "0",
354 .irq = intcs_evt2irq(0x520),
355};
356
357static struct resource veu2h_resources[] = {
358 [0] = {
359 .name = "VEU2H",
360 .start = 0xfe93c000,
361 .end = 0xfe93c27b,
362 .flags = IORESOURCE_MEM,
363 },
364};
365
366static struct platform_device veu2h_device = {
367 .name = "uio_pdrv_genirq",
368 .id = 5,
369 .dev = {
370 .platform_data = &veu2h_platform_data,
371 },
372 .resource = veu2h_resources,
373 .num_resources = ARRAY_SIZE(veu2h_resources),
374};
375
376/* JPU */
377static struct uio_info jpu_platform_data = {
378 .name = "JPU",
379 .version = "0",
380 .irq = intcs_evt2irq(0x560),
381};
382
383static struct resource jpu_resources[] = {
384 [0] = {
385 .name = "JPU",
386 .start = 0xfe980000,
387 .end = 0xfe9902d3,
388 .flags = IORESOURCE_MEM,
389 },
390};
391
392static struct platform_device jpu_device = {
393 .name = "uio_pdrv_genirq",
394 .id = 6,
395 .dev = {
396 .platform_data = &jpu_platform_data,
397 },
398 .resource = jpu_resources,
399 .num_resources = ARRAY_SIZE(jpu_resources),
400};
401
402/* SPU1 */
403static struct uio_info spu1_platform_data = {
404 .name = "SPU1",
405 .version = "0",
406 .irq = evt2irq(0xfc0),
407};
408
409static struct resource spu1_resources[] = {
410 [0] = {
411 .name = "SPU1",
412 .start = 0xfe300000,
413 .end = 0xfe3fffff,
414 .flags = IORESOURCE_MEM,
415 },
416};
417
418static struct platform_device spu1_device = {
419 .name = "uio_pdrv_genirq",
420 .id = 7,
421 .dev = {
422 .platform_data = &spu1_platform_data,
423 },
424 .resource = spu1_resources,
425 .num_resources = ARRAY_SIZE(spu1_resources),
426};
427
428static struct platform_device *sh7367_early_devices[] __initdata = {
429 &scif0_device,
430 &scif1_device,
431 &scif2_device,
432 &scif3_device,
433 &scif4_device,
434 &scif5_device,
435 &scif6_device,
436 &cmt10_device,
437};
438
439static struct platform_device *sh7367_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &veu2h_device,
446 &jpu_device,
447 &spu1_device,
448};
449
450void __init sh7367_add_standard_devices(void)
451{
452 platform_add_devices(sh7367_early_devices,
453 ARRAY_SIZE(sh7367_early_devices));
454
455 platform_add_devices(sh7367_devices,
456 ARRAY_SIZE(sh7367_devices));
457}
458
459static void __init sh7367_earlytimer_init(void)
460{
461 sh7367_clock_init();
462 shmobile_earlytimer_init();
463}
464
465#define SYMSTPCR2 0xe6158048
466#define SYMSTPCR2_CMT1 (1 << 29)
467
468void __init sh7367_add_early_devices(void)
469{
470 /* enable clock to CMT1 */
471 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
472
473 early_platform_add_devices(sh7367_early_devices,
474 ARRAY_SIZE(sh7367_early_devices));
475
476 /* setup early console here as well */
477 shmobile_setup_console();
478
479 /* override timer setup with soc-specific code */
480 shmobile_timer.init = sh7367_earlytimer_init;
481}
1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34
35/* SCIFA0 */
36static struct plat_sci_port scif0_platform_data = {
37 .mapbase = 0xe6c40000,
38 .flags = UPF_BOOT_AUTOCONF,
39 .scscr = SCSCR_RE | SCSCR_TE,
40 .scbrr_algo_id = SCBRR_ALGO_4,
41 .type = PORT_SCIFA,
42 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
43 evt2irq(0xc00), evt2irq(0xc00) },
44};
45
46static struct platform_device scif0_device = {
47 .name = "sh-sci",
48 .id = 0,
49 .dev = {
50 .platform_data = &scif0_platform_data,
51 },
52};
53
54/* SCIFA1 */
55static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF,
58 .scscr = SCSCR_RE | SCSCR_TE,
59 .scbrr_algo_id = SCBRR_ALGO_4,
60 .type = PORT_SCIFA,
61 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
62 evt2irq(0xc20), evt2irq(0xc20) },
63};
64
65static struct platform_device scif1_device = {
66 .name = "sh-sci",
67 .id = 1,
68 .dev = {
69 .platform_data = &scif1_platform_data,
70 },
71};
72
73/* SCIFA2 */
74static struct plat_sci_port scif2_platform_data = {
75 .mapbase = 0xe6c60000,
76 .flags = UPF_BOOT_AUTOCONF,
77 .scscr = SCSCR_RE | SCSCR_TE,
78 .scbrr_algo_id = SCBRR_ALGO_4,
79 .type = PORT_SCIFA,
80 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
81 evt2irq(0xc40), evt2irq(0xc40) },
82};
83
84static struct platform_device scif2_device = {
85 .name = "sh-sci",
86 .id = 2,
87 .dev = {
88 .platform_data = &scif2_platform_data,
89 },
90};
91
92/* SCIFA3 */
93static struct plat_sci_port scif3_platform_data = {
94 .mapbase = 0xe6c70000,
95 .flags = UPF_BOOT_AUTOCONF,
96 .scscr = SCSCR_RE | SCSCR_TE,
97 .scbrr_algo_id = SCBRR_ALGO_4,
98 .type = PORT_SCIFA,
99 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
100 evt2irq(0xc60), evt2irq(0xc60) },
101};
102
103static struct platform_device scif3_device = {
104 .name = "sh-sci",
105 .id = 3,
106 .dev = {
107 .platform_data = &scif3_platform_data,
108 },
109};
110
111/* SCIFA4 */
112static struct plat_sci_port scif4_platform_data = {
113 .mapbase = 0xe6c80000,
114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE,
116 .scbrr_algo_id = SCBRR_ALGO_4,
117 .type = PORT_SCIFA,
118 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
119 evt2irq(0xd20), evt2irq(0xd20) },
120};
121
122static struct platform_device scif4_device = {
123 .name = "sh-sci",
124 .id = 4,
125 .dev = {
126 .platform_data = &scif4_platform_data,
127 },
128};
129
130/* SCIFA5 */
131static struct plat_sci_port scif5_platform_data = {
132 .mapbase = 0xe6cb0000,
133 .flags = UPF_BOOT_AUTOCONF,
134 .scscr = SCSCR_RE | SCSCR_TE,
135 .scbrr_algo_id = SCBRR_ALGO_4,
136 .type = PORT_SCIFA,
137 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
138 evt2irq(0xd40), evt2irq(0xd40) },
139};
140
141static struct platform_device scif5_device = {
142 .name = "sh-sci",
143 .id = 5,
144 .dev = {
145 .platform_data = &scif5_platform_data,
146 },
147};
148
149/* SCIFB */
150static struct plat_sci_port scif6_platform_data = {
151 .mapbase = 0xe6c30000,
152 .flags = UPF_BOOT_AUTOCONF,
153 .scscr = SCSCR_RE | SCSCR_TE,
154 .scbrr_algo_id = SCBRR_ALGO_4,
155 .type = PORT_SCIFB,
156 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
157 evt2irq(0xd60), evt2irq(0xd60) },
158};
159
160static struct platform_device scif6_device = {
161 .name = "sh-sci",
162 .id = 6,
163 .dev = {
164 .platform_data = &scif6_platform_data,
165 },
166};
167
168static struct sh_timer_config cmt10_platform_data = {
169 .name = "CMT10",
170 .channel_offset = 0x10,
171 .timer_bit = 0,
172 .clockevent_rating = 125,
173 .clocksource_rating = 125,
174};
175
176static struct resource cmt10_resources[] = {
177 [0] = {
178 .name = "CMT10",
179 .start = 0xe6138010,
180 .end = 0xe613801b,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = evt2irq(0xb00), /* CMT1_CMT10 */
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device cmt10_device = {
190 .name = "sh_cmt",
191 .id = 10,
192 .dev = {
193 .platform_data = &cmt10_platform_data,
194 },
195 .resource = cmt10_resources,
196 .num_resources = ARRAY_SIZE(cmt10_resources),
197};
198
199/* VPU */
200static struct uio_info vpu_platform_data = {
201 .name = "VPU5",
202 .version = "0",
203 .irq = intcs_evt2irq(0x980),
204};
205
206static struct resource vpu_resources[] = {
207 [0] = {
208 .name = "VPU",
209 .start = 0xfe900000,
210 .end = 0xfe902807,
211 .flags = IORESOURCE_MEM,
212 },
213};
214
215static struct platform_device vpu_device = {
216 .name = "uio_pdrv_genirq",
217 .id = 0,
218 .dev = {
219 .platform_data = &vpu_platform_data,
220 },
221 .resource = vpu_resources,
222 .num_resources = ARRAY_SIZE(vpu_resources),
223};
224
225/* VEU0 */
226static struct uio_info veu0_platform_data = {
227 .name = "VEU0",
228 .version = "0",
229 .irq = intcs_evt2irq(0x700),
230};
231
232static struct resource veu0_resources[] = {
233 [0] = {
234 .name = "VEU0",
235 .start = 0xfe920000,
236 .end = 0xfe9200b7,
237 .flags = IORESOURCE_MEM,
238 },
239};
240
241static struct platform_device veu0_device = {
242 .name = "uio_pdrv_genirq",
243 .id = 1,
244 .dev = {
245 .platform_data = &veu0_platform_data,
246 },
247 .resource = veu0_resources,
248 .num_resources = ARRAY_SIZE(veu0_resources),
249};
250
251/* VEU1 */
252static struct uio_info veu1_platform_data = {
253 .name = "VEU1",
254 .version = "0",
255 .irq = intcs_evt2irq(0x720),
256};
257
258static struct resource veu1_resources[] = {
259 [0] = {
260 .name = "VEU1",
261 .start = 0xfe924000,
262 .end = 0xfe9240b7,
263 .flags = IORESOURCE_MEM,
264 },
265};
266
267static struct platform_device veu1_device = {
268 .name = "uio_pdrv_genirq",
269 .id = 2,
270 .dev = {
271 .platform_data = &veu1_platform_data,
272 },
273 .resource = veu1_resources,
274 .num_resources = ARRAY_SIZE(veu1_resources),
275};
276
277/* VEU2 */
278static struct uio_info veu2_platform_data = {
279 .name = "VEU2",
280 .version = "0",
281 .irq = intcs_evt2irq(0x740),
282};
283
284static struct resource veu2_resources[] = {
285 [0] = {
286 .name = "VEU2",
287 .start = 0xfe928000,
288 .end = 0xfe9280b7,
289 .flags = IORESOURCE_MEM,
290 },
291};
292
293static struct platform_device veu2_device = {
294 .name = "uio_pdrv_genirq",
295 .id = 3,
296 .dev = {
297 .platform_data = &veu2_platform_data,
298 },
299 .resource = veu2_resources,
300 .num_resources = ARRAY_SIZE(veu2_resources),
301};
302
303/* VEU3 */
304static struct uio_info veu3_platform_data = {
305 .name = "VEU3",
306 .version = "0",
307 .irq = intcs_evt2irq(0x760),
308};
309
310static struct resource veu3_resources[] = {
311 [0] = {
312 .name = "VEU3",
313 .start = 0xfe92c000,
314 .end = 0xfe92c0b7,
315 .flags = IORESOURCE_MEM,
316 },
317};
318
319static struct platform_device veu3_device = {
320 .name = "uio_pdrv_genirq",
321 .id = 4,
322 .dev = {
323 .platform_data = &veu3_platform_data,
324 },
325 .resource = veu3_resources,
326 .num_resources = ARRAY_SIZE(veu3_resources),
327};
328
329/* VEU2H */
330static struct uio_info veu2h_platform_data = {
331 .name = "VEU2H",
332 .version = "0",
333 .irq = intcs_evt2irq(0x520),
334};
335
336static struct resource veu2h_resources[] = {
337 [0] = {
338 .name = "VEU2H",
339 .start = 0xfe93c000,
340 .end = 0xfe93c27b,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device veu2h_device = {
346 .name = "uio_pdrv_genirq",
347 .id = 5,
348 .dev = {
349 .platform_data = &veu2h_platform_data,
350 },
351 .resource = veu2h_resources,
352 .num_resources = ARRAY_SIZE(veu2h_resources),
353};
354
355/* JPU */
356static struct uio_info jpu_platform_data = {
357 .name = "JPU",
358 .version = "0",
359 .irq = intcs_evt2irq(0x560),
360};
361
362static struct resource jpu_resources[] = {
363 [0] = {
364 .name = "JPU",
365 .start = 0xfe980000,
366 .end = 0xfe9902d3,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371static struct platform_device jpu_device = {
372 .name = "uio_pdrv_genirq",
373 .id = 6,
374 .dev = {
375 .platform_data = &jpu_platform_data,
376 },
377 .resource = jpu_resources,
378 .num_resources = ARRAY_SIZE(jpu_resources),
379};
380
381/* SPU1 */
382static struct uio_info spu1_platform_data = {
383 .name = "SPU1",
384 .version = "0",
385 .irq = evt2irq(0xfc0),
386};
387
388static struct resource spu1_resources[] = {
389 [0] = {
390 .name = "SPU1",
391 .start = 0xfe300000,
392 .end = 0xfe3fffff,
393 .flags = IORESOURCE_MEM,
394 },
395};
396
397static struct platform_device spu1_device = {
398 .name = "uio_pdrv_genirq",
399 .id = 7,
400 .dev = {
401 .platform_data = &spu1_platform_data,
402 },
403 .resource = spu1_resources,
404 .num_resources = ARRAY_SIZE(spu1_resources),
405};
406
407static struct platform_device *sh7367_early_devices[] __initdata = {
408 &scif0_device,
409 &scif1_device,
410 &scif2_device,
411 &scif3_device,
412 &scif4_device,
413 &scif5_device,
414 &scif6_device,
415 &cmt10_device,
416};
417
418static struct platform_device *sh7367_devices[] __initdata = {
419 &vpu_device,
420 &veu0_device,
421 &veu1_device,
422 &veu2_device,
423 &veu3_device,
424 &veu2h_device,
425 &jpu_device,
426 &spu1_device,
427};
428
429void __init sh7367_add_standard_devices(void)
430{
431 platform_add_devices(sh7367_early_devices,
432 ARRAY_SIZE(sh7367_early_devices));
433
434 platform_add_devices(sh7367_devices,
435 ARRAY_SIZE(sh7367_devices));
436}
437
438#define SYMSTPCR2 0xe6158048
439#define SYMSTPCR2_CMT1 (1 << 29)
440
441void __init sh7367_add_early_devices(void)
442{
443 /* enable clock to CMT1 */
444 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
445
446 early_platform_add_devices(sh7367_early_devices,
447 ARRAY_SIZE(sh7367_early_devices));
448}