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1/*
2 * Clock and PLL control for DaVinci devices
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/mutex.h>
20#include <linux/io.h>
21#include <linux/delay.h>
22
23#include <mach/hardware.h>
24
25#include <mach/clock.h>
26#include <mach/psc.h>
27#include <mach/cputype.h>
28#include "clock.h"
29
30static LIST_HEAD(clocks);
31static DEFINE_MUTEX(clocks_mutex);
32static DEFINE_SPINLOCK(clockfw_lock);
33
34static void __clk_enable(struct clk *clk)
35{
36 if (clk->parent)
37 __clk_enable(clk->parent);
38 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
39 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
40 true, clk->flags);
41}
42
43static void __clk_disable(struct clk *clk)
44{
45 if (WARN_ON(clk->usecount == 0))
46 return;
47 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
48 (clk->flags & CLK_PSC))
49 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
50 false, clk->flags);
51 if (clk->parent)
52 __clk_disable(clk->parent);
53}
54
55int clk_enable(struct clk *clk)
56{
57 unsigned long flags;
58
59 if (clk == NULL || IS_ERR(clk))
60 return -EINVAL;
61
62 spin_lock_irqsave(&clockfw_lock, flags);
63 __clk_enable(clk);
64 spin_unlock_irqrestore(&clockfw_lock, flags);
65
66 return 0;
67}
68EXPORT_SYMBOL(clk_enable);
69
70void clk_disable(struct clk *clk)
71{
72 unsigned long flags;
73
74 if (clk == NULL || IS_ERR(clk))
75 return;
76
77 spin_lock_irqsave(&clockfw_lock, flags);
78 __clk_disable(clk);
79 spin_unlock_irqrestore(&clockfw_lock, flags);
80}
81EXPORT_SYMBOL(clk_disable);
82
83unsigned long clk_get_rate(struct clk *clk)
84{
85 if (clk == NULL || IS_ERR(clk))
86 return -EINVAL;
87
88 return clk->rate;
89}
90EXPORT_SYMBOL(clk_get_rate);
91
92long clk_round_rate(struct clk *clk, unsigned long rate)
93{
94 if (clk == NULL || IS_ERR(clk))
95 return -EINVAL;
96
97 if (clk->round_rate)
98 return clk->round_rate(clk, rate);
99
100 return clk->rate;
101}
102EXPORT_SYMBOL(clk_round_rate);
103
104/* Propagate rate to children */
105static void propagate_rate(struct clk *root)
106{
107 struct clk *clk;
108
109 list_for_each_entry(clk, &root->children, childnode) {
110 if (clk->recalc)
111 clk->rate = clk->recalc(clk);
112 propagate_rate(clk);
113 }
114}
115
116int clk_set_rate(struct clk *clk, unsigned long rate)
117{
118 unsigned long flags;
119 int ret = -EINVAL;
120
121 if (clk == NULL || IS_ERR(clk))
122 return ret;
123
124 if (clk->set_rate)
125 ret = clk->set_rate(clk, rate);
126
127 spin_lock_irqsave(&clockfw_lock, flags);
128 if (ret == 0) {
129 if (clk->recalc)
130 clk->rate = clk->recalc(clk);
131 propagate_rate(clk);
132 }
133 spin_unlock_irqrestore(&clockfw_lock, flags);
134
135 return ret;
136}
137EXPORT_SYMBOL(clk_set_rate);
138
139int clk_set_parent(struct clk *clk, struct clk *parent)
140{
141 unsigned long flags;
142
143 if (clk == NULL || IS_ERR(clk))
144 return -EINVAL;
145
146 /* Cannot change parent on enabled clock */
147 if (WARN_ON(clk->usecount))
148 return -EINVAL;
149
150 mutex_lock(&clocks_mutex);
151 clk->parent = parent;
152 list_del_init(&clk->childnode);
153 list_add(&clk->childnode, &clk->parent->children);
154 mutex_unlock(&clocks_mutex);
155
156 spin_lock_irqsave(&clockfw_lock, flags);
157 if (clk->recalc)
158 clk->rate = clk->recalc(clk);
159 propagate_rate(clk);
160 spin_unlock_irqrestore(&clockfw_lock, flags);
161
162 return 0;
163}
164EXPORT_SYMBOL(clk_set_parent);
165
166int clk_register(struct clk *clk)
167{
168 if (clk == NULL || IS_ERR(clk))
169 return -EINVAL;
170
171 if (WARN(clk->parent && !clk->parent->rate,
172 "CLK: %s parent %s has no rate!\n",
173 clk->name, clk->parent->name))
174 return -EINVAL;
175
176 INIT_LIST_HEAD(&clk->children);
177
178 mutex_lock(&clocks_mutex);
179 list_add_tail(&clk->node, &clocks);
180 if (clk->parent)
181 list_add_tail(&clk->childnode, &clk->parent->children);
182 mutex_unlock(&clocks_mutex);
183
184 /* If rate is already set, use it */
185 if (clk->rate)
186 return 0;
187
188 /* Else, see if there is a way to calculate it */
189 if (clk->recalc)
190 clk->rate = clk->recalc(clk);
191
192 /* Otherwise, default to parent rate */
193 else if (clk->parent)
194 clk->rate = clk->parent->rate;
195
196 return 0;
197}
198EXPORT_SYMBOL(clk_register);
199
200void clk_unregister(struct clk *clk)
201{
202 if (clk == NULL || IS_ERR(clk))
203 return;
204
205 mutex_lock(&clocks_mutex);
206 list_del(&clk->node);
207 list_del(&clk->childnode);
208 mutex_unlock(&clocks_mutex);
209}
210EXPORT_SYMBOL(clk_unregister);
211
212#ifdef CONFIG_DAVINCI_RESET_CLOCKS
213/*
214 * Disable any unused clocks left on by the bootloader
215 */
216int __init davinci_clk_disable_unused(void)
217{
218 struct clk *ck;
219
220 spin_lock_irq(&clockfw_lock);
221 list_for_each_entry(ck, &clocks, node) {
222 if (ck->usecount > 0)
223 continue;
224 if (!(ck->flags & CLK_PSC))
225 continue;
226
227 /* ignore if in Disabled or SwRstDisable states */
228 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
229 continue;
230
231 pr_debug("Clocks: disable unused %s\n", ck->name);
232
233 davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
234 false, ck->flags);
235 }
236 spin_unlock_irq(&clockfw_lock);
237
238 return 0;
239}
240#endif
241
242static unsigned long clk_sysclk_recalc(struct clk *clk)
243{
244 u32 v, plldiv;
245 struct pll_data *pll;
246 unsigned long rate = clk->rate;
247
248 /* If this is the PLL base clock, no more calculations needed */
249 if (clk->pll_data)
250 return rate;
251
252 if (WARN_ON(!clk->parent))
253 return rate;
254
255 rate = clk->parent->rate;
256
257 /* Otherwise, the parent must be a PLL */
258 if (WARN_ON(!clk->parent->pll_data))
259 return rate;
260
261 pll = clk->parent->pll_data;
262
263 /* If pre-PLL, source clock is before the multiplier and divider(s) */
264 if (clk->flags & PRE_PLL)
265 rate = pll->input_rate;
266
267 if (!clk->div_reg)
268 return rate;
269
270 v = __raw_readl(pll->base + clk->div_reg);
271 if (v & PLLDIV_EN) {
272 plldiv = (v & pll->div_ratio_mask) + 1;
273 if (plldiv)
274 rate /= plldiv;
275 }
276
277 return rate;
278}
279
280int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
281{
282 unsigned v;
283 struct pll_data *pll;
284 unsigned long input;
285 unsigned ratio = 0;
286
287 /* If this is the PLL base clock, wrong function to call */
288 if (clk->pll_data)
289 return -EINVAL;
290
291 /* There must be a parent... */
292 if (WARN_ON(!clk->parent))
293 return -EINVAL;
294
295 /* ... the parent must be a PLL... */
296 if (WARN_ON(!clk->parent->pll_data))
297 return -EINVAL;
298
299 /* ... and this clock must have a divider. */
300 if (WARN_ON(!clk->div_reg))
301 return -EINVAL;
302
303 pll = clk->parent->pll_data;
304
305 input = clk->parent->rate;
306
307 /* If pre-PLL, source clock is before the multiplier and divider(s) */
308 if (clk->flags & PRE_PLL)
309 input = pll->input_rate;
310
311 if (input > rate) {
312 /*
313 * Can afford to provide an output little higher than requested
314 * only if maximum rate supported by hardware on this sysclk
315 * is known.
316 */
317 if (clk->maxrate) {
318 ratio = DIV_ROUND_CLOSEST(input, rate);
319 if (input / ratio > clk->maxrate)
320 ratio = 0;
321 }
322
323 if (ratio == 0)
324 ratio = DIV_ROUND_UP(input, rate);
325
326 ratio--;
327 }
328
329 if (ratio > pll->div_ratio_mask)
330 return -EINVAL;
331
332 do {
333 v = __raw_readl(pll->base + PLLSTAT);
334 } while (v & PLLSTAT_GOSTAT);
335
336 v = __raw_readl(pll->base + clk->div_reg);
337 v &= ~pll->div_ratio_mask;
338 v |= ratio | PLLDIV_EN;
339 __raw_writel(v, pll->base + clk->div_reg);
340
341 v = __raw_readl(pll->base + PLLCMD);
342 v |= PLLCMD_GOSET;
343 __raw_writel(v, pll->base + PLLCMD);
344
345 do {
346 v = __raw_readl(pll->base + PLLSTAT);
347 } while (v & PLLSTAT_GOSTAT);
348
349 return 0;
350}
351EXPORT_SYMBOL(davinci_set_sysclk_rate);
352
353static unsigned long clk_leafclk_recalc(struct clk *clk)
354{
355 if (WARN_ON(!clk->parent))
356 return clk->rate;
357
358 return clk->parent->rate;
359}
360
361int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
362{
363 clk->rate = rate;
364 return 0;
365}
366
367static unsigned long clk_pllclk_recalc(struct clk *clk)
368{
369 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
370 u8 bypass;
371 struct pll_data *pll = clk->pll_data;
372 unsigned long rate = clk->rate;
373
374 ctrl = __raw_readl(pll->base + PLLCTL);
375 rate = pll->input_rate = clk->parent->rate;
376
377 if (ctrl & PLLCTL_PLLEN) {
378 bypass = 0;
379 mult = __raw_readl(pll->base + PLLM);
380 if (cpu_is_davinci_dm365())
381 mult = 2 * (mult & PLLM_PLLM_MASK);
382 else
383 mult = (mult & PLLM_PLLM_MASK) + 1;
384 } else
385 bypass = 1;
386
387 if (pll->flags & PLL_HAS_PREDIV) {
388 prediv = __raw_readl(pll->base + PREDIV);
389 if (prediv & PLLDIV_EN)
390 prediv = (prediv & pll->div_ratio_mask) + 1;
391 else
392 prediv = 1;
393 }
394
395 /* pre-divider is fixed, but (some?) chips won't report that */
396 if (cpu_is_davinci_dm355() && pll->num == 1)
397 prediv = 8;
398
399 if (pll->flags & PLL_HAS_POSTDIV) {
400 postdiv = __raw_readl(pll->base + POSTDIV);
401 if (postdiv & PLLDIV_EN)
402 postdiv = (postdiv & pll->div_ratio_mask) + 1;
403 else
404 postdiv = 1;
405 }
406
407 if (!bypass) {
408 rate /= prediv;
409 rate *= mult;
410 rate /= postdiv;
411 }
412
413 pr_debug("PLL%d: input = %lu MHz [ ",
414 pll->num, clk->parent->rate / 1000000);
415 if (bypass)
416 pr_debug("bypass ");
417 if (prediv > 1)
418 pr_debug("/ %d ", prediv);
419 if (mult > 1)
420 pr_debug("* %d ", mult);
421 if (postdiv > 1)
422 pr_debug("/ %d ", postdiv);
423 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
424
425 return rate;
426}
427
428/**
429 * davinci_set_pllrate - set the output rate of a given PLL.
430 *
431 * Note: Currently tested to work with OMAP-L138 only.
432 *
433 * @pll: pll whose rate needs to be changed.
434 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
435 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
436 * @postdiv: The post divider value. Passing 0 disables the post-divider.
437 */
438int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
439 unsigned int mult, unsigned int postdiv)
440{
441 u32 ctrl;
442 unsigned int locktime;
443 unsigned long flags;
444
445 if (pll->base == NULL)
446 return -EINVAL;
447
448 /*
449 * PLL lock time required per OMAP-L138 datasheet is
450 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
451 * as 4 and OSCIN cycle as 25 MHz.
452 */
453 if (prediv) {
454 locktime = ((2000 * prediv) / 100);
455 prediv = (prediv - 1) | PLLDIV_EN;
456 } else {
457 locktime = PLL_LOCK_TIME;
458 }
459 if (postdiv)
460 postdiv = (postdiv - 1) | PLLDIV_EN;
461 if (mult)
462 mult = mult - 1;
463
464 /* Protect against simultaneous calls to PLL setting seqeunce */
465 spin_lock_irqsave(&clockfw_lock, flags);
466
467 ctrl = __raw_readl(pll->base + PLLCTL);
468
469 /* Switch the PLL to bypass mode */
470 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
471 __raw_writel(ctrl, pll->base + PLLCTL);
472
473 udelay(PLL_BYPASS_TIME);
474
475 /* Reset and enable PLL */
476 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
477 __raw_writel(ctrl, pll->base + PLLCTL);
478
479 if (pll->flags & PLL_HAS_PREDIV)
480 __raw_writel(prediv, pll->base + PREDIV);
481
482 __raw_writel(mult, pll->base + PLLM);
483
484 if (pll->flags & PLL_HAS_POSTDIV)
485 __raw_writel(postdiv, pll->base + POSTDIV);
486
487 udelay(PLL_RESET_TIME);
488
489 /* Bring PLL out of reset */
490 ctrl |= PLLCTL_PLLRST;
491 __raw_writel(ctrl, pll->base + PLLCTL);
492
493 udelay(locktime);
494
495 /* Remove PLL from bypass mode */
496 ctrl |= PLLCTL_PLLEN;
497 __raw_writel(ctrl, pll->base + PLLCTL);
498
499 spin_unlock_irqrestore(&clockfw_lock, flags);
500
501 return 0;
502}
503EXPORT_SYMBOL(davinci_set_pllrate);
504
505/**
506 * davinci_set_refclk_rate() - Set the reference clock rate
507 * @rate: The new rate.
508 *
509 * Sets the reference clock rate to a given value. This will most likely
510 * result in the entire clock tree getting updated.
511 *
512 * This is used to support boards which use a reference clock different
513 * than that used by default in <soc>.c file. The reference clock rate
514 * should be updated early in the boot process; ideally soon after the
515 * clock tree has been initialized once with the default reference clock
516 * rate (davinci_common_init()).
517 *
518 * Returns 0 on success, error otherwise.
519 */
520int davinci_set_refclk_rate(unsigned long rate)
521{
522 struct clk *refclk;
523
524 refclk = clk_get(NULL, "ref");
525 if (IS_ERR(refclk)) {
526 pr_err("%s: failed to get reference clock.\n", __func__);
527 return PTR_ERR(refclk);
528 }
529
530 clk_set_rate(refclk, rate);
531
532 clk_put(refclk);
533
534 return 0;
535}
536
537int __init davinci_clk_init(struct clk_lookup *clocks)
538 {
539 struct clk_lookup *c;
540 struct clk *clk;
541 size_t num_clocks = 0;
542
543 for (c = clocks; c->clk; c++) {
544 clk = c->clk;
545
546 if (!clk->recalc) {
547
548 /* Check if clock is a PLL */
549 if (clk->pll_data)
550 clk->recalc = clk_pllclk_recalc;
551
552 /* Else, if it is a PLL-derived clock */
553 else if (clk->flags & CLK_PLL)
554 clk->recalc = clk_sysclk_recalc;
555
556 /* Otherwise, it is a leaf clock (PSC clock) */
557 else if (clk->parent)
558 clk->recalc = clk_leafclk_recalc;
559 }
560
561 if (clk->pll_data) {
562 struct pll_data *pll = clk->pll_data;
563
564 if (!pll->div_ratio_mask)
565 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
566
567 if (pll->phys_base && !pll->base) {
568 pll->base = ioremap(pll->phys_base, SZ_4K);
569 WARN_ON(!pll->base);
570 }
571 }
572
573 if (clk->recalc)
574 clk->rate = clk->recalc(clk);
575
576 if (clk->lpsc)
577 clk->flags |= CLK_PSC;
578
579 clk_register(clk);
580 num_clocks++;
581
582 /* Turn on clocks that Linux doesn't otherwise manage */
583 if (clk->flags & ALWAYS_ENABLED)
584 clk_enable(clk);
585 }
586
587 clkdev_add_table(clocks, num_clocks);
588
589 return 0;
590}
591
592#ifdef CONFIG_DEBUG_FS
593
594#include <linux/debugfs.h>
595#include <linux/seq_file.h>
596
597#define CLKNAME_MAX 10 /* longest clock name */
598#define NEST_DELTA 2
599#define NEST_MAX 4
600
601static void
602dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
603{
604 char *state;
605 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
606 struct clk *clk;
607 unsigned i;
608
609 if (parent->flags & CLK_PLL)
610 state = "pll";
611 else if (parent->flags & CLK_PSC)
612 state = "psc";
613 else
614 state = "";
615
616 /* <nest spaces> name <pad to end> */
617 memset(buf, ' ', sizeof(buf) - 1);
618 buf[sizeof(buf) - 1] = 0;
619 i = strlen(parent->name);
620 memcpy(buf + nest, parent->name,
621 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
622
623 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
624 buf, parent->usecount, state, clk_get_rate(parent));
625 /* REVISIT show device associations too */
626
627 /* cost is now small, but not linear... */
628 list_for_each_entry(clk, &parent->children, childnode) {
629 dump_clock(s, nest + NEST_DELTA, clk);
630 }
631}
632
633static int davinci_ck_show(struct seq_file *m, void *v)
634{
635 struct clk *clk;
636
637 /*
638 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
639 */
640 mutex_lock(&clocks_mutex);
641 list_for_each_entry(clk, &clocks, node)
642 if (!clk->parent)
643 dump_clock(m, 0, clk);
644 mutex_unlock(&clocks_mutex);
645
646 return 0;
647}
648
649static int davinci_ck_open(struct inode *inode, struct file *file)
650{
651 return single_open(file, davinci_ck_show, NULL);
652}
653
654static const struct file_operations davinci_ck_operations = {
655 .open = davinci_ck_open,
656 .read = seq_read,
657 .llseek = seq_lseek,
658 .release = single_release,
659};
660
661static int __init davinci_clk_debugfs_init(void)
662{
663 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
664 &davinci_ck_operations);
665 return 0;
666
667}
668device_initcall(davinci_clk_debugfs_init);
669#endif /* CONFIG_DEBUG_FS */
1/*
2 * Clock and PLL control for DaVinci devices
3 *
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/errno.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/mutex.h>
20#include <linux/io.h>
21#include <linux/delay.h>
22
23#include <mach/hardware.h>
24
25#include <mach/clock.h>
26#include <mach/psc.h>
27#include <mach/cputype.h>
28#include "clock.h"
29
30static LIST_HEAD(clocks);
31static DEFINE_MUTEX(clocks_mutex);
32static DEFINE_SPINLOCK(clockfw_lock);
33
34static unsigned psc_domain(struct clk *clk)
35{
36 return (clk->flags & PSC_DSP)
37 ? DAVINCI_GPSC_DSPDOMAIN
38 : DAVINCI_GPSC_ARMDOMAIN;
39}
40
41static void __clk_enable(struct clk *clk)
42{
43 if (clk->parent)
44 __clk_enable(clk->parent);
45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
47 true, clk->flags);
48}
49
50static void __clk_disable(struct clk *clk)
51{
52 if (WARN_ON(clk->usecount == 0))
53 return;
54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
55 (clk->flags & CLK_PSC))
56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
57 false, clk->flags);
58 if (clk->parent)
59 __clk_disable(clk->parent);
60}
61
62int clk_enable(struct clk *clk)
63{
64 unsigned long flags;
65
66 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL;
68
69 spin_lock_irqsave(&clockfw_lock, flags);
70 __clk_enable(clk);
71 spin_unlock_irqrestore(&clockfw_lock, flags);
72
73 return 0;
74}
75EXPORT_SYMBOL(clk_enable);
76
77void clk_disable(struct clk *clk)
78{
79 unsigned long flags;
80
81 if (clk == NULL || IS_ERR(clk))
82 return;
83
84 spin_lock_irqsave(&clockfw_lock, flags);
85 __clk_disable(clk);
86 spin_unlock_irqrestore(&clockfw_lock, flags);
87}
88EXPORT_SYMBOL(clk_disable);
89
90unsigned long clk_get_rate(struct clk *clk)
91{
92 if (clk == NULL || IS_ERR(clk))
93 return -EINVAL;
94
95 return clk->rate;
96}
97EXPORT_SYMBOL(clk_get_rate);
98
99long clk_round_rate(struct clk *clk, unsigned long rate)
100{
101 if (clk == NULL || IS_ERR(clk))
102 return -EINVAL;
103
104 if (clk->round_rate)
105 return clk->round_rate(clk, rate);
106
107 return clk->rate;
108}
109EXPORT_SYMBOL(clk_round_rate);
110
111/* Propagate rate to children */
112static void propagate_rate(struct clk *root)
113{
114 struct clk *clk;
115
116 list_for_each_entry(clk, &root->children, childnode) {
117 if (clk->recalc)
118 clk->rate = clk->recalc(clk);
119 propagate_rate(clk);
120 }
121}
122
123int clk_set_rate(struct clk *clk, unsigned long rate)
124{
125 unsigned long flags;
126 int ret = -EINVAL;
127
128 if (clk == NULL || IS_ERR(clk))
129 return ret;
130
131 if (clk->set_rate)
132 ret = clk->set_rate(clk, rate);
133
134 spin_lock_irqsave(&clockfw_lock, flags);
135 if (ret == 0) {
136 if (clk->recalc)
137 clk->rate = clk->recalc(clk);
138 propagate_rate(clk);
139 }
140 spin_unlock_irqrestore(&clockfw_lock, flags);
141
142 return ret;
143}
144EXPORT_SYMBOL(clk_set_rate);
145
146int clk_set_parent(struct clk *clk, struct clk *parent)
147{
148 unsigned long flags;
149
150 if (clk == NULL || IS_ERR(clk))
151 return -EINVAL;
152
153 /* Cannot change parent on enabled clock */
154 if (WARN_ON(clk->usecount))
155 return -EINVAL;
156
157 mutex_lock(&clocks_mutex);
158 clk->parent = parent;
159 list_del_init(&clk->childnode);
160 list_add(&clk->childnode, &clk->parent->children);
161 mutex_unlock(&clocks_mutex);
162
163 spin_lock_irqsave(&clockfw_lock, flags);
164 if (clk->recalc)
165 clk->rate = clk->recalc(clk);
166 propagate_rate(clk);
167 spin_unlock_irqrestore(&clockfw_lock, flags);
168
169 return 0;
170}
171EXPORT_SYMBOL(clk_set_parent);
172
173int clk_register(struct clk *clk)
174{
175 if (clk == NULL || IS_ERR(clk))
176 return -EINVAL;
177
178 if (WARN(clk->parent && !clk->parent->rate,
179 "CLK: %s parent %s has no rate!\n",
180 clk->name, clk->parent->name))
181 return -EINVAL;
182
183 INIT_LIST_HEAD(&clk->children);
184
185 mutex_lock(&clocks_mutex);
186 list_add_tail(&clk->node, &clocks);
187 if (clk->parent)
188 list_add_tail(&clk->childnode, &clk->parent->children);
189 mutex_unlock(&clocks_mutex);
190
191 /* If rate is already set, use it */
192 if (clk->rate)
193 return 0;
194
195 /* Else, see if there is a way to calculate it */
196 if (clk->recalc)
197 clk->rate = clk->recalc(clk);
198
199 /* Otherwise, default to parent rate */
200 else if (clk->parent)
201 clk->rate = clk->parent->rate;
202
203 return 0;
204}
205EXPORT_SYMBOL(clk_register);
206
207void clk_unregister(struct clk *clk)
208{
209 if (clk == NULL || IS_ERR(clk))
210 return;
211
212 mutex_lock(&clocks_mutex);
213 list_del(&clk->node);
214 list_del(&clk->childnode);
215 mutex_unlock(&clocks_mutex);
216}
217EXPORT_SYMBOL(clk_unregister);
218
219#ifdef CONFIG_DAVINCI_RESET_CLOCKS
220/*
221 * Disable any unused clocks left on by the bootloader
222 */
223static int __init clk_disable_unused(void)
224{
225 struct clk *ck;
226
227 spin_lock_irq(&clockfw_lock);
228 list_for_each_entry(ck, &clocks, node) {
229 if (ck->usecount > 0)
230 continue;
231 if (!(ck->flags & CLK_PSC))
232 continue;
233
234 /* ignore if in Disabled or SwRstDisable states */
235 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
236 continue;
237
238 pr_debug("Clocks: disable unused %s\n", ck->name);
239
240 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
241 false, ck->flags);
242 }
243 spin_unlock_irq(&clockfw_lock);
244
245 return 0;
246}
247late_initcall(clk_disable_unused);
248#endif
249
250static unsigned long clk_sysclk_recalc(struct clk *clk)
251{
252 u32 v, plldiv;
253 struct pll_data *pll;
254 unsigned long rate = clk->rate;
255
256 /* If this is the PLL base clock, no more calculations needed */
257 if (clk->pll_data)
258 return rate;
259
260 if (WARN_ON(!clk->parent))
261 return rate;
262
263 rate = clk->parent->rate;
264
265 /* Otherwise, the parent must be a PLL */
266 if (WARN_ON(!clk->parent->pll_data))
267 return rate;
268
269 pll = clk->parent->pll_data;
270
271 /* If pre-PLL, source clock is before the multiplier and divider(s) */
272 if (clk->flags & PRE_PLL)
273 rate = pll->input_rate;
274
275 if (!clk->div_reg)
276 return rate;
277
278 v = __raw_readl(pll->base + clk->div_reg);
279 if (v & PLLDIV_EN) {
280 plldiv = (v & pll->div_ratio_mask) + 1;
281 if (plldiv)
282 rate /= plldiv;
283 }
284
285 return rate;
286}
287
288int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
289{
290 unsigned v;
291 struct pll_data *pll;
292 unsigned long input;
293 unsigned ratio = 0;
294
295 /* If this is the PLL base clock, wrong function to call */
296 if (clk->pll_data)
297 return -EINVAL;
298
299 /* There must be a parent... */
300 if (WARN_ON(!clk->parent))
301 return -EINVAL;
302
303 /* ... the parent must be a PLL... */
304 if (WARN_ON(!clk->parent->pll_data))
305 return -EINVAL;
306
307 /* ... and this clock must have a divider. */
308 if (WARN_ON(!clk->div_reg))
309 return -EINVAL;
310
311 pll = clk->parent->pll_data;
312
313 input = clk->parent->rate;
314
315 /* If pre-PLL, source clock is before the multiplier and divider(s) */
316 if (clk->flags & PRE_PLL)
317 input = pll->input_rate;
318
319 if (input > rate) {
320 /*
321 * Can afford to provide an output little higher than requested
322 * only if maximum rate supported by hardware on this sysclk
323 * is known.
324 */
325 if (clk->maxrate) {
326 ratio = DIV_ROUND_CLOSEST(input, rate);
327 if (input / ratio > clk->maxrate)
328 ratio = 0;
329 }
330
331 if (ratio == 0)
332 ratio = DIV_ROUND_UP(input, rate);
333
334 ratio--;
335 }
336
337 if (ratio > pll->div_ratio_mask)
338 return -EINVAL;
339
340 do {
341 v = __raw_readl(pll->base + PLLSTAT);
342 } while (v & PLLSTAT_GOSTAT);
343
344 v = __raw_readl(pll->base + clk->div_reg);
345 v &= ~pll->div_ratio_mask;
346 v |= ratio | PLLDIV_EN;
347 __raw_writel(v, pll->base + clk->div_reg);
348
349 v = __raw_readl(pll->base + PLLCMD);
350 v |= PLLCMD_GOSET;
351 __raw_writel(v, pll->base + PLLCMD);
352
353 do {
354 v = __raw_readl(pll->base + PLLSTAT);
355 } while (v & PLLSTAT_GOSTAT);
356
357 return 0;
358}
359EXPORT_SYMBOL(davinci_set_sysclk_rate);
360
361static unsigned long clk_leafclk_recalc(struct clk *clk)
362{
363 if (WARN_ON(!clk->parent))
364 return clk->rate;
365
366 return clk->parent->rate;
367}
368
369int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
370{
371 clk->rate = rate;
372 return 0;
373}
374
375static unsigned long clk_pllclk_recalc(struct clk *clk)
376{
377 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
378 u8 bypass;
379 struct pll_data *pll = clk->pll_data;
380 unsigned long rate = clk->rate;
381
382 ctrl = __raw_readl(pll->base + PLLCTL);
383 rate = pll->input_rate = clk->parent->rate;
384
385 if (ctrl & PLLCTL_PLLEN) {
386 bypass = 0;
387 mult = __raw_readl(pll->base + PLLM);
388 if (cpu_is_davinci_dm365())
389 mult = 2 * (mult & PLLM_PLLM_MASK);
390 else
391 mult = (mult & PLLM_PLLM_MASK) + 1;
392 } else
393 bypass = 1;
394
395 if (pll->flags & PLL_HAS_PREDIV) {
396 prediv = __raw_readl(pll->base + PREDIV);
397 if (prediv & PLLDIV_EN)
398 prediv = (prediv & pll->div_ratio_mask) + 1;
399 else
400 prediv = 1;
401 }
402
403 /* pre-divider is fixed, but (some?) chips won't report that */
404 if (cpu_is_davinci_dm355() && pll->num == 1)
405 prediv = 8;
406
407 if (pll->flags & PLL_HAS_POSTDIV) {
408 postdiv = __raw_readl(pll->base + POSTDIV);
409 if (postdiv & PLLDIV_EN)
410 postdiv = (postdiv & pll->div_ratio_mask) + 1;
411 else
412 postdiv = 1;
413 }
414
415 if (!bypass) {
416 rate /= prediv;
417 rate *= mult;
418 rate /= postdiv;
419 }
420
421 pr_debug("PLL%d: input = %lu MHz [ ",
422 pll->num, clk->parent->rate / 1000000);
423 if (bypass)
424 pr_debug("bypass ");
425 if (prediv > 1)
426 pr_debug("/ %d ", prediv);
427 if (mult > 1)
428 pr_debug("* %d ", mult);
429 if (postdiv > 1)
430 pr_debug("/ %d ", postdiv);
431 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
432
433 return rate;
434}
435
436/**
437 * davinci_set_pllrate - set the output rate of a given PLL.
438 *
439 * Note: Currently tested to work with OMAP-L138 only.
440 *
441 * @pll: pll whose rate needs to be changed.
442 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
443 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
444 * @postdiv: The post divider value. Passing 0 disables the post-divider.
445 */
446int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
447 unsigned int mult, unsigned int postdiv)
448{
449 u32 ctrl;
450 unsigned int locktime;
451 unsigned long flags;
452
453 if (pll->base == NULL)
454 return -EINVAL;
455
456 /*
457 * PLL lock time required per OMAP-L138 datasheet is
458 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
459 * as 4 and OSCIN cycle as 25 MHz.
460 */
461 if (prediv) {
462 locktime = ((2000 * prediv) / 100);
463 prediv = (prediv - 1) | PLLDIV_EN;
464 } else {
465 locktime = PLL_LOCK_TIME;
466 }
467 if (postdiv)
468 postdiv = (postdiv - 1) | PLLDIV_EN;
469 if (mult)
470 mult = mult - 1;
471
472 /* Protect against simultaneous calls to PLL setting seqeunce */
473 spin_lock_irqsave(&clockfw_lock, flags);
474
475 ctrl = __raw_readl(pll->base + PLLCTL);
476
477 /* Switch the PLL to bypass mode */
478 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
479 __raw_writel(ctrl, pll->base + PLLCTL);
480
481 udelay(PLL_BYPASS_TIME);
482
483 /* Reset and enable PLL */
484 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
485 __raw_writel(ctrl, pll->base + PLLCTL);
486
487 if (pll->flags & PLL_HAS_PREDIV)
488 __raw_writel(prediv, pll->base + PREDIV);
489
490 __raw_writel(mult, pll->base + PLLM);
491
492 if (pll->flags & PLL_HAS_POSTDIV)
493 __raw_writel(postdiv, pll->base + POSTDIV);
494
495 udelay(PLL_RESET_TIME);
496
497 /* Bring PLL out of reset */
498 ctrl |= PLLCTL_PLLRST;
499 __raw_writel(ctrl, pll->base + PLLCTL);
500
501 udelay(locktime);
502
503 /* Remove PLL from bypass mode */
504 ctrl |= PLLCTL_PLLEN;
505 __raw_writel(ctrl, pll->base + PLLCTL);
506
507 spin_unlock_irqrestore(&clockfw_lock, flags);
508
509 return 0;
510}
511EXPORT_SYMBOL(davinci_set_pllrate);
512
513/**
514 * davinci_set_refclk_rate() - Set the reference clock rate
515 * @rate: The new rate.
516 *
517 * Sets the reference clock rate to a given value. This will most likely
518 * result in the entire clock tree getting updated.
519 *
520 * This is used to support boards which use a reference clock different
521 * than that used by default in <soc>.c file. The reference clock rate
522 * should be updated early in the boot process; ideally soon after the
523 * clock tree has been initialized once with the default reference clock
524 * rate (davinci_common_init()).
525 *
526 * Returns 0 on success, error otherwise.
527 */
528int davinci_set_refclk_rate(unsigned long rate)
529{
530 struct clk *refclk;
531
532 refclk = clk_get(NULL, "ref");
533 if (IS_ERR(refclk)) {
534 pr_err("%s: failed to get reference clock.\n", __func__);
535 return PTR_ERR(refclk);
536 }
537
538 clk_set_rate(refclk, rate);
539
540 clk_put(refclk);
541
542 return 0;
543}
544
545int __init davinci_clk_init(struct clk_lookup *clocks)
546 {
547 struct clk_lookup *c;
548 struct clk *clk;
549 size_t num_clocks = 0;
550
551 for (c = clocks; c->clk; c++) {
552 clk = c->clk;
553
554 if (!clk->recalc) {
555
556 /* Check if clock is a PLL */
557 if (clk->pll_data)
558 clk->recalc = clk_pllclk_recalc;
559
560 /* Else, if it is a PLL-derived clock */
561 else if (clk->flags & CLK_PLL)
562 clk->recalc = clk_sysclk_recalc;
563
564 /* Otherwise, it is a leaf clock (PSC clock) */
565 else if (clk->parent)
566 clk->recalc = clk_leafclk_recalc;
567 }
568
569 if (clk->pll_data) {
570 struct pll_data *pll = clk->pll_data;
571
572 if (!pll->div_ratio_mask)
573 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
574
575 if (pll->phys_base && !pll->base) {
576 pll->base = ioremap(pll->phys_base, SZ_4K);
577 WARN_ON(!pll->base);
578 }
579 }
580
581 if (clk->recalc)
582 clk->rate = clk->recalc(clk);
583
584 if (clk->lpsc)
585 clk->flags |= CLK_PSC;
586
587 clk_register(clk);
588 num_clocks++;
589
590 /* Turn on clocks that Linux doesn't otherwise manage */
591 if (clk->flags & ALWAYS_ENABLED)
592 clk_enable(clk);
593 }
594
595 clkdev_add_table(clocks, num_clocks);
596
597 return 0;
598}
599
600#ifdef CONFIG_DEBUG_FS
601
602#include <linux/debugfs.h>
603#include <linux/seq_file.h>
604
605#define CLKNAME_MAX 10 /* longest clock name */
606#define NEST_DELTA 2
607#define NEST_MAX 4
608
609static void
610dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
611{
612 char *state;
613 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
614 struct clk *clk;
615 unsigned i;
616
617 if (parent->flags & CLK_PLL)
618 state = "pll";
619 else if (parent->flags & CLK_PSC)
620 state = "psc";
621 else
622 state = "";
623
624 /* <nest spaces> name <pad to end> */
625 memset(buf, ' ', sizeof(buf) - 1);
626 buf[sizeof(buf) - 1] = 0;
627 i = strlen(parent->name);
628 memcpy(buf + nest, parent->name,
629 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
630
631 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
632 buf, parent->usecount, state, clk_get_rate(parent));
633 /* REVISIT show device associations too */
634
635 /* cost is now small, but not linear... */
636 list_for_each_entry(clk, &parent->children, childnode) {
637 dump_clock(s, nest + NEST_DELTA, clk);
638 }
639}
640
641static int davinci_ck_show(struct seq_file *m, void *v)
642{
643 struct clk *clk;
644
645 /*
646 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
647 */
648 mutex_lock(&clocks_mutex);
649 list_for_each_entry(clk, &clocks, node)
650 if (!clk->parent)
651 dump_clock(m, 0, clk);
652 mutex_unlock(&clocks_mutex);
653
654 return 0;
655}
656
657static int davinci_ck_open(struct inode *inode, struct file *file)
658{
659 return single_open(file, davinci_ck_show, NULL);
660}
661
662static const struct file_operations davinci_ck_operations = {
663 .open = davinci_ck_open,
664 .read = seq_read,
665 .llseek = seq_lseek,
666 .release = single_release,
667};
668
669static int __init davinci_clk_debugfs_init(void)
670{
671 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
672 &davinci_ck_operations);
673 return 0;
674
675}
676device_initcall(davinci_clk_debugfs_init);
677#endif /* CONFIG_DEBUG_FS */