Loading...
1/*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8#include <linux/export.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/io.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/pci.h>
17
18static int debug_pci;
19
20/*
21 * We can't use pci_find_device() here since we are
22 * called from interrupt context.
23 */
24static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
25{
26 struct pci_dev *dev;
27
28 list_for_each_entry(dev, &bus->devices, bus_list) {
29 u16 status;
30
31 /*
32 * ignore host bridge - we handle
33 * that separately
34 */
35 if (dev->bus->number == 0 && dev->devfn == 0)
36 continue;
37
38 pci_read_config_word(dev, PCI_STATUS, &status);
39 if (status == 0xffff)
40 continue;
41
42 if ((status & status_mask) == 0)
43 continue;
44
45 /* clear the status errors */
46 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
47
48 if (warn)
49 printk("(%s: %04X) ", pci_name(dev), status);
50 }
51
52 list_for_each_entry(dev, &bus->devices, bus_list)
53 if (dev->subordinate)
54 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
55}
56
57void pcibios_report_status(u_int status_mask, int warn)
58{
59 struct list_head *l;
60
61 list_for_each(l, &pci_root_buses) {
62 struct pci_bus *bus = pci_bus_b(l);
63
64 pcibios_bus_report_status(bus, status_mask, warn);
65 }
66}
67
68/*
69 * We don't use this to fix the device, but initialisation of it.
70 * It's not the correct use for this, but it works.
71 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
72 * the following area:
73 * 1. park on CPU
74 * 2. ISA bridge ping-pong
75 * 3. ISA bridge master handling of target RETRY
76 *
77 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
78 * live with bug 2.
79 */
80static void __devinit pci_fixup_83c553(struct pci_dev *dev)
81{
82 /*
83 * Set memory region to start at address 0, and enable IO
84 */
85 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
86 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
87
88 dev->resource[0].end -= dev->resource[0].start;
89 dev->resource[0].start = 0;
90
91 /*
92 * All memory requests from ISA to be channelled to PCI
93 */
94 pci_write_config_byte(dev, 0x48, 0xff);
95
96 /*
97 * Enable ping-pong on bus master to ISA bridge transactions.
98 * This improves the sound DMA substantially. The fixed
99 * priority arbiter also helps (see below).
100 */
101 pci_write_config_byte(dev, 0x42, 0x01);
102
103 /*
104 * Enable PCI retry
105 */
106 pci_write_config_byte(dev, 0x40, 0x22);
107
108 /*
109 * We used to set the arbiter to "park on last master" (bit
110 * 1 set), but unfortunately the CyberPro does not park the
111 * bus. We must therefore park on CPU. Unfortunately, this
112 * may trigger yet another bug in the 553.
113 */
114 pci_write_config_byte(dev, 0x83, 0x02);
115
116 /*
117 * Make the ISA DMA request lowest priority, and disable
118 * rotating priorities completely.
119 */
120 pci_write_config_byte(dev, 0x80, 0x11);
121 pci_write_config_byte(dev, 0x81, 0x00);
122
123 /*
124 * Route INTA input to IRQ 11, and set IRQ11 to be level
125 * sensitive.
126 */
127 pci_write_config_word(dev, 0x44, 0xb000);
128 outb(0x08, 0x4d1);
129}
130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
131
132static void __devinit pci_fixup_unassign(struct pci_dev *dev)
133{
134 dev->resource[0].end -= dev->resource[0].start;
135 dev->resource[0].start = 0;
136}
137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
138
139/*
140 * Prevent the PCI layer from seeing the resources allocated to this device
141 * if it is the host bridge by marking it as such. These resources are of
142 * no consequence to the PCI layer (they are handled elsewhere).
143 */
144static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
145{
146 int i;
147
148 if (dev->devfn == 0) {
149 dev->class &= 0xff;
150 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
151 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
152 dev->resource[i].start = 0;
153 dev->resource[i].end = 0;
154 dev->resource[i].flags = 0;
155 }
156 }
157}
158DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
159
160/*
161 * PCI IDE controllers use non-standard I/O port decoding, respect it.
162 */
163static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
164{
165 struct resource *r;
166 int i;
167
168 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
169 return;
170
171 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
172 r = dev->resource + i;
173 if ((r->start & ~0x80) == 0x374) {
174 r->start |= 2;
175 r->end = r->start;
176 }
177 }
178}
179DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
180
181/*
182 * Put the DEC21142 to sleep
183 */
184static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
185{
186 pci_write_config_dword(dev, 0x40, 0x80000000);
187}
188DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
189
190/*
191 * The CY82C693 needs some rather major fixups to ensure that it does
192 * the right thing. Idea from the Alpha people, with a few additions.
193 *
194 * We ensure that the IDE base registers are set to 1f0/3f4 for the
195 * primary bus, and 170/374 for the secondary bus. Also, hide them
196 * from the PCI subsystem view as well so we won't try to perform
197 * our own auto-configuration on them.
198 *
199 * In addition, we ensure that the PCI IDE interrupts are routed to
200 * IRQ 14 and IRQ 15 respectively.
201 *
202 * The above gets us to a point where the IDE on this device is
203 * functional. However, The CY82C693U _does not work_ in bus
204 * master mode without locking the PCI bus solid.
205 */
206static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
207{
208 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
209 u32 base0, base1;
210
211 if (dev->class & 0x80) { /* primary */
212 base0 = 0x1f0;
213 base1 = 0x3f4;
214 } else { /* secondary */
215 base0 = 0x170;
216 base1 = 0x374;
217 }
218
219 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
220 base0 | PCI_BASE_ADDRESS_SPACE_IO);
221 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
222 base1 | PCI_BASE_ADDRESS_SPACE_IO);
223
224 dev->resource[0].start = 0;
225 dev->resource[0].end = 0;
226 dev->resource[0].flags = 0;
227
228 dev->resource[1].start = 0;
229 dev->resource[1].end = 0;
230 dev->resource[1].flags = 0;
231 } else if (PCI_FUNC(dev->devfn) == 0) {
232 /*
233 * Setup IDE IRQ routing.
234 */
235 pci_write_config_byte(dev, 0x4b, 14);
236 pci_write_config_byte(dev, 0x4c, 15);
237
238 /*
239 * Disable FREQACK handshake, enable USB.
240 */
241 pci_write_config_byte(dev, 0x4d, 0x41);
242
243 /*
244 * Enable PCI retry, and PCI post-write buffer.
245 */
246 pci_write_config_byte(dev, 0x44, 0x17);
247
248 /*
249 * Enable ISA master and DMA post write buffering.
250 */
251 pci_write_config_byte(dev, 0x45, 0x03);
252 }
253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
255
256static void __init pci_fixup_it8152(struct pci_dev *dev)
257{
258 int i;
259 /* fixup for ITE 8152 devices */
260 /* FIXME: add defines for class 0x68000 and 0x80103 */
261 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
262 dev->class == 0x68000 ||
263 dev->class == 0x80103) {
264 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
265 dev->resource[i].start = 0;
266 dev->resource[i].end = 0;
267 dev->resource[i].flags = 0;
268 }
269 }
270}
271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
272
273
274
275void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
276{
277 if (debug_pci)
278 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
280}
281
282/*
283 * If the bus contains any of these devices, then we must not turn on
284 * parity checking of any kind. Currently this is CyberPro 20x0 only.
285 */
286static inline int pdev_bad_for_parity(struct pci_dev *dev)
287{
288 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
289 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
290 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
291 (dev->vendor == PCI_VENDOR_ID_ITE &&
292 dev->device == PCI_DEVICE_ID_ITE_8152));
293
294}
295
296/*
297 * pcibios_fixup_bus - Called after each bus is probed,
298 * but before its children are examined.
299 */
300void pcibios_fixup_bus(struct pci_bus *bus)
301{
302 struct pci_dev *dev;
303 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
304
305 /*
306 * Walk the devices on this bus, working out what we can
307 * and can't support.
308 */
309 list_for_each_entry(dev, &bus->devices, bus_list) {
310 u16 status;
311
312 pci_read_config_word(dev, PCI_STATUS, &status);
313
314 /*
315 * If any device on this bus does not support fast back
316 * to back transfers, then the bus as a whole is not able
317 * to support them. Having fast back to back transfers
318 * on saves us one PCI cycle per transaction.
319 */
320 if (!(status & PCI_STATUS_FAST_BACK))
321 features &= ~PCI_COMMAND_FAST_BACK;
322
323 if (pdev_bad_for_parity(dev))
324 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
325
326 switch (dev->class >> 8) {
327 case PCI_CLASS_BRIDGE_PCI:
328 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
329 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
330 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
331 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
332 break;
333
334 case PCI_CLASS_BRIDGE_CARDBUS:
335 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
336 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
337 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
338 break;
339 }
340 }
341
342 /*
343 * Now walk the devices again, this time setting them up.
344 */
345 list_for_each_entry(dev, &bus->devices, bus_list) {
346 u16 cmd;
347
348 pci_read_config_word(dev, PCI_COMMAND, &cmd);
349 cmd |= features;
350 pci_write_config_word(dev, PCI_COMMAND, cmd);
351
352 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
353 L1_CACHE_BYTES >> 2);
354 }
355
356 /*
357 * Propagate the flags to the PCI bridge.
358 */
359 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
360 if (features & PCI_COMMAND_FAST_BACK)
361 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
362 if (features & PCI_COMMAND_PARITY)
363 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
364 }
365
366 /*
367 * Report what we did for this bus
368 */
369 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
370 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
371}
372#ifdef CONFIG_HOTPLUG
373EXPORT_SYMBOL(pcibios_fixup_bus);
374#endif
375
376/*
377 * Swizzle the device pin each time we cross a bridge. If a platform does
378 * not provide a swizzle function, we perform the standard PCI swizzling.
379 *
380 * The default swizzling walks up the bus tree one level at a time, applying
381 * the standard swizzle function at each step, stopping when it finds the PCI
382 * root bus. This will return the slot number of the bridge device on the
383 * root bus and the interrupt pin on that device which should correspond
384 * with the downstream device interrupt.
385 *
386 * Platforms may override this, in which case the slot and pin returned
387 * depend entirely on the platform code. However, please note that the
388 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
389 * PCI extenders, so it can not be ignored.
390 */
391static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
392{
393 struct pci_sys_data *sys = dev->sysdata;
394 int slot, oldpin = *pin;
395
396 if (sys->swizzle)
397 slot = sys->swizzle(dev, pin);
398 else
399 slot = pci_common_swizzle(dev, pin);
400
401 if (debug_pci)
402 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
403 pci_name(dev), oldpin, *pin, slot);
404
405 return slot;
406}
407
408/*
409 * Map a slot/pin to an IRQ.
410 */
411static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
412{
413 struct pci_sys_data *sys = dev->sysdata;
414 int irq = -1;
415
416 if (sys->map_irq)
417 irq = sys->map_irq(dev, slot, pin);
418
419 if (debug_pci)
420 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
421 pci_name(dev), slot, pin, irq);
422
423 return irq;
424}
425
426static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
427{
428 struct pci_sys_data *sys = NULL;
429 int ret;
430 int nr, busnr;
431
432 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
433 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
434 if (!sys)
435 panic("PCI: unable to allocate sys data!");
436
437#ifdef CONFIG_PCI_DOMAINS
438 sys->domain = hw->domain;
439#endif
440 sys->busnr = busnr;
441 sys->swizzle = hw->swizzle;
442 sys->map_irq = hw->map_irq;
443 INIT_LIST_HEAD(&sys->resources);
444
445 ret = hw->setup(nr, sys);
446
447 if (ret > 0) {
448 if (list_empty(&sys->resources)) {
449 pci_add_resource_offset(&sys->resources,
450 &ioport_resource, sys->io_offset);
451 pci_add_resource_offset(&sys->resources,
452 &iomem_resource, sys->mem_offset);
453 }
454
455 if (hw->scan)
456 sys->bus = hw->scan(nr, sys);
457 else
458 sys->bus = pci_scan_root_bus(NULL, sys->busnr,
459 hw->ops, sys, &sys->resources);
460
461 if (!sys->bus)
462 panic("PCI: unable to scan bus!");
463
464 busnr = sys->bus->subordinate + 1;
465
466 list_add(&sys->node, head);
467 } else {
468 kfree(sys);
469 if (ret < 0)
470 break;
471 }
472 }
473}
474
475void __init pci_common_init(struct hw_pci *hw)
476{
477 struct pci_sys_data *sys;
478 LIST_HEAD(head);
479
480 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
481 if (hw->preinit)
482 hw->preinit();
483 pcibios_init_hw(hw, &head);
484 if (hw->postinit)
485 hw->postinit();
486
487 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
488
489 list_for_each_entry(sys, &head, node) {
490 struct pci_bus *bus = sys->bus;
491
492 if (!pci_has_flag(PCI_PROBE_ONLY)) {
493 /*
494 * Size the bridge windows.
495 */
496 pci_bus_size_bridges(bus);
497
498 /*
499 * Assign resources.
500 */
501 pci_bus_assign_resources(bus);
502
503 /*
504 * Enable bridges
505 */
506 pci_enable_bridges(bus);
507 }
508
509 /*
510 * Tell drivers about devices found.
511 */
512 pci_bus_add_devices(bus);
513 }
514}
515
516#ifndef CONFIG_PCI_HOST_ITE8152
517void pcibios_set_master(struct pci_dev *dev)
518{
519 /* No special bus mastering setup handling */
520}
521#endif
522
523char * __init pcibios_setup(char *str)
524{
525 if (!strcmp(str, "debug")) {
526 debug_pci = 1;
527 return NULL;
528 } else if (!strcmp(str, "firmware")) {
529 pci_add_flags(PCI_PROBE_ONLY);
530 return NULL;
531 }
532 return str;
533}
534
535/*
536 * From arch/i386/kernel/pci-i386.c:
537 *
538 * We need to avoid collisions with `mirrored' VGA ports
539 * and other strange ISA hardware, so we always want the
540 * addresses to be allocated in the 0x000-0x0ff region
541 * modulo 0x400.
542 *
543 * Why? Because some silly external IO cards only decode
544 * the low 10 bits of the IO address. The 0x00-0xff region
545 * is reserved for motherboard devices that decode all 16
546 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
547 * but we want to try to avoid allocating at 0x2900-0x2bff
548 * which might be mirrored at 0x0100-0x03ff..
549 */
550resource_size_t pcibios_align_resource(void *data, const struct resource *res,
551 resource_size_t size, resource_size_t align)
552{
553 resource_size_t start = res->start;
554
555 if (res->flags & IORESOURCE_IO && start & 0x300)
556 start = (start + 0x3ff) & ~0x3ff;
557
558 start = (start + align - 1) & ~(align - 1);
559
560 return start;
561}
562
563/**
564 * pcibios_enable_device - Enable I/O and memory.
565 * @dev: PCI device to be enabled
566 */
567int pcibios_enable_device(struct pci_dev *dev, int mask)
568{
569 u16 cmd, old_cmd;
570 int idx;
571 struct resource *r;
572
573 pci_read_config_word(dev, PCI_COMMAND, &cmd);
574 old_cmd = cmd;
575 for (idx = 0; idx < 6; idx++) {
576 /* Only set up the requested stuff */
577 if (!(mask & (1 << idx)))
578 continue;
579
580 r = dev->resource + idx;
581 if (!r->start && r->end) {
582 printk(KERN_ERR "PCI: Device %s not available because"
583 " of resource collisions\n", pci_name(dev));
584 return -EINVAL;
585 }
586 if (r->flags & IORESOURCE_IO)
587 cmd |= PCI_COMMAND_IO;
588 if (r->flags & IORESOURCE_MEM)
589 cmd |= PCI_COMMAND_MEMORY;
590 }
591
592 /*
593 * Bridges (eg, cardbus bridges) need to be fully enabled
594 */
595 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
596 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
597
598 if (cmd != old_cmd) {
599 printk("PCI: enabling device %s (%04x -> %04x)\n",
600 pci_name(dev), old_cmd, cmd);
601 pci_write_config_word(dev, PCI_COMMAND, cmd);
602 }
603 return 0;
604}
605
606int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
607 enum pci_mmap_state mmap_state, int write_combine)
608{
609 struct pci_sys_data *root = dev->sysdata;
610 unsigned long phys;
611
612 if (mmap_state == pci_mmap_io) {
613 return -EINVAL;
614 } else {
615 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
616 }
617
618 /*
619 * Mark this as IO
620 */
621 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
622
623 if (remap_pfn_range(vma, vma->vm_start, phys,
624 vma->vm_end - vma->vm_start,
625 vma->vm_page_prot))
626 return -EAGAIN;
627
628 return 0;
629}
1/*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/io.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/pci.h>
17
18static int debug_pci;
19static int use_firmware;
20
21/*
22 * We can't use pci_find_device() here since we are
23 * called from interrupt context.
24 */
25static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
26{
27 struct pci_dev *dev;
28
29 list_for_each_entry(dev, &bus->devices, bus_list) {
30 u16 status;
31
32 /*
33 * ignore host bridge - we handle
34 * that separately
35 */
36 if (dev->bus->number == 0 && dev->devfn == 0)
37 continue;
38
39 pci_read_config_word(dev, PCI_STATUS, &status);
40 if (status == 0xffff)
41 continue;
42
43 if ((status & status_mask) == 0)
44 continue;
45
46 /* clear the status errors */
47 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
48
49 if (warn)
50 printk("(%s: %04X) ", pci_name(dev), status);
51 }
52
53 list_for_each_entry(dev, &bus->devices, bus_list)
54 if (dev->subordinate)
55 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
56}
57
58void pcibios_report_status(u_int status_mask, int warn)
59{
60 struct list_head *l;
61
62 list_for_each(l, &pci_root_buses) {
63 struct pci_bus *bus = pci_bus_b(l);
64
65 pcibios_bus_report_status(bus, status_mask, warn);
66 }
67}
68
69/*
70 * We don't use this to fix the device, but initialisation of it.
71 * It's not the correct use for this, but it works.
72 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
73 * the following area:
74 * 1. park on CPU
75 * 2. ISA bridge ping-pong
76 * 3. ISA bridge master handling of target RETRY
77 *
78 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
79 * live with bug 2.
80 */
81static void __devinit pci_fixup_83c553(struct pci_dev *dev)
82{
83 /*
84 * Set memory region to start at address 0, and enable IO
85 */
86 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
87 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
88
89 dev->resource[0].end -= dev->resource[0].start;
90 dev->resource[0].start = 0;
91
92 /*
93 * All memory requests from ISA to be channelled to PCI
94 */
95 pci_write_config_byte(dev, 0x48, 0xff);
96
97 /*
98 * Enable ping-pong on bus master to ISA bridge transactions.
99 * This improves the sound DMA substantially. The fixed
100 * priority arbiter also helps (see below).
101 */
102 pci_write_config_byte(dev, 0x42, 0x01);
103
104 /*
105 * Enable PCI retry
106 */
107 pci_write_config_byte(dev, 0x40, 0x22);
108
109 /*
110 * We used to set the arbiter to "park on last master" (bit
111 * 1 set), but unfortunately the CyberPro does not park the
112 * bus. We must therefore park on CPU. Unfortunately, this
113 * may trigger yet another bug in the 553.
114 */
115 pci_write_config_byte(dev, 0x83, 0x02);
116
117 /*
118 * Make the ISA DMA request lowest priority, and disable
119 * rotating priorities completely.
120 */
121 pci_write_config_byte(dev, 0x80, 0x11);
122 pci_write_config_byte(dev, 0x81, 0x00);
123
124 /*
125 * Route INTA input to IRQ 11, and set IRQ11 to be level
126 * sensitive.
127 */
128 pci_write_config_word(dev, 0x44, 0xb000);
129 outb(0x08, 0x4d1);
130}
131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
132
133static void __devinit pci_fixup_unassign(struct pci_dev *dev)
134{
135 dev->resource[0].end -= dev->resource[0].start;
136 dev->resource[0].start = 0;
137}
138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
139
140/*
141 * Prevent the PCI layer from seeing the resources allocated to this device
142 * if it is the host bridge by marking it as such. These resources are of
143 * no consequence to the PCI layer (they are handled elsewhere).
144 */
145static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
146{
147 int i;
148
149 if (dev->devfn == 0) {
150 dev->class &= 0xff;
151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
152 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
153 dev->resource[i].start = 0;
154 dev->resource[i].end = 0;
155 dev->resource[i].flags = 0;
156 }
157 }
158}
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
160
161/*
162 * PCI IDE controllers use non-standard I/O port decoding, respect it.
163 */
164static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
165{
166 struct resource *r;
167 int i;
168
169 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
170 return;
171
172 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
173 r = dev->resource + i;
174 if ((r->start & ~0x80) == 0x374) {
175 r->start |= 2;
176 r->end = r->start;
177 }
178 }
179}
180DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
181
182/*
183 * Put the DEC21142 to sleep
184 */
185static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
186{
187 pci_write_config_dword(dev, 0x40, 0x80000000);
188}
189DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
190
191/*
192 * The CY82C693 needs some rather major fixups to ensure that it does
193 * the right thing. Idea from the Alpha people, with a few additions.
194 *
195 * We ensure that the IDE base registers are set to 1f0/3f4 for the
196 * primary bus, and 170/374 for the secondary bus. Also, hide them
197 * from the PCI subsystem view as well so we won't try to perform
198 * our own auto-configuration on them.
199 *
200 * In addition, we ensure that the PCI IDE interrupts are routed to
201 * IRQ 14 and IRQ 15 respectively.
202 *
203 * The above gets us to a point where the IDE on this device is
204 * functional. However, The CY82C693U _does not work_ in bus
205 * master mode without locking the PCI bus solid.
206 */
207static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
208{
209 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
210 u32 base0, base1;
211
212 if (dev->class & 0x80) { /* primary */
213 base0 = 0x1f0;
214 base1 = 0x3f4;
215 } else { /* secondary */
216 base0 = 0x170;
217 base1 = 0x374;
218 }
219
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
221 base0 | PCI_BASE_ADDRESS_SPACE_IO);
222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
223 base1 | PCI_BASE_ADDRESS_SPACE_IO);
224
225 dev->resource[0].start = 0;
226 dev->resource[0].end = 0;
227 dev->resource[0].flags = 0;
228
229 dev->resource[1].start = 0;
230 dev->resource[1].end = 0;
231 dev->resource[1].flags = 0;
232 } else if (PCI_FUNC(dev->devfn) == 0) {
233 /*
234 * Setup IDE IRQ routing.
235 */
236 pci_write_config_byte(dev, 0x4b, 14);
237 pci_write_config_byte(dev, 0x4c, 15);
238
239 /*
240 * Disable FREQACK handshake, enable USB.
241 */
242 pci_write_config_byte(dev, 0x4d, 0x41);
243
244 /*
245 * Enable PCI retry, and PCI post-write buffer.
246 */
247 pci_write_config_byte(dev, 0x44, 0x17);
248
249 /*
250 * Enable ISA master and DMA post write buffering.
251 */
252 pci_write_config_byte(dev, 0x45, 0x03);
253 }
254}
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
256
257static void __init pci_fixup_it8152(struct pci_dev *dev)
258{
259 int i;
260 /* fixup for ITE 8152 devices */
261 /* FIXME: add defines for class 0x68000 and 0x80103 */
262 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
263 dev->class == 0x68000 ||
264 dev->class == 0x80103) {
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 dev->resource[i].start = 0;
267 dev->resource[i].end = 0;
268 dev->resource[i].flags = 0;
269 }
270 }
271}
272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
273
274
275
276void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
277{
278 if (debug_pci)
279 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
281}
282
283/*
284 * If the bus contains any of these devices, then we must not turn on
285 * parity checking of any kind. Currently this is CyberPro 20x0 only.
286 */
287static inline int pdev_bad_for_parity(struct pci_dev *dev)
288{
289 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
290 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
291 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
292 (dev->vendor == PCI_VENDOR_ID_ITE &&
293 dev->device == PCI_DEVICE_ID_ITE_8152));
294
295}
296
297/*
298 * Adjust the device resources from bus-centric to Linux-centric.
299 */
300static void __devinit
301pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
302{
303 resource_size_t offset;
304 int i;
305
306 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
307 if (dev->resource[i].start == 0)
308 continue;
309 if (dev->resource[i].flags & IORESOURCE_MEM)
310 offset = root->mem_offset;
311 else
312 offset = root->io_offset;
313
314 dev->resource[i].start += offset;
315 dev->resource[i].end += offset;
316 }
317}
318
319static void __devinit
320pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
321{
322 struct pci_dev *dev = bus->self;
323 int i;
324
325 if (!dev) {
326 /*
327 * Assign root bus resources.
328 */
329 for (i = 0; i < 3; i++)
330 bus->resource[i] = root->resource[i];
331 }
332}
333
334/*
335 * pcibios_fixup_bus - Called after each bus is probed,
336 * but before its children are examined.
337 */
338void pcibios_fixup_bus(struct pci_bus *bus)
339{
340 struct pci_sys_data *root = bus->sysdata;
341 struct pci_dev *dev;
342 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
343
344 pbus_assign_bus_resources(bus, root);
345
346 /*
347 * Walk the devices on this bus, working out what we can
348 * and can't support.
349 */
350 list_for_each_entry(dev, &bus->devices, bus_list) {
351 u16 status;
352
353 pdev_fixup_device_resources(root, dev);
354
355 pci_read_config_word(dev, PCI_STATUS, &status);
356
357 /*
358 * If any device on this bus does not support fast back
359 * to back transfers, then the bus as a whole is not able
360 * to support them. Having fast back to back transfers
361 * on saves us one PCI cycle per transaction.
362 */
363 if (!(status & PCI_STATUS_FAST_BACK))
364 features &= ~PCI_COMMAND_FAST_BACK;
365
366 if (pdev_bad_for_parity(dev))
367 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
368
369 switch (dev->class >> 8) {
370 case PCI_CLASS_BRIDGE_PCI:
371 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
372 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
373 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
374 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
375 break;
376
377 case PCI_CLASS_BRIDGE_CARDBUS:
378 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
379 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
380 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
381 break;
382 }
383 }
384
385 /*
386 * Now walk the devices again, this time setting them up.
387 */
388 list_for_each_entry(dev, &bus->devices, bus_list) {
389 u16 cmd;
390
391 pci_read_config_word(dev, PCI_COMMAND, &cmd);
392 cmd |= features;
393 pci_write_config_word(dev, PCI_COMMAND, cmd);
394
395 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
396 L1_CACHE_BYTES >> 2);
397 }
398
399 /*
400 * Propagate the flags to the PCI bridge.
401 */
402 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
403 if (features & PCI_COMMAND_FAST_BACK)
404 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
405 if (features & PCI_COMMAND_PARITY)
406 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
407 }
408
409 /*
410 * Report what we did for this bus
411 */
412 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
413 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
414}
415
416/*
417 * Convert from Linux-centric to bus-centric addresses for bridge devices.
418 */
419void
420pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
421 struct resource *res)
422{
423 struct pci_sys_data *root = dev->sysdata;
424 unsigned long offset = 0;
425
426 if (res->flags & IORESOURCE_IO)
427 offset = root->io_offset;
428 if (res->flags & IORESOURCE_MEM)
429 offset = root->mem_offset;
430
431 region->start = res->start - offset;
432 region->end = res->end - offset;
433}
434
435void __devinit
436pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
437 struct pci_bus_region *region)
438{
439 struct pci_sys_data *root = dev->sysdata;
440 unsigned long offset = 0;
441
442 if (res->flags & IORESOURCE_IO)
443 offset = root->io_offset;
444 if (res->flags & IORESOURCE_MEM)
445 offset = root->mem_offset;
446
447 res->start = region->start + offset;
448 res->end = region->end + offset;
449}
450
451#ifdef CONFIG_HOTPLUG
452EXPORT_SYMBOL(pcibios_fixup_bus);
453EXPORT_SYMBOL(pcibios_resource_to_bus);
454EXPORT_SYMBOL(pcibios_bus_to_resource);
455#endif
456
457/*
458 * Swizzle the device pin each time we cross a bridge.
459 * This might update pin and returns the slot number.
460 */
461static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
462{
463 struct pci_sys_data *sys = dev->sysdata;
464 int slot = 0, oldpin = *pin;
465
466 if (sys->swizzle)
467 slot = sys->swizzle(dev, pin);
468
469 if (debug_pci)
470 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
471 pci_name(dev), oldpin, *pin, slot);
472
473 return slot;
474}
475
476/*
477 * Map a slot/pin to an IRQ.
478 */
479static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
480{
481 struct pci_sys_data *sys = dev->sysdata;
482 int irq = -1;
483
484 if (sys->map_irq)
485 irq = sys->map_irq(dev, slot, pin);
486
487 if (debug_pci)
488 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
489 pci_name(dev), slot, pin, irq);
490
491 return irq;
492}
493
494static void __init pcibios_init_hw(struct hw_pci *hw)
495{
496 struct pci_sys_data *sys = NULL;
497 int ret;
498 int nr, busnr;
499
500 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
501 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
502 if (!sys)
503 panic("PCI: unable to allocate sys data!");
504
505#ifdef CONFIG_PCI_DOMAINS
506 sys->domain = hw->domain;
507#endif
508 sys->hw = hw;
509 sys->busnr = busnr;
510 sys->swizzle = hw->swizzle;
511 sys->map_irq = hw->map_irq;
512 sys->resource[0] = &ioport_resource;
513 sys->resource[1] = &iomem_resource;
514
515 ret = hw->setup(nr, sys);
516
517 if (ret > 0) {
518 sys->bus = hw->scan(nr, sys);
519
520 if (!sys->bus)
521 panic("PCI: unable to scan bus!");
522
523 busnr = sys->bus->subordinate + 1;
524
525 list_add(&sys->node, &hw->buses);
526 } else {
527 kfree(sys);
528 if (ret < 0)
529 break;
530 }
531 }
532}
533
534void __init pci_common_init(struct hw_pci *hw)
535{
536 struct pci_sys_data *sys;
537
538 INIT_LIST_HEAD(&hw->buses);
539
540 if (hw->preinit)
541 hw->preinit();
542 pcibios_init_hw(hw);
543 if (hw->postinit)
544 hw->postinit();
545
546 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
547
548 list_for_each_entry(sys, &hw->buses, node) {
549 struct pci_bus *bus = sys->bus;
550
551 if (!use_firmware) {
552 /*
553 * Size the bridge windows.
554 */
555 pci_bus_size_bridges(bus);
556
557 /*
558 * Assign resources.
559 */
560 pci_bus_assign_resources(bus);
561
562 /*
563 * Enable bridges
564 */
565 pci_enable_bridges(bus);
566 }
567
568 /*
569 * Tell drivers about devices found.
570 */
571 pci_bus_add_devices(bus);
572 }
573}
574
575char * __init pcibios_setup(char *str)
576{
577 if (!strcmp(str, "debug")) {
578 debug_pci = 1;
579 return NULL;
580 } else if (!strcmp(str, "firmware")) {
581 use_firmware = 1;
582 return NULL;
583 }
584 return str;
585}
586
587/*
588 * From arch/i386/kernel/pci-i386.c:
589 *
590 * We need to avoid collisions with `mirrored' VGA ports
591 * and other strange ISA hardware, so we always want the
592 * addresses to be allocated in the 0x000-0x0ff region
593 * modulo 0x400.
594 *
595 * Why? Because some silly external IO cards only decode
596 * the low 10 bits of the IO address. The 0x00-0xff region
597 * is reserved for motherboard devices that decode all 16
598 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
599 * but we want to try to avoid allocating at 0x2900-0x2bff
600 * which might be mirrored at 0x0100-0x03ff..
601 */
602resource_size_t pcibios_align_resource(void *data, const struct resource *res,
603 resource_size_t size, resource_size_t align)
604{
605 resource_size_t start = res->start;
606
607 if (res->flags & IORESOURCE_IO && start & 0x300)
608 start = (start + 0x3ff) & ~0x3ff;
609
610 start = (start + align - 1) & ~(align - 1);
611
612 return start;
613}
614
615/**
616 * pcibios_enable_device - Enable I/O and memory.
617 * @dev: PCI device to be enabled
618 */
619int pcibios_enable_device(struct pci_dev *dev, int mask)
620{
621 u16 cmd, old_cmd;
622 int idx;
623 struct resource *r;
624
625 pci_read_config_word(dev, PCI_COMMAND, &cmd);
626 old_cmd = cmd;
627 for (idx = 0; idx < 6; idx++) {
628 /* Only set up the requested stuff */
629 if (!(mask & (1 << idx)))
630 continue;
631
632 r = dev->resource + idx;
633 if (!r->start && r->end) {
634 printk(KERN_ERR "PCI: Device %s not available because"
635 " of resource collisions\n", pci_name(dev));
636 return -EINVAL;
637 }
638 if (r->flags & IORESOURCE_IO)
639 cmd |= PCI_COMMAND_IO;
640 if (r->flags & IORESOURCE_MEM)
641 cmd |= PCI_COMMAND_MEMORY;
642 }
643
644 /*
645 * Bridges (eg, cardbus bridges) need to be fully enabled
646 */
647 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
648 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
649
650 if (cmd != old_cmd) {
651 printk("PCI: enabling device %s (%04x -> %04x)\n",
652 pci_name(dev), old_cmd, cmd);
653 pci_write_config_word(dev, PCI_COMMAND, cmd);
654 }
655 return 0;
656}
657
658int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
659 enum pci_mmap_state mmap_state, int write_combine)
660{
661 struct pci_sys_data *root = dev->sysdata;
662 unsigned long phys;
663
664 if (mmap_state == pci_mmap_io) {
665 return -EINVAL;
666 } else {
667 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
668 }
669
670 /*
671 * Mark this as IO
672 */
673 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
674
675 if (remap_pfn_range(vma, vma->vm_start, phys,
676 vma->vm_end - vma->vm_start,
677 vma->vm_page_prot))
678 return -EAGAIN;
679
680 return 0;
681}