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1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
22#include <linux/clk.h>
23#include <linux/gpio.h>
24#include <linux/mmc/host.h>
25
26#include <asm/sizes.h>
27#include <asm/unaligned.h>
28#include <plat/mvsdio.h>
29
30#include "mvsdio.h"
31
32#define DRIVER_NAME "mvsdio"
33
34static int maxfreq = MVSD_CLOCKRATE_MAX;
35static int nodma;
36
37struct mvsd_host {
38 void __iomem *base;
39 struct mmc_request *mrq;
40 spinlock_t lock;
41 unsigned int xfer_mode;
42 unsigned int intr_en;
43 unsigned int ctrl;
44 unsigned int pio_size;
45 void *pio_ptr;
46 unsigned int sg_frags;
47 unsigned int ns_per_clk;
48 unsigned int clock;
49 unsigned int base_clock;
50 struct timer_list timer;
51 struct mmc_host *mmc;
52 struct device *dev;
53 struct resource *res;
54 int irq;
55 struct clk *clk;
56 int gpio_card_detect;
57 int gpio_write_protect;
58};
59
60#define mvsd_write(offs, val) writel(val, iobase + (offs))
61#define mvsd_read(offs) readl(iobase + (offs))
62
63static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
64{
65 void __iomem *iobase = host->base;
66 unsigned int tmout;
67 int tmout_index;
68
69 /*
70 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
71 * register is sometimes not set before a while when some
72 * "unusual" data block sizes are used (such as with the SWITCH
73 * command), even despite the fact that the XFER_DONE interrupt
74 * was raised. And if another data transfer starts before
75 * this bit comes to good sense (which eventually happens by
76 * itself) then the new transfer simply fails with a timeout.
77 */
78 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
79 unsigned long t = jiffies + HZ;
80 unsigned int hw_state, count = 0;
81 do {
82 if (time_after(jiffies, t)) {
83 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
84 break;
85 }
86 hw_state = mvsd_read(MVSD_HW_STATE);
87 count++;
88 } while (!(hw_state & (1 << 13)));
89 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
90 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
91 hw_state, count, jiffies - (t - HZ));
92 }
93
94 /* If timeout=0 then maximum timeout index is used. */
95 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
96 tmout += data->timeout_clks;
97 tmout_index = fls(tmout - 1) - 12;
98 if (tmout_index < 0)
99 tmout_index = 0;
100 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
101 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
102
103 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
104 (data->flags & MMC_DATA_READ) ? "read" : "write",
105 (u32)sg_virt(data->sg), data->blocks, data->blksz,
106 tmout, tmout_index);
107
108 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
109 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
110 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
111 mvsd_write(MVSD_BLK_COUNT, data->blocks);
112 mvsd_write(MVSD_BLK_SIZE, data->blksz);
113
114 if (nodma || (data->blksz | data->sg->offset) & 3) {
115 /*
116 * We cannot do DMA on a buffer which offset or size
117 * is not aligned on a 4-byte boundary.
118 */
119 host->pio_size = data->blocks * data->blksz;
120 host->pio_ptr = sg_virt(data->sg);
121 if (!nodma)
122 pr_debug("%s: fallback to PIO for data "
123 "at 0x%p size %d\n",
124 mmc_hostname(host->mmc),
125 host->pio_ptr, host->pio_size);
126 return 1;
127 } else {
128 dma_addr_t phys_addr;
129 int dma_dir = (data->flags & MMC_DATA_READ) ?
130 DMA_FROM_DEVICE : DMA_TO_DEVICE;
131 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
132 data->sg_len, dma_dir);
133 phys_addr = sg_dma_address(data->sg);
134 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
135 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
136 return 0;
137 }
138}
139
140static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
141{
142 struct mvsd_host *host = mmc_priv(mmc);
143 void __iomem *iobase = host->base;
144 struct mmc_command *cmd = mrq->cmd;
145 u32 cmdreg = 0, xfer = 0, intr = 0;
146 unsigned long flags;
147
148 BUG_ON(host->mrq != NULL);
149 host->mrq = mrq;
150
151 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
152 cmd->opcode, mvsd_read(MVSD_HW_STATE));
153
154 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
155
156 if (cmd->flags & MMC_RSP_BUSY)
157 cmdreg |= MVSD_CMD_RSP_48BUSY;
158 else if (cmd->flags & MMC_RSP_136)
159 cmdreg |= MVSD_CMD_RSP_136;
160 else if (cmd->flags & MMC_RSP_PRESENT)
161 cmdreg |= MVSD_CMD_RSP_48;
162 else
163 cmdreg |= MVSD_CMD_RSP_NONE;
164
165 if (cmd->flags & MMC_RSP_CRC)
166 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
167
168 if (cmd->flags & MMC_RSP_OPCODE)
169 cmdreg |= MVSD_CMD_INDX_CHECK;
170
171 if (cmd->flags & MMC_RSP_PRESENT) {
172 cmdreg |= MVSD_UNEXPECTED_RESP;
173 intr |= MVSD_NOR_UNEXP_RSP;
174 }
175
176 if (mrq->data) {
177 struct mmc_data *data = mrq->data;
178 int pio;
179
180 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
181 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
182 if (data->flags & MMC_DATA_READ)
183 xfer |= MVSD_XFER_MODE_TO_HOST;
184
185 pio = mvsd_setup_data(host, data);
186 if (pio) {
187 xfer |= MVSD_XFER_MODE_PIO;
188 /* PIO section of mvsd_irq has comments on those bits */
189 if (data->flags & MMC_DATA_WRITE)
190 intr |= MVSD_NOR_TX_AVAIL;
191 else if (host->pio_size > 32)
192 intr |= MVSD_NOR_RX_FIFO_8W;
193 else
194 intr |= MVSD_NOR_RX_READY;
195 }
196
197 if (data->stop) {
198 struct mmc_command *stop = data->stop;
199 u32 cmd12reg = 0;
200
201 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
202 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
203
204 if (stop->flags & MMC_RSP_BUSY)
205 cmd12reg |= MVSD_AUTOCMD12_BUSY;
206 if (stop->flags & MMC_RSP_OPCODE)
207 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
208 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
209 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
210
211 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
212 intr |= MVSD_NOR_AUTOCMD12_DONE;
213 } else {
214 intr |= MVSD_NOR_XFER_DONE;
215 }
216 } else {
217 intr |= MVSD_NOR_CMD_DONE;
218 }
219
220 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
221 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
222
223 spin_lock_irqsave(&host->lock, flags);
224
225 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
226 host->xfer_mode |= xfer;
227 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
228
229 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
230 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
231 mvsd_write(MVSD_CMD, cmdreg);
232
233 host->intr_en &= MVSD_NOR_CARD_INT;
234 host->intr_en |= intr | MVSD_NOR_ERROR;
235 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
236 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
237
238 mod_timer(&host->timer, jiffies + 5 * HZ);
239
240 spin_unlock_irqrestore(&host->lock, flags);
241}
242
243static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
244 u32 err_status)
245{
246 void __iomem *iobase = host->base;
247
248 if (cmd->flags & MMC_RSP_136) {
249 unsigned int response[8], i;
250 for (i = 0; i < 8; i++)
251 response[i] = mvsd_read(MVSD_RSP(i));
252 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
253 ((response[1] & 0xffff) << 6) |
254 ((response[2] & 0xfc00) >> 10);
255 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
256 ((response[3] & 0xffff) << 6) |
257 ((response[4] & 0xfc00) >> 10);
258 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
259 ((response[5] & 0xffff) << 6) |
260 ((response[6] & 0xfc00) >> 10);
261 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
262 ((response[7] & 0x3fff) << 8);
263 } else if (cmd->flags & MMC_RSP_PRESENT) {
264 unsigned int response[3], i;
265 for (i = 0; i < 3; i++)
266 response[i] = mvsd_read(MVSD_RSP(i));
267 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
268 ((response[1] & 0xffff) << (14 - 8)) |
269 ((response[0] & 0x03ff) << (30 - 8));
270 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
271 cmd->resp[2] = 0;
272 cmd->resp[3] = 0;
273 }
274
275 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
276 cmd->error = -ETIMEDOUT;
277 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
278 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
279 cmd->error = -EILSEQ;
280 }
281 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
282 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
283 MVSD_ERR_CMD_STARTBIT);
284
285 return err_status;
286}
287
288static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
289 u32 err_status)
290{
291 void __iomem *iobase = host->base;
292
293 if (host->pio_ptr) {
294 host->pio_ptr = NULL;
295 host->pio_size = 0;
296 } else {
297 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
298 (data->flags & MMC_DATA_READ) ?
299 DMA_FROM_DEVICE : DMA_TO_DEVICE);
300 }
301
302 if (err_status & MVSD_ERR_DATA_TIMEOUT)
303 data->error = -ETIMEDOUT;
304 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
305 data->error = -EILSEQ;
306 else if (err_status & MVSD_ERR_XFER_SIZE)
307 data->error = -EBADE;
308 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
309 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
310
311 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
312 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
313 data->bytes_xfered =
314 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
315 /* We can't be sure about the last block when errors are detected */
316 if (data->bytes_xfered && data->error)
317 data->bytes_xfered -= data->blksz;
318
319 /* Handle Auto cmd 12 response */
320 if (data->stop) {
321 unsigned int response[3], i;
322 for (i = 0; i < 3; i++)
323 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
324 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
325 ((response[1] & 0xffff) << (14 - 8)) |
326 ((response[0] & 0x03ff) << (30 - 8));
327 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
328 data->stop->resp[2] = 0;
329 data->stop->resp[3] = 0;
330
331 if (err_status & MVSD_ERR_AUTOCMD12) {
332 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
333 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
334 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
335 data->stop->error = -ENOEXEC;
336 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
337 data->stop->error = -ETIMEDOUT;
338 else if (err_cmd12)
339 data->stop->error = -EILSEQ;
340 err_status &= ~MVSD_ERR_AUTOCMD12;
341 }
342 }
343
344 return err_status;
345}
346
347static irqreturn_t mvsd_irq(int irq, void *dev)
348{
349 struct mvsd_host *host = dev;
350 void __iomem *iobase = host->base;
351 u32 intr_status, intr_done_mask;
352 int irq_handled = 0;
353
354 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
355 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
356 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
357 mvsd_read(MVSD_HW_STATE));
358
359 spin_lock(&host->lock);
360
361 /* PIO handling, if needed. Messy business... */
362 if (host->pio_size &&
363 (intr_status & host->intr_en &
364 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
365 u16 *p = host->pio_ptr;
366 int s = host->pio_size;
367 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
368 readsw(iobase + MVSD_FIFO, p, 16);
369 p += 16;
370 s -= 32;
371 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
372 }
373 /*
374 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
375 * doesn't appear to assert when there is exactly 32 bytes
376 * (8 words) left to fetch in a transfer.
377 */
378 if (s <= 32) {
379 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
380 put_unaligned(mvsd_read(MVSD_FIFO), p++);
381 put_unaligned(mvsd_read(MVSD_FIFO), p++);
382 s -= 4;
383 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
384 }
385 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
386 u16 val[2] = {0, 0};
387 val[0] = mvsd_read(MVSD_FIFO);
388 val[1] = mvsd_read(MVSD_FIFO);
389 memcpy(p, ((void *)&val) + 4 - s, s);
390 s = 0;
391 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
392 }
393 if (s == 0) {
394 host->intr_en &=
395 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
396 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
397 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
398 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
399 host->intr_en |= MVSD_NOR_RX_READY;
400 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
401 }
402 }
403 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
404 s, intr_status, mvsd_read(MVSD_HW_STATE));
405 host->pio_ptr = p;
406 host->pio_size = s;
407 irq_handled = 1;
408 } else if (host->pio_size &&
409 (intr_status & host->intr_en &
410 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
411 u16 *p = host->pio_ptr;
412 int s = host->pio_size;
413 /*
414 * The TX_FIFO_8W bit is unreliable. When set, bursting
415 * 16 halfwords all at once in the FIFO drops data. Actually
416 * TX_AVAIL does go off after only one word is pushed even if
417 * TX_FIFO_8W remains set.
418 */
419 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
420 mvsd_write(MVSD_FIFO, get_unaligned(p++));
421 mvsd_write(MVSD_FIFO, get_unaligned(p++));
422 s -= 4;
423 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
424 }
425 if (s < 4) {
426 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
427 u16 val[2] = {0, 0};
428 memcpy(((void *)&val) + 4 - s, p, s);
429 mvsd_write(MVSD_FIFO, val[0]);
430 mvsd_write(MVSD_FIFO, val[1]);
431 s = 0;
432 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
433 }
434 if (s == 0) {
435 host->intr_en &=
436 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
437 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
438 }
439 }
440 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
441 s, intr_status, mvsd_read(MVSD_HW_STATE));
442 host->pio_ptr = p;
443 host->pio_size = s;
444 irq_handled = 1;
445 }
446
447 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
448
449 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
450 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
451 if (intr_status & host->intr_en & ~intr_done_mask) {
452 struct mmc_request *mrq = host->mrq;
453 struct mmc_command *cmd = mrq->cmd;
454 u32 err_status = 0;
455
456 del_timer(&host->timer);
457 host->mrq = NULL;
458
459 host->intr_en &= MVSD_NOR_CARD_INT;
460 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
461 mvsd_write(MVSD_ERR_INTR_EN, 0);
462
463 spin_unlock(&host->lock);
464
465 if (intr_status & MVSD_NOR_UNEXP_RSP) {
466 cmd->error = -EPROTO;
467 } else if (intr_status & MVSD_NOR_ERROR) {
468 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
469 dev_dbg(host->dev, "err 0x%04x\n", err_status);
470 }
471
472 err_status = mvsd_finish_cmd(host, cmd, err_status);
473 if (mrq->data)
474 err_status = mvsd_finish_data(host, mrq->data, err_status);
475 if (err_status) {
476 pr_err("%s: unhandled error status %#04x\n",
477 mmc_hostname(host->mmc), err_status);
478 cmd->error = -ENOMSG;
479 }
480
481 mmc_request_done(host->mmc, mrq);
482 irq_handled = 1;
483 } else
484 spin_unlock(&host->lock);
485
486 if (intr_status & MVSD_NOR_CARD_INT) {
487 mmc_signal_sdio_irq(host->mmc);
488 irq_handled = 1;
489 }
490
491 if (irq_handled)
492 return IRQ_HANDLED;
493
494 pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x "
495 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
496 host->intr_en, host->pio_size);
497 return IRQ_NONE;
498}
499
500static void mvsd_timeout_timer(unsigned long data)
501{
502 struct mvsd_host *host = (struct mvsd_host *)data;
503 void __iomem *iobase = host->base;
504 struct mmc_request *mrq;
505 unsigned long flags;
506
507 spin_lock_irqsave(&host->lock, flags);
508 mrq = host->mrq;
509 if (mrq) {
510 pr_err("%s: Timeout waiting for hardware interrupt.\n",
511 mmc_hostname(host->mmc));
512 pr_err("%s: hw_state=0x%04x, intr_status=0x%04x "
513 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
514 mvsd_read(MVSD_HW_STATE),
515 mvsd_read(MVSD_NOR_INTR_STATUS),
516 mvsd_read(MVSD_NOR_INTR_EN));
517
518 host->mrq = NULL;
519
520 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
521
522 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
523 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
524
525 host->intr_en &= MVSD_NOR_CARD_INT;
526 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
527 mvsd_write(MVSD_ERR_INTR_EN, 0);
528 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
529
530 mrq->cmd->error = -ETIMEDOUT;
531 mvsd_finish_cmd(host, mrq->cmd, 0);
532 if (mrq->data) {
533 mrq->data->error = -ETIMEDOUT;
534 mvsd_finish_data(host, mrq->data, 0);
535 }
536 }
537 spin_unlock_irqrestore(&host->lock, flags);
538
539 if (mrq)
540 mmc_request_done(host->mmc, mrq);
541}
542
543static irqreturn_t mvsd_card_detect_irq(int irq, void *dev)
544{
545 struct mvsd_host *host = dev;
546 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
547 return IRQ_HANDLED;
548}
549
550static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
551{
552 struct mvsd_host *host = mmc_priv(mmc);
553 void __iomem *iobase = host->base;
554 unsigned long flags;
555
556 spin_lock_irqsave(&host->lock, flags);
557 if (enable) {
558 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
559 host->intr_en |= MVSD_NOR_CARD_INT;
560 } else {
561 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
562 host->intr_en &= ~MVSD_NOR_CARD_INT;
563 }
564 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
565 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
566 spin_unlock_irqrestore(&host->lock, flags);
567}
568
569static int mvsd_get_ro(struct mmc_host *mmc)
570{
571 struct mvsd_host *host = mmc_priv(mmc);
572
573 if (host->gpio_write_protect)
574 return gpio_get_value(host->gpio_write_protect);
575
576 /*
577 * Board doesn't support read only detection; let the mmc core
578 * decide what to do.
579 */
580 return -ENOSYS;
581}
582
583static void mvsd_power_up(struct mvsd_host *host)
584{
585 void __iomem *iobase = host->base;
586 dev_dbg(host->dev, "power up\n");
587 mvsd_write(MVSD_NOR_INTR_EN, 0);
588 mvsd_write(MVSD_ERR_INTR_EN, 0);
589 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
590 mvsd_write(MVSD_XFER_MODE, 0);
591 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
592 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
593 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
594 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
595}
596
597static void mvsd_power_down(struct mvsd_host *host)
598{
599 void __iomem *iobase = host->base;
600 dev_dbg(host->dev, "power down\n");
601 mvsd_write(MVSD_NOR_INTR_EN, 0);
602 mvsd_write(MVSD_ERR_INTR_EN, 0);
603 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
604 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
605 mvsd_write(MVSD_NOR_STATUS_EN, 0);
606 mvsd_write(MVSD_ERR_STATUS_EN, 0);
607 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
608 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
609}
610
611static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
612{
613 struct mvsd_host *host = mmc_priv(mmc);
614 void __iomem *iobase = host->base;
615 u32 ctrl_reg = 0;
616
617 if (ios->power_mode == MMC_POWER_UP)
618 mvsd_power_up(host);
619
620 if (ios->clock == 0) {
621 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
622 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
623 host->clock = 0;
624 dev_dbg(host->dev, "clock off\n");
625 } else if (ios->clock != host->clock) {
626 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
627 if (m > MVSD_BASE_DIV_MAX)
628 m = MVSD_BASE_DIV_MAX;
629 mvsd_write(MVSD_CLK_DIV, m);
630 host->clock = ios->clock;
631 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
632 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
633 ios->clock, host->base_clock / (m+1), m);
634 }
635
636 /* default transfer mode */
637 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
638 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
639
640 /* default to maximum timeout */
641 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
642 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
643
644 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
645 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
646
647 if (ios->bus_width == MMC_BUS_WIDTH_4)
648 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
649
650 /*
651 * The HI_SPEED_EN bit is causing trouble with many (but not all)
652 * high speed SD, SDHC and SDIO cards. Not enabling that bit
653 * makes all cards work. So let's just ignore that bit for now
654 * and revisit this issue if problems for not enabling this bit
655 * are ever reported.
656 */
657#if 0
658 if (ios->timing == MMC_TIMING_MMC_HS ||
659 ios->timing == MMC_TIMING_SD_HS)
660 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
661#endif
662
663 host->ctrl = ctrl_reg;
664 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
665 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
666 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
667 "push-pull" : "open-drain",
668 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
669 "4bit-width" : "1bit-width",
670 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
671 "high-speed" : "");
672
673 if (ios->power_mode == MMC_POWER_OFF)
674 mvsd_power_down(host);
675}
676
677static const struct mmc_host_ops mvsd_ops = {
678 .request = mvsd_request,
679 .get_ro = mvsd_get_ro,
680 .set_ios = mvsd_set_ios,
681 .enable_sdio_irq = mvsd_enable_sdio_irq,
682};
683
684static void __init
685mv_conf_mbus_windows(struct mvsd_host *host,
686 const struct mbus_dram_target_info *dram)
687{
688 void __iomem *iobase = host->base;
689 int i;
690
691 for (i = 0; i < 4; i++) {
692 writel(0, iobase + MVSD_WINDOW_CTRL(i));
693 writel(0, iobase + MVSD_WINDOW_BASE(i));
694 }
695
696 for (i = 0; i < dram->num_cs; i++) {
697 const struct mbus_dram_window *cs = dram->cs + i;
698 writel(((cs->size - 1) & 0xffff0000) |
699 (cs->mbus_attr << 8) |
700 (dram->mbus_dram_target_id << 4) | 1,
701 iobase + MVSD_WINDOW_CTRL(i));
702 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
703 }
704}
705
706static int __init mvsd_probe(struct platform_device *pdev)
707{
708 struct mmc_host *mmc = NULL;
709 struct mvsd_host *host = NULL;
710 const struct mvsdio_platform_data *mvsd_data;
711 const struct mbus_dram_target_info *dram;
712 struct resource *r;
713 int ret, irq;
714
715 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716 irq = platform_get_irq(pdev, 0);
717 mvsd_data = pdev->dev.platform_data;
718 if (!r || irq < 0 || !mvsd_data)
719 return -ENXIO;
720
721 r = request_mem_region(r->start, SZ_1K, DRIVER_NAME);
722 if (!r)
723 return -EBUSY;
724
725 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
726 if (!mmc) {
727 ret = -ENOMEM;
728 goto out;
729 }
730
731 host = mmc_priv(mmc);
732 host->mmc = mmc;
733 host->dev = &pdev->dev;
734 host->res = r;
735 host->base_clock = mvsd_data->clock / 2;
736
737 mmc->ops = &mvsd_ops;
738
739 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
740 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
741 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
742
743 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
744 mmc->f_max = maxfreq;
745
746 mmc->max_blk_size = 2048;
747 mmc->max_blk_count = 65535;
748
749 mmc->max_segs = 1;
750 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
751 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
752
753 spin_lock_init(&host->lock);
754
755 host->base = ioremap(r->start, SZ_4K);
756 if (!host->base) {
757 ret = -ENOMEM;
758 goto out;
759 }
760
761 /* (Re-)program MBUS remapping windows if we are asked to. */
762 dram = mv_mbus_dram_info();
763 if (dram)
764 mv_conf_mbus_windows(host, dram);
765
766 mvsd_power_down(host);
767
768 ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host);
769 if (ret) {
770 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq);
771 goto out;
772 } else
773 host->irq = irq;
774
775 /* Not all platforms can gate the clock, so it is not
776 an error if the clock does not exists. */
777 host->clk = clk_get(&pdev->dev, NULL);
778 if (!IS_ERR(host->clk)) {
779 clk_prepare_enable(host->clk);
780 }
781
782 if (mvsd_data->gpio_card_detect) {
783 ret = gpio_request(mvsd_data->gpio_card_detect,
784 DRIVER_NAME " cd");
785 if (ret == 0) {
786 gpio_direction_input(mvsd_data->gpio_card_detect);
787 irq = gpio_to_irq(mvsd_data->gpio_card_detect);
788 ret = request_irq(irq, mvsd_card_detect_irq,
789 IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
790 DRIVER_NAME " cd", host);
791 if (ret == 0)
792 host->gpio_card_detect =
793 mvsd_data->gpio_card_detect;
794 else
795 gpio_free(mvsd_data->gpio_card_detect);
796 }
797 }
798 if (!host->gpio_card_detect)
799 mmc->caps |= MMC_CAP_NEEDS_POLL;
800
801 if (mvsd_data->gpio_write_protect) {
802 ret = gpio_request(mvsd_data->gpio_write_protect,
803 DRIVER_NAME " wp");
804 if (ret == 0) {
805 gpio_direction_input(mvsd_data->gpio_write_protect);
806 host->gpio_write_protect =
807 mvsd_data->gpio_write_protect;
808 }
809 }
810
811 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
812 platform_set_drvdata(pdev, mmc);
813 ret = mmc_add_host(mmc);
814 if (ret)
815 goto out;
816
817 pr_notice("%s: %s driver initialized, ",
818 mmc_hostname(mmc), DRIVER_NAME);
819 if (host->gpio_card_detect)
820 printk("using GPIO %d for card detection\n",
821 host->gpio_card_detect);
822 else
823 printk("lacking card detect (fall back to polling)\n");
824 return 0;
825
826out:
827 if (host) {
828 if (host->irq)
829 free_irq(host->irq, host);
830 if (host->gpio_card_detect) {
831 free_irq(gpio_to_irq(host->gpio_card_detect), host);
832 gpio_free(host->gpio_card_detect);
833 }
834 if (host->gpio_write_protect)
835 gpio_free(host->gpio_write_protect);
836 if (host->base)
837 iounmap(host->base);
838 }
839 if (r)
840 release_resource(r);
841 if (mmc)
842 mmc_free_host(mmc);
843
844 return ret;
845}
846
847static int __exit mvsd_remove(struct platform_device *pdev)
848{
849 struct mmc_host *mmc = platform_get_drvdata(pdev);
850
851 if (mmc) {
852 struct mvsd_host *host = mmc_priv(mmc);
853
854 if (host->gpio_card_detect) {
855 free_irq(gpio_to_irq(host->gpio_card_detect), host);
856 gpio_free(host->gpio_card_detect);
857 }
858 mmc_remove_host(mmc);
859 free_irq(host->irq, host);
860 if (host->gpio_write_protect)
861 gpio_free(host->gpio_write_protect);
862 del_timer_sync(&host->timer);
863 mvsd_power_down(host);
864 iounmap(host->base);
865 release_resource(host->res);
866
867 if (!IS_ERR(host->clk)) {
868 clk_disable_unprepare(host->clk);
869 clk_put(host->clk);
870 }
871 mmc_free_host(mmc);
872 }
873 platform_set_drvdata(pdev, NULL);
874 return 0;
875}
876
877#ifdef CONFIG_PM
878static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
879{
880 struct mmc_host *mmc = platform_get_drvdata(dev);
881 int ret = 0;
882
883 if (mmc)
884 ret = mmc_suspend_host(mmc);
885
886 return ret;
887}
888
889static int mvsd_resume(struct platform_device *dev)
890{
891 struct mmc_host *mmc = platform_get_drvdata(dev);
892 int ret = 0;
893
894 if (mmc)
895 ret = mmc_resume_host(mmc);
896
897 return ret;
898}
899#else
900#define mvsd_suspend NULL
901#define mvsd_resume NULL
902#endif
903
904static struct platform_driver mvsd_driver = {
905 .remove = __exit_p(mvsd_remove),
906 .suspend = mvsd_suspend,
907 .resume = mvsd_resume,
908 .driver = {
909 .name = DRIVER_NAME,
910 },
911};
912
913static int __init mvsd_init(void)
914{
915 return platform_driver_probe(&mvsd_driver, mvsd_probe);
916}
917
918static void __exit mvsd_exit(void)
919{
920 platform_driver_unregister(&mvsd_driver);
921}
922
923module_init(mvsd_init);
924module_exit(mvsd_exit);
925
926/* maximum card clock frequency (default 50MHz) */
927module_param(maxfreq, int, 0);
928
929/* force PIO transfers all the time */
930module_param(nodma, int, 0);
931
932MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
933MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
934MODULE_LICENSE("GPL");
935MODULE_ALIAS("platform:mvsdio");
1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
22#include <linux/gpio.h>
23#include <linux/mmc/host.h>
24
25#include <asm/sizes.h>
26#include <asm/unaligned.h>
27#include <plat/mvsdio.h>
28
29#include "mvsdio.h"
30
31#define DRIVER_NAME "mvsdio"
32
33static int maxfreq = MVSD_CLOCKRATE_MAX;
34static int nodma;
35
36struct mvsd_host {
37 void __iomem *base;
38 struct mmc_request *mrq;
39 spinlock_t lock;
40 unsigned int xfer_mode;
41 unsigned int intr_en;
42 unsigned int ctrl;
43 unsigned int pio_size;
44 void *pio_ptr;
45 unsigned int sg_frags;
46 unsigned int ns_per_clk;
47 unsigned int clock;
48 unsigned int base_clock;
49 struct timer_list timer;
50 struct mmc_host *mmc;
51 struct device *dev;
52 struct resource *res;
53 int irq;
54 int gpio_card_detect;
55 int gpio_write_protect;
56};
57
58#define mvsd_write(offs, val) writel(val, iobase + (offs))
59#define mvsd_read(offs) readl(iobase + (offs))
60
61static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
62{
63 void __iomem *iobase = host->base;
64 unsigned int tmout;
65 int tmout_index;
66
67 /*
68 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
69 * register is sometimes not set before a while when some
70 * "unusual" data block sizes are used (such as with the SWITCH
71 * command), even despite the fact that the XFER_DONE interrupt
72 * was raised. And if another data transfer starts before
73 * this bit comes to good sense (which eventually happens by
74 * itself) then the new transfer simply fails with a timeout.
75 */
76 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
77 unsigned long t = jiffies + HZ;
78 unsigned int hw_state, count = 0;
79 do {
80 if (time_after(jiffies, t)) {
81 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
82 break;
83 }
84 hw_state = mvsd_read(MVSD_HW_STATE);
85 count++;
86 } while (!(hw_state & (1 << 13)));
87 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
88 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
89 hw_state, count, jiffies - (t - HZ));
90 }
91
92 /* If timeout=0 then maximum timeout index is used. */
93 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
94 tmout += data->timeout_clks;
95 tmout_index = fls(tmout - 1) - 12;
96 if (tmout_index < 0)
97 tmout_index = 0;
98 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
99 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
100
101 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
102 (data->flags & MMC_DATA_READ) ? "read" : "write",
103 (u32)sg_virt(data->sg), data->blocks, data->blksz,
104 tmout, tmout_index);
105
106 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
107 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
108 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
109 mvsd_write(MVSD_BLK_COUNT, data->blocks);
110 mvsd_write(MVSD_BLK_SIZE, data->blksz);
111
112 if (nodma || (data->blksz | data->sg->offset) & 3) {
113 /*
114 * We cannot do DMA on a buffer which offset or size
115 * is not aligned on a 4-byte boundary.
116 */
117 host->pio_size = data->blocks * data->blksz;
118 host->pio_ptr = sg_virt(data->sg);
119 if (!nodma)
120 printk(KERN_DEBUG "%s: fallback to PIO for data "
121 "at 0x%p size %d\n",
122 mmc_hostname(host->mmc),
123 host->pio_ptr, host->pio_size);
124 return 1;
125 } else {
126 dma_addr_t phys_addr;
127 int dma_dir = (data->flags & MMC_DATA_READ) ?
128 DMA_FROM_DEVICE : DMA_TO_DEVICE;
129 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
130 data->sg_len, dma_dir);
131 phys_addr = sg_dma_address(data->sg);
132 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
133 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
134 return 0;
135 }
136}
137
138static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
139{
140 struct mvsd_host *host = mmc_priv(mmc);
141 void __iomem *iobase = host->base;
142 struct mmc_command *cmd = mrq->cmd;
143 u32 cmdreg = 0, xfer = 0, intr = 0;
144 unsigned long flags;
145
146 BUG_ON(host->mrq != NULL);
147 host->mrq = mrq;
148
149 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
150 cmd->opcode, mvsd_read(MVSD_HW_STATE));
151
152 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
153
154 if (cmd->flags & MMC_RSP_BUSY)
155 cmdreg |= MVSD_CMD_RSP_48BUSY;
156 else if (cmd->flags & MMC_RSP_136)
157 cmdreg |= MVSD_CMD_RSP_136;
158 else if (cmd->flags & MMC_RSP_PRESENT)
159 cmdreg |= MVSD_CMD_RSP_48;
160 else
161 cmdreg |= MVSD_CMD_RSP_NONE;
162
163 if (cmd->flags & MMC_RSP_CRC)
164 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
165
166 if (cmd->flags & MMC_RSP_OPCODE)
167 cmdreg |= MVSD_CMD_INDX_CHECK;
168
169 if (cmd->flags & MMC_RSP_PRESENT) {
170 cmdreg |= MVSD_UNEXPECTED_RESP;
171 intr |= MVSD_NOR_UNEXP_RSP;
172 }
173
174 if (mrq->data) {
175 struct mmc_data *data = mrq->data;
176 int pio;
177
178 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
179 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
180 if (data->flags & MMC_DATA_READ)
181 xfer |= MVSD_XFER_MODE_TO_HOST;
182
183 pio = mvsd_setup_data(host, data);
184 if (pio) {
185 xfer |= MVSD_XFER_MODE_PIO;
186 /* PIO section of mvsd_irq has comments on those bits */
187 if (data->flags & MMC_DATA_WRITE)
188 intr |= MVSD_NOR_TX_AVAIL;
189 else if (host->pio_size > 32)
190 intr |= MVSD_NOR_RX_FIFO_8W;
191 else
192 intr |= MVSD_NOR_RX_READY;
193 }
194
195 if (data->stop) {
196 struct mmc_command *stop = data->stop;
197 u32 cmd12reg = 0;
198
199 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
200 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
201
202 if (stop->flags & MMC_RSP_BUSY)
203 cmd12reg |= MVSD_AUTOCMD12_BUSY;
204 if (stop->flags & MMC_RSP_OPCODE)
205 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
206 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
207 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
208
209 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
210 intr |= MVSD_NOR_AUTOCMD12_DONE;
211 } else {
212 intr |= MVSD_NOR_XFER_DONE;
213 }
214 } else {
215 intr |= MVSD_NOR_CMD_DONE;
216 }
217
218 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
219 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
220
221 spin_lock_irqsave(&host->lock, flags);
222
223 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
224 host->xfer_mode |= xfer;
225 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
226
227 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
228 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
229 mvsd_write(MVSD_CMD, cmdreg);
230
231 host->intr_en &= MVSD_NOR_CARD_INT;
232 host->intr_en |= intr | MVSD_NOR_ERROR;
233 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
234 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
235
236 mod_timer(&host->timer, jiffies + 5 * HZ);
237
238 spin_unlock_irqrestore(&host->lock, flags);
239}
240
241static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
242 u32 err_status)
243{
244 void __iomem *iobase = host->base;
245
246 if (cmd->flags & MMC_RSP_136) {
247 unsigned int response[8], i;
248 for (i = 0; i < 8; i++)
249 response[i] = mvsd_read(MVSD_RSP(i));
250 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
251 ((response[1] & 0xffff) << 6) |
252 ((response[2] & 0xfc00) >> 10);
253 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
254 ((response[3] & 0xffff) << 6) |
255 ((response[4] & 0xfc00) >> 10);
256 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
257 ((response[5] & 0xffff) << 6) |
258 ((response[6] & 0xfc00) >> 10);
259 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
260 ((response[7] & 0x3fff) << 8);
261 } else if (cmd->flags & MMC_RSP_PRESENT) {
262 unsigned int response[3], i;
263 for (i = 0; i < 3; i++)
264 response[i] = mvsd_read(MVSD_RSP(i));
265 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
266 ((response[1] & 0xffff) << (14 - 8)) |
267 ((response[0] & 0x03ff) << (30 - 8));
268 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
269 cmd->resp[2] = 0;
270 cmd->resp[3] = 0;
271 }
272
273 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
274 cmd->error = -ETIMEDOUT;
275 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
276 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
277 cmd->error = -EILSEQ;
278 }
279 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
280 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
281 MVSD_ERR_CMD_STARTBIT);
282
283 return err_status;
284}
285
286static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
287 u32 err_status)
288{
289 void __iomem *iobase = host->base;
290
291 if (host->pio_ptr) {
292 host->pio_ptr = NULL;
293 host->pio_size = 0;
294 } else {
295 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
296 (data->flags & MMC_DATA_READ) ?
297 DMA_FROM_DEVICE : DMA_TO_DEVICE);
298 }
299
300 if (err_status & MVSD_ERR_DATA_TIMEOUT)
301 data->error = -ETIMEDOUT;
302 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
303 data->error = -EILSEQ;
304 else if (err_status & MVSD_ERR_XFER_SIZE)
305 data->error = -EBADE;
306 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
307 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
308
309 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
310 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
311 data->bytes_xfered =
312 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
313 /* We can't be sure about the last block when errors are detected */
314 if (data->bytes_xfered && data->error)
315 data->bytes_xfered -= data->blksz;
316
317 /* Handle Auto cmd 12 response */
318 if (data->stop) {
319 unsigned int response[3], i;
320 for (i = 0; i < 3; i++)
321 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
322 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
323 ((response[1] & 0xffff) << (14 - 8)) |
324 ((response[0] & 0x03ff) << (30 - 8));
325 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
326 data->stop->resp[2] = 0;
327 data->stop->resp[3] = 0;
328
329 if (err_status & MVSD_ERR_AUTOCMD12) {
330 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
331 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
332 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
333 data->stop->error = -ENOEXEC;
334 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
335 data->stop->error = -ETIMEDOUT;
336 else if (err_cmd12)
337 data->stop->error = -EILSEQ;
338 err_status &= ~MVSD_ERR_AUTOCMD12;
339 }
340 }
341
342 return err_status;
343}
344
345static irqreturn_t mvsd_irq(int irq, void *dev)
346{
347 struct mvsd_host *host = dev;
348 void __iomem *iobase = host->base;
349 u32 intr_status, intr_done_mask;
350 int irq_handled = 0;
351
352 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
353 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
355 mvsd_read(MVSD_HW_STATE));
356
357 spin_lock(&host->lock);
358
359 /* PIO handling, if needed. Messy business... */
360 if (host->pio_size &&
361 (intr_status & host->intr_en &
362 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
363 u16 *p = host->pio_ptr;
364 int s = host->pio_size;
365 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
366 readsw(iobase + MVSD_FIFO, p, 16);
367 p += 16;
368 s -= 32;
369 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
370 }
371 /*
372 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
373 * doesn't appear to assert when there is exactly 32 bytes
374 * (8 words) left to fetch in a transfer.
375 */
376 if (s <= 32) {
377 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
378 put_unaligned(mvsd_read(MVSD_FIFO), p++);
379 put_unaligned(mvsd_read(MVSD_FIFO), p++);
380 s -= 4;
381 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
382 }
383 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
384 u16 val[2] = {0, 0};
385 val[0] = mvsd_read(MVSD_FIFO);
386 val[1] = mvsd_read(MVSD_FIFO);
387 memcpy(p, ((void *)&val) + 4 - s, s);
388 s = 0;
389 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
390 }
391 if (s == 0) {
392 host->intr_en &=
393 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
394 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
395 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
396 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
397 host->intr_en |= MVSD_NOR_RX_READY;
398 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
399 }
400 }
401 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
402 s, intr_status, mvsd_read(MVSD_HW_STATE));
403 host->pio_ptr = p;
404 host->pio_size = s;
405 irq_handled = 1;
406 } else if (host->pio_size &&
407 (intr_status & host->intr_en &
408 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
409 u16 *p = host->pio_ptr;
410 int s = host->pio_size;
411 /*
412 * The TX_FIFO_8W bit is unreliable. When set, bursting
413 * 16 halfwords all at once in the FIFO drops data. Actually
414 * TX_AVAIL does go off after only one word is pushed even if
415 * TX_FIFO_8W remains set.
416 */
417 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
418 mvsd_write(MVSD_FIFO, get_unaligned(p++));
419 mvsd_write(MVSD_FIFO, get_unaligned(p++));
420 s -= 4;
421 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
422 }
423 if (s < 4) {
424 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
425 u16 val[2] = {0, 0};
426 memcpy(((void *)&val) + 4 - s, p, s);
427 mvsd_write(MVSD_FIFO, val[0]);
428 mvsd_write(MVSD_FIFO, val[1]);
429 s = 0;
430 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
431 }
432 if (s == 0) {
433 host->intr_en &=
434 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
435 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
436 }
437 }
438 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
439 s, intr_status, mvsd_read(MVSD_HW_STATE));
440 host->pio_ptr = p;
441 host->pio_size = s;
442 irq_handled = 1;
443 }
444
445 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
446
447 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
448 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
449 if (intr_status & host->intr_en & ~intr_done_mask) {
450 struct mmc_request *mrq = host->mrq;
451 struct mmc_command *cmd = mrq->cmd;
452 u32 err_status = 0;
453
454 del_timer(&host->timer);
455 host->mrq = NULL;
456
457 host->intr_en &= MVSD_NOR_CARD_INT;
458 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
459 mvsd_write(MVSD_ERR_INTR_EN, 0);
460
461 spin_unlock(&host->lock);
462
463 if (intr_status & MVSD_NOR_UNEXP_RSP) {
464 cmd->error = -EPROTO;
465 } else if (intr_status & MVSD_NOR_ERROR) {
466 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
467 dev_dbg(host->dev, "err 0x%04x\n", err_status);
468 }
469
470 err_status = mvsd_finish_cmd(host, cmd, err_status);
471 if (mrq->data)
472 err_status = mvsd_finish_data(host, mrq->data, err_status);
473 if (err_status) {
474 printk(KERN_ERR "%s: unhandled error status %#04x\n",
475 mmc_hostname(host->mmc), err_status);
476 cmd->error = -ENOMSG;
477 }
478
479 mmc_request_done(host->mmc, mrq);
480 irq_handled = 1;
481 } else
482 spin_unlock(&host->lock);
483
484 if (intr_status & MVSD_NOR_CARD_INT) {
485 mmc_signal_sdio_irq(host->mmc);
486 irq_handled = 1;
487 }
488
489 if (irq_handled)
490 return IRQ_HANDLED;
491
492 printk(KERN_ERR "%s: unhandled interrupt status=0x%04x en=0x%04x "
493 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
494 host->intr_en, host->pio_size);
495 return IRQ_NONE;
496}
497
498static void mvsd_timeout_timer(unsigned long data)
499{
500 struct mvsd_host *host = (struct mvsd_host *)data;
501 void __iomem *iobase = host->base;
502 struct mmc_request *mrq;
503 unsigned long flags;
504
505 spin_lock_irqsave(&host->lock, flags);
506 mrq = host->mrq;
507 if (mrq) {
508 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt.\n",
509 mmc_hostname(host->mmc));
510 printk(KERN_ERR "%s: hw_state=0x%04x, intr_status=0x%04x "
511 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
512 mvsd_read(MVSD_HW_STATE),
513 mvsd_read(MVSD_NOR_INTR_STATUS),
514 mvsd_read(MVSD_NOR_INTR_EN));
515
516 host->mrq = NULL;
517
518 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
519
520 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
521 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
522
523 host->intr_en &= MVSD_NOR_CARD_INT;
524 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
525 mvsd_write(MVSD_ERR_INTR_EN, 0);
526 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
527
528 mrq->cmd->error = -ETIMEDOUT;
529 mvsd_finish_cmd(host, mrq->cmd, 0);
530 if (mrq->data) {
531 mrq->data->error = -ETIMEDOUT;
532 mvsd_finish_data(host, mrq->data, 0);
533 }
534 }
535 spin_unlock_irqrestore(&host->lock, flags);
536
537 if (mrq)
538 mmc_request_done(host->mmc, mrq);
539}
540
541static irqreturn_t mvsd_card_detect_irq(int irq, void *dev)
542{
543 struct mvsd_host *host = dev;
544 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
545 return IRQ_HANDLED;
546}
547
548static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
549{
550 struct mvsd_host *host = mmc_priv(mmc);
551 void __iomem *iobase = host->base;
552 unsigned long flags;
553
554 spin_lock_irqsave(&host->lock, flags);
555 if (enable) {
556 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
557 host->intr_en |= MVSD_NOR_CARD_INT;
558 } else {
559 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
560 host->intr_en &= ~MVSD_NOR_CARD_INT;
561 }
562 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
563 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
564 spin_unlock_irqrestore(&host->lock, flags);
565}
566
567static int mvsd_get_ro(struct mmc_host *mmc)
568{
569 struct mvsd_host *host = mmc_priv(mmc);
570
571 if (host->gpio_write_protect)
572 return gpio_get_value(host->gpio_write_protect);
573
574 /*
575 * Board doesn't support read only detection; let the mmc core
576 * decide what to do.
577 */
578 return -ENOSYS;
579}
580
581static void mvsd_power_up(struct mvsd_host *host)
582{
583 void __iomem *iobase = host->base;
584 dev_dbg(host->dev, "power up\n");
585 mvsd_write(MVSD_NOR_INTR_EN, 0);
586 mvsd_write(MVSD_ERR_INTR_EN, 0);
587 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
588 mvsd_write(MVSD_XFER_MODE, 0);
589 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
590 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
591 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
592 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
593}
594
595static void mvsd_power_down(struct mvsd_host *host)
596{
597 void __iomem *iobase = host->base;
598 dev_dbg(host->dev, "power down\n");
599 mvsd_write(MVSD_NOR_INTR_EN, 0);
600 mvsd_write(MVSD_ERR_INTR_EN, 0);
601 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
602 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
603 mvsd_write(MVSD_NOR_STATUS_EN, 0);
604 mvsd_write(MVSD_ERR_STATUS_EN, 0);
605 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
606 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
607}
608
609static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
610{
611 struct mvsd_host *host = mmc_priv(mmc);
612 void __iomem *iobase = host->base;
613 u32 ctrl_reg = 0;
614
615 if (ios->power_mode == MMC_POWER_UP)
616 mvsd_power_up(host);
617
618 if (ios->clock == 0) {
619 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
620 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
621 host->clock = 0;
622 dev_dbg(host->dev, "clock off\n");
623 } else if (ios->clock != host->clock) {
624 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
625 if (m > MVSD_BASE_DIV_MAX)
626 m = MVSD_BASE_DIV_MAX;
627 mvsd_write(MVSD_CLK_DIV, m);
628 host->clock = ios->clock;
629 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
630 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
631 ios->clock, host->base_clock / (m+1), m);
632 }
633
634 /* default transfer mode */
635 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
636 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
637
638 /* default to maximum timeout */
639 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
640 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
641
642 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
643 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
644
645 if (ios->bus_width == MMC_BUS_WIDTH_4)
646 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
647
648 /*
649 * The HI_SPEED_EN bit is causing trouble with many (but not all)
650 * high speed SD, SDHC and SDIO cards. Not enabling that bit
651 * makes all cards work. So let's just ignore that bit for now
652 * and revisit this issue if problems for not enabling this bit
653 * are ever reported.
654 */
655#if 0
656 if (ios->timing == MMC_TIMING_MMC_HS ||
657 ios->timing == MMC_TIMING_SD_HS)
658 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
659#endif
660
661 host->ctrl = ctrl_reg;
662 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
663 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
664 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
665 "push-pull" : "open-drain",
666 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
667 "4bit-width" : "1bit-width",
668 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
669 "high-speed" : "");
670
671 if (ios->power_mode == MMC_POWER_OFF)
672 mvsd_power_down(host);
673}
674
675static const struct mmc_host_ops mvsd_ops = {
676 .request = mvsd_request,
677 .get_ro = mvsd_get_ro,
678 .set_ios = mvsd_set_ios,
679 .enable_sdio_irq = mvsd_enable_sdio_irq,
680};
681
682static void __init mv_conf_mbus_windows(struct mvsd_host *host,
683 struct mbus_dram_target_info *dram)
684{
685 void __iomem *iobase = host->base;
686 int i;
687
688 for (i = 0; i < 4; i++) {
689 writel(0, iobase + MVSD_WINDOW_CTRL(i));
690 writel(0, iobase + MVSD_WINDOW_BASE(i));
691 }
692
693 for (i = 0; i < dram->num_cs; i++) {
694 struct mbus_dram_window *cs = dram->cs + i;
695 writel(((cs->size - 1) & 0xffff0000) |
696 (cs->mbus_attr << 8) |
697 (dram->mbus_dram_target_id << 4) | 1,
698 iobase + MVSD_WINDOW_CTRL(i));
699 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
700 }
701}
702
703static int __init mvsd_probe(struct platform_device *pdev)
704{
705 struct mmc_host *mmc = NULL;
706 struct mvsd_host *host = NULL;
707 const struct mvsdio_platform_data *mvsd_data;
708 struct resource *r;
709 int ret, irq;
710
711 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 irq = platform_get_irq(pdev, 0);
713 mvsd_data = pdev->dev.platform_data;
714 if (!r || irq < 0 || !mvsd_data)
715 return -ENXIO;
716
717 r = request_mem_region(r->start, SZ_1K, DRIVER_NAME);
718 if (!r)
719 return -EBUSY;
720
721 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
722 if (!mmc) {
723 ret = -ENOMEM;
724 goto out;
725 }
726
727 host = mmc_priv(mmc);
728 host->mmc = mmc;
729 host->dev = &pdev->dev;
730 host->res = r;
731 host->base_clock = mvsd_data->clock / 2;
732
733 mmc->ops = &mvsd_ops;
734
735 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
736 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
737 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
738
739 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
740 mmc->f_max = maxfreq;
741
742 mmc->max_blk_size = 2048;
743 mmc->max_blk_count = 65535;
744
745 mmc->max_segs = 1;
746 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
747 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
748
749 spin_lock_init(&host->lock);
750
751 host->base = ioremap(r->start, SZ_4K);
752 if (!host->base) {
753 ret = -ENOMEM;
754 goto out;
755 }
756
757 /* (Re-)program MBUS remapping windows if we are asked to. */
758 if (mvsd_data->dram != NULL)
759 mv_conf_mbus_windows(host, mvsd_data->dram);
760
761 mvsd_power_down(host);
762
763 ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host);
764 if (ret) {
765 printk(KERN_ERR "%s: cannot assign irq %d\n", DRIVER_NAME, irq);
766 goto out;
767 } else
768 host->irq = irq;
769
770 if (mvsd_data->gpio_card_detect) {
771 ret = gpio_request(mvsd_data->gpio_card_detect,
772 DRIVER_NAME " cd");
773 if (ret == 0) {
774 gpio_direction_input(mvsd_data->gpio_card_detect);
775 irq = gpio_to_irq(mvsd_data->gpio_card_detect);
776 ret = request_irq(irq, mvsd_card_detect_irq,
777 IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
778 DRIVER_NAME " cd", host);
779 if (ret == 0)
780 host->gpio_card_detect =
781 mvsd_data->gpio_card_detect;
782 else
783 gpio_free(mvsd_data->gpio_card_detect);
784 }
785 }
786 if (!host->gpio_card_detect)
787 mmc->caps |= MMC_CAP_NEEDS_POLL;
788
789 if (mvsd_data->gpio_write_protect) {
790 ret = gpio_request(mvsd_data->gpio_write_protect,
791 DRIVER_NAME " wp");
792 if (ret == 0) {
793 gpio_direction_input(mvsd_data->gpio_write_protect);
794 host->gpio_write_protect =
795 mvsd_data->gpio_write_protect;
796 }
797 }
798
799 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
800 platform_set_drvdata(pdev, mmc);
801 ret = mmc_add_host(mmc);
802 if (ret)
803 goto out;
804
805 printk(KERN_NOTICE "%s: %s driver initialized, ",
806 mmc_hostname(mmc), DRIVER_NAME);
807 if (host->gpio_card_detect)
808 printk("using GPIO %d for card detection\n",
809 host->gpio_card_detect);
810 else
811 printk("lacking card detect (fall back to polling)\n");
812 return 0;
813
814out:
815 if (host) {
816 if (host->irq)
817 free_irq(host->irq, host);
818 if (host->gpio_card_detect) {
819 free_irq(gpio_to_irq(host->gpio_card_detect), host);
820 gpio_free(host->gpio_card_detect);
821 }
822 if (host->gpio_write_protect)
823 gpio_free(host->gpio_write_protect);
824 if (host->base)
825 iounmap(host->base);
826 }
827 if (r)
828 release_resource(r);
829 if (mmc)
830 mmc_free_host(mmc);
831
832 return ret;
833}
834
835static int __exit mvsd_remove(struct platform_device *pdev)
836{
837 struct mmc_host *mmc = platform_get_drvdata(pdev);
838
839 if (mmc) {
840 struct mvsd_host *host = mmc_priv(mmc);
841
842 if (host->gpio_card_detect) {
843 free_irq(gpio_to_irq(host->gpio_card_detect), host);
844 gpio_free(host->gpio_card_detect);
845 }
846 mmc_remove_host(mmc);
847 free_irq(host->irq, host);
848 if (host->gpio_write_protect)
849 gpio_free(host->gpio_write_protect);
850 del_timer_sync(&host->timer);
851 mvsd_power_down(host);
852 iounmap(host->base);
853 release_resource(host->res);
854 mmc_free_host(mmc);
855 }
856 platform_set_drvdata(pdev, NULL);
857 return 0;
858}
859
860#ifdef CONFIG_PM
861static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
862{
863 struct mmc_host *mmc = platform_get_drvdata(dev);
864 int ret = 0;
865
866 if (mmc)
867 ret = mmc_suspend_host(mmc);
868
869 return ret;
870}
871
872static int mvsd_resume(struct platform_device *dev)
873{
874 struct mmc_host *mmc = platform_get_drvdata(dev);
875 int ret = 0;
876
877 if (mmc)
878 ret = mmc_resume_host(mmc);
879
880 return ret;
881}
882#else
883#define mvsd_suspend NULL
884#define mvsd_resume NULL
885#endif
886
887static struct platform_driver mvsd_driver = {
888 .remove = __exit_p(mvsd_remove),
889 .suspend = mvsd_suspend,
890 .resume = mvsd_resume,
891 .driver = {
892 .name = DRIVER_NAME,
893 },
894};
895
896static int __init mvsd_init(void)
897{
898 return platform_driver_probe(&mvsd_driver, mvsd_probe);
899}
900
901static void __exit mvsd_exit(void)
902{
903 platform_driver_unregister(&mvsd_driver);
904}
905
906module_init(mvsd_init);
907module_exit(mvsd_exit);
908
909/* maximum card clock frequency (default 50MHz) */
910module_param(maxfreq, int, 0);
911
912/* force PIO transfers all the time */
913module_param(nodma, int, 0);
914
915MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
916MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
917MODULE_LICENSE("GPL");
918MODULE_ALIAS("platform:mvsdio");