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1/* Sparc SS1000/SC2000 SMP support.
2 *
3 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
4 *
5 * Based on sun4m's smp.c, which is:
6 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 */
8
9#include <linux/clockchips.h>
10#include <linux/interrupt.h>
11#include <linux/profile.h>
12#include <linux/delay.h>
13#include <linux/sched.h>
14#include <linux/cpu.h>
15
16#include <asm/cacheflush.h>
17#include <asm/switch_to.h>
18#include <asm/tlbflush.h>
19#include <asm/timer.h>
20#include <asm/oplib.h>
21#include <asm/sbi.h>
22#include <asm/mmu.h>
23
24#include "kernel.h"
25#include "irq.h"
26
27#define IRQ_CROSS_CALL 15
28
29static volatile int smp_processors_ready;
30static int smp_highest_cpu;
31
32static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
33{
34 __asm__ __volatile__("swap [%1], %0\n\t" :
35 "=&r" (val), "=&r" (ptr) :
36 "0" (val), "1" (ptr));
37 return val;
38}
39
40static void smp4d_ipi_init(void);
41
42static unsigned char cpu_leds[32];
43
44static inline void show_leds(int cpuid)
45{
46 cpuid &= 0x1e;
47 __asm__ __volatile__ ("stba %0, [%1] %2" : :
48 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
49 "r" (ECSR_BASE(cpuid) | BB_LEDS),
50 "i" (ASI_M_CTL));
51}
52
53void __cpuinit smp4d_callin(void)
54{
55 int cpuid = hard_smp_processor_id();
56 unsigned long flags;
57
58 /* Show we are alive */
59 cpu_leds[cpuid] = 0x6;
60 show_leds(cpuid);
61
62 /* Enable level15 interrupt, disable level14 interrupt for now */
63 cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
64
65 local_ops->cache_all();
66 local_ops->tlb_all();
67
68 notify_cpu_starting(cpuid);
69 /*
70 * Unblock the master CPU _only_ when the scheduler state
71 * of all secondary CPUs will be up-to-date, so after
72 * the SMP initialization the master will be just allowed
73 * to call the scheduler code.
74 */
75 /* Get our local ticker going. */
76 register_percpu_ce(cpuid);
77
78 calibrate_delay();
79 smp_store_cpu_info(cpuid);
80 local_ops->cache_all();
81 local_ops->tlb_all();
82
83 /* Allow master to continue. */
84 sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
85 local_ops->cache_all();
86 local_ops->tlb_all();
87
88 while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
89 barrier();
90
91 while (current_set[cpuid]->cpu != cpuid)
92 barrier();
93
94 /* Fix idle thread fields. */
95 __asm__ __volatile__("ld [%0], %%g6\n\t"
96 : : "r" (¤t_set[cpuid])
97 : "memory" /* paranoid */);
98
99 cpu_leds[cpuid] = 0x9;
100 show_leds(cpuid);
101
102 /* Attach to the address space of init_task. */
103 atomic_inc(&init_mm.mm_count);
104 current->active_mm = &init_mm;
105
106 local_ops->cache_all();
107 local_ops->tlb_all();
108
109 local_irq_enable(); /* We don't allow PIL 14 yet */
110
111 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
112 barrier();
113
114 spin_lock_irqsave(&sun4d_imsk_lock, flags);
115 cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
116 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
117 set_cpu_online(cpuid, true);
118
119}
120
121/*
122 * Cycle through the processors asking the PROM to start each one.
123 */
124void __init smp4d_boot_cpus(void)
125{
126 smp4d_ipi_init();
127 if (boot_cpu_id)
128 current_set[0] = NULL;
129 local_ops->cache_all();
130}
131
132int __cpuinit smp4d_boot_one_cpu(int i, struct task_struct *idle)
133{
134 unsigned long *entry = &sun4d_cpu_startup;
135 int timeout;
136 int cpu_node;
137
138 cpu_find_by_instance(i, &cpu_node, NULL);
139 current_set[i] = task_thread_info(idle);
140 /*
141 * Initialize the contexts table
142 * Since the call to prom_startcpu() trashes the structure,
143 * we need to re-initialize it for each cpu
144 */
145 smp_penguin_ctable.which_io = 0;
146 smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
147 smp_penguin_ctable.reg_size = 0;
148
149 /* whirrr, whirrr, whirrrrrrrrr... */
150 printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
151 local_ops->cache_all();
152 prom_startcpu(cpu_node,
153 &smp_penguin_ctable, 0, (char *)entry);
154
155 printk(KERN_INFO "prom_startcpu returned :)\n");
156
157 /* wheee... it's going... */
158 for (timeout = 0; timeout < 10000; timeout++) {
159 if (cpu_callin_map[i])
160 break;
161 udelay(200);
162 }
163
164 if (!(cpu_callin_map[i])) {
165 printk(KERN_ERR "Processor %d is stuck.\n", i);
166 return -ENODEV;
167
168 }
169 local_ops->cache_all();
170 return 0;
171}
172
173void __init smp4d_smp_done(void)
174{
175 int i, first;
176 int *prev;
177
178 /* setup cpu list for irq rotation */
179 first = 0;
180 prev = &first;
181 for_each_online_cpu(i) {
182 *prev = i;
183 prev = &cpu_data(i).next;
184 }
185 *prev = first;
186 local_ops->cache_all();
187
188 /* Ok, they are spinning and ready to go. */
189 smp_processors_ready = 1;
190 sun4d_distribute_irqs();
191}
192
193/* Memory structure giving interrupt handler information about IPI generated */
194struct sun4d_ipi_work {
195 int single;
196 int msk;
197 int resched;
198};
199
200static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
201
202/* Initialize IPIs on the SUN4D SMP machine */
203static void __init smp4d_ipi_init(void)
204{
205 int cpu;
206 struct sun4d_ipi_work *work;
207
208 printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
209
210 for_each_possible_cpu(cpu) {
211 work = &per_cpu(sun4d_ipi_work, cpu);
212 work->single = work->msk = work->resched = 0;
213 }
214}
215
216void sun4d_ipi_interrupt(void)
217{
218 struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
219
220 if (work->single) {
221 work->single = 0;
222 smp_call_function_single_interrupt();
223 }
224 if (work->msk) {
225 work->msk = 0;
226 smp_call_function_interrupt();
227 }
228 if (work->resched) {
229 work->resched = 0;
230 smp_resched_interrupt();
231 }
232}
233
234/* +-------+-------------+-----------+------------------------------------+
235 * | bcast | devid | sid | levels mask |
236 * +-------+-------------+-----------+------------------------------------+
237 * 31 30 23 22 15 14 0
238 */
239#define IGEN_MESSAGE(bcast, devid, sid, levels) \
240 (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
241
242static void sun4d_send_ipi(int cpu, int level)
243{
244 cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
245}
246
247static void sun4d_ipi_single(int cpu)
248{
249 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
250
251 /* Mark work */
252 work->single = 1;
253
254 /* Generate IRQ on the CPU */
255 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
256}
257
258static void sun4d_ipi_mask_one(int cpu)
259{
260 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
261
262 /* Mark work */
263 work->msk = 1;
264
265 /* Generate IRQ on the CPU */
266 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
267}
268
269static void sun4d_ipi_resched(int cpu)
270{
271 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
272
273 /* Mark work */
274 work->resched = 1;
275
276 /* Generate IRQ on the CPU (any IRQ will cause resched) */
277 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
278}
279
280static struct smp_funcall {
281 smpfunc_t func;
282 unsigned long arg1;
283 unsigned long arg2;
284 unsigned long arg3;
285 unsigned long arg4;
286 unsigned long arg5;
287 unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
288 unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
289} ccall_info __attribute__((aligned(8)));
290
291static DEFINE_SPINLOCK(cross_call_lock);
292
293/* Cross calls must be serialized, at least currently. */
294static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
295 unsigned long arg2, unsigned long arg3,
296 unsigned long arg4)
297{
298 if (smp_processors_ready) {
299 register int high = smp_highest_cpu;
300 unsigned long flags;
301
302 spin_lock_irqsave(&cross_call_lock, flags);
303
304 {
305 /*
306 * If you make changes here, make sure
307 * gcc generates proper code...
308 */
309 register smpfunc_t f asm("i0") = func;
310 register unsigned long a1 asm("i1") = arg1;
311 register unsigned long a2 asm("i2") = arg2;
312 register unsigned long a3 asm("i3") = arg3;
313 register unsigned long a4 asm("i4") = arg4;
314 register unsigned long a5 asm("i5") = 0;
315
316 __asm__ __volatile__(
317 "std %0, [%6]\n\t"
318 "std %2, [%6 + 8]\n\t"
319 "std %4, [%6 + 16]\n\t" : :
320 "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
321 "r" (&ccall_info.func));
322 }
323
324 /* Init receive/complete mapping, plus fire the IPI's off. */
325 {
326 register int i;
327
328 cpumask_clear_cpu(smp_processor_id(), &mask);
329 cpumask_and(&mask, cpu_online_mask, &mask);
330 for (i = 0; i <= high; i++) {
331 if (cpumask_test_cpu(i, &mask)) {
332 ccall_info.processors_in[i] = 0;
333 ccall_info.processors_out[i] = 0;
334 sun4d_send_ipi(i, IRQ_CROSS_CALL);
335 }
336 }
337 }
338
339 {
340 register int i;
341
342 i = 0;
343 do {
344 if (!cpumask_test_cpu(i, &mask))
345 continue;
346 while (!ccall_info.processors_in[i])
347 barrier();
348 } while (++i <= high);
349
350 i = 0;
351 do {
352 if (!cpumask_test_cpu(i, &mask))
353 continue;
354 while (!ccall_info.processors_out[i])
355 barrier();
356 } while (++i <= high);
357 }
358
359 spin_unlock_irqrestore(&cross_call_lock, flags);
360 }
361}
362
363/* Running cross calls. */
364void smp4d_cross_call_irq(void)
365{
366 int i = hard_smp_processor_id();
367
368 ccall_info.processors_in[i] = 1;
369 ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
370 ccall_info.arg4, ccall_info.arg5);
371 ccall_info.processors_out[i] = 1;
372}
373
374void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
375{
376 struct pt_regs *old_regs;
377 int cpu = hard_smp_processor_id();
378 struct clock_event_device *ce;
379 static int cpu_tick[NR_CPUS];
380 static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
381
382 old_regs = set_irq_regs(regs);
383 bw_get_prof_limit(cpu);
384 bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
385
386 cpu_tick[cpu]++;
387 if (!(cpu_tick[cpu] & 15)) {
388 if (cpu_tick[cpu] == 0x60)
389 cpu_tick[cpu] = 0;
390 cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
391 show_leds(cpu);
392 }
393
394 ce = &per_cpu(sparc32_clockevent, cpu);
395
396 irq_enter();
397 ce->event_handler(ce);
398 irq_exit();
399
400 set_irq_regs(old_regs);
401}
402
403static const struct sparc32_ipi_ops sun4d_ipi_ops = {
404 .cross_call = sun4d_cross_call,
405 .resched = sun4d_ipi_resched,
406 .single = sun4d_ipi_single,
407 .mask_one = sun4d_ipi_mask_one,
408};
409
410void __init sun4d_init_smp(void)
411{
412 int i;
413
414 /* Patch ipi15 trap table */
415 t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
416
417 sparc32_ipi_ops = &sun4d_ipi_ops;
418
419 for (i = 0; i < NR_CPUS; i++) {
420 ccall_info.processors_in[i] = 1;
421 ccall_info.processors_out[i] = 1;
422 }
423}
1/* Sparc SS1000/SC2000 SMP support.
2 *
3 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
4 *
5 * Based on sun4m's smp.c, which is:
6 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 */
8
9#include <linux/interrupt.h>
10#include <linux/profile.h>
11#include <linux/delay.h>
12#include <linux/cpu.h>
13
14#include <asm/sbi.h>
15#include <asm/mmu.h>
16#include <asm/tlbflush.h>
17#include <asm/cacheflush.h>
18
19#include "kernel.h"
20#include "irq.h"
21
22#define IRQ_CROSS_CALL 15
23
24static volatile int smp_processors_ready;
25static int smp_highest_cpu;
26
27static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
28{
29 __asm__ __volatile__("swap [%1], %0\n\t" :
30 "=&r" (val), "=&r" (ptr) :
31 "0" (val), "1" (ptr));
32 return val;
33}
34
35static void smp4d_ipi_init(void);
36static void smp_setup_percpu_timer(void);
37
38static unsigned char cpu_leds[32];
39
40static inline void show_leds(int cpuid)
41{
42 cpuid &= 0x1e;
43 __asm__ __volatile__ ("stba %0, [%1] %2" : :
44 "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
45 "r" (ECSR_BASE(cpuid) | BB_LEDS),
46 "i" (ASI_M_CTL));
47}
48
49void __cpuinit smp4d_callin(void)
50{
51 int cpuid = hard_smp4d_processor_id();
52 unsigned long flags;
53
54 /* Show we are alive */
55 cpu_leds[cpuid] = 0x6;
56 show_leds(cpuid);
57
58 /* Enable level15 interrupt, disable level14 interrupt for now */
59 cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
60
61 local_flush_cache_all();
62 local_flush_tlb_all();
63
64 notify_cpu_starting(cpuid);
65 /*
66 * Unblock the master CPU _only_ when the scheduler state
67 * of all secondary CPUs will be up-to-date, so after
68 * the SMP initialization the master will be just allowed
69 * to call the scheduler code.
70 */
71 /* Get our local ticker going. */
72 smp_setup_percpu_timer();
73
74 calibrate_delay();
75 smp_store_cpu_info(cpuid);
76 local_flush_cache_all();
77 local_flush_tlb_all();
78
79 /* Allow master to continue. */
80 sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
81 local_flush_cache_all();
82 local_flush_tlb_all();
83
84 while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
85 barrier();
86
87 while (current_set[cpuid]->cpu != cpuid)
88 barrier();
89
90 /* Fix idle thread fields. */
91 __asm__ __volatile__("ld [%0], %%g6\n\t"
92 : : "r" (¤t_set[cpuid])
93 : "memory" /* paranoid */);
94
95 cpu_leds[cpuid] = 0x9;
96 show_leds(cpuid);
97
98 /* Attach to the address space of init_task. */
99 atomic_inc(&init_mm.mm_count);
100 current->active_mm = &init_mm;
101
102 local_flush_cache_all();
103 local_flush_tlb_all();
104
105 local_irq_enable(); /* We don't allow PIL 14 yet */
106
107 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
108 barrier();
109
110 spin_lock_irqsave(&sun4d_imsk_lock, flags);
111 cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
112 spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
113 set_cpu_online(cpuid, true);
114
115}
116
117/*
118 * Cycle through the processors asking the PROM to start each one.
119 */
120void __init smp4d_boot_cpus(void)
121{
122 smp4d_ipi_init();
123 if (boot_cpu_id)
124 current_set[0] = NULL;
125 smp_setup_percpu_timer();
126 local_flush_cache_all();
127}
128
129int __cpuinit smp4d_boot_one_cpu(int i)
130{
131 unsigned long *entry = &sun4d_cpu_startup;
132 struct task_struct *p;
133 int timeout;
134 int cpu_node;
135
136 cpu_find_by_instance(i, &cpu_node, NULL);
137 /* Cook up an idler for this guy. */
138 p = fork_idle(i);
139 current_set[i] = task_thread_info(p);
140
141 /*
142 * Initialize the contexts table
143 * Since the call to prom_startcpu() trashes the structure,
144 * we need to re-initialize it for each cpu
145 */
146 smp_penguin_ctable.which_io = 0;
147 smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
148 smp_penguin_ctable.reg_size = 0;
149
150 /* whirrr, whirrr, whirrrrrrrrr... */
151 printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
152 local_flush_cache_all();
153 prom_startcpu(cpu_node,
154 &smp_penguin_ctable, 0, (char *)entry);
155
156 printk(KERN_INFO "prom_startcpu returned :)\n");
157
158 /* wheee... it's going... */
159 for (timeout = 0; timeout < 10000; timeout++) {
160 if (cpu_callin_map[i])
161 break;
162 udelay(200);
163 }
164
165 if (!(cpu_callin_map[i])) {
166 printk(KERN_ERR "Processor %d is stuck.\n", i);
167 return -ENODEV;
168
169 }
170 local_flush_cache_all();
171 return 0;
172}
173
174void __init smp4d_smp_done(void)
175{
176 int i, first;
177 int *prev;
178
179 /* setup cpu list for irq rotation */
180 first = 0;
181 prev = &first;
182 for_each_online_cpu(i) {
183 *prev = i;
184 prev = &cpu_data(i).next;
185 }
186 *prev = first;
187 local_flush_cache_all();
188
189 /* Ok, they are spinning and ready to go. */
190 smp_processors_ready = 1;
191 sun4d_distribute_irqs();
192}
193
194/* Memory structure giving interrupt handler information about IPI generated */
195struct sun4d_ipi_work {
196 int single;
197 int msk;
198 int resched;
199};
200
201static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
202
203/* Initialize IPIs on the SUN4D SMP machine */
204static void __init smp4d_ipi_init(void)
205{
206 int cpu;
207 struct sun4d_ipi_work *work;
208
209 printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
210
211 for_each_possible_cpu(cpu) {
212 work = &per_cpu(sun4d_ipi_work, cpu);
213 work->single = work->msk = work->resched = 0;
214 }
215}
216
217void sun4d_ipi_interrupt(void)
218{
219 struct sun4d_ipi_work *work = &__get_cpu_var(sun4d_ipi_work);
220
221 if (work->single) {
222 work->single = 0;
223 smp_call_function_single_interrupt();
224 }
225 if (work->msk) {
226 work->msk = 0;
227 smp_call_function_interrupt();
228 }
229 if (work->resched) {
230 work->resched = 0;
231 smp_resched_interrupt();
232 }
233}
234
235static void smp4d_ipi_single(int cpu)
236{
237 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
238
239 /* Mark work */
240 work->single = 1;
241
242 /* Generate IRQ on the CPU */
243 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
244}
245
246static void smp4d_ipi_mask_one(int cpu)
247{
248 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
249
250 /* Mark work */
251 work->msk = 1;
252
253 /* Generate IRQ on the CPU */
254 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
255}
256
257static void smp4d_ipi_resched(int cpu)
258{
259 struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
260
261 /* Mark work */
262 work->resched = 1;
263
264 /* Generate IRQ on the CPU (any IRQ will cause resched) */
265 sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
266}
267
268static struct smp_funcall {
269 smpfunc_t func;
270 unsigned long arg1;
271 unsigned long arg2;
272 unsigned long arg3;
273 unsigned long arg4;
274 unsigned long arg5;
275 unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
276 unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
277} ccall_info __attribute__((aligned(8)));
278
279static DEFINE_SPINLOCK(cross_call_lock);
280
281/* Cross calls must be serialized, at least currently. */
282static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
283 unsigned long arg2, unsigned long arg3,
284 unsigned long arg4)
285{
286 if (smp_processors_ready) {
287 register int high = smp_highest_cpu;
288 unsigned long flags;
289
290 spin_lock_irqsave(&cross_call_lock, flags);
291
292 {
293 /*
294 * If you make changes here, make sure
295 * gcc generates proper code...
296 */
297 register smpfunc_t f asm("i0") = func;
298 register unsigned long a1 asm("i1") = arg1;
299 register unsigned long a2 asm("i2") = arg2;
300 register unsigned long a3 asm("i3") = arg3;
301 register unsigned long a4 asm("i4") = arg4;
302 register unsigned long a5 asm("i5") = 0;
303
304 __asm__ __volatile__(
305 "std %0, [%6]\n\t"
306 "std %2, [%6 + 8]\n\t"
307 "std %4, [%6 + 16]\n\t" : :
308 "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
309 "r" (&ccall_info.func));
310 }
311
312 /* Init receive/complete mapping, plus fire the IPI's off. */
313 {
314 register int i;
315
316 cpumask_clear_cpu(smp_processor_id(), &mask);
317 cpumask_and(&mask, cpu_online_mask, &mask);
318 for (i = 0; i <= high; i++) {
319 if (cpumask_test_cpu(i, &mask)) {
320 ccall_info.processors_in[i] = 0;
321 ccall_info.processors_out[i] = 0;
322 sun4d_send_ipi(i, IRQ_CROSS_CALL);
323 }
324 }
325 }
326
327 {
328 register int i;
329
330 i = 0;
331 do {
332 if (!cpumask_test_cpu(i, &mask))
333 continue;
334 while (!ccall_info.processors_in[i])
335 barrier();
336 } while (++i <= high);
337
338 i = 0;
339 do {
340 if (!cpumask_test_cpu(i, &mask))
341 continue;
342 while (!ccall_info.processors_out[i])
343 barrier();
344 } while (++i <= high);
345 }
346
347 spin_unlock_irqrestore(&cross_call_lock, flags);
348 }
349}
350
351/* Running cross calls. */
352void smp4d_cross_call_irq(void)
353{
354 int i = hard_smp4d_processor_id();
355
356 ccall_info.processors_in[i] = 1;
357 ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
358 ccall_info.arg4, ccall_info.arg5);
359 ccall_info.processors_out[i] = 1;
360}
361
362void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
363{
364 struct pt_regs *old_regs;
365 int cpu = hard_smp4d_processor_id();
366 static int cpu_tick[NR_CPUS];
367 static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
368
369 old_regs = set_irq_regs(regs);
370 bw_get_prof_limit(cpu);
371 bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
372
373 cpu_tick[cpu]++;
374 if (!(cpu_tick[cpu] & 15)) {
375 if (cpu_tick[cpu] == 0x60)
376 cpu_tick[cpu] = 0;
377 cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
378 show_leds(cpu);
379 }
380
381 profile_tick(CPU_PROFILING);
382
383 if (!--prof_counter(cpu)) {
384 int user = user_mode(regs);
385
386 irq_enter();
387 update_process_times(user);
388 irq_exit();
389
390 prof_counter(cpu) = prof_multiplier(cpu);
391 }
392 set_irq_regs(old_regs);
393}
394
395static void __cpuinit smp_setup_percpu_timer(void)
396{
397 int cpu = hard_smp4d_processor_id();
398
399 prof_counter(cpu) = prof_multiplier(cpu) = 1;
400 load_profile_irq(cpu, lvl14_resolution);
401}
402
403void __init smp4d_blackbox_id(unsigned *addr)
404{
405 int rd = *addr & 0x3e000000;
406
407 addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
408 addr[1] = 0x01000000; /* nop */
409 addr[2] = 0x01000000; /* nop */
410}
411
412void __init smp4d_blackbox_current(unsigned *addr)
413{
414 int rd = *addr & 0x3e000000;
415
416 addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
417 addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */
418 addr[4] = 0x01000000; /* nop */
419}
420
421void __init sun4d_init_smp(void)
422{
423 int i;
424
425 /* Patch ipi15 trap table */
426 t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
427
428 /* And set btfixup... */
429 BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
430 BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
431 BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
432 BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
433 BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
434 BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
435 BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
436
437 for (i = 0; i < NR_CPUS; i++) {
438 ccall_info.processors_in[i] = 1;
439 ccall_info.processors_out[i] = 1;
440 }
441}