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1/*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19#undef DEBUG
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/of.h>
25#include <linux/bootmem.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28
29#include <asm/io.h>
30#include <asm/pci-bridge.h>
31#include <asm/machdep.h>
32#include <asm/dcr.h>
33#include <asm/dcr-regs.h>
34#include <mm/mmu_decl.h>
35
36#include "ppc4xx_pci.h"
37
38static int dma_offset_set;
39
40#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
41#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42
43#define RES_TO_U32_LOW(val) \
44 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
45#define RES_TO_U32_HIGH(val) \
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
47
48static inline int ppc440spe_revA(void)
49{
50 /* Catch both 440SPe variants, with and without RAID6 support */
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
52 return 1;
53 else
54 return 0;
55}
56
57static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
58{
59 struct pci_controller *hose;
60 int i;
61
62 if (dev->devfn != 0 || dev->bus->self != NULL)
63 return;
64
65 hose = pci_bus_to_host(dev->bus);
66 if (hose == NULL)
67 return;
68
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
72 return;
73
74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
77 }
78
79 /* Hide the PCI host BARs from the kernel as their content doesn't
80 * fit well in the resource management
81 */
82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
83 dev->resource[i].start = dev->resource[i].end = 0;
84 dev->resource[i].flags = 0;
85 }
86
87 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
88 pci_name(dev));
89}
90DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
91
92static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
93 void __iomem *reg,
94 struct resource *res)
95{
96 u64 size;
97 const u32 *ranges;
98 int rlen;
99 int pna = of_n_addr_cells(hose->dn);
100 int np = pna + 5;
101
102 /* Default */
103 res->start = 0;
104 size = 0x80000000;
105 res->end = size - 1;
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107
108 /* Get dma-ranges property */
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
110 if (ranges == NULL)
111 goto out;
112
113 /* Walk it */
114 while ((rlen -= np * 4) >= 0) {
115 u32 pci_space = ranges[0];
116 u64 pci_addr = of_read_number(ranges + 1, 2);
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
118 size = of_read_number(ranges + pna + 3, 2);
119 ranges += np;
120 if (cpu_addr == OF_BAD_ADDR || size == 0)
121 continue;
122
123 /* We only care about memory */
124 if ((pci_space & 0x03000000) != 0x02000000)
125 continue;
126
127 /* We currently only support memory at 0, and pci_addr
128 * within 32 bits space
129 */
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
131 printk(KERN_WARNING "%s: Ignored unsupported dma range"
132 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 hose->dn->full_name,
134 pci_addr, pci_addr + size - 1, cpu_addr);
135 continue;
136 }
137
138 /* Check if not prefetchable */
139 if (!(pci_space & 0x40000000))
140 res->flags &= ~IORESOURCE_PREFETCH;
141
142
143 /* Use that */
144 res->start = pci_addr;
145 /* Beware of 32 bits resources */
146 if (sizeof(resource_size_t) == sizeof(u32) &&
147 (pci_addr + size) > 0x100000000ull)
148 res->end = 0xffffffff;
149 else
150 res->end = res->start + size - 1;
151 break;
152 }
153
154 /* We only support one global DMA offset */
155 if (dma_offset_set && pci_dram_offset != res->start) {
156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
157 hose->dn->full_name);
158 return -ENXIO;
159 }
160
161 /* Check that we can fit all of memory as we don't support
162 * DMA bounce buffers
163 */
164 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small "
166 "(size=%llx total_memory=%llx)\n",
167 hose->dn->full_name, size, (u64)total_memory);
168 return -ENXIO;
169 }
170
171 /* Check we are a power of 2 size and that base is a multiple of size*/
172 if ((size & (size - 1)) != 0 ||
173 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name);
176 return -ENXIO;
177 }
178
179 /* Check that we are fully contained within 32 bits space */
180 if (res->end > 0xffffffff) {
181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
182 hose->dn->full_name);
183 return -ENXIO;
184 }
185 out:
186 dma_offset_set = 1;
187 pci_dram_offset = res->start;
188 hose->dma_window_base_cur = res->start;
189 hose->dma_window_size = resource_size(res);
190
191 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
192 pci_dram_offset);
193 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
194 (unsigned long long)hose->dma_window_base_cur);
195 printk(KERN_INFO "DMA window size 0x%016llx\n",
196 (unsigned long long)hose->dma_window_size);
197 return 0;
198}
199
200/*
201 * 4xx PCI 2.x part
202 */
203
204static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
205 void __iomem *reg,
206 u64 plb_addr,
207 u64 pci_addr,
208 u64 size,
209 unsigned int flags,
210 int index)
211{
212 u32 ma, pcila, pciha;
213
214 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
215 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
216 * address are actually hard wired to a value that appears to depend
217 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
218 *
219 * The trick here is we just crop those top bits and ignore them when
220 * programming the chip. That means the device-tree has to be right
221 * for the specific part used (we don't print a warning if it's wrong
222 * but on the other hand, you'll crash quickly enough), but at least
223 * this code should work whatever the hard coded value is
224 */
225 plb_addr &= 0xffffffffull;
226
227 /* Note: Due to the above hack, the test below doesn't actually test
228 * if you address is above 4G, but it tests that address and
229 * (address + size) are both contained in the same 4G
230 */
231 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
232 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
233 printk(KERN_WARNING "%s: Resource out of range\n",
234 hose->dn->full_name);
235 return -1;
236 }
237 ma = (0xffffffffu << ilog2(size)) | 1;
238 if (flags & IORESOURCE_PREFETCH)
239 ma |= 2;
240
241 pciha = RES_TO_U32_HIGH(pci_addr);
242 pcila = RES_TO_U32_LOW(pci_addr);
243
244 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
245 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
246 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
247 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
248
249 return 0;
250}
251
252static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
253 void __iomem *reg)
254{
255 int i, j, found_isa_hole = 0;
256
257 /* Setup outbound memory windows */
258 for (i = j = 0; i < 3; i++) {
259 struct resource *res = &hose->mem_resources[i];
260
261 /* we only care about memory windows */
262 if (!(res->flags & IORESOURCE_MEM))
263 continue;
264 if (j > 2) {
265 printk(KERN_WARNING "%s: Too many ranges\n",
266 hose->dn->full_name);
267 break;
268 }
269
270 /* Configure the resource */
271 if (ppc4xx_setup_one_pci_PMM(hose, reg,
272 res->start,
273 res->start - hose->pci_mem_offset,
274 resource_size(res),
275 res->flags,
276 j) == 0) {
277 j++;
278
279 /* If the resource PCI address is 0 then we have our
280 * ISA memory hole
281 */
282 if (res->start == hose->pci_mem_offset)
283 found_isa_hole = 1;
284 }
285 }
286
287 /* Handle ISA memory hole if not already covered */
288 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
289 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
290 hose->isa_mem_size, 0, j) == 0)
291 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
292 hose->dn->full_name);
293}
294
295static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
296 void __iomem *reg,
297 const struct resource *res)
298{
299 resource_size_t size = resource_size(res);
300 u32 sa;
301
302 /* Calculate window size */
303 sa = (0xffffffffu << ilog2(size)) | 1;
304 sa |= 0x1;
305
306 /* RAM is always at 0 local for now */
307 writel(0, reg + PCIL0_PTM1LA);
308 writel(sa, reg + PCIL0_PTM1MS);
309
310 /* Map on PCI side */
311 early_write_config_dword(hose, hose->first_busno, 0,
312 PCI_BASE_ADDRESS_1, res->start);
313 early_write_config_dword(hose, hose->first_busno, 0,
314 PCI_BASE_ADDRESS_2, 0x00000000);
315 early_write_config_word(hose, hose->first_busno, 0,
316 PCI_COMMAND, 0x0006);
317}
318
319static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
320{
321 /* NYI */
322 struct resource rsrc_cfg;
323 struct resource rsrc_reg;
324 struct resource dma_window;
325 struct pci_controller *hose = NULL;
326 void __iomem *reg = NULL;
327 const int *bus_range;
328 int primary = 0;
329
330 /* Check if device is enabled */
331 if (!of_device_is_available(np)) {
332 printk(KERN_INFO "%s: Port disabled via device-tree\n",
333 np->full_name);
334 return;
335 }
336
337 /* Fetch config space registers address */
338 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
339 printk(KERN_ERR "%s: Can't get PCI config register base !",
340 np->full_name);
341 return;
342 }
343 /* Fetch host bridge internal registers address */
344 if (of_address_to_resource(np, 3, &rsrc_reg)) {
345 printk(KERN_ERR "%s: Can't get PCI internal register base !",
346 np->full_name);
347 return;
348 }
349
350 /* Check if primary bridge */
351 if (of_get_property(np, "primary", NULL))
352 primary = 1;
353
354 /* Get bus range if any */
355 bus_range = of_get_property(np, "bus-range", NULL);
356
357 /* Map registers */
358 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
359 if (reg == NULL) {
360 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
361 goto fail;
362 }
363
364 /* Allocate the host controller data structure */
365 hose = pcibios_alloc_controller(np);
366 if (!hose)
367 goto fail;
368
369 hose->first_busno = bus_range ? bus_range[0] : 0x0;
370 hose->last_busno = bus_range ? bus_range[1] : 0xff;
371
372 /* Setup config space */
373 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
374
375 /* Disable all windows */
376 writel(0, reg + PCIL0_PMM0MA);
377 writel(0, reg + PCIL0_PMM1MA);
378 writel(0, reg + PCIL0_PMM2MA);
379 writel(0, reg + PCIL0_PTM1MS);
380 writel(0, reg + PCIL0_PTM2MS);
381
382 /* Parse outbound mapping resources */
383 pci_process_bridge_OF_ranges(hose, np, primary);
384
385 /* Parse inbound mapping resources */
386 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
387 goto fail;
388
389 /* Configure outbound ranges POMs */
390 ppc4xx_configure_pci_PMMs(hose, reg);
391
392 /* Configure inbound ranges PIMs */
393 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
394
395 /* We don't need the registers anymore */
396 iounmap(reg);
397 return;
398
399 fail:
400 if (hose)
401 pcibios_free_controller(hose);
402 if (reg)
403 iounmap(reg);
404}
405
406/*
407 * 4xx PCI-X part
408 */
409
410static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
411 void __iomem *reg,
412 u64 plb_addr,
413 u64 pci_addr,
414 u64 size,
415 unsigned int flags,
416 int index)
417{
418 u32 lah, lal, pciah, pcial, sa;
419
420 if (!is_power_of_2(size) || size < 0x1000 ||
421 (plb_addr & (size - 1)) != 0) {
422 printk(KERN_WARNING "%s: Resource out of range\n",
423 hose->dn->full_name);
424 return -1;
425 }
426
427 /* Calculate register values */
428 lah = RES_TO_U32_HIGH(plb_addr);
429 lal = RES_TO_U32_LOW(plb_addr);
430 pciah = RES_TO_U32_HIGH(pci_addr);
431 pcial = RES_TO_U32_LOW(pci_addr);
432 sa = (0xffffffffu << ilog2(size)) | 0x1;
433
434 /* Program register values */
435 if (index == 0) {
436 writel(lah, reg + PCIX0_POM0LAH);
437 writel(lal, reg + PCIX0_POM0LAL);
438 writel(pciah, reg + PCIX0_POM0PCIAH);
439 writel(pcial, reg + PCIX0_POM0PCIAL);
440 writel(sa, reg + PCIX0_POM0SA);
441 } else {
442 writel(lah, reg + PCIX0_POM1LAH);
443 writel(lal, reg + PCIX0_POM1LAL);
444 writel(pciah, reg + PCIX0_POM1PCIAH);
445 writel(pcial, reg + PCIX0_POM1PCIAL);
446 writel(sa, reg + PCIX0_POM1SA);
447 }
448
449 return 0;
450}
451
452static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
453 void __iomem *reg)
454{
455 int i, j, found_isa_hole = 0;
456
457 /* Setup outbound memory windows */
458 for (i = j = 0; i < 3; i++) {
459 struct resource *res = &hose->mem_resources[i];
460
461 /* we only care about memory windows */
462 if (!(res->flags & IORESOURCE_MEM))
463 continue;
464 if (j > 1) {
465 printk(KERN_WARNING "%s: Too many ranges\n",
466 hose->dn->full_name);
467 break;
468 }
469
470 /* Configure the resource */
471 if (ppc4xx_setup_one_pcix_POM(hose, reg,
472 res->start,
473 res->start - hose->pci_mem_offset,
474 resource_size(res),
475 res->flags,
476 j) == 0) {
477 j++;
478
479 /* If the resource PCI address is 0 then we have our
480 * ISA memory hole
481 */
482 if (res->start == hose->pci_mem_offset)
483 found_isa_hole = 1;
484 }
485 }
486
487 /* Handle ISA memory hole if not already covered */
488 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
489 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
490 hose->isa_mem_size, 0, j) == 0)
491 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
492 hose->dn->full_name);
493}
494
495static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
496 void __iomem *reg,
497 const struct resource *res,
498 int big_pim,
499 int enable_msi_hole)
500{
501 resource_size_t size = resource_size(res);
502 u32 sa;
503
504 /* RAM is always at 0 */
505 writel(0x00000000, reg + PCIX0_PIM0LAH);
506 writel(0x00000000, reg + PCIX0_PIM0LAL);
507
508 /* Calculate window size */
509 sa = (0xffffffffu << ilog2(size)) | 1;
510 sa |= 0x1;
511 if (res->flags & IORESOURCE_PREFETCH)
512 sa |= 0x2;
513 if (enable_msi_hole)
514 sa |= 0x4;
515 writel(sa, reg + PCIX0_PIM0SA);
516 if (big_pim)
517 writel(0xffffffff, reg + PCIX0_PIM0SAH);
518
519 /* Map on PCI side */
520 writel(0x00000000, reg + PCIX0_BAR0H);
521 writel(res->start, reg + PCIX0_BAR0L);
522 writew(0x0006, reg + PCIX0_COMMAND);
523}
524
525static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
526{
527 struct resource rsrc_cfg;
528 struct resource rsrc_reg;
529 struct resource dma_window;
530 struct pci_controller *hose = NULL;
531 void __iomem *reg = NULL;
532 const int *bus_range;
533 int big_pim = 0, msi = 0, primary = 0;
534
535 /* Fetch config space registers address */
536 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
537 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
538 np->full_name);
539 return;
540 }
541 /* Fetch host bridge internal registers address */
542 if (of_address_to_resource(np, 3, &rsrc_reg)) {
543 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
544 np->full_name);
545 return;
546 }
547
548 /* Check if it supports large PIMs (440GX) */
549 if (of_get_property(np, "large-inbound-windows", NULL))
550 big_pim = 1;
551
552 /* Check if we should enable MSIs inbound hole */
553 if (of_get_property(np, "enable-msi-hole", NULL))
554 msi = 1;
555
556 /* Check if primary bridge */
557 if (of_get_property(np, "primary", NULL))
558 primary = 1;
559
560 /* Get bus range if any */
561 bus_range = of_get_property(np, "bus-range", NULL);
562
563 /* Map registers */
564 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
565 if (reg == NULL) {
566 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
567 goto fail;
568 }
569
570 /* Allocate the host controller data structure */
571 hose = pcibios_alloc_controller(np);
572 if (!hose)
573 goto fail;
574
575 hose->first_busno = bus_range ? bus_range[0] : 0x0;
576 hose->last_busno = bus_range ? bus_range[1] : 0xff;
577
578 /* Setup config space */
579 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
580 PPC_INDIRECT_TYPE_SET_CFG_TYPE);
581
582 /* Disable all windows */
583 writel(0, reg + PCIX0_POM0SA);
584 writel(0, reg + PCIX0_POM1SA);
585 writel(0, reg + PCIX0_POM2SA);
586 writel(0, reg + PCIX0_PIM0SA);
587 writel(0, reg + PCIX0_PIM1SA);
588 writel(0, reg + PCIX0_PIM2SA);
589 if (big_pim) {
590 writel(0, reg + PCIX0_PIM0SAH);
591 writel(0, reg + PCIX0_PIM2SAH);
592 }
593
594 /* Parse outbound mapping resources */
595 pci_process_bridge_OF_ranges(hose, np, primary);
596
597 /* Parse inbound mapping resources */
598 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
599 goto fail;
600
601 /* Configure outbound ranges POMs */
602 ppc4xx_configure_pcix_POMs(hose, reg);
603
604 /* Configure inbound ranges PIMs */
605 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
606
607 /* We don't need the registers anymore */
608 iounmap(reg);
609 return;
610
611 fail:
612 if (hose)
613 pcibios_free_controller(hose);
614 if (reg)
615 iounmap(reg);
616}
617
618#ifdef CONFIG_PPC4xx_PCI_EXPRESS
619
620/*
621 * 4xx PCI-Express part
622 *
623 * We support 3 parts currently based on the compatible property:
624 *
625 * ibm,plb-pciex-440spe
626 * ibm,plb-pciex-405ex
627 * ibm,plb-pciex-460ex
628 *
629 * Anything else will be rejected for now as they are all subtly
630 * different unfortunately.
631 *
632 */
633
634#define MAX_PCIE_BUS_MAPPED 0x40
635
636struct ppc4xx_pciex_port
637{
638 struct pci_controller *hose;
639 struct device_node *node;
640 unsigned int index;
641 int endpoint;
642 int link;
643 int has_ibpre;
644 unsigned int sdr_base;
645 dcr_host_t dcrs;
646 struct resource cfg_space;
647 struct resource utl_regs;
648 void __iomem *utl_base;
649};
650
651static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
652static unsigned int ppc4xx_pciex_port_count;
653
654struct ppc4xx_pciex_hwops
655{
656 bool want_sdr;
657 int (*core_init)(struct device_node *np);
658 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
659 int (*setup_utl)(struct ppc4xx_pciex_port *port);
660 void (*check_link)(struct ppc4xx_pciex_port *port);
661};
662
663static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
664
665static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
666 unsigned int sdr_offset,
667 unsigned int mask,
668 unsigned int value,
669 int timeout_ms)
670{
671 u32 val;
672
673 while(timeout_ms--) {
674 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
675 if ((val & mask) == value) {
676 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
677 port->index, sdr_offset, timeout_ms, val);
678 return 0;
679 }
680 msleep(1);
681 }
682 return -1;
683}
684
685static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
686{
687 /* Wait for reset to complete */
688 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
689 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
690 port->index);
691 return -1;
692 }
693 return 0;
694}
695
696
697static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
698{
699 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
700
701 /* Check for card presence detect if supported, if not, just wait for
702 * link unconditionally.
703 *
704 * note that we don't fail if there is no link, we just filter out
705 * config space accesses. That way, it will be easier to implement
706 * hotplug later on.
707 */
708 if (!port->has_ibpre ||
709 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
710 1 << 28, 1 << 28, 100)) {
711 printk(KERN_INFO
712 "PCIE%d: Device detected, waiting for link...\n",
713 port->index);
714 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
715 0x1000, 0x1000, 2000))
716 printk(KERN_WARNING
717 "PCIE%d: Link up failed\n", port->index);
718 else {
719 printk(KERN_INFO
720 "PCIE%d: link is up !\n", port->index);
721 port->link = 1;
722 }
723 } else
724 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
725}
726
727#ifdef CONFIG_44x
728
729/* Check various reset bits of the 440SPe PCIe core */
730static int __init ppc440spe_pciex_check_reset(struct device_node *np)
731{
732 u32 valPE0, valPE1, valPE2;
733 int err = 0;
734
735 /* SDR0_PEGPLLLCT1 reset */
736 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
737 /*
738 * the PCIe core was probably already initialised
739 * by firmware - let's re-reset RCSSET regs
740 *
741 * -- Shouldn't we also re-reset the whole thing ? -- BenH
742 */
743 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
744 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
745 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
746 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
747 }
748
749 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
750 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
751 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
752
753 /* SDR0_PExRCSSET rstgu */
754 if (!(valPE0 & 0x01000000) ||
755 !(valPE1 & 0x01000000) ||
756 !(valPE2 & 0x01000000)) {
757 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
758 err = -1;
759 }
760
761 /* SDR0_PExRCSSET rstdl */
762 if (!(valPE0 & 0x00010000) ||
763 !(valPE1 & 0x00010000) ||
764 !(valPE2 & 0x00010000)) {
765 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
766 err = -1;
767 }
768
769 /* SDR0_PExRCSSET rstpyn */
770 if ((valPE0 & 0x00001000) ||
771 (valPE1 & 0x00001000) ||
772 (valPE2 & 0x00001000)) {
773 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
774 err = -1;
775 }
776
777 /* SDR0_PExRCSSET hldplb */
778 if ((valPE0 & 0x10000000) ||
779 (valPE1 & 0x10000000) ||
780 (valPE2 & 0x10000000)) {
781 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
782 err = -1;
783 }
784
785 /* SDR0_PExRCSSET rdy */
786 if ((valPE0 & 0x00100000) ||
787 (valPE1 & 0x00100000) ||
788 (valPE2 & 0x00100000)) {
789 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
790 err = -1;
791 }
792
793 /* SDR0_PExRCSSET shutdown */
794 if ((valPE0 & 0x00000100) ||
795 (valPE1 & 0x00000100) ||
796 (valPE2 & 0x00000100)) {
797 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
798 err = -1;
799 }
800
801 return err;
802}
803
804/* Global PCIe core initializations for 440SPe core */
805static int __init ppc440spe_pciex_core_init(struct device_node *np)
806{
807 int time_out = 20;
808
809 /* Set PLL clock receiver to LVPECL */
810 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
811
812 /* Shouldn't we do all the calibration stuff etc... here ? */
813 if (ppc440spe_pciex_check_reset(np))
814 return -ENXIO;
815
816 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
817 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
818 "failed (0x%08x)\n",
819 mfdcri(SDR0, PESDR0_PLLLCT2));
820 return -1;
821 }
822
823 /* De-assert reset of PCIe PLL, wait for lock */
824 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
825 udelay(3);
826
827 while (time_out) {
828 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
829 time_out--;
830 udelay(1);
831 } else
832 break;
833 }
834 if (!time_out) {
835 printk(KERN_INFO "PCIE: VCO output not locked\n");
836 return -1;
837 }
838
839 pr_debug("PCIE initialization OK\n");
840
841 return 3;
842}
843
844static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
845{
846 u32 val = 1 << 24;
847
848 if (port->endpoint)
849 val = PTYPE_LEGACY_ENDPOINT << 20;
850 else
851 val = PTYPE_ROOT_PORT << 20;
852
853 if (port->index == 0)
854 val |= LNKW_X8 << 12;
855 else
856 val |= LNKW_X4 << 12;
857
858 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
859 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
860 if (ppc440spe_revA())
861 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
865 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
866 if (port->index == 0) {
867 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
868 0x35000000);
869 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
870 0x35000000);
871 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
872 0x35000000);
873 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
874 0x35000000);
875 }
876 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
877 (1 << 24) | (1 << 16), 1 << 12);
878
879 return ppc4xx_pciex_port_reset_sdr(port);
880}
881
882static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
883{
884 return ppc440spe_pciex_init_port_hw(port);
885}
886
887static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
888{
889 int rc = ppc440spe_pciex_init_port_hw(port);
890
891 port->has_ibpre = 1;
892
893 return rc;
894}
895
896static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
897{
898 /* XXX Check what that value means... I hate magic */
899 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
900
901 /*
902 * Set buffer allocations and then assert VRB and TXE.
903 */
904 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
905 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
906 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
907 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
908 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
909 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
910 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
911 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
912
913 return 0;
914}
915
916static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
917{
918 /* Report CRS to the operating system */
919 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
920
921 return 0;
922}
923
924static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
925{
926 .want_sdr = true,
927 .core_init = ppc440spe_pciex_core_init,
928 .port_init_hw = ppc440speA_pciex_init_port_hw,
929 .setup_utl = ppc440speA_pciex_init_utl,
930 .check_link = ppc4xx_pciex_check_link_sdr,
931};
932
933static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
934{
935 .want_sdr = true,
936 .core_init = ppc440spe_pciex_core_init,
937 .port_init_hw = ppc440speB_pciex_init_port_hw,
938 .setup_utl = ppc440speB_pciex_init_utl,
939 .check_link = ppc4xx_pciex_check_link_sdr,
940};
941
942static int __init ppc460ex_pciex_core_init(struct device_node *np)
943{
944 /* Nothing to do, return 2 ports */
945 return 2;
946}
947
948static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
949{
950 u32 val;
951 u32 utlset1;
952
953 if (port->endpoint)
954 val = PTYPE_LEGACY_ENDPOINT << 20;
955 else
956 val = PTYPE_ROOT_PORT << 20;
957
958 if (port->index == 0) {
959 val |= LNKW_X1 << 12;
960 utlset1 = 0x20000000;
961 } else {
962 val |= LNKW_X4 << 12;
963 utlset1 = 0x20101101;
964 }
965
966 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
968 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
969
970 switch (port->index) {
971 case 0:
972 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
973 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
974 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
975
976 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
977 break;
978
979 case 1:
980 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
981 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
982 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
983 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
984 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
985 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
986 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
987 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
988 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
989 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
990 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
991 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
992
993 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
994 break;
995 }
996
997 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
998 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
999 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1000
1001 /* Poll for PHY reset */
1002 /* XXX FIXME add timeout */
1003 switch (port->index) {
1004 case 0:
1005 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
1006 udelay(10);
1007 break;
1008 case 1:
1009 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
1010 udelay(10);
1011 break;
1012 }
1013
1014 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1015 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1016 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1017 PESDRx_RCSSET_RSTPYN);
1018
1019 port->has_ibpre = 1;
1020
1021 return ppc4xx_pciex_port_reset_sdr(port);
1022}
1023
1024static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1025{
1026 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1027
1028 /*
1029 * Set buffer allocations and then assert VRB and TXE.
1030 */
1031 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1032 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1033 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1034 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1035 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1036 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1037 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1038 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1039 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1040
1041 return 0;
1042}
1043
1044static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1045{
1046 .want_sdr = true,
1047 .core_init = ppc460ex_pciex_core_init,
1048 .port_init_hw = ppc460ex_pciex_init_port_hw,
1049 .setup_utl = ppc460ex_pciex_init_utl,
1050 .check_link = ppc4xx_pciex_check_link_sdr,
1051};
1052
1053static int __init apm821xx_pciex_core_init(struct device_node *np)
1054{
1055 /* Return the number of pcie port */
1056 return 1;
1057}
1058
1059static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1060{
1061 u32 val;
1062
1063 /*
1064 * Do a software reset on PCIe ports.
1065 * This code is to fix the issue that pci drivers doesn't re-assign
1066 * bus number for PCIE devices after Uboot
1067 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
1068 * PT quad port, SAS LSI 1064E)
1069 */
1070
1071 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
1072 mdelay(10);
1073
1074 if (port->endpoint)
1075 val = PTYPE_LEGACY_ENDPOINT << 20;
1076 else
1077 val = PTYPE_ROOT_PORT << 20;
1078
1079 val |= LNKW_X1 << 12;
1080
1081 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
1082 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1083 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1084
1085 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
1086 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
1087 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
1088
1089 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
1090 mdelay(50);
1091 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
1092
1093 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1094 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1095 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1096
1097 /* Poll for PHY reset */
1098 val = PESDR0_460EX_RSTSTA - port->sdr_base;
1099 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
1100 printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
1101 return -EBUSY;
1102 } else {
1103 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1104 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1105 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1106 PESDRx_RCSSET_RSTPYN);
1107
1108 port->has_ibpre = 1;
1109 return 0;
1110 }
1111}
1112
1113static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
1114 .want_sdr = true,
1115 .core_init = apm821xx_pciex_core_init,
1116 .port_init_hw = apm821xx_pciex_init_port_hw,
1117 .setup_utl = ppc460ex_pciex_init_utl,
1118 .check_link = ppc4xx_pciex_check_link_sdr,
1119};
1120
1121static int __init ppc460sx_pciex_core_init(struct device_node *np)
1122{
1123 /* HSS drive amplitude */
1124 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
1125 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
1126 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
1127 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
1128 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
1129 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
1130 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
1131 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
1132
1133 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
1134 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
1135 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
1136 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
1137
1138 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
1139 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
1140 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
1141 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
1142
1143 /* HSS TX pre-emphasis */
1144 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1145 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1146 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1147 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1148 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1149 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1150 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1151 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1152
1153 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1154 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1155 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1156 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1157
1158 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1159 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1160 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1161 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1162
1163 /* HSS TX calibration control */
1164 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1165 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1166 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1167
1168 /* HSS TX slew control */
1169 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1170 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1171 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1172
1173 /* Set HSS PRBS enabled */
1174 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
1175 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
1176
1177 udelay(100);
1178
1179 /* De-assert PLLRESET */
1180 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1181
1182 /* Reset DL, UTL, GPL before configuration */
1183 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1184 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1185 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1186 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1187 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1188 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1189
1190 udelay(100);
1191
1192 /*
1193 * If bifurcation is not enabled, u-boot would have disabled the
1194 * third PCIe port
1195 */
1196 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1197 0x00000001)) {
1198 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1199 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1200 return 3;
1201 }
1202
1203 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1204 return 2;
1205}
1206
1207static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1208{
1209
1210 if (port->endpoint)
1211 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1212 0x01000000, 0);
1213 else
1214 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1215 0, 0x01000000);
1216
1217 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1218 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1219 PESDRx_RCSSET_RSTPYN);
1220
1221 port->has_ibpre = 1;
1222
1223 return ppc4xx_pciex_port_reset_sdr(port);
1224}
1225
1226static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1227{
1228 /* Max 128 Bytes */
1229 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1230 /* Assert VRB and TXE - per datasheet turn off addr validation */
1231 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
1232 return 0;
1233}
1234
1235static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1236{
1237 void __iomem *mbase;
1238 int attempt = 50;
1239
1240 port->link = 0;
1241
1242 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1243 if (mbase == NULL) {
1244 printk(KERN_ERR "%s: Can't map internal config space !",
1245 port->node->full_name);
1246 goto done;
1247 }
1248
1249 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
1250 & PECFG_460SX_DLLSTA_LINKUP))) {
1251 attempt--;
1252 mdelay(10);
1253 }
1254 if (attempt)
1255 port->link = 1;
1256done:
1257 iounmap(mbase);
1258
1259}
1260
1261static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1262 .want_sdr = true,
1263 .core_init = ppc460sx_pciex_core_init,
1264 .port_init_hw = ppc460sx_pciex_init_port_hw,
1265 .setup_utl = ppc460sx_pciex_init_utl,
1266 .check_link = ppc460sx_pciex_check_link,
1267};
1268
1269#endif /* CONFIG_44x */
1270
1271#ifdef CONFIG_40x
1272
1273static int __init ppc405ex_pciex_core_init(struct device_node *np)
1274{
1275 /* Nothing to do, return 2 ports */
1276 return 2;
1277}
1278
1279static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1280{
1281 /* Assert the PE0_PHY reset */
1282 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1283 msleep(1);
1284
1285 /* deassert the PE0_hotreset */
1286 if (port->endpoint)
1287 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1288 else
1289 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1290
1291 /* poll for phy !reset */
1292 /* XXX FIXME add timeout */
1293 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1294 ;
1295
1296 /* deassert the PE0_gpl_utl_reset */
1297 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1298}
1299
1300static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1301{
1302 u32 val;
1303
1304 if (port->endpoint)
1305 val = PTYPE_LEGACY_ENDPOINT;
1306 else
1307 val = PTYPE_ROOT_PORT;
1308
1309 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1310 1 << 24 | val << 20 | LNKW_X1 << 12);
1311
1312 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1313 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1314 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1315 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1316
1317 /*
1318 * Only reset the PHY when no link is currently established.
1319 * This is for the Atheros PCIe board which has problems to establish
1320 * the link (again) after this PHY reset. All other currently tested
1321 * PCIe boards don't show this problem.
1322 * This has to be re-tested and fixed in a later release!
1323 */
1324 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1325 if (!(val & 0x00001000))
1326 ppc405ex_pcie_phy_reset(port);
1327
1328 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1329
1330 port->has_ibpre = 1;
1331
1332 return ppc4xx_pciex_port_reset_sdr(port);
1333}
1334
1335static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1336{
1337 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1338
1339 /*
1340 * Set buffer allocations and then assert VRB and TXE.
1341 */
1342 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1343 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1344 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1345 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1346 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1347 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1348 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1349 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1350
1351 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1352
1353 return 0;
1354}
1355
1356static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1357{
1358 .want_sdr = true,
1359 .core_init = ppc405ex_pciex_core_init,
1360 .port_init_hw = ppc405ex_pciex_init_port_hw,
1361 .setup_utl = ppc405ex_pciex_init_utl,
1362 .check_link = ppc4xx_pciex_check_link_sdr,
1363};
1364
1365#endif /* CONFIG_40x */
1366
1367#ifdef CONFIG_476FPE
1368static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
1369{
1370 return 4;
1371}
1372
1373static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1374{
1375 u32 timeout_ms = 20;
1376 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
1377 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1378 0x1000);
1379
1380 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1381
1382 if (mbase == NULL) {
1383 printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
1384 port->index);
1385 return;
1386 }
1387
1388 while (timeout_ms--) {
1389 val = in_le32(mbase + PECFG_TLDLP);
1390
1391 if ((val & mask) == mask)
1392 break;
1393 msleep(10);
1394 }
1395
1396 if (val & PECFG_TLDLP_PRESENT) {
1397 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1398 port->link = 1;
1399 } else
1400 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1401
1402 iounmap(mbase);
1403 return;
1404}
1405
1406static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
1407{
1408 .core_init = ppc_476fpe_pciex_core_init,
1409 .check_link = ppc_476fpe_pciex_check_link,
1410};
1411#endif /* CONFIG_476FPE */
1412
1413/* Check that the core has been initied and if not, do it */
1414static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1415{
1416 static int core_init;
1417 int count = -ENODEV;
1418
1419 if (core_init++)
1420 return 0;
1421
1422#ifdef CONFIG_44x
1423 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1424 if (ppc440spe_revA())
1425 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1426 else
1427 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1428 }
1429 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1430 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1431 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1432 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1433 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
1434 ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
1435#endif /* CONFIG_44x */
1436#ifdef CONFIG_40x
1437 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1438 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1439#endif
1440#ifdef CONFIG_476FPE
1441 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
1442 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
1443#endif
1444 if (ppc4xx_pciex_hwops == NULL) {
1445 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1446 np->full_name);
1447 return -ENODEV;
1448 }
1449
1450 count = ppc4xx_pciex_hwops->core_init(np);
1451 if (count > 0) {
1452 ppc4xx_pciex_ports =
1453 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1454 GFP_KERNEL);
1455 if (ppc4xx_pciex_ports) {
1456 ppc4xx_pciex_port_count = count;
1457 return 0;
1458 }
1459 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1460 return -ENOMEM;
1461 }
1462 return -ENODEV;
1463}
1464
1465static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1466{
1467 /* We map PCI Express configuration based on the reg property */
1468 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1469 RES_TO_U32_HIGH(port->cfg_space.start));
1470 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1471 RES_TO_U32_LOW(port->cfg_space.start));
1472
1473 /* XXX FIXME: Use size from reg property. For now, map 512M */
1474 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1475
1476 /* We map UTL registers based on the reg property */
1477 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1478 RES_TO_U32_HIGH(port->utl_regs.start));
1479 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1480 RES_TO_U32_LOW(port->utl_regs.start));
1481
1482 /* XXX FIXME: Use size from reg property */
1483 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1484
1485 /* Disable all other outbound windows */
1486 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1487 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1488 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1489 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1490}
1491
1492static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1493{
1494 int rc = 0;
1495
1496 /* Init HW */
1497 if (ppc4xx_pciex_hwops->port_init_hw)
1498 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1499 if (rc != 0)
1500 return rc;
1501
1502 /*
1503 * Initialize mapping: disable all regions and configure
1504 * CFG and REG regions based on resources in the device tree
1505 */
1506 ppc4xx_pciex_port_init_mapping(port);
1507
1508 if (ppc4xx_pciex_hwops->check_link)
1509 ppc4xx_pciex_hwops->check_link(port);
1510
1511 /*
1512 * Map UTL
1513 */
1514 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1515 BUG_ON(port->utl_base == NULL);
1516
1517 /*
1518 * Setup UTL registers --BenH.
1519 */
1520 if (ppc4xx_pciex_hwops->setup_utl)
1521 ppc4xx_pciex_hwops->setup_utl(port);
1522
1523 /*
1524 * Check for VC0 active or PLL Locked and assert RDY.
1525 */
1526 if (port->sdr_base) {
1527 if (of_device_is_compatible(port->node,
1528 "ibm,plb-pciex-460sx")){
1529 if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1530 PESDRn_RCSSTS,
1531 1 << 12, 1 << 12, 5000)) {
1532 printk(KERN_INFO "PCIE%d: PLL not locked\n",
1533 port->index);
1534 port->link = 0;
1535 }
1536 } else if (port->link &&
1537 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1538 1 << 16, 1 << 16, 5000)) {
1539 printk(KERN_INFO "PCIE%d: VC0 not active\n",
1540 port->index);
1541 port->link = 0;
1542 }
1543
1544 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1545 }
1546
1547 msleep(100);
1548
1549 return 0;
1550}
1551
1552static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1553 struct pci_bus *bus,
1554 unsigned int devfn)
1555{
1556 static int message;
1557
1558 /* Endpoint can not generate upstream(remote) config cycles */
1559 if (port->endpoint && bus->number != port->hose->first_busno)
1560 return PCIBIOS_DEVICE_NOT_FOUND;
1561
1562 /* Check we are within the mapped range */
1563 if (bus->number > port->hose->last_busno) {
1564 if (!message) {
1565 printk(KERN_WARNING "Warning! Probing bus %u"
1566 " out of range !\n", bus->number);
1567 message++;
1568 }
1569 return PCIBIOS_DEVICE_NOT_FOUND;
1570 }
1571
1572 /* The root complex has only one device / function */
1573 if (bus->number == port->hose->first_busno && devfn != 0)
1574 return PCIBIOS_DEVICE_NOT_FOUND;
1575
1576 /* The other side of the RC has only one device as well */
1577 if (bus->number == (port->hose->first_busno + 1) &&
1578 PCI_SLOT(devfn) != 0)
1579 return PCIBIOS_DEVICE_NOT_FOUND;
1580
1581 /* Check if we have a link */
1582 if ((bus->number != port->hose->first_busno) && !port->link)
1583 return PCIBIOS_DEVICE_NOT_FOUND;
1584
1585 return 0;
1586}
1587
1588static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1589 struct pci_bus *bus,
1590 unsigned int devfn)
1591{
1592 int relbus;
1593
1594 /* Remove the casts when we finally remove the stupid volatile
1595 * in struct pci_controller
1596 */
1597 if (bus->number == port->hose->first_busno)
1598 return (void __iomem *)port->hose->cfg_addr;
1599
1600 relbus = bus->number - (port->hose->first_busno + 1);
1601 return (void __iomem *)port->hose->cfg_data +
1602 ((relbus << 20) | (devfn << 12));
1603}
1604
1605static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1606 int offset, int len, u32 *val)
1607{
1608 struct pci_controller *hose = pci_bus_to_host(bus);
1609 struct ppc4xx_pciex_port *port =
1610 &ppc4xx_pciex_ports[hose->indirect_type];
1611 void __iomem *addr;
1612 u32 gpl_cfg;
1613
1614 BUG_ON(hose != port->hose);
1615
1616 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1617 return PCIBIOS_DEVICE_NOT_FOUND;
1618
1619 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1620
1621 /*
1622 * Reading from configuration space of non-existing device can
1623 * generate transaction errors. For the read duration we suppress
1624 * assertion of machine check exceptions to avoid those.
1625 */
1626 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1627 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1628
1629 /* Make sure no CRS is recorded */
1630 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1631
1632 switch (len) {
1633 case 1:
1634 *val = in_8((u8 *)(addr + offset));
1635 break;
1636 case 2:
1637 *val = in_le16((u16 *)(addr + offset));
1638 break;
1639 default:
1640 *val = in_le32((u32 *)(addr + offset));
1641 break;
1642 }
1643
1644 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1645 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1646 bus->number, hose->first_busno, hose->last_busno,
1647 devfn, offset, len, addr + offset, *val);
1648
1649 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1650 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1651 pr_debug("Got CRS !\n");
1652 if (len != 4 || offset != 0)
1653 return PCIBIOS_DEVICE_NOT_FOUND;
1654 *val = 0xffff0001;
1655 }
1656
1657 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1658
1659 return PCIBIOS_SUCCESSFUL;
1660}
1661
1662static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1663 int offset, int len, u32 val)
1664{
1665 struct pci_controller *hose = pci_bus_to_host(bus);
1666 struct ppc4xx_pciex_port *port =
1667 &ppc4xx_pciex_ports[hose->indirect_type];
1668 void __iomem *addr;
1669 u32 gpl_cfg;
1670
1671 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1672 return PCIBIOS_DEVICE_NOT_FOUND;
1673
1674 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1675
1676 /*
1677 * Reading from configuration space of non-existing device can
1678 * generate transaction errors. For the read duration we suppress
1679 * assertion of machine check exceptions to avoid those.
1680 */
1681 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1682 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1683
1684 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1685 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1686 bus->number, hose->first_busno, hose->last_busno,
1687 devfn, offset, len, addr + offset, val);
1688
1689 switch (len) {
1690 case 1:
1691 out_8((u8 *)(addr + offset), val);
1692 break;
1693 case 2:
1694 out_le16((u16 *)(addr + offset), val);
1695 break;
1696 default:
1697 out_le32((u32 *)(addr + offset), val);
1698 break;
1699 }
1700
1701 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1702
1703 return PCIBIOS_SUCCESSFUL;
1704}
1705
1706static struct pci_ops ppc4xx_pciex_pci_ops =
1707{
1708 .read = ppc4xx_pciex_read_config,
1709 .write = ppc4xx_pciex_write_config,
1710};
1711
1712static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1713 struct pci_controller *hose,
1714 void __iomem *mbase,
1715 u64 plb_addr,
1716 u64 pci_addr,
1717 u64 size,
1718 unsigned int flags,
1719 int index)
1720{
1721 u32 lah, lal, pciah, pcial, sa;
1722
1723 if (!is_power_of_2(size) ||
1724 (index < 2 && size < 0x100000) ||
1725 (index == 2 && size < 0x100) ||
1726 (plb_addr & (size - 1)) != 0) {
1727 printk(KERN_WARNING "%s: Resource out of range\n",
1728 hose->dn->full_name);
1729 return -1;
1730 }
1731
1732 /* Calculate register values */
1733 lah = RES_TO_U32_HIGH(plb_addr);
1734 lal = RES_TO_U32_LOW(plb_addr);
1735 pciah = RES_TO_U32_HIGH(pci_addr);
1736 pcial = RES_TO_U32_LOW(pci_addr);
1737 sa = (0xffffffffu << ilog2(size)) | 0x1;
1738
1739 /* Program register values */
1740 switch (index) {
1741 case 0:
1742 out_le32(mbase + PECFG_POM0LAH, pciah);
1743 out_le32(mbase + PECFG_POM0LAL, pcial);
1744 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1745 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1746 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1747 /*Enabled and single region */
1748 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1749 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1750 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
1751 | DCRO_PEGPL_OMRxMSKL_VAL);
1752 else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1753 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1754 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
1755 | DCRO_PEGPL_OMRxMSKL_VAL);
1756 else
1757 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1758 sa | DCRO_PEGPL_OMR1MSKL_UOT
1759 | DCRO_PEGPL_OMRxMSKL_VAL);
1760 break;
1761 case 1:
1762 out_le32(mbase + PECFG_POM1LAH, pciah);
1763 out_le32(mbase + PECFG_POM1LAL, pcial);
1764 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1765 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1766 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1767 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1768 sa | DCRO_PEGPL_OMRxMSKL_VAL);
1769 break;
1770 case 2:
1771 out_le32(mbase + PECFG_POM2LAH, pciah);
1772 out_le32(mbase + PECFG_POM2LAL, pcial);
1773 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1774 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1775 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1776 /* Note that 3 here means enabled | IO space !!! */
1777 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1778 sa | DCRO_PEGPL_OMR3MSKL_IO
1779 | DCRO_PEGPL_OMRxMSKL_VAL);
1780 break;
1781 }
1782
1783 return 0;
1784}
1785
1786static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1787 struct pci_controller *hose,
1788 void __iomem *mbase)
1789{
1790 int i, j, found_isa_hole = 0;
1791
1792 /* Setup outbound memory windows */
1793 for (i = j = 0; i < 3; i++) {
1794 struct resource *res = &hose->mem_resources[i];
1795
1796 /* we only care about memory windows */
1797 if (!(res->flags & IORESOURCE_MEM))
1798 continue;
1799 if (j > 1) {
1800 printk(KERN_WARNING "%s: Too many ranges\n",
1801 port->node->full_name);
1802 break;
1803 }
1804
1805 /* Configure the resource */
1806 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1807 res->start,
1808 res->start - hose->pci_mem_offset,
1809 resource_size(res),
1810 res->flags,
1811 j) == 0) {
1812 j++;
1813
1814 /* If the resource PCI address is 0 then we have our
1815 * ISA memory hole
1816 */
1817 if (res->start == hose->pci_mem_offset)
1818 found_isa_hole = 1;
1819 }
1820 }
1821
1822 /* Handle ISA memory hole if not already covered */
1823 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1824 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1825 hose->isa_mem_phys, 0,
1826 hose->isa_mem_size, 0, j) == 0)
1827 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
1828 hose->dn->full_name);
1829
1830 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1831 * Note also that it -has- to be region index 2 on this HW
1832 */
1833 if (hose->io_resource.flags & IORESOURCE_IO)
1834 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1835 hose->io_base_phys, 0,
1836 0x10000, IORESOURCE_IO, 2);
1837}
1838
1839static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1840 struct pci_controller *hose,
1841 void __iomem *mbase,
1842 struct resource *res)
1843{
1844 resource_size_t size = resource_size(res);
1845 u64 sa;
1846
1847 if (port->endpoint) {
1848 resource_size_t ep_addr = 0;
1849 resource_size_t ep_size = 32 << 20;
1850
1851 /* Currently we map a fixed 64MByte window to PLB address
1852 * 0 (SDRAM). This should probably be configurable via a dts
1853 * property.
1854 */
1855
1856 /* Calculate window size */
1857 sa = (0xffffffffffffffffull << ilog2(ep_size));
1858
1859 /* Setup BAR0 */
1860 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1861 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1862 PCI_BASE_ADDRESS_MEM_TYPE_64);
1863
1864 /* Disable BAR1 & BAR2 */
1865 out_le32(mbase + PECFG_BAR1MPA, 0);
1866 out_le32(mbase + PECFG_BAR2HMPA, 0);
1867 out_le32(mbase + PECFG_BAR2LMPA, 0);
1868
1869 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1870 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1871
1872 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1873 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1874 } else {
1875 /* Calculate window size */
1876 sa = (0xffffffffffffffffull << ilog2(size));
1877 if (res->flags & IORESOURCE_PREFETCH)
1878 sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1879
1880 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1881 of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1882 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
1883
1884 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1885 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1886
1887 /* The setup of the split looks weird to me ... let's see
1888 * if it works
1889 */
1890 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1891 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1892 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1893 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1894 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1895 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1896
1897 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1898 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1899 }
1900
1901 /* Enable inbound mapping */
1902 out_le32(mbase + PECFG_PIMEN, 0x1);
1903
1904 /* Enable I/O, Mem, and Busmaster cycles */
1905 out_le16(mbase + PCI_COMMAND,
1906 in_le16(mbase + PCI_COMMAND) |
1907 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1908}
1909
1910static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1911{
1912 struct resource dma_window;
1913 struct pci_controller *hose = NULL;
1914 const int *bus_range;
1915 int primary = 0, busses;
1916 void __iomem *mbase = NULL, *cfg_data = NULL;
1917 const u32 *pval;
1918 u32 val;
1919
1920 /* Check if primary bridge */
1921 if (of_get_property(port->node, "primary", NULL))
1922 primary = 1;
1923
1924 /* Get bus range if any */
1925 bus_range = of_get_property(port->node, "bus-range", NULL);
1926
1927 /* Allocate the host controller data structure */
1928 hose = pcibios_alloc_controller(port->node);
1929 if (!hose)
1930 goto fail;
1931
1932 /* We stick the port number in "indirect_type" so the config space
1933 * ops can retrieve the port data structure easily
1934 */
1935 hose->indirect_type = port->index;
1936
1937 /* Get bus range */
1938 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1939 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1940
1941 /* Because of how big mapping the config space is (1M per bus), we
1942 * limit how many busses we support. In the long run, we could replace
1943 * that with something akin to kmap_atomic instead. We set aside 1 bus
1944 * for the host itself too.
1945 */
1946 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1947 if (busses > MAX_PCIE_BUS_MAPPED) {
1948 busses = MAX_PCIE_BUS_MAPPED;
1949 hose->last_busno = hose->first_busno + busses;
1950 }
1951
1952 if (!port->endpoint) {
1953 /* Only map the external config space in cfg_data for
1954 * PCIe root-complexes. External space is 1M per bus
1955 */
1956 cfg_data = ioremap(port->cfg_space.start +
1957 (hose->first_busno + 1) * 0x100000,
1958 busses * 0x100000);
1959 if (cfg_data == NULL) {
1960 printk(KERN_ERR "%s: Can't map external config space !",
1961 port->node->full_name);
1962 goto fail;
1963 }
1964 hose->cfg_data = cfg_data;
1965 }
1966
1967 /* Always map the host config space in cfg_addr.
1968 * Internal space is 4K
1969 */
1970 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1971 if (mbase == NULL) {
1972 printk(KERN_ERR "%s: Can't map internal config space !",
1973 port->node->full_name);
1974 goto fail;
1975 }
1976 hose->cfg_addr = mbase;
1977
1978 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1979 hose->first_busno, hose->last_busno);
1980 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1981 hose->cfg_addr, hose->cfg_data);
1982
1983 /* Setup config space */
1984 hose->ops = &ppc4xx_pciex_pci_ops;
1985 port->hose = hose;
1986 mbase = (void __iomem *)hose->cfg_addr;
1987
1988 if (!port->endpoint) {
1989 /*
1990 * Set bus numbers on our root port
1991 */
1992 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1993 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1994 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1995 }
1996
1997 /*
1998 * OMRs are already reset, also disable PIMs
1999 */
2000 out_le32(mbase + PECFG_PIMEN, 0);
2001
2002 /* Parse outbound mapping resources */
2003 pci_process_bridge_OF_ranges(hose, port->node, primary);
2004
2005 /* Parse inbound mapping resources */
2006 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
2007 goto fail;
2008
2009 /* Configure outbound ranges POMs */
2010 ppc4xx_configure_pciex_POMs(port, hose, mbase);
2011
2012 /* Configure inbound ranges PIMs */
2013 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
2014
2015 /* The root complex doesn't show up if we don't set some vendor
2016 * and device IDs into it. The defaults below are the same bogus
2017 * one that the initial code in arch/ppc had. This can be
2018 * overwritten by setting the "vendor-id/device-id" properties
2019 * in the pciex node.
2020 */
2021
2022 /* Get the (optional) vendor-/device-id from the device-tree */
2023 pval = of_get_property(port->node, "vendor-id", NULL);
2024 if (pval) {
2025 val = *pval;
2026 } else {
2027 if (!port->endpoint)
2028 val = 0xaaa0 + port->index;
2029 else
2030 val = 0xeee0 + port->index;
2031 }
2032 out_le16(mbase + 0x200, val);
2033
2034 pval = of_get_property(port->node, "device-id", NULL);
2035 if (pval) {
2036 val = *pval;
2037 } else {
2038 if (!port->endpoint)
2039 val = 0xbed0 + port->index;
2040 else
2041 val = 0xfed0 + port->index;
2042 }
2043 out_le16(mbase + 0x202, val);
2044
2045 /* Enable Bus master, memory, and io space */
2046 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
2047 out_le16(mbase + 0x204, 0x7);
2048
2049 if (!port->endpoint) {
2050 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
2051 out_le32(mbase + 0x208, 0x06040001);
2052
2053 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
2054 port->index);
2055 } else {
2056 /* Set Class Code to Processor/PPC */
2057 out_le32(mbase + 0x208, 0x0b200001);
2058
2059 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
2060 port->index);
2061 }
2062
2063 return;
2064 fail:
2065 if (hose)
2066 pcibios_free_controller(hose);
2067 if (cfg_data)
2068 iounmap(cfg_data);
2069 if (mbase)
2070 iounmap(mbase);
2071}
2072
2073static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
2074{
2075 struct ppc4xx_pciex_port *port;
2076 const u32 *pval;
2077 int portno;
2078 unsigned int dcrs;
2079 const char *val;
2080
2081 /* First, proceed to core initialization as we assume there's
2082 * only one PCIe core in the system
2083 */
2084 if (ppc4xx_pciex_check_core_init(np))
2085 return;
2086
2087 /* Get the port number from the device-tree */
2088 pval = of_get_property(np, "port", NULL);
2089 if (pval == NULL) {
2090 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
2091 np->full_name);
2092 return;
2093 }
2094 portno = *pval;
2095 if (portno >= ppc4xx_pciex_port_count) {
2096 printk(KERN_ERR "PCIE: port number out of range for %s\n",
2097 np->full_name);
2098 return;
2099 }
2100 port = &ppc4xx_pciex_ports[portno];
2101 port->index = portno;
2102
2103 /*
2104 * Check if device is enabled
2105 */
2106 if (!of_device_is_available(np)) {
2107 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2108 return;
2109 }
2110
2111 port->node = of_node_get(np);
2112 if (ppc4xx_pciex_hwops->want_sdr) {
2113 pval = of_get_property(np, "sdr-base", NULL);
2114 if (pval == NULL) {
2115 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
2116 np->full_name);
2117 return;
2118 }
2119 port->sdr_base = *pval;
2120 }
2121
2122 /* Check if device_type property is set to "pci" or "pci-endpoint".
2123 * Resulting from this setup this PCIe port will be configured
2124 * as root-complex or as endpoint.
2125 */
2126 val = of_get_property(port->node, "device_type", NULL);
2127 if (!strcmp(val, "pci-endpoint")) {
2128 port->endpoint = 1;
2129 } else if (!strcmp(val, "pci")) {
2130 port->endpoint = 0;
2131 } else {
2132 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
2133 np->full_name);
2134 return;
2135 }
2136
2137 /* Fetch config space registers address */
2138 if (of_address_to_resource(np, 0, &port->cfg_space)) {
2139 printk(KERN_ERR "%s: Can't get PCI-E config space !",
2140 np->full_name);
2141 return;
2142 }
2143 /* Fetch host bridge internal registers address */
2144 if (of_address_to_resource(np, 1, &port->utl_regs)) {
2145 printk(KERN_ERR "%s: Can't get UTL register base !",
2146 np->full_name);
2147 return;
2148 }
2149
2150 /* Map DCRs */
2151 dcrs = dcr_resource_start(np, 0);
2152 if (dcrs == 0) {
2153 printk(KERN_ERR "%s: Can't get DCR register base !",
2154 np->full_name);
2155 return;
2156 }
2157 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2158
2159 /* Initialize the port specific registers */
2160 if (ppc4xx_pciex_port_init(port)) {
2161 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2162 return;
2163 }
2164
2165 /* Setup the linux hose data structure */
2166 ppc4xx_pciex_port_setup_hose(port);
2167}
2168
2169#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
2170
2171static int __init ppc4xx_pci_find_bridges(void)
2172{
2173 struct device_node *np;
2174
2175 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
2176
2177#ifdef CONFIG_PPC4xx_PCI_EXPRESS
2178 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
2179 ppc4xx_probe_pciex_bridge(np);
2180#endif
2181 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
2182 ppc4xx_probe_pcix_bridge(np);
2183 for_each_compatible_node(np, NULL, "ibm,plb-pci")
2184 ppc4xx_probe_pci_bridge(np);
2185
2186 return 0;
2187}
2188arch_initcall(ppc4xx_pci_find_bridges);
2189
1/*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19#undef DEBUG
20
21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/of.h>
25#include <linux/bootmem.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28
29#include <asm/io.h>
30#include <asm/pci-bridge.h>
31#include <asm/machdep.h>
32#include <asm/dcr.h>
33#include <asm/dcr-regs.h>
34#include <mm/mmu_decl.h>
35
36#include "ppc4xx_pci.h"
37
38static int dma_offset_set;
39
40#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
41#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42
43#define RES_TO_U32_LOW(val) \
44 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
45#define RES_TO_U32_HIGH(val) \
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
47
48static inline int ppc440spe_revA(void)
49{
50 /* Catch both 440SPe variants, with and without RAID6 support */
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
52 return 1;
53 else
54 return 0;
55}
56
57static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
58{
59 struct pci_controller *hose;
60 int i;
61
62 if (dev->devfn != 0 || dev->bus->self != NULL)
63 return;
64
65 hose = pci_bus_to_host(dev->bus);
66 if (hose == NULL)
67 return;
68
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
72 return;
73
74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
77 }
78
79 /* Hide the PCI host BARs from the kernel as their content doesn't
80 * fit well in the resource management
81 */
82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
83 dev->resource[i].start = dev->resource[i].end = 0;
84 dev->resource[i].flags = 0;
85 }
86
87 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
88 pci_name(dev));
89}
90DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
91
92static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
93 void __iomem *reg,
94 struct resource *res)
95{
96 u64 size;
97 const u32 *ranges;
98 int rlen;
99 int pna = of_n_addr_cells(hose->dn);
100 int np = pna + 5;
101
102 /* Default */
103 res->start = 0;
104 size = 0x80000000;
105 res->end = size - 1;
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107
108 /* Get dma-ranges property */
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
110 if (ranges == NULL)
111 goto out;
112
113 /* Walk it */
114 while ((rlen -= np * 4) >= 0) {
115 u32 pci_space = ranges[0];
116 u64 pci_addr = of_read_number(ranges + 1, 2);
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
118 size = of_read_number(ranges + pna + 3, 2);
119 ranges += np;
120 if (cpu_addr == OF_BAD_ADDR || size == 0)
121 continue;
122
123 /* We only care about memory */
124 if ((pci_space & 0x03000000) != 0x02000000)
125 continue;
126
127 /* We currently only support memory at 0, and pci_addr
128 * within 32 bits space
129 */
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
131 printk(KERN_WARNING "%s: Ignored unsupported dma range"
132 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 hose->dn->full_name,
134 pci_addr, pci_addr + size - 1, cpu_addr);
135 continue;
136 }
137
138 /* Check if not prefetchable */
139 if (!(pci_space & 0x40000000))
140 res->flags &= ~IORESOURCE_PREFETCH;
141
142
143 /* Use that */
144 res->start = pci_addr;
145 /* Beware of 32 bits resources */
146 if (sizeof(resource_size_t) == sizeof(u32) &&
147 (pci_addr + size) > 0x100000000ull)
148 res->end = 0xffffffff;
149 else
150 res->end = res->start + size - 1;
151 break;
152 }
153
154 /* We only support one global DMA offset */
155 if (dma_offset_set && pci_dram_offset != res->start) {
156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
157 hose->dn->full_name);
158 return -ENXIO;
159 }
160
161 /* Check that we can fit all of memory as we don't support
162 * DMA bounce buffers
163 */
164 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small "
166 "(size=%llx total_memory=%llx)\n",
167 hose->dn->full_name, size, (u64)total_memory);
168 return -ENXIO;
169 }
170
171 /* Check we are a power of 2 size and that base is a multiple of size*/
172 if ((size & (size - 1)) != 0 ||
173 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name);
176 return -ENXIO;
177 }
178
179 /* Check that we are fully contained within 32 bits space */
180 if (res->end > 0xffffffff) {
181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
182 hose->dn->full_name);
183 return -ENXIO;
184 }
185 out:
186 dma_offset_set = 1;
187 pci_dram_offset = res->start;
188
189 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
190 pci_dram_offset);
191 return 0;
192}
193
194/*
195 * 4xx PCI 2.x part
196 */
197
198static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
199 void __iomem *reg,
200 u64 plb_addr,
201 u64 pci_addr,
202 u64 size,
203 unsigned int flags,
204 int index)
205{
206 u32 ma, pcila, pciha;
207
208 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
209 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
210 * address are actually hard wired to a value that appears to depend
211 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
212 *
213 * The trick here is we just crop those top bits and ignore them when
214 * programming the chip. That means the device-tree has to be right
215 * for the specific part used (we don't print a warning if it's wrong
216 * but on the other hand, you'll crash quickly enough), but at least
217 * this code should work whatever the hard coded value is
218 */
219 plb_addr &= 0xffffffffull;
220
221 /* Note: Due to the above hack, the test below doesn't actually test
222 * if you address is above 4G, but it tests that address and
223 * (address + size) are both contained in the same 4G
224 */
225 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
226 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
227 printk(KERN_WARNING "%s: Resource out of range\n",
228 hose->dn->full_name);
229 return -1;
230 }
231 ma = (0xffffffffu << ilog2(size)) | 1;
232 if (flags & IORESOURCE_PREFETCH)
233 ma |= 2;
234
235 pciha = RES_TO_U32_HIGH(pci_addr);
236 pcila = RES_TO_U32_LOW(pci_addr);
237
238 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
239 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
240 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
241 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
242
243 return 0;
244}
245
246static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
247 void __iomem *reg)
248{
249 int i, j, found_isa_hole = 0;
250
251 /* Setup outbound memory windows */
252 for (i = j = 0; i < 3; i++) {
253 struct resource *res = &hose->mem_resources[i];
254
255 /* we only care about memory windows */
256 if (!(res->flags & IORESOURCE_MEM))
257 continue;
258 if (j > 2) {
259 printk(KERN_WARNING "%s: Too many ranges\n",
260 hose->dn->full_name);
261 break;
262 }
263
264 /* Configure the resource */
265 if (ppc4xx_setup_one_pci_PMM(hose, reg,
266 res->start,
267 res->start - hose->pci_mem_offset,
268 resource_size(res),
269 res->flags,
270 j) == 0) {
271 j++;
272
273 /* If the resource PCI address is 0 then we have our
274 * ISA memory hole
275 */
276 if (res->start == hose->pci_mem_offset)
277 found_isa_hole = 1;
278 }
279 }
280
281 /* Handle ISA memory hole if not already covered */
282 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
283 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
284 hose->isa_mem_size, 0, j) == 0)
285 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
286 hose->dn->full_name);
287}
288
289static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
290 void __iomem *reg,
291 const struct resource *res)
292{
293 resource_size_t size = resource_size(res);
294 u32 sa;
295
296 /* Calculate window size */
297 sa = (0xffffffffu << ilog2(size)) | 1;
298 sa |= 0x1;
299
300 /* RAM is always at 0 local for now */
301 writel(0, reg + PCIL0_PTM1LA);
302 writel(sa, reg + PCIL0_PTM1MS);
303
304 /* Map on PCI side */
305 early_write_config_dword(hose, hose->first_busno, 0,
306 PCI_BASE_ADDRESS_1, res->start);
307 early_write_config_dword(hose, hose->first_busno, 0,
308 PCI_BASE_ADDRESS_2, 0x00000000);
309 early_write_config_word(hose, hose->first_busno, 0,
310 PCI_COMMAND, 0x0006);
311}
312
313static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
314{
315 /* NYI */
316 struct resource rsrc_cfg;
317 struct resource rsrc_reg;
318 struct resource dma_window;
319 struct pci_controller *hose = NULL;
320 void __iomem *reg = NULL;
321 const int *bus_range;
322 int primary = 0;
323
324 /* Check if device is enabled */
325 if (!of_device_is_available(np)) {
326 printk(KERN_INFO "%s: Port disabled via device-tree\n",
327 np->full_name);
328 return;
329 }
330
331 /* Fetch config space registers address */
332 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
333 printk(KERN_ERR "%s: Can't get PCI config register base !",
334 np->full_name);
335 return;
336 }
337 /* Fetch host bridge internal registers address */
338 if (of_address_to_resource(np, 3, &rsrc_reg)) {
339 printk(KERN_ERR "%s: Can't get PCI internal register base !",
340 np->full_name);
341 return;
342 }
343
344 /* Check if primary bridge */
345 if (of_get_property(np, "primary", NULL))
346 primary = 1;
347
348 /* Get bus range if any */
349 bus_range = of_get_property(np, "bus-range", NULL);
350
351 /* Map registers */
352 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
353 if (reg == NULL) {
354 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
355 goto fail;
356 }
357
358 /* Allocate the host controller data structure */
359 hose = pcibios_alloc_controller(np);
360 if (!hose)
361 goto fail;
362
363 hose->first_busno = bus_range ? bus_range[0] : 0x0;
364 hose->last_busno = bus_range ? bus_range[1] : 0xff;
365
366 /* Setup config space */
367 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
368
369 /* Disable all windows */
370 writel(0, reg + PCIL0_PMM0MA);
371 writel(0, reg + PCIL0_PMM1MA);
372 writel(0, reg + PCIL0_PMM2MA);
373 writel(0, reg + PCIL0_PTM1MS);
374 writel(0, reg + PCIL0_PTM2MS);
375
376 /* Parse outbound mapping resources */
377 pci_process_bridge_OF_ranges(hose, np, primary);
378
379 /* Parse inbound mapping resources */
380 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
381 goto fail;
382
383 /* Configure outbound ranges POMs */
384 ppc4xx_configure_pci_PMMs(hose, reg);
385
386 /* Configure inbound ranges PIMs */
387 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
388
389 /* We don't need the registers anymore */
390 iounmap(reg);
391 return;
392
393 fail:
394 if (hose)
395 pcibios_free_controller(hose);
396 if (reg)
397 iounmap(reg);
398}
399
400/*
401 * 4xx PCI-X part
402 */
403
404static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
405 void __iomem *reg,
406 u64 plb_addr,
407 u64 pci_addr,
408 u64 size,
409 unsigned int flags,
410 int index)
411{
412 u32 lah, lal, pciah, pcial, sa;
413
414 if (!is_power_of_2(size) || size < 0x1000 ||
415 (plb_addr & (size - 1)) != 0) {
416 printk(KERN_WARNING "%s: Resource out of range\n",
417 hose->dn->full_name);
418 return -1;
419 }
420
421 /* Calculate register values */
422 lah = RES_TO_U32_HIGH(plb_addr);
423 lal = RES_TO_U32_LOW(plb_addr);
424 pciah = RES_TO_U32_HIGH(pci_addr);
425 pcial = RES_TO_U32_LOW(pci_addr);
426 sa = (0xffffffffu << ilog2(size)) | 0x1;
427
428 /* Program register values */
429 if (index == 0) {
430 writel(lah, reg + PCIX0_POM0LAH);
431 writel(lal, reg + PCIX0_POM0LAL);
432 writel(pciah, reg + PCIX0_POM0PCIAH);
433 writel(pcial, reg + PCIX0_POM0PCIAL);
434 writel(sa, reg + PCIX0_POM0SA);
435 } else {
436 writel(lah, reg + PCIX0_POM1LAH);
437 writel(lal, reg + PCIX0_POM1LAL);
438 writel(pciah, reg + PCIX0_POM1PCIAH);
439 writel(pcial, reg + PCIX0_POM1PCIAL);
440 writel(sa, reg + PCIX0_POM1SA);
441 }
442
443 return 0;
444}
445
446static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
447 void __iomem *reg)
448{
449 int i, j, found_isa_hole = 0;
450
451 /* Setup outbound memory windows */
452 for (i = j = 0; i < 3; i++) {
453 struct resource *res = &hose->mem_resources[i];
454
455 /* we only care about memory windows */
456 if (!(res->flags & IORESOURCE_MEM))
457 continue;
458 if (j > 1) {
459 printk(KERN_WARNING "%s: Too many ranges\n",
460 hose->dn->full_name);
461 break;
462 }
463
464 /* Configure the resource */
465 if (ppc4xx_setup_one_pcix_POM(hose, reg,
466 res->start,
467 res->start - hose->pci_mem_offset,
468 resource_size(res),
469 res->flags,
470 j) == 0) {
471 j++;
472
473 /* If the resource PCI address is 0 then we have our
474 * ISA memory hole
475 */
476 if (res->start == hose->pci_mem_offset)
477 found_isa_hole = 1;
478 }
479 }
480
481 /* Handle ISA memory hole if not already covered */
482 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
483 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
484 hose->isa_mem_size, 0, j) == 0)
485 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
486 hose->dn->full_name);
487}
488
489static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
490 void __iomem *reg,
491 const struct resource *res,
492 int big_pim,
493 int enable_msi_hole)
494{
495 resource_size_t size = resource_size(res);
496 u32 sa;
497
498 /* RAM is always at 0 */
499 writel(0x00000000, reg + PCIX0_PIM0LAH);
500 writel(0x00000000, reg + PCIX0_PIM0LAL);
501
502 /* Calculate window size */
503 sa = (0xffffffffu << ilog2(size)) | 1;
504 sa |= 0x1;
505 if (res->flags & IORESOURCE_PREFETCH)
506 sa |= 0x2;
507 if (enable_msi_hole)
508 sa |= 0x4;
509 writel(sa, reg + PCIX0_PIM0SA);
510 if (big_pim)
511 writel(0xffffffff, reg + PCIX0_PIM0SAH);
512
513 /* Map on PCI side */
514 writel(0x00000000, reg + PCIX0_BAR0H);
515 writel(res->start, reg + PCIX0_BAR0L);
516 writew(0x0006, reg + PCIX0_COMMAND);
517}
518
519static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
520{
521 struct resource rsrc_cfg;
522 struct resource rsrc_reg;
523 struct resource dma_window;
524 struct pci_controller *hose = NULL;
525 void __iomem *reg = NULL;
526 const int *bus_range;
527 int big_pim = 0, msi = 0, primary = 0;
528
529 /* Fetch config space registers address */
530 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
531 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
532 np->full_name);
533 return;
534 }
535 /* Fetch host bridge internal registers address */
536 if (of_address_to_resource(np, 3, &rsrc_reg)) {
537 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
538 np->full_name);
539 return;
540 }
541
542 /* Check if it supports large PIMs (440GX) */
543 if (of_get_property(np, "large-inbound-windows", NULL))
544 big_pim = 1;
545
546 /* Check if we should enable MSIs inbound hole */
547 if (of_get_property(np, "enable-msi-hole", NULL))
548 msi = 1;
549
550 /* Check if primary bridge */
551 if (of_get_property(np, "primary", NULL))
552 primary = 1;
553
554 /* Get bus range if any */
555 bus_range = of_get_property(np, "bus-range", NULL);
556
557 /* Map registers */
558 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
559 if (reg == NULL) {
560 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
561 goto fail;
562 }
563
564 /* Allocate the host controller data structure */
565 hose = pcibios_alloc_controller(np);
566 if (!hose)
567 goto fail;
568
569 hose->first_busno = bus_range ? bus_range[0] : 0x0;
570 hose->last_busno = bus_range ? bus_range[1] : 0xff;
571
572 /* Setup config space */
573 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
574 PPC_INDIRECT_TYPE_SET_CFG_TYPE);
575
576 /* Disable all windows */
577 writel(0, reg + PCIX0_POM0SA);
578 writel(0, reg + PCIX0_POM1SA);
579 writel(0, reg + PCIX0_POM2SA);
580 writel(0, reg + PCIX0_PIM0SA);
581 writel(0, reg + PCIX0_PIM1SA);
582 writel(0, reg + PCIX0_PIM2SA);
583 if (big_pim) {
584 writel(0, reg + PCIX0_PIM0SAH);
585 writel(0, reg + PCIX0_PIM2SAH);
586 }
587
588 /* Parse outbound mapping resources */
589 pci_process_bridge_OF_ranges(hose, np, primary);
590
591 /* Parse inbound mapping resources */
592 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
593 goto fail;
594
595 /* Configure outbound ranges POMs */
596 ppc4xx_configure_pcix_POMs(hose, reg);
597
598 /* Configure inbound ranges PIMs */
599 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
600
601 /* We don't need the registers anymore */
602 iounmap(reg);
603 return;
604
605 fail:
606 if (hose)
607 pcibios_free_controller(hose);
608 if (reg)
609 iounmap(reg);
610}
611
612#ifdef CONFIG_PPC4xx_PCI_EXPRESS
613
614/*
615 * 4xx PCI-Express part
616 *
617 * We support 3 parts currently based on the compatible property:
618 *
619 * ibm,plb-pciex-440spe
620 * ibm,plb-pciex-405ex
621 * ibm,plb-pciex-460ex
622 *
623 * Anything else will be rejected for now as they are all subtly
624 * different unfortunately.
625 *
626 */
627
628#define MAX_PCIE_BUS_MAPPED 0x40
629
630struct ppc4xx_pciex_port
631{
632 struct pci_controller *hose;
633 struct device_node *node;
634 unsigned int index;
635 int endpoint;
636 int link;
637 int has_ibpre;
638 unsigned int sdr_base;
639 dcr_host_t dcrs;
640 struct resource cfg_space;
641 struct resource utl_regs;
642 void __iomem *utl_base;
643};
644
645static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
646static unsigned int ppc4xx_pciex_port_count;
647
648struct ppc4xx_pciex_hwops
649{
650 int (*core_init)(struct device_node *np);
651 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
652 int (*setup_utl)(struct ppc4xx_pciex_port *port);
653 void (*check_link)(struct ppc4xx_pciex_port *port);
654};
655
656static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
657
658static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
659 unsigned int sdr_offset,
660 unsigned int mask,
661 unsigned int value,
662 int timeout_ms)
663{
664 u32 val;
665
666 while(timeout_ms--) {
667 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
668 if ((val & mask) == value) {
669 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
670 port->index, sdr_offset, timeout_ms, val);
671 return 0;
672 }
673 msleep(1);
674 }
675 return -1;
676}
677
678static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
679{
680 /* Wait for reset to complete */
681 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
682 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
683 port->index);
684 return -1;
685 }
686 return 0;
687}
688
689
690static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
691{
692 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
693
694 /* Check for card presence detect if supported, if not, just wait for
695 * link unconditionally.
696 *
697 * note that we don't fail if there is no link, we just filter out
698 * config space accesses. That way, it will be easier to implement
699 * hotplug later on.
700 */
701 if (!port->has_ibpre ||
702 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
703 1 << 28, 1 << 28, 100)) {
704 printk(KERN_INFO
705 "PCIE%d: Device detected, waiting for link...\n",
706 port->index);
707 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
708 0x1000, 0x1000, 2000))
709 printk(KERN_WARNING
710 "PCIE%d: Link up failed\n", port->index);
711 else {
712 printk(KERN_INFO
713 "PCIE%d: link is up !\n", port->index);
714 port->link = 1;
715 }
716 } else
717 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
718}
719
720#ifdef CONFIG_44x
721
722/* Check various reset bits of the 440SPe PCIe core */
723static int __init ppc440spe_pciex_check_reset(struct device_node *np)
724{
725 u32 valPE0, valPE1, valPE2;
726 int err = 0;
727
728 /* SDR0_PEGPLLLCT1 reset */
729 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
730 /*
731 * the PCIe core was probably already initialised
732 * by firmware - let's re-reset RCSSET regs
733 *
734 * -- Shouldn't we also re-reset the whole thing ? -- BenH
735 */
736 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
737 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
738 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
739 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
740 }
741
742 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
743 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
744 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
745
746 /* SDR0_PExRCSSET rstgu */
747 if (!(valPE0 & 0x01000000) ||
748 !(valPE1 & 0x01000000) ||
749 !(valPE2 & 0x01000000)) {
750 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
751 err = -1;
752 }
753
754 /* SDR0_PExRCSSET rstdl */
755 if (!(valPE0 & 0x00010000) ||
756 !(valPE1 & 0x00010000) ||
757 !(valPE2 & 0x00010000)) {
758 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
759 err = -1;
760 }
761
762 /* SDR0_PExRCSSET rstpyn */
763 if ((valPE0 & 0x00001000) ||
764 (valPE1 & 0x00001000) ||
765 (valPE2 & 0x00001000)) {
766 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
767 err = -1;
768 }
769
770 /* SDR0_PExRCSSET hldplb */
771 if ((valPE0 & 0x10000000) ||
772 (valPE1 & 0x10000000) ||
773 (valPE2 & 0x10000000)) {
774 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
775 err = -1;
776 }
777
778 /* SDR0_PExRCSSET rdy */
779 if ((valPE0 & 0x00100000) ||
780 (valPE1 & 0x00100000) ||
781 (valPE2 & 0x00100000)) {
782 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
783 err = -1;
784 }
785
786 /* SDR0_PExRCSSET shutdown */
787 if ((valPE0 & 0x00000100) ||
788 (valPE1 & 0x00000100) ||
789 (valPE2 & 0x00000100)) {
790 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
791 err = -1;
792 }
793
794 return err;
795}
796
797/* Global PCIe core initializations for 440SPe core */
798static int __init ppc440spe_pciex_core_init(struct device_node *np)
799{
800 int time_out = 20;
801
802 /* Set PLL clock receiver to LVPECL */
803 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
804
805 /* Shouldn't we do all the calibration stuff etc... here ? */
806 if (ppc440spe_pciex_check_reset(np))
807 return -ENXIO;
808
809 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
810 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
811 "failed (0x%08x)\n",
812 mfdcri(SDR0, PESDR0_PLLLCT2));
813 return -1;
814 }
815
816 /* De-assert reset of PCIe PLL, wait for lock */
817 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
818 udelay(3);
819
820 while (time_out) {
821 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
822 time_out--;
823 udelay(1);
824 } else
825 break;
826 }
827 if (!time_out) {
828 printk(KERN_INFO "PCIE: VCO output not locked\n");
829 return -1;
830 }
831
832 pr_debug("PCIE initialization OK\n");
833
834 return 3;
835}
836
837static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
838{
839 u32 val = 1 << 24;
840
841 if (port->endpoint)
842 val = PTYPE_LEGACY_ENDPOINT << 20;
843 else
844 val = PTYPE_ROOT_PORT << 20;
845
846 if (port->index == 0)
847 val |= LNKW_X8 << 12;
848 else
849 val |= LNKW_X4 << 12;
850
851 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
852 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
853 if (ppc440spe_revA())
854 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
855 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
856 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
857 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
858 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
859 if (port->index == 0) {
860 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
861 0x35000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
863 0x35000000);
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
865 0x35000000);
866 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
867 0x35000000);
868 }
869 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
870 (1 << 24) | (1 << 16), 1 << 12);
871
872 return ppc4xx_pciex_port_reset_sdr(port);
873}
874
875static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
876{
877 return ppc440spe_pciex_init_port_hw(port);
878}
879
880static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
881{
882 int rc = ppc440spe_pciex_init_port_hw(port);
883
884 port->has_ibpre = 1;
885
886 return rc;
887}
888
889static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
890{
891 /* XXX Check what that value means... I hate magic */
892 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
893
894 /*
895 * Set buffer allocations and then assert VRB and TXE.
896 */
897 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
898 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
899 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
900 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
901 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
902 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
903 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
904 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
905
906 return 0;
907}
908
909static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
910{
911 /* Report CRS to the operating system */
912 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
913
914 return 0;
915}
916
917static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
918{
919 .core_init = ppc440spe_pciex_core_init,
920 .port_init_hw = ppc440speA_pciex_init_port_hw,
921 .setup_utl = ppc440speA_pciex_init_utl,
922 .check_link = ppc4xx_pciex_check_link_sdr,
923};
924
925static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
926{
927 .core_init = ppc440spe_pciex_core_init,
928 .port_init_hw = ppc440speB_pciex_init_port_hw,
929 .setup_utl = ppc440speB_pciex_init_utl,
930 .check_link = ppc4xx_pciex_check_link_sdr,
931};
932
933static int __init ppc460ex_pciex_core_init(struct device_node *np)
934{
935 /* Nothing to do, return 2 ports */
936 return 2;
937}
938
939static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
940{
941 u32 val;
942 u32 utlset1;
943
944 if (port->endpoint)
945 val = PTYPE_LEGACY_ENDPOINT << 20;
946 else
947 val = PTYPE_ROOT_PORT << 20;
948
949 if (port->index == 0) {
950 val |= LNKW_X1 << 12;
951 utlset1 = 0x20000000;
952 } else {
953 val |= LNKW_X4 << 12;
954 utlset1 = 0x20101101;
955 }
956
957 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
958 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
959 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
960
961 switch (port->index) {
962 case 0:
963 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
964 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
965 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
966
967 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
968 break;
969
970 case 1:
971 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
972 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
973 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
974 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
975 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
976 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
977 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
978 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
979 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
980 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
981 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
982 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
983
984 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
985 break;
986 }
987
988 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
989 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
990 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
991
992 /* Poll for PHY reset */
993 /* XXX FIXME add timeout */
994 switch (port->index) {
995 case 0:
996 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
997 udelay(10);
998 break;
999 case 1:
1000 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
1001 udelay(10);
1002 break;
1003 }
1004
1005 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1006 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1007 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1008 PESDRx_RCSSET_RSTPYN);
1009
1010 port->has_ibpre = 1;
1011
1012 return ppc4xx_pciex_port_reset_sdr(port);
1013}
1014
1015static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1016{
1017 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1018
1019 /*
1020 * Set buffer allocations and then assert VRB and TXE.
1021 */
1022 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1023 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1024 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1025 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1026 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1027 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1028 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1029 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1030 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1031
1032 return 0;
1033}
1034
1035static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1036{
1037 .core_init = ppc460ex_pciex_core_init,
1038 .port_init_hw = ppc460ex_pciex_init_port_hw,
1039 .setup_utl = ppc460ex_pciex_init_utl,
1040 .check_link = ppc4xx_pciex_check_link_sdr,
1041};
1042
1043static int __init ppc460sx_pciex_core_init(struct device_node *np)
1044{
1045 /* HSS drive amplitude */
1046 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
1047 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
1048 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
1049 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
1050 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
1051 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
1052 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
1053 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
1054
1055 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
1056 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
1057 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
1058 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
1059
1060 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
1061 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
1062 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
1063 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
1064
1065 /* HSS TX pre-emphasis */
1066 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1067 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1068 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1069 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1070 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1071 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1072 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1073 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1074
1075 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1076 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1077 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1078 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1079
1080 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1081 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1082 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1083 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1084
1085 /* HSS TX calibration control */
1086 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1087 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1088 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1089
1090 /* HSS TX slew control */
1091 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1092 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1093 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1094
1095 udelay(100);
1096
1097 /* De-assert PLLRESET */
1098 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1099
1100 /* Reset DL, UTL, GPL before configuration */
1101 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1102 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1103 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1104 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1105 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1106 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1107
1108 udelay(100);
1109
1110 /*
1111 * If bifurcation is not enabled, u-boot would have disabled the
1112 * third PCIe port
1113 */
1114 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1115 0x00000001)) {
1116 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1117 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1118 return 3;
1119 }
1120
1121 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1122 return 2;
1123}
1124
1125static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1126{
1127
1128 if (port->endpoint)
1129 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1130 0x01000000, 0);
1131 else
1132 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1133 0, 0x01000000);
1134
1135 /*Gen-1*/
1136 mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
1137
1138 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1139 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1140 PESDRx_RCSSET_RSTPYN);
1141
1142 port->has_ibpre = 1;
1143
1144 return ppc4xx_pciex_port_reset_sdr(port);
1145}
1146
1147static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1148{
1149 /* Max 128 Bytes */
1150 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1151 return 0;
1152}
1153
1154static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1155 .core_init = ppc460sx_pciex_core_init,
1156 .port_init_hw = ppc460sx_pciex_init_port_hw,
1157 .setup_utl = ppc460sx_pciex_init_utl,
1158 .check_link = ppc4xx_pciex_check_link_sdr,
1159};
1160
1161#endif /* CONFIG_44x */
1162
1163#ifdef CONFIG_40x
1164
1165static int __init ppc405ex_pciex_core_init(struct device_node *np)
1166{
1167 /* Nothing to do, return 2 ports */
1168 return 2;
1169}
1170
1171static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1172{
1173 /* Assert the PE0_PHY reset */
1174 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1175 msleep(1);
1176
1177 /* deassert the PE0_hotreset */
1178 if (port->endpoint)
1179 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1180 else
1181 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1182
1183 /* poll for phy !reset */
1184 /* XXX FIXME add timeout */
1185 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1186 ;
1187
1188 /* deassert the PE0_gpl_utl_reset */
1189 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1190}
1191
1192static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1193{
1194 u32 val;
1195
1196 if (port->endpoint)
1197 val = PTYPE_LEGACY_ENDPOINT;
1198 else
1199 val = PTYPE_ROOT_PORT;
1200
1201 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1202 1 << 24 | val << 20 | LNKW_X1 << 12);
1203
1204 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1205 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1206 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1207 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1208
1209 /*
1210 * Only reset the PHY when no link is currently established.
1211 * This is for the Atheros PCIe board which has problems to establish
1212 * the link (again) after this PHY reset. All other currently tested
1213 * PCIe boards don't show this problem.
1214 * This has to be re-tested and fixed in a later release!
1215 */
1216 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1217 if (!(val & 0x00001000))
1218 ppc405ex_pcie_phy_reset(port);
1219
1220 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1221
1222 port->has_ibpre = 1;
1223
1224 return ppc4xx_pciex_port_reset_sdr(port);
1225}
1226
1227static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1228{
1229 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1230
1231 /*
1232 * Set buffer allocations and then assert VRB and TXE.
1233 */
1234 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1235 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1236 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1237 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1238 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1239 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1240 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1241 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1242
1243 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1244
1245 return 0;
1246}
1247
1248static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1249{
1250 .core_init = ppc405ex_pciex_core_init,
1251 .port_init_hw = ppc405ex_pciex_init_port_hw,
1252 .setup_utl = ppc405ex_pciex_init_utl,
1253 .check_link = ppc4xx_pciex_check_link_sdr,
1254};
1255
1256#endif /* CONFIG_40x */
1257
1258/* Check that the core has been initied and if not, do it */
1259static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1260{
1261 static int core_init;
1262 int count = -ENODEV;
1263
1264 if (core_init++)
1265 return 0;
1266
1267#ifdef CONFIG_44x
1268 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1269 if (ppc440spe_revA())
1270 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1271 else
1272 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1273 }
1274 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1275 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1276 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1277 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1278#endif /* CONFIG_44x */
1279#ifdef CONFIG_40x
1280 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1281 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1282#endif
1283 if (ppc4xx_pciex_hwops == NULL) {
1284 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1285 np->full_name);
1286 return -ENODEV;
1287 }
1288
1289 count = ppc4xx_pciex_hwops->core_init(np);
1290 if (count > 0) {
1291 ppc4xx_pciex_ports =
1292 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1293 GFP_KERNEL);
1294 if (ppc4xx_pciex_ports) {
1295 ppc4xx_pciex_port_count = count;
1296 return 0;
1297 }
1298 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1299 return -ENOMEM;
1300 }
1301 return -ENODEV;
1302}
1303
1304static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1305{
1306 /* We map PCI Express configuration based on the reg property */
1307 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1308 RES_TO_U32_HIGH(port->cfg_space.start));
1309 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1310 RES_TO_U32_LOW(port->cfg_space.start));
1311
1312 /* XXX FIXME: Use size from reg property. For now, map 512M */
1313 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1314
1315 /* We map UTL registers based on the reg property */
1316 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1317 RES_TO_U32_HIGH(port->utl_regs.start));
1318 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1319 RES_TO_U32_LOW(port->utl_regs.start));
1320
1321 /* XXX FIXME: Use size from reg property */
1322 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1323
1324 /* Disable all other outbound windows */
1325 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1326 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1327 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1328 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1329}
1330
1331static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1332{
1333 int rc = 0;
1334
1335 /* Init HW */
1336 if (ppc4xx_pciex_hwops->port_init_hw)
1337 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1338 if (rc != 0)
1339 return rc;
1340
1341 if (ppc4xx_pciex_hwops->check_link)
1342 ppc4xx_pciex_hwops->check_link(port);
1343
1344 /*
1345 * Initialize mapping: disable all regions and configure
1346 * CFG and REG regions based on resources in the device tree
1347 */
1348 ppc4xx_pciex_port_init_mapping(port);
1349
1350 /*
1351 * Map UTL
1352 */
1353 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1354 BUG_ON(port->utl_base == NULL);
1355
1356 /*
1357 * Setup UTL registers --BenH.
1358 */
1359 if (ppc4xx_pciex_hwops->setup_utl)
1360 ppc4xx_pciex_hwops->setup_utl(port);
1361
1362 /*
1363 * Check for VC0 active and assert RDY.
1364 */
1365 if (port->sdr_base) {
1366 if (port->link &&
1367 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1368 1 << 16, 1 << 16, 5000)) {
1369 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1370 port->link = 0;
1371 }
1372
1373 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1374 }
1375
1376 msleep(100);
1377
1378 return 0;
1379}
1380
1381static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1382 struct pci_bus *bus,
1383 unsigned int devfn)
1384{
1385 static int message;
1386
1387 /* Endpoint can not generate upstream(remote) config cycles */
1388 if (port->endpoint && bus->number != port->hose->first_busno)
1389 return PCIBIOS_DEVICE_NOT_FOUND;
1390
1391 /* Check we are within the mapped range */
1392 if (bus->number > port->hose->last_busno) {
1393 if (!message) {
1394 printk(KERN_WARNING "Warning! Probing bus %u"
1395 " out of range !\n", bus->number);
1396 message++;
1397 }
1398 return PCIBIOS_DEVICE_NOT_FOUND;
1399 }
1400
1401 /* The root complex has only one device / function */
1402 if (bus->number == port->hose->first_busno && devfn != 0)
1403 return PCIBIOS_DEVICE_NOT_FOUND;
1404
1405 /* The other side of the RC has only one device as well */
1406 if (bus->number == (port->hose->first_busno + 1) &&
1407 PCI_SLOT(devfn) != 0)
1408 return PCIBIOS_DEVICE_NOT_FOUND;
1409
1410 /* Check if we have a link */
1411 if ((bus->number != port->hose->first_busno) && !port->link)
1412 return PCIBIOS_DEVICE_NOT_FOUND;
1413
1414 return 0;
1415}
1416
1417static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1418 struct pci_bus *bus,
1419 unsigned int devfn)
1420{
1421 int relbus;
1422
1423 /* Remove the casts when we finally remove the stupid volatile
1424 * in struct pci_controller
1425 */
1426 if (bus->number == port->hose->first_busno)
1427 return (void __iomem *)port->hose->cfg_addr;
1428
1429 relbus = bus->number - (port->hose->first_busno + 1);
1430 return (void __iomem *)port->hose->cfg_data +
1431 ((relbus << 20) | (devfn << 12));
1432}
1433
1434static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1435 int offset, int len, u32 *val)
1436{
1437 struct pci_controller *hose = pci_bus_to_host(bus);
1438 struct ppc4xx_pciex_port *port =
1439 &ppc4xx_pciex_ports[hose->indirect_type];
1440 void __iomem *addr;
1441 u32 gpl_cfg;
1442
1443 BUG_ON(hose != port->hose);
1444
1445 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1446 return PCIBIOS_DEVICE_NOT_FOUND;
1447
1448 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1449
1450 /*
1451 * Reading from configuration space of non-existing device can
1452 * generate transaction errors. For the read duration we suppress
1453 * assertion of machine check exceptions to avoid those.
1454 */
1455 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1456 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1457
1458 /* Make sure no CRS is recorded */
1459 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1460
1461 switch (len) {
1462 case 1:
1463 *val = in_8((u8 *)(addr + offset));
1464 break;
1465 case 2:
1466 *val = in_le16((u16 *)(addr + offset));
1467 break;
1468 default:
1469 *val = in_le32((u32 *)(addr + offset));
1470 break;
1471 }
1472
1473 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1474 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1475 bus->number, hose->first_busno, hose->last_busno,
1476 devfn, offset, len, addr + offset, *val);
1477
1478 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1479 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1480 pr_debug("Got CRS !\n");
1481 if (len != 4 || offset != 0)
1482 return PCIBIOS_DEVICE_NOT_FOUND;
1483 *val = 0xffff0001;
1484 }
1485
1486 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1487
1488 return PCIBIOS_SUCCESSFUL;
1489}
1490
1491static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1492 int offset, int len, u32 val)
1493{
1494 struct pci_controller *hose = pci_bus_to_host(bus);
1495 struct ppc4xx_pciex_port *port =
1496 &ppc4xx_pciex_ports[hose->indirect_type];
1497 void __iomem *addr;
1498 u32 gpl_cfg;
1499
1500 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1501 return PCIBIOS_DEVICE_NOT_FOUND;
1502
1503 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1504
1505 /*
1506 * Reading from configuration space of non-existing device can
1507 * generate transaction errors. For the read duration we suppress
1508 * assertion of machine check exceptions to avoid those.
1509 */
1510 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1511 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1512
1513 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1514 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1515 bus->number, hose->first_busno, hose->last_busno,
1516 devfn, offset, len, addr + offset, val);
1517
1518 switch (len) {
1519 case 1:
1520 out_8((u8 *)(addr + offset), val);
1521 break;
1522 case 2:
1523 out_le16((u16 *)(addr + offset), val);
1524 break;
1525 default:
1526 out_le32((u32 *)(addr + offset), val);
1527 break;
1528 }
1529
1530 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1531
1532 return PCIBIOS_SUCCESSFUL;
1533}
1534
1535static struct pci_ops ppc4xx_pciex_pci_ops =
1536{
1537 .read = ppc4xx_pciex_read_config,
1538 .write = ppc4xx_pciex_write_config,
1539};
1540
1541static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1542 struct pci_controller *hose,
1543 void __iomem *mbase,
1544 u64 plb_addr,
1545 u64 pci_addr,
1546 u64 size,
1547 unsigned int flags,
1548 int index)
1549{
1550 u32 lah, lal, pciah, pcial, sa;
1551
1552 if (!is_power_of_2(size) ||
1553 (index < 2 && size < 0x100000) ||
1554 (index == 2 && size < 0x100) ||
1555 (plb_addr & (size - 1)) != 0) {
1556 printk(KERN_WARNING "%s: Resource out of range\n",
1557 hose->dn->full_name);
1558 return -1;
1559 }
1560
1561 /* Calculate register values */
1562 lah = RES_TO_U32_HIGH(plb_addr);
1563 lal = RES_TO_U32_LOW(plb_addr);
1564 pciah = RES_TO_U32_HIGH(pci_addr);
1565 pcial = RES_TO_U32_LOW(pci_addr);
1566 sa = (0xffffffffu << ilog2(size)) | 0x1;
1567
1568 /* Program register values */
1569 switch (index) {
1570 case 0:
1571 out_le32(mbase + PECFG_POM0LAH, pciah);
1572 out_le32(mbase + PECFG_POM0LAL, pcial);
1573 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1574 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1575 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1576 /* Note that 3 here means enabled | single region */
1577 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1578 break;
1579 case 1:
1580 out_le32(mbase + PECFG_POM1LAH, pciah);
1581 out_le32(mbase + PECFG_POM1LAL, pcial);
1582 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1583 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1584 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1585 /* Note that 3 here means enabled | single region */
1586 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1587 break;
1588 case 2:
1589 out_le32(mbase + PECFG_POM2LAH, pciah);
1590 out_le32(mbase + PECFG_POM2LAL, pcial);
1591 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1592 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1593 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1594 /* Note that 3 here means enabled | IO space !!! */
1595 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3);
1596 break;
1597 }
1598
1599 return 0;
1600}
1601
1602static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1603 struct pci_controller *hose,
1604 void __iomem *mbase)
1605{
1606 int i, j, found_isa_hole = 0;
1607
1608 /* Setup outbound memory windows */
1609 for (i = j = 0; i < 3; i++) {
1610 struct resource *res = &hose->mem_resources[i];
1611
1612 /* we only care about memory windows */
1613 if (!(res->flags & IORESOURCE_MEM))
1614 continue;
1615 if (j > 1) {
1616 printk(KERN_WARNING "%s: Too many ranges\n",
1617 port->node->full_name);
1618 break;
1619 }
1620
1621 /* Configure the resource */
1622 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1623 res->start,
1624 res->start - hose->pci_mem_offset,
1625 resource_size(res),
1626 res->flags,
1627 j) == 0) {
1628 j++;
1629
1630 /* If the resource PCI address is 0 then we have our
1631 * ISA memory hole
1632 */
1633 if (res->start == hose->pci_mem_offset)
1634 found_isa_hole = 1;
1635 }
1636 }
1637
1638 /* Handle ISA memory hole if not already covered */
1639 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1640 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1641 hose->isa_mem_phys, 0,
1642 hose->isa_mem_size, 0, j) == 0)
1643 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
1644 hose->dn->full_name);
1645
1646 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1647 * Note also that it -has- to be region index 2 on this HW
1648 */
1649 if (hose->io_resource.flags & IORESOURCE_IO)
1650 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1651 hose->io_base_phys, 0,
1652 0x10000, IORESOURCE_IO, 2);
1653}
1654
1655static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1656 struct pci_controller *hose,
1657 void __iomem *mbase,
1658 struct resource *res)
1659{
1660 resource_size_t size = resource_size(res);
1661 u64 sa;
1662
1663 if (port->endpoint) {
1664 resource_size_t ep_addr = 0;
1665 resource_size_t ep_size = 32 << 20;
1666
1667 /* Currently we map a fixed 64MByte window to PLB address
1668 * 0 (SDRAM). This should probably be configurable via a dts
1669 * property.
1670 */
1671
1672 /* Calculate window size */
1673 sa = (0xffffffffffffffffull << ilog2(ep_size));
1674
1675 /* Setup BAR0 */
1676 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1677 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1678 PCI_BASE_ADDRESS_MEM_TYPE_64);
1679
1680 /* Disable BAR1 & BAR2 */
1681 out_le32(mbase + PECFG_BAR1MPA, 0);
1682 out_le32(mbase + PECFG_BAR2HMPA, 0);
1683 out_le32(mbase + PECFG_BAR2LMPA, 0);
1684
1685 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1686 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1687
1688 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1689 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1690 } else {
1691 /* Calculate window size */
1692 sa = (0xffffffffffffffffull << ilog2(size));
1693 if (res->flags & IORESOURCE_PREFETCH)
1694 sa |= 0x8;
1695
1696 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1697 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1698
1699 /* The setup of the split looks weird to me ... let's see
1700 * if it works
1701 */
1702 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1703 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1704 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1705 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1706 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1707 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1708
1709 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1710 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1711 }
1712
1713 /* Enable inbound mapping */
1714 out_le32(mbase + PECFG_PIMEN, 0x1);
1715
1716 /* Enable I/O, Mem, and Busmaster cycles */
1717 out_le16(mbase + PCI_COMMAND,
1718 in_le16(mbase + PCI_COMMAND) |
1719 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1720}
1721
1722static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1723{
1724 struct resource dma_window;
1725 struct pci_controller *hose = NULL;
1726 const int *bus_range;
1727 int primary = 0, busses;
1728 void __iomem *mbase = NULL, *cfg_data = NULL;
1729 const u32 *pval;
1730 u32 val;
1731
1732 /* Check if primary bridge */
1733 if (of_get_property(port->node, "primary", NULL))
1734 primary = 1;
1735
1736 /* Get bus range if any */
1737 bus_range = of_get_property(port->node, "bus-range", NULL);
1738
1739 /* Allocate the host controller data structure */
1740 hose = pcibios_alloc_controller(port->node);
1741 if (!hose)
1742 goto fail;
1743
1744 /* We stick the port number in "indirect_type" so the config space
1745 * ops can retrieve the port data structure easily
1746 */
1747 hose->indirect_type = port->index;
1748
1749 /* Get bus range */
1750 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1751 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1752
1753 /* Because of how big mapping the config space is (1M per bus), we
1754 * limit how many busses we support. In the long run, we could replace
1755 * that with something akin to kmap_atomic instead. We set aside 1 bus
1756 * for the host itself too.
1757 */
1758 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1759 if (busses > MAX_PCIE_BUS_MAPPED) {
1760 busses = MAX_PCIE_BUS_MAPPED;
1761 hose->last_busno = hose->first_busno + busses;
1762 }
1763
1764 if (!port->endpoint) {
1765 /* Only map the external config space in cfg_data for
1766 * PCIe root-complexes. External space is 1M per bus
1767 */
1768 cfg_data = ioremap(port->cfg_space.start +
1769 (hose->first_busno + 1) * 0x100000,
1770 busses * 0x100000);
1771 if (cfg_data == NULL) {
1772 printk(KERN_ERR "%s: Can't map external config space !",
1773 port->node->full_name);
1774 goto fail;
1775 }
1776 hose->cfg_data = cfg_data;
1777 }
1778
1779 /* Always map the host config space in cfg_addr.
1780 * Internal space is 4K
1781 */
1782 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1783 if (mbase == NULL) {
1784 printk(KERN_ERR "%s: Can't map internal config space !",
1785 port->node->full_name);
1786 goto fail;
1787 }
1788 hose->cfg_addr = mbase;
1789
1790 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1791 hose->first_busno, hose->last_busno);
1792 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1793 hose->cfg_addr, hose->cfg_data);
1794
1795 /* Setup config space */
1796 hose->ops = &ppc4xx_pciex_pci_ops;
1797 port->hose = hose;
1798 mbase = (void __iomem *)hose->cfg_addr;
1799
1800 if (!port->endpoint) {
1801 /*
1802 * Set bus numbers on our root port
1803 */
1804 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1805 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1806 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1807 }
1808
1809 /*
1810 * OMRs are already reset, also disable PIMs
1811 */
1812 out_le32(mbase + PECFG_PIMEN, 0);
1813
1814 /* Parse outbound mapping resources */
1815 pci_process_bridge_OF_ranges(hose, port->node, primary);
1816
1817 /* Parse inbound mapping resources */
1818 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1819 goto fail;
1820
1821 /* Configure outbound ranges POMs */
1822 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1823
1824 /* Configure inbound ranges PIMs */
1825 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1826
1827 /* The root complex doesn't show up if we don't set some vendor
1828 * and device IDs into it. The defaults below are the same bogus
1829 * one that the initial code in arch/ppc had. This can be
1830 * overwritten by setting the "vendor-id/device-id" properties
1831 * in the pciex node.
1832 */
1833
1834 /* Get the (optional) vendor-/device-id from the device-tree */
1835 pval = of_get_property(port->node, "vendor-id", NULL);
1836 if (pval) {
1837 val = *pval;
1838 } else {
1839 if (!port->endpoint)
1840 val = 0xaaa0 + port->index;
1841 else
1842 val = 0xeee0 + port->index;
1843 }
1844 out_le16(mbase + 0x200, val);
1845
1846 pval = of_get_property(port->node, "device-id", NULL);
1847 if (pval) {
1848 val = *pval;
1849 } else {
1850 if (!port->endpoint)
1851 val = 0xbed0 + port->index;
1852 else
1853 val = 0xfed0 + port->index;
1854 }
1855 out_le16(mbase + 0x202, val);
1856
1857 if (!port->endpoint) {
1858 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1859 out_le32(mbase + 0x208, 0x06040001);
1860
1861 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1862 port->index);
1863 } else {
1864 /* Set Class Code to Processor/PPC */
1865 out_le32(mbase + 0x208, 0x0b200001);
1866
1867 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1868 port->index);
1869 }
1870
1871 return;
1872 fail:
1873 if (hose)
1874 pcibios_free_controller(hose);
1875 if (cfg_data)
1876 iounmap(cfg_data);
1877 if (mbase)
1878 iounmap(mbase);
1879}
1880
1881static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1882{
1883 struct ppc4xx_pciex_port *port;
1884 const u32 *pval;
1885 int portno;
1886 unsigned int dcrs;
1887 const char *val;
1888
1889 /* First, proceed to core initialization as we assume there's
1890 * only one PCIe core in the system
1891 */
1892 if (ppc4xx_pciex_check_core_init(np))
1893 return;
1894
1895 /* Get the port number from the device-tree */
1896 pval = of_get_property(np, "port", NULL);
1897 if (pval == NULL) {
1898 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1899 np->full_name);
1900 return;
1901 }
1902 portno = *pval;
1903 if (portno >= ppc4xx_pciex_port_count) {
1904 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1905 np->full_name);
1906 return;
1907 }
1908 port = &ppc4xx_pciex_ports[portno];
1909 port->index = portno;
1910
1911 /*
1912 * Check if device is enabled
1913 */
1914 if (!of_device_is_available(np)) {
1915 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1916 return;
1917 }
1918
1919 port->node = of_node_get(np);
1920 pval = of_get_property(np, "sdr-base", NULL);
1921 if (pval == NULL) {
1922 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1923 np->full_name);
1924 return;
1925 }
1926 port->sdr_base = *pval;
1927
1928 /* Check if device_type property is set to "pci" or "pci-endpoint".
1929 * Resulting from this setup this PCIe port will be configured
1930 * as root-complex or as endpoint.
1931 */
1932 val = of_get_property(port->node, "device_type", NULL);
1933 if (!strcmp(val, "pci-endpoint")) {
1934 port->endpoint = 1;
1935 } else if (!strcmp(val, "pci")) {
1936 port->endpoint = 0;
1937 } else {
1938 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1939 np->full_name);
1940 return;
1941 }
1942
1943 /* Fetch config space registers address */
1944 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1945 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1946 np->full_name);
1947 return;
1948 }
1949 /* Fetch host bridge internal registers address */
1950 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1951 printk(KERN_ERR "%s: Can't get UTL register base !",
1952 np->full_name);
1953 return;
1954 }
1955
1956 /* Map DCRs */
1957 dcrs = dcr_resource_start(np, 0);
1958 if (dcrs == 0) {
1959 printk(KERN_ERR "%s: Can't get DCR register base !",
1960 np->full_name);
1961 return;
1962 }
1963 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1964
1965 /* Initialize the port specific registers */
1966 if (ppc4xx_pciex_port_init(port)) {
1967 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1968 return;
1969 }
1970
1971 /* Setup the linux hose data structure */
1972 ppc4xx_pciex_port_setup_hose(port);
1973}
1974
1975#endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1976
1977static int __init ppc4xx_pci_find_bridges(void)
1978{
1979 struct device_node *np;
1980
1981 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
1982
1983#ifdef CONFIG_PPC4xx_PCI_EXPRESS
1984 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1985 ppc4xx_probe_pciex_bridge(np);
1986#endif
1987 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1988 ppc4xx_probe_pcix_bridge(np);
1989 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1990 ppc4xx_probe_pci_bridge(np);
1991
1992 return 0;
1993}
1994arch_initcall(ppc4xx_pci_find_bridges);
1995