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1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
14 */
15#include <plat/omap_hwmod.h>
16#include <mach/irqs.h>
17#include <plat/cpu.h>
18#include <plat/dma.h>
19#include <plat/serial.h>
20#include <plat/i2c.h>
21#include <plat/gpio.h>
22#include <plat/mcspi.h>
23#include <plat/dmtimer.h>
24#include <plat/l3_2xxx.h>
25#include <plat/l4_2xxx.h>
26#include <plat/mmc.h>
27
28#include "omap_hwmod_common_data.h"
29
30#include "cm-regbits-24xx.h"
31#include "prm-regbits-24xx.h"
32#include "wd_timer.h"
33
34/*
35 * OMAP2420 hardware module integration data
36 *
37 * All of the data in this section should be autogeneratable from the
38 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
40 * elsewhere.
41 */
42
43/*
44 * IP blocks
45 */
46
47/* IVA1 (IVA1) */
48static struct omap_hwmod_class iva1_hwmod_class = {
49 .name = "iva1",
50};
51
52static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
53 { .name = "iva", .rst_shift = 8 },
54};
55
56static struct omap_hwmod omap2420_iva_hwmod = {
57 .name = "iva",
58 .class = &iva1_hwmod_class,
59 .clkdm_name = "iva1_clkdm",
60 .rst_lines = omap2420_iva_resets,
61 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
62 .main_clk = "iva1_ifck",
63};
64
65/* DSP */
66static struct omap_hwmod_class dsp_hwmod_class = {
67 .name = "dsp",
68};
69
70static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
71 { .name = "logic", .rst_shift = 0 },
72 { .name = "mmu", .rst_shift = 1 },
73};
74
75static struct omap_hwmod omap2420_dsp_hwmod = {
76 .name = "dsp",
77 .class = &dsp_hwmod_class,
78 .clkdm_name = "dsp_clkdm",
79 .rst_lines = omap2420_dsp_resets,
80 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
81 .main_clk = "dsp_fck",
82};
83
84/* I2C common */
85static struct omap_hwmod_class_sysconfig i2c_sysc = {
86 .rev_offs = 0x00,
87 .sysc_offs = 0x20,
88 .syss_offs = 0x10,
89 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
90 .sysc_fields = &omap_hwmod_sysc_type1,
91};
92
93static struct omap_hwmod_class i2c_class = {
94 .name = "i2c",
95 .sysc = &i2c_sysc,
96 .rev = OMAP_I2C_IP_VERSION_1,
97 .reset = &omap_i2c_reset,
98};
99
100static struct omap_i2c_dev_attr i2c_dev_attr = {
101 .flags = OMAP_I2C_FLAG_NO_FIFO |
102 OMAP_I2C_FLAG_SIMPLE_CLOCK |
103 OMAP_I2C_FLAG_16BIT_DATA_REG |
104 OMAP_I2C_FLAG_BUS_SHIFT_2,
105};
106
107/* I2C1 */
108static struct omap_hwmod omap2420_i2c1_hwmod = {
109 .name = "i2c1",
110 .mpu_irqs = omap2_i2c1_mpu_irqs,
111 .sdma_reqs = omap2_i2c1_sdma_reqs,
112 .main_clk = "i2c1_fck",
113 .prcm = {
114 .omap2 = {
115 .module_offs = CORE_MOD,
116 .prcm_reg_id = 1,
117 .module_bit = OMAP2420_EN_I2C1_SHIFT,
118 .idlest_reg_id = 1,
119 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
120 },
121 },
122 .class = &i2c_class,
123 .dev_attr = &i2c_dev_attr,
124 .flags = HWMOD_16BIT_REG,
125};
126
127/* I2C2 */
128static struct omap_hwmod omap2420_i2c2_hwmod = {
129 .name = "i2c2",
130 .mpu_irqs = omap2_i2c2_mpu_irqs,
131 .sdma_reqs = omap2_i2c2_sdma_reqs,
132 .main_clk = "i2c2_fck",
133 .prcm = {
134 .omap2 = {
135 .module_offs = CORE_MOD,
136 .prcm_reg_id = 1,
137 .module_bit = OMAP2420_EN_I2C2_SHIFT,
138 .idlest_reg_id = 1,
139 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
140 },
141 },
142 .class = &i2c_class,
143 .dev_attr = &i2c_dev_attr,
144 .flags = HWMOD_16BIT_REG,
145};
146
147/* dma attributes */
148static struct omap_dma_dev_attr dma_dev_attr = {
149 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
150 IS_CSSA_32 | IS_CDSA_32,
151 .lch_count = 32,
152};
153
154static struct omap_hwmod omap2420_dma_system_hwmod = {
155 .name = "dma",
156 .class = &omap2xxx_dma_hwmod_class,
157 .mpu_irqs = omap2_dma_system_irqs,
158 .main_clk = "core_l3_ck",
159 .dev_attr = &dma_dev_attr,
160 .flags = HWMOD_NO_IDLEST,
161};
162
163/* mailbox */
164static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
165 { .name = "dsp", .irq = 26 },
166 { .name = "iva", .irq = 34 },
167 { .irq = -1 }
168};
169
170static struct omap_hwmod omap2420_mailbox_hwmod = {
171 .name = "mailbox",
172 .class = &omap2xxx_mailbox_hwmod_class,
173 .mpu_irqs = omap2420_mailbox_irqs,
174 .main_clk = "mailboxes_ick",
175 .prcm = {
176 .omap2 = {
177 .prcm_reg_id = 1,
178 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
179 .module_offs = CORE_MOD,
180 .idlest_reg_id = 1,
181 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
182 },
183 },
184};
185
186/*
187 * 'mcbsp' class
188 * multi channel buffered serial port controller
189 */
190
191static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
192 .name = "mcbsp",
193};
194
195/* mcbsp1 */
196static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
197 { .name = "tx", .irq = 59 },
198 { .name = "rx", .irq = 60 },
199 { .irq = -1 }
200};
201
202static struct omap_hwmod omap2420_mcbsp1_hwmod = {
203 .name = "mcbsp1",
204 .class = &omap2420_mcbsp_hwmod_class,
205 .mpu_irqs = omap2420_mcbsp1_irqs,
206 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
207 .main_clk = "mcbsp1_fck",
208 .prcm = {
209 .omap2 = {
210 .prcm_reg_id = 1,
211 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
212 .module_offs = CORE_MOD,
213 .idlest_reg_id = 1,
214 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
215 },
216 },
217};
218
219/* mcbsp2 */
220static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
221 { .name = "tx", .irq = 62 },
222 { .name = "rx", .irq = 63 },
223 { .irq = -1 }
224};
225
226static struct omap_hwmod omap2420_mcbsp2_hwmod = {
227 .name = "mcbsp2",
228 .class = &omap2420_mcbsp_hwmod_class,
229 .mpu_irqs = omap2420_mcbsp2_irqs,
230 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
231 .main_clk = "mcbsp2_fck",
232 .prcm = {
233 .omap2 = {
234 .prcm_reg_id = 1,
235 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
236 .module_offs = CORE_MOD,
237 .idlest_reg_id = 1,
238 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
239 },
240 },
241};
242
243static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
244 .rev_offs = 0x3c,
245 .sysc_offs = 0x64,
246 .syss_offs = 0x68,
247 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
248 .sysc_fields = &omap_hwmod_sysc_type1,
249};
250
251static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
252 .name = "msdi",
253 .sysc = &omap2420_msdi_sysc,
254 .reset = &omap_msdi_reset,
255};
256
257/* msdi1 */
258static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
259 { .irq = 83 },
260 { .irq = -1 }
261};
262
263static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
264 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
265 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
266 { .dma_req = -1 }
267};
268
269static struct omap_hwmod omap2420_msdi1_hwmod = {
270 .name = "msdi1",
271 .class = &omap2420_msdi_hwmod_class,
272 .mpu_irqs = omap2420_msdi1_irqs,
273 .sdma_reqs = omap2420_msdi1_sdma_reqs,
274 .main_clk = "mmc_fck",
275 .prcm = {
276 .omap2 = {
277 .prcm_reg_id = 1,
278 .module_bit = OMAP2420_EN_MMC_SHIFT,
279 .module_offs = CORE_MOD,
280 .idlest_reg_id = 1,
281 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
282 },
283 },
284 .flags = HWMOD_16BIT_REG,
285};
286
287/* HDQ1W/1-wire */
288static struct omap_hwmod omap2420_hdq1w_hwmod = {
289 .name = "hdq1w",
290 .mpu_irqs = omap2_hdq1w_mpu_irqs,
291 .main_clk = "hdq_fck",
292 .prcm = {
293 .omap2 = {
294 .module_offs = CORE_MOD,
295 .prcm_reg_id = 1,
296 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
297 .idlest_reg_id = 1,
298 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
299 },
300 },
301 .class = &omap2_hdq1w_class,
302};
303
304/*
305 * interfaces
306 */
307
308/* L4 CORE -> I2C1 interface */
309static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
310 .master = &omap2xxx_l4_core_hwmod,
311 .slave = &omap2420_i2c1_hwmod,
312 .clk = "i2c1_ick",
313 .addr = omap2_i2c1_addr_space,
314 .user = OCP_USER_MPU | OCP_USER_SDMA,
315};
316
317/* L4 CORE -> I2C2 interface */
318static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
319 .master = &omap2xxx_l4_core_hwmod,
320 .slave = &omap2420_i2c2_hwmod,
321 .clk = "i2c2_ick",
322 .addr = omap2_i2c2_addr_space,
323 .user = OCP_USER_MPU | OCP_USER_SDMA,
324};
325
326/* IVA <- L3 interface */
327static struct omap_hwmod_ocp_if omap2420_l3__iva = {
328 .master = &omap2xxx_l3_main_hwmod,
329 .slave = &omap2420_iva_hwmod,
330 .clk = "core_l3_ck",
331 .user = OCP_USER_MPU | OCP_USER_SDMA,
332};
333
334/* DSP <- L3 interface */
335static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
336 .master = &omap2xxx_l3_main_hwmod,
337 .slave = &omap2420_dsp_hwmod,
338 .clk = "dsp_ick",
339 .user = OCP_USER_MPU | OCP_USER_SDMA,
340};
341
342static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
343 {
344 .pa_start = 0x48028000,
345 .pa_end = 0x48028000 + SZ_1K - 1,
346 .flags = ADDR_TYPE_RT
347 },
348 { }
349};
350
351/* l4_wkup -> timer1 */
352static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
353 .master = &omap2xxx_l4_wkup_hwmod,
354 .slave = &omap2xxx_timer1_hwmod,
355 .clk = "gpt1_ick",
356 .addr = omap2420_timer1_addrs,
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
358};
359
360/* l4_wkup -> wd_timer2 */
361static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
362 {
363 .pa_start = 0x48022000,
364 .pa_end = 0x4802207f,
365 .flags = ADDR_TYPE_RT
366 },
367 { }
368};
369
370static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
371 .master = &omap2xxx_l4_wkup_hwmod,
372 .slave = &omap2xxx_wd_timer2_hwmod,
373 .clk = "mpu_wdt_ick",
374 .addr = omap2420_wd_timer2_addrs,
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376};
377
378/* l4_wkup -> gpio1 */
379static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
380 {
381 .pa_start = 0x48018000,
382 .pa_end = 0x480181ff,
383 .flags = ADDR_TYPE_RT
384 },
385 { }
386};
387
388static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
389 .master = &omap2xxx_l4_wkup_hwmod,
390 .slave = &omap2xxx_gpio1_hwmod,
391 .clk = "gpios_ick",
392 .addr = omap2420_gpio1_addr_space,
393 .user = OCP_USER_MPU | OCP_USER_SDMA,
394};
395
396/* l4_wkup -> gpio2 */
397static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
398 {
399 .pa_start = 0x4801a000,
400 .pa_end = 0x4801a1ff,
401 .flags = ADDR_TYPE_RT
402 },
403 { }
404};
405
406static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
407 .master = &omap2xxx_l4_wkup_hwmod,
408 .slave = &omap2xxx_gpio2_hwmod,
409 .clk = "gpios_ick",
410 .addr = omap2420_gpio2_addr_space,
411 .user = OCP_USER_MPU | OCP_USER_SDMA,
412};
413
414/* l4_wkup -> gpio3 */
415static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
416 {
417 .pa_start = 0x4801c000,
418 .pa_end = 0x4801c1ff,
419 .flags = ADDR_TYPE_RT
420 },
421 { }
422};
423
424static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
425 .master = &omap2xxx_l4_wkup_hwmod,
426 .slave = &omap2xxx_gpio3_hwmod,
427 .clk = "gpios_ick",
428 .addr = omap2420_gpio3_addr_space,
429 .user = OCP_USER_MPU | OCP_USER_SDMA,
430};
431
432/* l4_wkup -> gpio4 */
433static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
434 {
435 .pa_start = 0x4801e000,
436 .pa_end = 0x4801e1ff,
437 .flags = ADDR_TYPE_RT
438 },
439 { }
440};
441
442static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
443 .master = &omap2xxx_l4_wkup_hwmod,
444 .slave = &omap2xxx_gpio4_hwmod,
445 .clk = "gpios_ick",
446 .addr = omap2420_gpio4_addr_space,
447 .user = OCP_USER_MPU | OCP_USER_SDMA,
448};
449
450/* dma_system -> L3 */
451static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
452 .master = &omap2420_dma_system_hwmod,
453 .slave = &omap2xxx_l3_main_hwmod,
454 .clk = "core_l3_ck",
455 .user = OCP_USER_MPU | OCP_USER_SDMA,
456};
457
458/* l4_core -> dma_system */
459static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
460 .master = &omap2xxx_l4_core_hwmod,
461 .slave = &omap2420_dma_system_hwmod,
462 .clk = "sdma_ick",
463 .addr = omap2_dma_system_addrs,
464 .user = OCP_USER_MPU | OCP_USER_SDMA,
465};
466
467/* l4_core -> mailbox */
468static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
469 .master = &omap2xxx_l4_core_hwmod,
470 .slave = &omap2420_mailbox_hwmod,
471 .addr = omap2_mailbox_addrs,
472 .user = OCP_USER_MPU | OCP_USER_SDMA,
473};
474
475/* l4_core -> mcbsp1 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
477 .master = &omap2xxx_l4_core_hwmod,
478 .slave = &omap2420_mcbsp1_hwmod,
479 .clk = "mcbsp1_ick",
480 .addr = omap2_mcbsp1_addrs,
481 .user = OCP_USER_MPU | OCP_USER_SDMA,
482};
483
484/* l4_core -> mcbsp2 */
485static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
486 .master = &omap2xxx_l4_core_hwmod,
487 .slave = &omap2420_mcbsp2_hwmod,
488 .clk = "mcbsp2_ick",
489 .addr = omap2xxx_mcbsp2_addrs,
490 .user = OCP_USER_MPU | OCP_USER_SDMA,
491};
492
493static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
494 {
495 .pa_start = 0x4809c000,
496 .pa_end = 0x4809c000 + SZ_128 - 1,
497 .flags = ADDR_TYPE_RT,
498 },
499 { }
500};
501
502/* l4_core -> msdi1 */
503static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
504 .master = &omap2xxx_l4_core_hwmod,
505 .slave = &omap2420_msdi1_hwmod,
506 .clk = "mmc_ick",
507 .addr = omap2420_msdi1_addrs,
508 .user = OCP_USER_MPU | OCP_USER_SDMA,
509};
510
511/* l4_core -> hdq1w interface */
512static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
513 .master = &omap2xxx_l4_core_hwmod,
514 .slave = &omap2420_hdq1w_hwmod,
515 .clk = "hdq_ick",
516 .addr = omap2_hdq1w_addr_space,
517 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
519};
520
521
522/* l4_wkup -> 32ksync_counter */
523static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
524 {
525 .pa_start = 0x48004000,
526 .pa_end = 0x4800401f,
527 .flags = ADDR_TYPE_RT
528 },
529 { }
530};
531
532static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
533 .master = &omap2xxx_l4_wkup_hwmod,
534 .slave = &omap2xxx_counter_32k_hwmod,
535 .clk = "sync_32k_ick",
536 .addr = omap2420_counter_32k_addrs,
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
538};
539
540static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
541 &omap2xxx_l3_main__l4_core,
542 &omap2xxx_mpu__l3_main,
543 &omap2xxx_dss__l3,
544 &omap2xxx_l4_core__mcspi1,
545 &omap2xxx_l4_core__mcspi2,
546 &omap2xxx_l4_core__l4_wkup,
547 &omap2_l4_core__uart1,
548 &omap2_l4_core__uart2,
549 &omap2_l4_core__uart3,
550 &omap2420_l4_core__i2c1,
551 &omap2420_l4_core__i2c2,
552 &omap2420_l3__iva,
553 &omap2420_l3__dsp,
554 &omap2420_l4_wkup__timer1,
555 &omap2xxx_l4_core__timer2,
556 &omap2xxx_l4_core__timer3,
557 &omap2xxx_l4_core__timer4,
558 &omap2xxx_l4_core__timer5,
559 &omap2xxx_l4_core__timer6,
560 &omap2xxx_l4_core__timer7,
561 &omap2xxx_l4_core__timer8,
562 &omap2xxx_l4_core__timer9,
563 &omap2xxx_l4_core__timer10,
564 &omap2xxx_l4_core__timer11,
565 &omap2xxx_l4_core__timer12,
566 &omap2420_l4_wkup__wd_timer2,
567 &omap2xxx_l4_core__dss,
568 &omap2xxx_l4_core__dss_dispc,
569 &omap2xxx_l4_core__dss_rfbi,
570 &omap2xxx_l4_core__dss_venc,
571 &omap2420_l4_wkup__gpio1,
572 &omap2420_l4_wkup__gpio2,
573 &omap2420_l4_wkup__gpio3,
574 &omap2420_l4_wkup__gpio4,
575 &omap2420_dma_system__l3,
576 &omap2420_l4_core__dma_system,
577 &omap2420_l4_core__mailbox,
578 &omap2420_l4_core__mcbsp1,
579 &omap2420_l4_core__mcbsp2,
580 &omap2420_l4_core__msdi1,
581 &omap2420_l4_core__hdq1w,
582 &omap2420_l4_wkup__counter_32k,
583 NULL,
584};
585
586int __init omap2420_hwmod_init(void)
587{
588 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
589}
1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <plat/omap_hwmod.h>
15#include <mach/irqs.h>
16#include <plat/cpu.h>
17#include <plat/dma.h>
18#include <plat/serial.h>
19#include <plat/i2c.h>
20#include <plat/gpio.h>
21#include <plat/mcspi.h>
22#include <plat/dmtimer.h>
23#include <plat/l3_2xxx.h>
24#include <plat/l4_2xxx.h>
25
26#include "omap_hwmod_common_data.h"
27
28#include "cm-regbits-24xx.h"
29#include "prm-regbits-24xx.h"
30#include "wd_timer.h"
31
32/*
33 * OMAP2420 hardware module integration data
34 *
35 * ALl of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere.
39 */
40
41static struct omap_hwmod omap2420_mpu_hwmod;
42static struct omap_hwmod omap2420_iva_hwmod;
43static struct omap_hwmod omap2420_l3_main_hwmod;
44static struct omap_hwmod omap2420_l4_core_hwmod;
45static struct omap_hwmod omap2420_dss_core_hwmod;
46static struct omap_hwmod omap2420_dss_dispc_hwmod;
47static struct omap_hwmod omap2420_dss_rfbi_hwmod;
48static struct omap_hwmod omap2420_dss_venc_hwmod;
49static struct omap_hwmod omap2420_wd_timer2_hwmod;
50static struct omap_hwmod omap2420_gpio1_hwmod;
51static struct omap_hwmod omap2420_gpio2_hwmod;
52static struct omap_hwmod omap2420_gpio3_hwmod;
53static struct omap_hwmod omap2420_gpio4_hwmod;
54static struct omap_hwmod omap2420_dma_system_hwmod;
55static struct omap_hwmod omap2420_mcspi1_hwmod;
56static struct omap_hwmod omap2420_mcspi2_hwmod;
57
58/* L3 -> L4_CORE interface */
59static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
60 .master = &omap2420_l3_main_hwmod,
61 .slave = &omap2420_l4_core_hwmod,
62 .user = OCP_USER_MPU | OCP_USER_SDMA,
63};
64
65/* MPU -> L3 interface */
66static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
67 .master = &omap2420_mpu_hwmod,
68 .slave = &omap2420_l3_main_hwmod,
69 .user = OCP_USER_MPU,
70};
71
72/* Slave interfaces on the L3 interconnect */
73static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
74 &omap2420_mpu__l3_main,
75};
76
77/* DSS -> l3 */
78static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
79 .master = &omap2420_dss_core_hwmod,
80 .slave = &omap2420_l3_main_hwmod,
81 .fw = {
82 .omap2 = {
83 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
84 .flags = OMAP_FIREWALL_L3,
85 }
86 },
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88};
89
90/* Master interfaces on the L3 interconnect */
91static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
92 &omap2420_l3_main__l4_core,
93};
94
95/* L3 */
96static struct omap_hwmod omap2420_l3_main_hwmod = {
97 .name = "l3_main",
98 .class = &l3_hwmod_class,
99 .masters = omap2420_l3_main_masters,
100 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
101 .slaves = omap2420_l3_main_slaves,
102 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
104 .flags = HWMOD_NO_IDLEST,
105};
106
107static struct omap_hwmod omap2420_l4_wkup_hwmod;
108static struct omap_hwmod omap2420_uart1_hwmod;
109static struct omap_hwmod omap2420_uart2_hwmod;
110static struct omap_hwmod omap2420_uart3_hwmod;
111static struct omap_hwmod omap2420_i2c1_hwmod;
112static struct omap_hwmod omap2420_i2c2_hwmod;
113static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod;
115
116/* l4 core -> mcspi1 interface */
117static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
118 .master = &omap2420_l4_core_hwmod,
119 .slave = &omap2420_mcspi1_hwmod,
120 .clk = "mcspi1_ick",
121 .addr = omap2_mcspi1_addr_space,
122 .user = OCP_USER_MPU | OCP_USER_SDMA,
123};
124
125/* l4 core -> mcspi2 interface */
126static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
127 .master = &omap2420_l4_core_hwmod,
128 .slave = &omap2420_mcspi2_hwmod,
129 .clk = "mcspi2_ick",
130 .addr = omap2_mcspi2_addr_space,
131 .user = OCP_USER_MPU | OCP_USER_SDMA,
132};
133
134/* L4_CORE -> L4_WKUP interface */
135static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
136 .master = &omap2420_l4_core_hwmod,
137 .slave = &omap2420_l4_wkup_hwmod,
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139};
140
141/* L4 CORE -> UART1 interface */
142static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
143 .master = &omap2420_l4_core_hwmod,
144 .slave = &omap2420_uart1_hwmod,
145 .clk = "uart1_ick",
146 .addr = omap2xxx_uart1_addr_space,
147 .user = OCP_USER_MPU | OCP_USER_SDMA,
148};
149
150/* L4 CORE -> UART2 interface */
151static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
152 .master = &omap2420_l4_core_hwmod,
153 .slave = &omap2420_uart2_hwmod,
154 .clk = "uart2_ick",
155 .addr = omap2xxx_uart2_addr_space,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
157};
158
159/* L4 PER -> UART3 interface */
160static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
161 .master = &omap2420_l4_core_hwmod,
162 .slave = &omap2420_uart3_hwmod,
163 .clk = "uart3_ick",
164 .addr = omap2xxx_uart3_addr_space,
165 .user = OCP_USER_MPU | OCP_USER_SDMA,
166};
167
168/* L4 CORE -> I2C1 interface */
169static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
170 .master = &omap2420_l4_core_hwmod,
171 .slave = &omap2420_i2c1_hwmod,
172 .clk = "i2c1_ick",
173 .addr = omap2_i2c1_addr_space,
174 .user = OCP_USER_MPU | OCP_USER_SDMA,
175};
176
177/* L4 CORE -> I2C2 interface */
178static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
179 .master = &omap2420_l4_core_hwmod,
180 .slave = &omap2420_i2c2_hwmod,
181 .clk = "i2c2_ick",
182 .addr = omap2_i2c2_addr_space,
183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184};
185
186/* Slave interfaces on the L4_CORE interconnect */
187static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
188 &omap2420_l3_main__l4_core,
189};
190
191/* Master interfaces on the L4_CORE interconnect */
192static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
193 &omap2420_l4_core__l4_wkup,
194 &omap2_l4_core__uart1,
195 &omap2_l4_core__uart2,
196 &omap2_l4_core__uart3,
197 &omap2420_l4_core__i2c1,
198 &omap2420_l4_core__i2c2
199};
200
201/* L4 CORE */
202static struct omap_hwmod omap2420_l4_core_hwmod = {
203 .name = "l4_core",
204 .class = &l4_hwmod_class,
205 .masters = omap2420_l4_core_masters,
206 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
207 .slaves = omap2420_l4_core_slaves,
208 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
209 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
210 .flags = HWMOD_NO_IDLEST,
211};
212
213/* Slave interfaces on the L4_WKUP interconnect */
214static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
215 &omap2420_l4_core__l4_wkup,
216};
217
218/* Master interfaces on the L4_WKUP interconnect */
219static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
220};
221
222/* L4 WKUP */
223static struct omap_hwmod omap2420_l4_wkup_hwmod = {
224 .name = "l4_wkup",
225 .class = &l4_hwmod_class,
226 .masters = omap2420_l4_wkup_masters,
227 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
228 .slaves = omap2420_l4_wkup_slaves,
229 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
231 .flags = HWMOD_NO_IDLEST,
232};
233
234/* Master interfaces on the MPU device */
235static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
236 &omap2420_mpu__l3_main,
237};
238
239/* MPU */
240static struct omap_hwmod omap2420_mpu_hwmod = {
241 .name = "mpu",
242 .class = &mpu_hwmod_class,
243 .main_clk = "mpu_ck",
244 .masters = omap2420_mpu_masters,
245 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
247};
248
249/*
250 * IVA1 interface data
251 */
252
253/* IVA <- L3 interface */
254static struct omap_hwmod_ocp_if omap2420_l3__iva = {
255 .master = &omap2420_l3_main_hwmod,
256 .slave = &omap2420_iva_hwmod,
257 .clk = "iva1_ifck",
258 .user = OCP_USER_MPU | OCP_USER_SDMA,
259};
260
261static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
262 &omap2420_l3__iva,
263};
264
265/*
266 * IVA2 (IVA2)
267 */
268
269static struct omap_hwmod omap2420_iva_hwmod = {
270 .name = "iva",
271 .class = &iva_hwmod_class,
272 .masters = omap2420_iva_masters,
273 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
275};
276
277/* timer1 */
278static struct omap_hwmod omap2420_timer1_hwmod;
279
280static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
281 {
282 .pa_start = 0x48028000,
283 .pa_end = 0x48028000 + SZ_1K - 1,
284 .flags = ADDR_TYPE_RT
285 },
286 { }
287};
288
289/* l4_wkup -> timer1 */
290static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
291 .master = &omap2420_l4_wkup_hwmod,
292 .slave = &omap2420_timer1_hwmod,
293 .clk = "gpt1_ick",
294 .addr = omap2420_timer1_addrs,
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296};
297
298/* timer1 slave port */
299static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
300 &omap2420_l4_wkup__timer1,
301};
302
303/* timer1 hwmod */
304static struct omap_hwmod omap2420_timer1_hwmod = {
305 .name = "timer1",
306 .mpu_irqs = omap2_timer1_mpu_irqs,
307 .main_clk = "gpt1_fck",
308 .prcm = {
309 .omap2 = {
310 .prcm_reg_id = 1,
311 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
312 .module_offs = WKUP_MOD,
313 .idlest_reg_id = 1,
314 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
315 },
316 },
317 .slaves = omap2420_timer1_slaves,
318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
319 .class = &omap2xxx_timer_hwmod_class,
320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
321};
322
323/* timer2 */
324static struct omap_hwmod omap2420_timer2_hwmod;
325
326/* l4_core -> timer2 */
327static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
328 .master = &omap2420_l4_core_hwmod,
329 .slave = &omap2420_timer2_hwmod,
330 .clk = "gpt2_ick",
331 .addr = omap2xxx_timer2_addrs,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333};
334
335/* timer2 slave port */
336static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
337 &omap2420_l4_core__timer2,
338};
339
340/* timer2 hwmod */
341static struct omap_hwmod omap2420_timer2_hwmod = {
342 .name = "timer2",
343 .mpu_irqs = omap2_timer2_mpu_irqs,
344 .main_clk = "gpt2_fck",
345 .prcm = {
346 .omap2 = {
347 .prcm_reg_id = 1,
348 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
349 .module_offs = CORE_MOD,
350 .idlest_reg_id = 1,
351 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
352 },
353 },
354 .slaves = omap2420_timer2_slaves,
355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
356 .class = &omap2xxx_timer_hwmod_class,
357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
358};
359
360/* timer3 */
361static struct omap_hwmod omap2420_timer3_hwmod;
362
363/* l4_core -> timer3 */
364static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
365 .master = &omap2420_l4_core_hwmod,
366 .slave = &omap2420_timer3_hwmod,
367 .clk = "gpt3_ick",
368 .addr = omap2xxx_timer3_addrs,
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370};
371
372/* timer3 slave port */
373static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
374 &omap2420_l4_core__timer3,
375};
376
377/* timer3 hwmod */
378static struct omap_hwmod omap2420_timer3_hwmod = {
379 .name = "timer3",
380 .mpu_irqs = omap2_timer3_mpu_irqs,
381 .main_clk = "gpt3_fck",
382 .prcm = {
383 .omap2 = {
384 .prcm_reg_id = 1,
385 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
386 .module_offs = CORE_MOD,
387 .idlest_reg_id = 1,
388 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
389 },
390 },
391 .slaves = omap2420_timer3_slaves,
392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
393 .class = &omap2xxx_timer_hwmod_class,
394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
395};
396
397/* timer4 */
398static struct omap_hwmod omap2420_timer4_hwmod;
399
400/* l4_core -> timer4 */
401static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
402 .master = &omap2420_l4_core_hwmod,
403 .slave = &omap2420_timer4_hwmod,
404 .clk = "gpt4_ick",
405 .addr = omap2xxx_timer4_addrs,
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
407};
408
409/* timer4 slave port */
410static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
411 &omap2420_l4_core__timer4,
412};
413
414/* timer4 hwmod */
415static struct omap_hwmod omap2420_timer4_hwmod = {
416 .name = "timer4",
417 .mpu_irqs = omap2_timer4_mpu_irqs,
418 .main_clk = "gpt4_fck",
419 .prcm = {
420 .omap2 = {
421 .prcm_reg_id = 1,
422 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
423 .module_offs = CORE_MOD,
424 .idlest_reg_id = 1,
425 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
426 },
427 },
428 .slaves = omap2420_timer4_slaves,
429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
430 .class = &omap2xxx_timer_hwmod_class,
431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
432};
433
434/* timer5 */
435static struct omap_hwmod omap2420_timer5_hwmod;
436
437/* l4_core -> timer5 */
438static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
439 .master = &omap2420_l4_core_hwmod,
440 .slave = &omap2420_timer5_hwmod,
441 .clk = "gpt5_ick",
442 .addr = omap2xxx_timer5_addrs,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
444};
445
446/* timer5 slave port */
447static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
448 &omap2420_l4_core__timer5,
449};
450
451/* timer5 hwmod */
452static struct omap_hwmod omap2420_timer5_hwmod = {
453 .name = "timer5",
454 .mpu_irqs = omap2_timer5_mpu_irqs,
455 .main_clk = "gpt5_fck",
456 .prcm = {
457 .omap2 = {
458 .prcm_reg_id = 1,
459 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
460 .module_offs = CORE_MOD,
461 .idlest_reg_id = 1,
462 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
463 },
464 },
465 .slaves = omap2420_timer5_slaves,
466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
467 .class = &omap2xxx_timer_hwmod_class,
468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
469};
470
471
472/* timer6 */
473static struct omap_hwmod omap2420_timer6_hwmod;
474
475/* l4_core -> timer6 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
477 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer6_hwmod,
479 .clk = "gpt6_ick",
480 .addr = omap2xxx_timer6_addrs,
481 .user = OCP_USER_MPU | OCP_USER_SDMA,
482};
483
484/* timer6 slave port */
485static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
486 &omap2420_l4_core__timer6,
487};
488
489/* timer6 hwmod */
490static struct omap_hwmod omap2420_timer6_hwmod = {
491 .name = "timer6",
492 .mpu_irqs = omap2_timer6_mpu_irqs,
493 .main_clk = "gpt6_fck",
494 .prcm = {
495 .omap2 = {
496 .prcm_reg_id = 1,
497 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
498 .module_offs = CORE_MOD,
499 .idlest_reg_id = 1,
500 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
501 },
502 },
503 .slaves = omap2420_timer6_slaves,
504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
505 .class = &omap2xxx_timer_hwmod_class,
506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
507};
508
509/* timer7 */
510static struct omap_hwmod omap2420_timer7_hwmod;
511
512/* l4_core -> timer7 */
513static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
514 .master = &omap2420_l4_core_hwmod,
515 .slave = &omap2420_timer7_hwmod,
516 .clk = "gpt7_ick",
517 .addr = omap2xxx_timer7_addrs,
518 .user = OCP_USER_MPU | OCP_USER_SDMA,
519};
520
521/* timer7 slave port */
522static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
523 &omap2420_l4_core__timer7,
524};
525
526/* timer7 hwmod */
527static struct omap_hwmod omap2420_timer7_hwmod = {
528 .name = "timer7",
529 .mpu_irqs = omap2_timer7_mpu_irqs,
530 .main_clk = "gpt7_fck",
531 .prcm = {
532 .omap2 = {
533 .prcm_reg_id = 1,
534 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
535 .module_offs = CORE_MOD,
536 .idlest_reg_id = 1,
537 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
538 },
539 },
540 .slaves = omap2420_timer7_slaves,
541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
542 .class = &omap2xxx_timer_hwmod_class,
543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
544};
545
546/* timer8 */
547static struct omap_hwmod omap2420_timer8_hwmod;
548
549/* l4_core -> timer8 */
550static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
551 .master = &omap2420_l4_core_hwmod,
552 .slave = &omap2420_timer8_hwmod,
553 .clk = "gpt8_ick",
554 .addr = omap2xxx_timer8_addrs,
555 .user = OCP_USER_MPU | OCP_USER_SDMA,
556};
557
558/* timer8 slave port */
559static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
560 &omap2420_l4_core__timer8,
561};
562
563/* timer8 hwmod */
564static struct omap_hwmod omap2420_timer8_hwmod = {
565 .name = "timer8",
566 .mpu_irqs = omap2_timer8_mpu_irqs,
567 .main_clk = "gpt8_fck",
568 .prcm = {
569 .omap2 = {
570 .prcm_reg_id = 1,
571 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
572 .module_offs = CORE_MOD,
573 .idlest_reg_id = 1,
574 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
575 },
576 },
577 .slaves = omap2420_timer8_slaves,
578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
579 .class = &omap2xxx_timer_hwmod_class,
580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
581};
582
583/* timer9 */
584static struct omap_hwmod omap2420_timer9_hwmod;
585
586/* l4_core -> timer9 */
587static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
588 .master = &omap2420_l4_core_hwmod,
589 .slave = &omap2420_timer9_hwmod,
590 .clk = "gpt9_ick",
591 .addr = omap2xxx_timer9_addrs,
592 .user = OCP_USER_MPU | OCP_USER_SDMA,
593};
594
595/* timer9 slave port */
596static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
597 &omap2420_l4_core__timer9,
598};
599
600/* timer9 hwmod */
601static struct omap_hwmod omap2420_timer9_hwmod = {
602 .name = "timer9",
603 .mpu_irqs = omap2_timer9_mpu_irqs,
604 .main_clk = "gpt9_fck",
605 .prcm = {
606 .omap2 = {
607 .prcm_reg_id = 1,
608 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
609 .module_offs = CORE_MOD,
610 .idlest_reg_id = 1,
611 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
612 },
613 },
614 .slaves = omap2420_timer9_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
616 .class = &omap2xxx_timer_hwmod_class,
617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
618};
619
620/* timer10 */
621static struct omap_hwmod omap2420_timer10_hwmod;
622
623/* l4_core -> timer10 */
624static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
625 .master = &omap2420_l4_core_hwmod,
626 .slave = &omap2420_timer10_hwmod,
627 .clk = "gpt10_ick",
628 .addr = omap2_timer10_addrs,
629 .user = OCP_USER_MPU | OCP_USER_SDMA,
630};
631
632/* timer10 slave port */
633static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
634 &omap2420_l4_core__timer10,
635};
636
637/* timer10 hwmod */
638static struct omap_hwmod omap2420_timer10_hwmod = {
639 .name = "timer10",
640 .mpu_irqs = omap2_timer10_mpu_irqs,
641 .main_clk = "gpt10_fck",
642 .prcm = {
643 .omap2 = {
644 .prcm_reg_id = 1,
645 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
646 .module_offs = CORE_MOD,
647 .idlest_reg_id = 1,
648 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
649 },
650 },
651 .slaves = omap2420_timer10_slaves,
652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
653 .class = &omap2xxx_timer_hwmod_class,
654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
655};
656
657/* timer11 */
658static struct omap_hwmod omap2420_timer11_hwmod;
659
660/* l4_core -> timer11 */
661static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
662 .master = &omap2420_l4_core_hwmod,
663 .slave = &omap2420_timer11_hwmod,
664 .clk = "gpt11_ick",
665 .addr = omap2_timer11_addrs,
666 .user = OCP_USER_MPU | OCP_USER_SDMA,
667};
668
669/* timer11 slave port */
670static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
671 &omap2420_l4_core__timer11,
672};
673
674/* timer11 hwmod */
675static struct omap_hwmod omap2420_timer11_hwmod = {
676 .name = "timer11",
677 .mpu_irqs = omap2_timer11_mpu_irqs,
678 .main_clk = "gpt11_fck",
679 .prcm = {
680 .omap2 = {
681 .prcm_reg_id = 1,
682 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
683 .module_offs = CORE_MOD,
684 .idlest_reg_id = 1,
685 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
686 },
687 },
688 .slaves = omap2420_timer11_slaves,
689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
690 .class = &omap2xxx_timer_hwmod_class,
691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
692};
693
694/* timer12 */
695static struct omap_hwmod omap2420_timer12_hwmod;
696
697/* l4_core -> timer12 */
698static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
699 .master = &omap2420_l4_core_hwmod,
700 .slave = &omap2420_timer12_hwmod,
701 .clk = "gpt12_ick",
702 .addr = omap2xxx_timer12_addrs,
703 .user = OCP_USER_MPU | OCP_USER_SDMA,
704};
705
706/* timer12 slave port */
707static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
708 &omap2420_l4_core__timer12,
709};
710
711/* timer12 hwmod */
712static struct omap_hwmod omap2420_timer12_hwmod = {
713 .name = "timer12",
714 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
715 .main_clk = "gpt12_fck",
716 .prcm = {
717 .omap2 = {
718 .prcm_reg_id = 1,
719 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
720 .module_offs = CORE_MOD,
721 .idlest_reg_id = 1,
722 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
723 },
724 },
725 .slaves = omap2420_timer12_slaves,
726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
727 .class = &omap2xxx_timer_hwmod_class,
728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
729};
730
731/* l4_wkup -> wd_timer2 */
732static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
733 {
734 .pa_start = 0x48022000,
735 .pa_end = 0x4802207f,
736 .flags = ADDR_TYPE_RT
737 },
738 { }
739};
740
741static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
742 .master = &omap2420_l4_wkup_hwmod,
743 .slave = &omap2420_wd_timer2_hwmod,
744 .clk = "mpu_wdt_ick",
745 .addr = omap2420_wd_timer2_addrs,
746 .user = OCP_USER_MPU | OCP_USER_SDMA,
747};
748
749/* wd_timer2 */
750static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
751 &omap2420_l4_wkup__wd_timer2,
752};
753
754static struct omap_hwmod omap2420_wd_timer2_hwmod = {
755 .name = "wd_timer2",
756 .class = &omap2xxx_wd_timer_hwmod_class,
757 .main_clk = "mpu_wdt_fck",
758 .prcm = {
759 .omap2 = {
760 .prcm_reg_id = 1,
761 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
762 .module_offs = WKUP_MOD,
763 .idlest_reg_id = 1,
764 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
765 },
766 },
767 .slaves = omap2420_wd_timer2_slaves,
768 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
770};
771
772/* UART1 */
773
774static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
775 &omap2_l4_core__uart1,
776};
777
778static struct omap_hwmod omap2420_uart1_hwmod = {
779 .name = "uart1",
780 .mpu_irqs = omap2_uart1_mpu_irqs,
781 .sdma_reqs = omap2_uart1_sdma_reqs,
782 .main_clk = "uart1_fck",
783 .prcm = {
784 .omap2 = {
785 .module_offs = CORE_MOD,
786 .prcm_reg_id = 1,
787 .module_bit = OMAP24XX_EN_UART1_SHIFT,
788 .idlest_reg_id = 1,
789 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
790 },
791 },
792 .slaves = omap2420_uart1_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
794 .class = &omap2_uart_class,
795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
796};
797
798/* UART2 */
799
800static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
801 &omap2_l4_core__uart2,
802};
803
804static struct omap_hwmod omap2420_uart2_hwmod = {
805 .name = "uart2",
806 .mpu_irqs = omap2_uart2_mpu_irqs,
807 .sdma_reqs = omap2_uart2_sdma_reqs,
808 .main_clk = "uart2_fck",
809 .prcm = {
810 .omap2 = {
811 .module_offs = CORE_MOD,
812 .prcm_reg_id = 1,
813 .module_bit = OMAP24XX_EN_UART2_SHIFT,
814 .idlest_reg_id = 1,
815 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
816 },
817 },
818 .slaves = omap2420_uart2_slaves,
819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
820 .class = &omap2_uart_class,
821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
822};
823
824/* UART3 */
825
826static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
827 &omap2_l4_core__uart3,
828};
829
830static struct omap_hwmod omap2420_uart3_hwmod = {
831 .name = "uart3",
832 .mpu_irqs = omap2_uart3_mpu_irqs,
833 .sdma_reqs = omap2_uart3_sdma_reqs,
834 .main_clk = "uart3_fck",
835 .prcm = {
836 .omap2 = {
837 .module_offs = CORE_MOD,
838 .prcm_reg_id = 2,
839 .module_bit = OMAP24XX_EN_UART3_SHIFT,
840 .idlest_reg_id = 2,
841 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
842 },
843 },
844 .slaves = omap2420_uart3_slaves,
845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
846 .class = &omap2_uart_class,
847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
848};
849
850/* dss */
851/* dss master ports */
852static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
853 &omap2420_dss__l3,
854};
855
856/* l4_core -> dss */
857static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
858 .master = &omap2420_l4_core_hwmod,
859 .slave = &omap2420_dss_core_hwmod,
860 .clk = "dss_ick",
861 .addr = omap2_dss_addrs,
862 .fw = {
863 .omap2 = {
864 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
865 .flags = OMAP_FIREWALL_L4,
866 }
867 },
868 .user = OCP_USER_MPU | OCP_USER_SDMA,
869};
870
871/* dss slave ports */
872static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
873 &omap2420_l4_core__dss,
874};
875
876static struct omap_hwmod_opt_clk dss_opt_clks[] = {
877 { .role = "tv_clk", .clk = "dss_54m_fck" },
878 { .role = "sys_clk", .clk = "dss2_fck" },
879};
880
881static struct omap_hwmod omap2420_dss_core_hwmod = {
882 .name = "dss_core",
883 .class = &omap2_dss_hwmod_class,
884 .main_clk = "dss1_fck", /* instead of dss_fck */
885 .sdma_reqs = omap2xxx_dss_sdma_chs,
886 .prcm = {
887 .omap2 = {
888 .prcm_reg_id = 1,
889 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
890 .module_offs = CORE_MOD,
891 .idlest_reg_id = 1,
892 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
893 },
894 },
895 .opt_clks = dss_opt_clks,
896 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
897 .slaves = omap2420_dss_slaves,
898 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
899 .masters = omap2420_dss_masters,
900 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
901 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
902 .flags = HWMOD_NO_IDLEST,
903};
904
905/* l4_core -> dss_dispc */
906static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
907 .master = &omap2420_l4_core_hwmod,
908 .slave = &omap2420_dss_dispc_hwmod,
909 .clk = "dss_ick",
910 .addr = omap2_dss_dispc_addrs,
911 .fw = {
912 .omap2 = {
913 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
914 .flags = OMAP_FIREWALL_L4,
915 }
916 },
917 .user = OCP_USER_MPU | OCP_USER_SDMA,
918};
919
920/* dss_dispc slave ports */
921static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
922 &omap2420_l4_core__dss_dispc,
923};
924
925static struct omap_hwmod omap2420_dss_dispc_hwmod = {
926 .name = "dss_dispc",
927 .class = &omap2_dispc_hwmod_class,
928 .mpu_irqs = omap2_dispc_irqs,
929 .main_clk = "dss1_fck",
930 .prcm = {
931 .omap2 = {
932 .prcm_reg_id = 1,
933 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
934 .module_offs = CORE_MOD,
935 .idlest_reg_id = 1,
936 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
937 },
938 },
939 .slaves = omap2420_dss_dispc_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
941 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
942 .flags = HWMOD_NO_IDLEST,
943};
944
945/* l4_core -> dss_rfbi */
946static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
947 .master = &omap2420_l4_core_hwmod,
948 .slave = &omap2420_dss_rfbi_hwmod,
949 .clk = "dss_ick",
950 .addr = omap2_dss_rfbi_addrs,
951 .fw = {
952 .omap2 = {
953 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
954 .flags = OMAP_FIREWALL_L4,
955 }
956 },
957 .user = OCP_USER_MPU | OCP_USER_SDMA,
958};
959
960/* dss_rfbi slave ports */
961static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
962 &omap2420_l4_core__dss_rfbi,
963};
964
965static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
966 .name = "dss_rfbi",
967 .class = &omap2_rfbi_hwmod_class,
968 .main_clk = "dss1_fck",
969 .prcm = {
970 .omap2 = {
971 .prcm_reg_id = 1,
972 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
973 .module_offs = CORE_MOD,
974 },
975 },
976 .slaves = omap2420_dss_rfbi_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
978 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
979 .flags = HWMOD_NO_IDLEST,
980};
981
982/* l4_core -> dss_venc */
983static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
984 .master = &omap2420_l4_core_hwmod,
985 .slave = &omap2420_dss_venc_hwmod,
986 .clk = "dss_54m_fck",
987 .addr = omap2_dss_venc_addrs,
988 .fw = {
989 .omap2 = {
990 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
991 .flags = OMAP_FIREWALL_L4,
992 }
993 },
994 .flags = OCPIF_SWSUP_IDLE,
995 .user = OCP_USER_MPU | OCP_USER_SDMA,
996};
997
998/* dss_venc slave ports */
999static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1000 &omap2420_l4_core__dss_venc,
1001};
1002
1003static struct omap_hwmod omap2420_dss_venc_hwmod = {
1004 .name = "dss_venc",
1005 .class = &omap2_venc_hwmod_class,
1006 .main_clk = "dss1_fck",
1007 .prcm = {
1008 .omap2 = {
1009 .prcm_reg_id = 1,
1010 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1011 .module_offs = CORE_MOD,
1012 },
1013 },
1014 .slaves = omap2420_dss_venc_slaves,
1015 .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
1016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1017 .flags = HWMOD_NO_IDLEST,
1018};
1019
1020/* I2C common */
1021static struct omap_hwmod_class_sysconfig i2c_sysc = {
1022 .rev_offs = 0x00,
1023 .sysc_offs = 0x20,
1024 .syss_offs = 0x10,
1025 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1026 .sysc_fields = &omap_hwmod_sysc_type1,
1027};
1028
1029static struct omap_hwmod_class i2c_class = {
1030 .name = "i2c",
1031 .sysc = &i2c_sysc,
1032 .rev = OMAP_I2C_IP_VERSION_1,
1033 .reset = &omap_i2c_reset,
1034};
1035
1036static struct omap_i2c_dev_attr i2c_dev_attr = {
1037 .flags = OMAP_I2C_FLAG_NO_FIFO |
1038 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1039 OMAP_I2C_FLAG_16BIT_DATA_REG |
1040 OMAP_I2C_FLAG_BUS_SHIFT_2,
1041};
1042
1043/* I2C1 */
1044
1045static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1046 &omap2420_l4_core__i2c1,
1047};
1048
1049static struct omap_hwmod omap2420_i2c1_hwmod = {
1050 .name = "i2c1",
1051 .mpu_irqs = omap2_i2c1_mpu_irqs,
1052 .sdma_reqs = omap2_i2c1_sdma_reqs,
1053 .main_clk = "i2c1_fck",
1054 .prcm = {
1055 .omap2 = {
1056 .module_offs = CORE_MOD,
1057 .prcm_reg_id = 1,
1058 .module_bit = OMAP2420_EN_I2C1_SHIFT,
1059 .idlest_reg_id = 1,
1060 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1061 },
1062 },
1063 .slaves = omap2420_i2c1_slaves,
1064 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
1065 .class = &i2c_class,
1066 .dev_attr = &i2c_dev_attr,
1067 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1068 .flags = HWMOD_16BIT_REG,
1069};
1070
1071/* I2C2 */
1072
1073static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1074 &omap2420_l4_core__i2c2,
1075};
1076
1077static struct omap_hwmod omap2420_i2c2_hwmod = {
1078 .name = "i2c2",
1079 .mpu_irqs = omap2_i2c2_mpu_irqs,
1080 .sdma_reqs = omap2_i2c2_sdma_reqs,
1081 .main_clk = "i2c2_fck",
1082 .prcm = {
1083 .omap2 = {
1084 .module_offs = CORE_MOD,
1085 .prcm_reg_id = 1,
1086 .module_bit = OMAP2420_EN_I2C2_SHIFT,
1087 .idlest_reg_id = 1,
1088 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1089 },
1090 },
1091 .slaves = omap2420_i2c2_slaves,
1092 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
1093 .class = &i2c_class,
1094 .dev_attr = &i2c_dev_attr,
1095 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1096 .flags = HWMOD_16BIT_REG,
1097};
1098
1099/* l4_wkup -> gpio1 */
1100static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1101 {
1102 .pa_start = 0x48018000,
1103 .pa_end = 0x480181ff,
1104 .flags = ADDR_TYPE_RT
1105 },
1106 { }
1107};
1108
1109static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1110 .master = &omap2420_l4_wkup_hwmod,
1111 .slave = &omap2420_gpio1_hwmod,
1112 .clk = "gpios_ick",
1113 .addr = omap2420_gpio1_addr_space,
1114 .user = OCP_USER_MPU | OCP_USER_SDMA,
1115};
1116
1117/* l4_wkup -> gpio2 */
1118static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1119 {
1120 .pa_start = 0x4801a000,
1121 .pa_end = 0x4801a1ff,
1122 .flags = ADDR_TYPE_RT
1123 },
1124 { }
1125};
1126
1127static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1128 .master = &omap2420_l4_wkup_hwmod,
1129 .slave = &omap2420_gpio2_hwmod,
1130 .clk = "gpios_ick",
1131 .addr = omap2420_gpio2_addr_space,
1132 .user = OCP_USER_MPU | OCP_USER_SDMA,
1133};
1134
1135/* l4_wkup -> gpio3 */
1136static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1137 {
1138 .pa_start = 0x4801c000,
1139 .pa_end = 0x4801c1ff,
1140 .flags = ADDR_TYPE_RT
1141 },
1142 { }
1143};
1144
1145static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1146 .master = &omap2420_l4_wkup_hwmod,
1147 .slave = &omap2420_gpio3_hwmod,
1148 .clk = "gpios_ick",
1149 .addr = omap2420_gpio3_addr_space,
1150 .user = OCP_USER_MPU | OCP_USER_SDMA,
1151};
1152
1153/* l4_wkup -> gpio4 */
1154static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1155 {
1156 .pa_start = 0x4801e000,
1157 .pa_end = 0x4801e1ff,
1158 .flags = ADDR_TYPE_RT
1159 },
1160 { }
1161};
1162
1163static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1164 .master = &omap2420_l4_wkup_hwmod,
1165 .slave = &omap2420_gpio4_hwmod,
1166 .clk = "gpios_ick",
1167 .addr = omap2420_gpio4_addr_space,
1168 .user = OCP_USER_MPU | OCP_USER_SDMA,
1169};
1170
1171/* gpio dev_attr */
1172static struct omap_gpio_dev_attr gpio_dev_attr = {
1173 .bank_width = 32,
1174 .dbck_flag = false,
1175};
1176
1177/* gpio1 */
1178static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1179 &omap2420_l4_wkup__gpio1,
1180};
1181
1182static struct omap_hwmod omap2420_gpio1_hwmod = {
1183 .name = "gpio1",
1184 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1185 .mpu_irqs = omap2_gpio1_irqs,
1186 .main_clk = "gpios_fck",
1187 .prcm = {
1188 .omap2 = {
1189 .prcm_reg_id = 1,
1190 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1191 .module_offs = WKUP_MOD,
1192 .idlest_reg_id = 1,
1193 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1194 },
1195 },
1196 .slaves = omap2420_gpio1_slaves,
1197 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1198 .class = &omap2xxx_gpio_hwmod_class,
1199 .dev_attr = &gpio_dev_attr,
1200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1201};
1202
1203/* gpio2 */
1204static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1205 &omap2420_l4_wkup__gpio2,
1206};
1207
1208static struct omap_hwmod omap2420_gpio2_hwmod = {
1209 .name = "gpio2",
1210 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1211 .mpu_irqs = omap2_gpio2_irqs,
1212 .main_clk = "gpios_fck",
1213 .prcm = {
1214 .omap2 = {
1215 .prcm_reg_id = 1,
1216 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1217 .module_offs = WKUP_MOD,
1218 .idlest_reg_id = 1,
1219 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1220 },
1221 },
1222 .slaves = omap2420_gpio2_slaves,
1223 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1224 .class = &omap2xxx_gpio_hwmod_class,
1225 .dev_attr = &gpio_dev_attr,
1226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1227};
1228
1229/* gpio3 */
1230static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1231 &omap2420_l4_wkup__gpio3,
1232};
1233
1234static struct omap_hwmod omap2420_gpio3_hwmod = {
1235 .name = "gpio3",
1236 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1237 .mpu_irqs = omap2_gpio3_irqs,
1238 .main_clk = "gpios_fck",
1239 .prcm = {
1240 .omap2 = {
1241 .prcm_reg_id = 1,
1242 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1243 .module_offs = WKUP_MOD,
1244 .idlest_reg_id = 1,
1245 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1246 },
1247 },
1248 .slaves = omap2420_gpio3_slaves,
1249 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1250 .class = &omap2xxx_gpio_hwmod_class,
1251 .dev_attr = &gpio_dev_attr,
1252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1253};
1254
1255/* gpio4 */
1256static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1257 &omap2420_l4_wkup__gpio4,
1258};
1259
1260static struct omap_hwmod omap2420_gpio4_hwmod = {
1261 .name = "gpio4",
1262 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1263 .mpu_irqs = omap2_gpio4_irqs,
1264 .main_clk = "gpios_fck",
1265 .prcm = {
1266 .omap2 = {
1267 .prcm_reg_id = 1,
1268 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1269 .module_offs = WKUP_MOD,
1270 .idlest_reg_id = 1,
1271 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1272 },
1273 },
1274 .slaves = omap2420_gpio4_slaves,
1275 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1276 .class = &omap2xxx_gpio_hwmod_class,
1277 .dev_attr = &gpio_dev_attr,
1278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1279};
1280
1281/* dma attributes */
1282static struct omap_dma_dev_attr dma_dev_attr = {
1283 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1284 IS_CSSA_32 | IS_CDSA_32,
1285 .lch_count = 32,
1286};
1287
1288/* dma_system -> L3 */
1289static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1290 .master = &omap2420_dma_system_hwmod,
1291 .slave = &omap2420_l3_main_hwmod,
1292 .clk = "core_l3_ck",
1293 .user = OCP_USER_MPU | OCP_USER_SDMA,
1294};
1295
1296/* dma_system master ports */
1297static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1298 &omap2420_dma_system__l3,
1299};
1300
1301/* l4_core -> dma_system */
1302static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1303 .master = &omap2420_l4_core_hwmod,
1304 .slave = &omap2420_dma_system_hwmod,
1305 .clk = "sdma_ick",
1306 .addr = omap2_dma_system_addrs,
1307 .user = OCP_USER_MPU | OCP_USER_SDMA,
1308};
1309
1310/* dma_system slave ports */
1311static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1312 &omap2420_l4_core__dma_system,
1313};
1314
1315static struct omap_hwmod omap2420_dma_system_hwmod = {
1316 .name = "dma",
1317 .class = &omap2xxx_dma_hwmod_class,
1318 .mpu_irqs = omap2_dma_system_irqs,
1319 .main_clk = "core_l3_ck",
1320 .slaves = omap2420_dma_system_slaves,
1321 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
1322 .masters = omap2420_dma_system_masters,
1323 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
1324 .dev_attr = &dma_dev_attr,
1325 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1326 .flags = HWMOD_NO_IDLEST,
1327};
1328
1329/* mailbox */
1330static struct omap_hwmod omap2420_mailbox_hwmod;
1331static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1332 { .name = "dsp", .irq = 26 },
1333 { .name = "iva", .irq = 34 },
1334 { .irq = -1 }
1335};
1336
1337/* l4_core -> mailbox */
1338static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1339 .master = &omap2420_l4_core_hwmod,
1340 .slave = &omap2420_mailbox_hwmod,
1341 .addr = omap2_mailbox_addrs,
1342 .user = OCP_USER_MPU | OCP_USER_SDMA,
1343};
1344
1345/* mailbox slave ports */
1346static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1347 &omap2420_l4_core__mailbox,
1348};
1349
1350static struct omap_hwmod omap2420_mailbox_hwmod = {
1351 .name = "mailbox",
1352 .class = &omap2xxx_mailbox_hwmod_class,
1353 .mpu_irqs = omap2420_mailbox_irqs,
1354 .main_clk = "mailboxes_ick",
1355 .prcm = {
1356 .omap2 = {
1357 .prcm_reg_id = 1,
1358 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1359 .module_offs = CORE_MOD,
1360 .idlest_reg_id = 1,
1361 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1362 },
1363 },
1364 .slaves = omap2420_mailbox_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1367};
1368
1369/* mcspi1 */
1370static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1371 &omap2420_l4_core__mcspi1,
1372};
1373
1374static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1375 .num_chipselect = 4,
1376};
1377
1378static struct omap_hwmod omap2420_mcspi1_hwmod = {
1379 .name = "mcspi1_hwmod",
1380 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1381 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1382 .main_clk = "mcspi1_fck",
1383 .prcm = {
1384 .omap2 = {
1385 .module_offs = CORE_MOD,
1386 .prcm_reg_id = 1,
1387 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1388 .idlest_reg_id = 1,
1389 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1390 },
1391 },
1392 .slaves = omap2420_mcspi1_slaves,
1393 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1394 .class = &omap2xxx_mcspi_class,
1395 .dev_attr = &omap_mcspi1_dev_attr,
1396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1397};
1398
1399/* mcspi2 */
1400static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1401 &omap2420_l4_core__mcspi2,
1402};
1403
1404static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1405 .num_chipselect = 2,
1406};
1407
1408static struct omap_hwmod omap2420_mcspi2_hwmod = {
1409 .name = "mcspi2_hwmod",
1410 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1411 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1412 .main_clk = "mcspi2_fck",
1413 .prcm = {
1414 .omap2 = {
1415 .module_offs = CORE_MOD,
1416 .prcm_reg_id = 1,
1417 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1418 .idlest_reg_id = 1,
1419 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1420 },
1421 },
1422 .slaves = omap2420_mcspi2_slaves,
1423 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
1424 .class = &omap2xxx_mcspi_class,
1425 .dev_attr = &omap_mcspi2_dev_attr,
1426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1427};
1428
1429/*
1430 * 'mcbsp' class
1431 * multi channel buffered serial port controller
1432 */
1433
1434static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1435 .name = "mcbsp",
1436};
1437
1438/* mcbsp1 */
1439static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1440 { .name = "tx", .irq = 59 },
1441 { .name = "rx", .irq = 60 },
1442 { .irq = -1 }
1443};
1444
1445/* l4_core -> mcbsp1 */
1446static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1447 .master = &omap2420_l4_core_hwmod,
1448 .slave = &omap2420_mcbsp1_hwmod,
1449 .clk = "mcbsp1_ick",
1450 .addr = omap2_mcbsp1_addrs,
1451 .user = OCP_USER_MPU | OCP_USER_SDMA,
1452};
1453
1454/* mcbsp1 slave ports */
1455static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1456 &omap2420_l4_core__mcbsp1,
1457};
1458
1459static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1460 .name = "mcbsp1",
1461 .class = &omap2420_mcbsp_hwmod_class,
1462 .mpu_irqs = omap2420_mcbsp1_irqs,
1463 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1464 .main_clk = "mcbsp1_fck",
1465 .prcm = {
1466 .omap2 = {
1467 .prcm_reg_id = 1,
1468 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1469 .module_offs = CORE_MOD,
1470 .idlest_reg_id = 1,
1471 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1472 },
1473 },
1474 .slaves = omap2420_mcbsp1_slaves,
1475 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1476 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1477};
1478
1479/* mcbsp2 */
1480static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1481 { .name = "tx", .irq = 62 },
1482 { .name = "rx", .irq = 63 },
1483 { .irq = -1 }
1484};
1485
1486/* l4_core -> mcbsp2 */
1487static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1488 .master = &omap2420_l4_core_hwmod,
1489 .slave = &omap2420_mcbsp2_hwmod,
1490 .clk = "mcbsp2_ick",
1491 .addr = omap2xxx_mcbsp2_addrs,
1492 .user = OCP_USER_MPU | OCP_USER_SDMA,
1493};
1494
1495/* mcbsp2 slave ports */
1496static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1497 &omap2420_l4_core__mcbsp2,
1498};
1499
1500static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1501 .name = "mcbsp2",
1502 .class = &omap2420_mcbsp_hwmod_class,
1503 .mpu_irqs = omap2420_mcbsp2_irqs,
1504 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1505 .main_clk = "mcbsp2_fck",
1506 .prcm = {
1507 .omap2 = {
1508 .prcm_reg_id = 1,
1509 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1510 .module_offs = CORE_MOD,
1511 .idlest_reg_id = 1,
1512 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1513 },
1514 },
1515 .slaves = omap2420_mcbsp2_slaves,
1516 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1518};
1519
1520static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1521 &omap2420_l3_main_hwmod,
1522 &omap2420_l4_core_hwmod,
1523 &omap2420_l4_wkup_hwmod,
1524 &omap2420_mpu_hwmod,
1525 &omap2420_iva_hwmod,
1526
1527 &omap2420_timer1_hwmod,
1528 &omap2420_timer2_hwmod,
1529 &omap2420_timer3_hwmod,
1530 &omap2420_timer4_hwmod,
1531 &omap2420_timer5_hwmod,
1532 &omap2420_timer6_hwmod,
1533 &omap2420_timer7_hwmod,
1534 &omap2420_timer8_hwmod,
1535 &omap2420_timer9_hwmod,
1536 &omap2420_timer10_hwmod,
1537 &omap2420_timer11_hwmod,
1538 &omap2420_timer12_hwmod,
1539
1540 &omap2420_wd_timer2_hwmod,
1541 &omap2420_uart1_hwmod,
1542 &omap2420_uart2_hwmod,
1543 &omap2420_uart3_hwmod,
1544 /* dss class */
1545 &omap2420_dss_core_hwmod,
1546 &omap2420_dss_dispc_hwmod,
1547 &omap2420_dss_rfbi_hwmod,
1548 &omap2420_dss_venc_hwmod,
1549 /* i2c class */
1550 &omap2420_i2c1_hwmod,
1551 &omap2420_i2c2_hwmod,
1552
1553 /* gpio class */
1554 &omap2420_gpio1_hwmod,
1555 &omap2420_gpio2_hwmod,
1556 &omap2420_gpio3_hwmod,
1557 &omap2420_gpio4_hwmod,
1558
1559 /* dma_system class*/
1560 &omap2420_dma_system_hwmod,
1561
1562 /* mailbox class */
1563 &omap2420_mailbox_hwmod,
1564
1565 /* mcbsp class */
1566 &omap2420_mcbsp1_hwmod,
1567 &omap2420_mcbsp2_hwmod,
1568
1569 /* mcspi class */
1570 &omap2420_mcspi1_hwmod,
1571 &omap2420_mcspi2_hwmod,
1572 NULL,
1573};
1574
1575int __init omap2420_hwmod_init(void)
1576{
1577 return omap_hwmod_register(omap2420_hwmods);
1578}